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475 lines
25 KiB
475 lines
25 KiB
// AsmJit - Machine code generation for C++
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//
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// * Official AsmJit Home Page: https://asmjit.com
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// * Official Github Repository: https://github.com/asmjit/asmjit
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//
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// Copyright (c) 2008-2020 The AsmJit Authors
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//
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// This software is provided 'as-is', without any express or implied
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// warranty. In no event will the authors be held liable for any damages
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// arising from the use of this software.
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//
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// Permission is granted to anyone to use this software for any purpose,
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// including commercial applications, and to alter it and redistribute it
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// freely, subject to the following restrictions:
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//
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// 1. The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software. If you use this software
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// in a product, an acknowledgment in the product documentation would be
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// appreciated but is not required.
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// 2. Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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// 3. This notice may not be removed or altered from any source distribution.
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#ifndef ASMJIT_X86_X86INSTDB_H_INCLUDED
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#define ASMJIT_X86_X86INSTDB_H_INCLUDED
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#include "../x86/x86globals.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(x86)
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//! \addtogroup asmjit_x86
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//! \{
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//! Instruction database (X86).
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namespace InstDB {
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// ============================================================================
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// [asmjit::x86::InstDB::Mode]
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// ============================================================================
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//! Describes which mode is supported by an instruction or instruction signature.
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enum Mode : uint32_t {
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kModeNone = 0x00u, //!< Invalid.
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kModeX86 = 0x01u, //!< X86 mode supported.
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kModeX64 = 0x02u, //!< X64 mode supported.
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kModeAny = 0x03u //!< Both X86 and X64 modes supported.
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};
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static constexpr uint32_t modeFromArch(uint32_t arch) noexcept {
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return arch == Environment::kArchX86 ? kModeX86 :
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arch == Environment::kArchX64 ? kModeX64 : kModeNone;
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}
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// ============================================================================
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// [asmjit::x86::InstDB::OpFlags]
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// ============================================================================
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//! Operand flags (X86).
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enum OpFlags : uint32_t {
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kOpNone = 0x00000000u, //!< No flags.
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kOpGpbLo = 0x00000001u, //!< Operand can be low 8-bit GPB register.
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kOpGpbHi = 0x00000002u, //!< Operand can be high 8-bit GPB register.
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kOpGpw = 0x00000004u, //!< Operand can be 16-bit GPW register.
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kOpGpd = 0x00000008u, //!< Operand can be 32-bit GPD register.
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kOpGpq = 0x00000010u, //!< Operand can be 64-bit GPQ register.
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kOpXmm = 0x00000020u, //!< Operand can be 128-bit XMM register.
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kOpYmm = 0x00000040u, //!< Operand can be 256-bit YMM register.
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kOpZmm = 0x00000080u, //!< Operand can be 512-bit ZMM register.
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kOpMm = 0x00000100u, //!< Operand can be 64-bit MM register.
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kOpKReg = 0x00000200u, //!< Operand can be 64-bit K register.
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kOpSReg = 0x00000400u, //!< Operand can be SReg (segment register).
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kOpCReg = 0x00000800u, //!< Operand can be CReg (control register).
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kOpDReg = 0x00001000u, //!< Operand can be DReg (debug register).
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kOpSt = 0x00002000u, //!< Operand can be 80-bit ST register (X87).
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kOpBnd = 0x00004000u, //!< Operand can be 128-bit BND register.
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kOpTmm = 0x00008000u, //!< Operand can be 0..8192-bit TMM register.
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kOpAllRegs = 0x0000FFFFu, //!< Combination of all possible registers.
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kOpI4 = 0x00010000u, //!< Operand can be unsigned 4-bit immediate.
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kOpU4 = 0x00020000u, //!< Operand can be unsigned 4-bit immediate.
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kOpI8 = 0x00040000u, //!< Operand can be signed 8-bit immediate.
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kOpU8 = 0x00080000u, //!< Operand can be unsigned 8-bit immediate.
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kOpI16 = 0x00100000u, //!< Operand can be signed 16-bit immediate.
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kOpU16 = 0x00200000u, //!< Operand can be unsigned 16-bit immediate.
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kOpI32 = 0x00400000u, //!< Operand can be signed 32-bit immediate.
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kOpU32 = 0x00800000u, //!< Operand can be unsigned 32-bit immediate.
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kOpI64 = 0x01000000u, //!< Operand can be signed 64-bit immediate.
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kOpU64 = 0x02000000u, //!< Operand can be unsigned 64-bit immediate.
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kOpAllImm = 0x03FF0000u, //!< Operand can be any immediate.
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kOpMem = 0x04000000u, //!< Operand can be a scalar memory pointer.
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kOpVm = 0x08000000u, //!< Operand can be a vector memory pointer.
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kOpRel8 = 0x10000000u, //!< Operand can be relative 8-bit displacement.
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kOpRel32 = 0x20000000u, //!< Operand can be relative 32-bit displacement.
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kOpImplicit = 0x80000000u //!< Operand is implicit.
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};
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// ============================================================================
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// [asmjit::x86::InstDB::MemFlags]
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// ============================================================================
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//! Memory operand flags (X86).
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enum MemFlags : uint32_t {
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// NOTE: Instruction uses either scalar or vector memory operands, they never
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// collide. This allows us to share bits between "M" and "Vm" enums.
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kMemOpAny = 0x0001u, //!< Operand can be any scalar memory pointer.
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kMemOpM8 = 0x0002u, //!< Operand can be an 8-bit memory pointer.
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kMemOpM16 = 0x0004u, //!< Operand can be a 16-bit memory pointer.
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kMemOpM32 = 0x0008u, //!< Operand can be a 32-bit memory pointer.
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kMemOpM48 = 0x0010u, //!< Operand can be a 48-bit memory pointer (FAR pointers only).
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kMemOpM64 = 0x0020u, //!< Operand can be a 64-bit memory pointer.
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kMemOpM80 = 0x0040u, //!< Operand can be an 80-bit memory pointer.
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kMemOpM128 = 0x0080u, //!< Operand can be a 128-bit memory pointer.
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kMemOpM256 = 0x0100u, //!< Operand can be a 256-bit memory pointer.
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kMemOpM512 = 0x0200u, //!< Operand can be a 512-bit memory pointer.
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kMemOpM1024 = 0x0400u, //!< Operand can be a 1024-bit memory pointer.
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kMemOpVm32x = 0x0002u, //!< Operand can be a vm32x (vector) pointer.
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kMemOpVm32y = 0x0004u, //!< Operand can be a vm32y (vector) pointer.
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kMemOpVm32z = 0x0008u, //!< Operand can be a vm32z (vector) pointer.
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kMemOpVm64x = 0x0020u, //!< Operand can be a vm64x (vector) pointer.
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kMemOpVm64y = 0x0040u, //!< Operand can be a vm64y (vector) pointer.
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kMemOpVm64z = 0x0080u, //!< Operand can be a vm64z (vector) pointer.
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kMemOpBaseOnly = 0x0800u, //!< Only memory base is allowed (no index, no offset).
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kMemOpDs = 0x1000u, //!< Implicit memory operand's DS segment.
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kMemOpEs = 0x2000u, //!< Implicit memory operand's ES segment.
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kMemOpMib = 0x4000u, //!< Operand must be MIB (base+index) pointer.
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kMemOpTMem = 0x8000u //!< Operand is a sib_mem (ADX memory operand).
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};
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// ============================================================================
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// [asmjit::x86::InstDB::Flags]
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// ============================================================================
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//! Instruction flags (X86).
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//!
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//! Details about instruction encoding, operation, features, and some limitations.
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enum Flags : uint32_t {
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kFlagNone = 0x00000000u, //!< No flags.
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// Instruction Family
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// ------------------
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//
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// Instruction family information.
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kFlagFpu = 0x00000100u, //!< Instruction that accesses FPU registers.
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kFlagMmx = 0x00000200u, //!< Instruction that accesses MMX registers (including 3DNOW and GEODE) and EMMS.
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kFlagVec = 0x00000400u, //!< Instruction that accesses XMM registers (SSE, AVX, AVX512).
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// Prefixes and Encoding Flags
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// ---------------------------
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//
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// These describe optional X86 prefixes that can be used to change the instruction's operation.
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kFlagTsib = 0x00000800u, //!< Instruction uses TSIB (or SIB_MEM) encoding (MODRM followed by SIB).
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kFlagRep = 0x00001000u, //!< Instruction can be prefixed with using the REP(REPE) or REPNE prefix.
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kFlagRepIgnored = 0x00002000u, //!< Instruction ignores REP|REPNE prefixes, but they are accepted.
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kFlagLock = 0x00004000u, //!< Instruction can be prefixed with using the LOCK prefix.
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kFlagXAcquire = 0x00008000u, //!< Instruction can be prefixed with using the XACQUIRE prefix.
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kFlagXRelease = 0x00010000u, //!< Instruction can be prefixed with using the XRELEASE prefix.
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kFlagMib = 0x00020000u, //!< Instruction uses MIB (BNDLDX|BNDSTX) to encode two registers.
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kFlagVsib = 0x00040000u, //!< Instruction uses VSIB instead of legacy SIB.
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kFlagVex = 0x00080000u, //!< Instruction can be encoded by VEX|XOP (AVX|AVX2|BMI|XOP|...).
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kFlagEvex = 0x00100000u, //!< Instruction can be encoded by EVEX (AVX512).
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kFlagPreferEvex = 0x00200000u, //!< EVEX encoding is preferred over VEX encoding (AVX515_VNNI vs AVX_VNNI).
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// FPU Flags
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// ---------
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//
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// Used to tell the encoder which memory operand sizes are encodable.
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kFlagFpuM16 = 0x00200000u, //!< FPU instruction can address `word_ptr` (shared with M80).
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kFlagFpuM32 = 0x00400000u, //!< FPU instruction can address `dword_ptr`.
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kFlagFpuM64 = 0x00800000u, //!< FPU instruction can address `qword_ptr`.
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kFlagFpuM80 = 0x00200000u, //!< FPU instruction can address `tword_ptr` (shared with M16).
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// AVX and AVX515 Flags
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// --------------------
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//
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// If both `kFlagPrefixVex` and `kFlagPrefixEvex` flags are specified it
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// means that the instructions can be encoded by either VEX or EVEX prefix.
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// In that case AsmJit checks global options and also instruction options
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// to decide whether to emit VEX or EVEX prefix.
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kFlagAvx512_ = 0x00000000u, //!< Internally used in tables, has no meaning.
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kFlagAvx512K = 0x01000000u, //!< Supports masking {k1..k7}.
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kFlagAvx512Z = 0x02000000u, //!< Supports zeroing {z}, must be used together with `kAvx512k`.
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kFlagAvx512ER = 0x04000000u, //!< Supports 'embedded-rounding' {er} with implicit {sae},
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kFlagAvx512SAE = 0x08000000u, //!< Supports 'suppress-all-exceptions' {sae}.
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kFlagAvx512B32 = 0x10000000u, //!< Supports 32-bit broadcast 'b32'.
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kFlagAvx512B64 = 0x20000000u, //!< Supports 64-bit broadcast 'b64'.
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kFlagAvx512T4X = 0x80000000u, //!< Operates on a vector of consecutive registers (AVX512_4FMAPS and AVX512_4VNNIW).
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// Combinations used by instruction tables to make AVX512 definitions more compact.
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kFlagAvx512KZ = kFlagAvx512K | kFlagAvx512Z,
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kFlagAvx512ER_SAE = kFlagAvx512ER | kFlagAvx512SAE,
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kFlagAvx512KZ_SAE = kFlagAvx512KZ | kFlagAvx512SAE,
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kFlagAvx512KZ_SAE_B32 = kFlagAvx512KZ_SAE | kFlagAvx512B32,
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kFlagAvx512KZ_SAE_B64 = kFlagAvx512KZ_SAE | kFlagAvx512B64,
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kFlagAvx512KZ_ER_SAE = kFlagAvx512KZ | kFlagAvx512ER_SAE,
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kFlagAvx512KZ_ER_SAE_B32 = kFlagAvx512KZ_ER_SAE | kFlagAvx512B32,
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kFlagAvx512KZ_ER_SAE_B64 = kFlagAvx512KZ_ER_SAE | kFlagAvx512B64,
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kFlagAvx512K_B32 = kFlagAvx512K | kFlagAvx512B32,
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kFlagAvx512K_B64 = kFlagAvx512K | kFlagAvx512B64,
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kFlagAvx512KZ_B32 = kFlagAvx512KZ | kFlagAvx512B32,
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kFlagAvx512KZ_B64 = kFlagAvx512KZ | kFlagAvx512B64
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};
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// ============================================================================
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// [asmjit::x86::InstDB::SingleRegCase]
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// ============================================================================
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enum SingleRegCase : uint32_t {
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//! No special handling.
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kSingleRegNone = 0,
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//! Operands become read-only - `REG & REG` and similar.
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kSingleRegRO = 1,
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//! Operands become write-only - `REG ^ REG` and similar.
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kSingleRegWO = 2
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};
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// ============================================================================
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// [asmjit::x86::InstDB::InstSignature / OpSignature]
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// ============================================================================
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//! Operand signature (X86).
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//!
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//! Contains all possible operand combinations, memory size information, and
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//! a fixed register id (or `BaseReg::kIdBad` if fixed id isn't required).
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struct OpSignature {
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//! Operand flags.
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uint32_t opFlags;
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//! Memory flags.
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uint16_t memFlags;
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//! Extra flags.
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uint8_t extFlags;
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//! Mask of possible register IDs.
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uint8_t regMask;
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};
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ASMJIT_VARAPI const OpSignature _opSignatureTable[];
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//! Instruction signature (X86).
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//!
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//! Contains a sequence of operands' combinations and other metadata that defines
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//! a single instruction. This data is used by instruction validator.
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struct InstSignature {
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//! Count of operands in `opIndex` (0..6).
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uint8_t opCount : 3;
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//! Architecture modes supported (X86 / X64).
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uint8_t modes : 2;
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//! Number of implicit operands.
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uint8_t implicit : 3;
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//! Reserved for future use.
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uint8_t reserved;
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//! Indexes to `OpSignature` table.
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uint8_t operands[Globals::kMaxOpCount];
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};
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ASMJIT_VARAPI const InstSignature _instSignatureTable[];
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// ============================================================================
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// [asmjit::x86::InstDB::CommonInfo]
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// ============================================================================
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//! Instruction common information (X86)
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//!
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//! Aggregated information shared across one or more instruction.
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struct CommonInfo {
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//! Instruction flags.
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uint32_t _flags;
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//! First `InstSignature` entry in the database.
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uint32_t _iSignatureIndex : 11;
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//! Number of relevant `ISignature` entries.
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uint32_t _iSignatureCount : 5;
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//! Control type, see `ControlType`.
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uint32_t _controlType : 3;
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//! Specifies what happens if all source operands share the same register.
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uint32_t _singleRegCase : 2;
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//! Reserved for future use.
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uint32_t _reserved : 11;
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// --------------------------------------------------------------------------
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// [Accessors]
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// --------------------------------------------------------------------------
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//! Returns instruction flags, see `InstInfo::Flags`.
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inline uint32_t flags() const noexcept { return _flags; }
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//! Tests whether the instruction has a `flag`, see `InstInfo::Flags`.
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inline bool hasFlag(uint32_t flag) const noexcept { return (_flags & flag) != 0; }
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//! Tests whether the instruction is FPU instruction.
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inline bool isFpu() const noexcept { return hasFlag(kFlagFpu); }
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//! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
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inline bool isMmx() const noexcept { return hasFlag(kFlagMmx); }
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//! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
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inline bool isVec() const noexcept { return hasFlag(kFlagVec); }
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//! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
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inline bool isSse() const noexcept { return (flags() & (kFlagVec | kFlagVex | kFlagEvex)) == kFlagVec; }
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//! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
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inline bool isAvx() const noexcept { return isVec() && isVexOrEvex(); }
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//! Tests whether the instruction can be prefixed with LOCK prefix.
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inline bool hasLockPrefix() const noexcept { return hasFlag(kFlagLock); }
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//! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
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inline bool hasRepPrefix() const noexcept { return hasFlag(kFlagRep); }
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//! Tests whether the instruction can be prefixed with XACQUIRE prefix.
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inline bool hasXAcquirePrefix() const noexcept { return hasFlag(kFlagXAcquire); }
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//! Tests whether the instruction can be prefixed with XRELEASE prefix.
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inline bool hasXReleasePrefix() const noexcept { return hasFlag(kFlagXRelease); }
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//! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
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inline bool isRepIgnored() const noexcept { return hasFlag(kFlagRepIgnored); }
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//! Tests whether the instruction uses MIB.
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inline bool isMibOp() const noexcept { return hasFlag(kFlagMib); }
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//! Tests whether the instruction uses VSIB.
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inline bool isVsibOp() const noexcept { return hasFlag(kFlagVsib); }
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//! Tests whether the instruction uses TSIB (AMX, instruction requires MOD+SIB).
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inline bool isTsibOp() const noexcept { return hasFlag(kFlagTsib); }
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//! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
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inline bool isVex() const noexcept { return hasFlag(kFlagVex); }
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//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
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inline bool isEvex() const noexcept { return hasFlag(kFlagEvex); }
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//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
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inline bool isVexOrEvex() const noexcept { return hasFlag(kFlagVex | kFlagEvex); }
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//! Tests whether the instruction should prefer EVEX prefix instead of VEX prefix.
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inline bool preferEvex() const noexcept { return hasFlag(kFlagPreferEvex); }
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//! Tests whether the instruction supports AVX512 masking {k}.
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inline bool hasAvx512K() const noexcept { return hasFlag(kFlagAvx512K); }
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//! Tests whether the instruction supports AVX512 zeroing {k}{z}.
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inline bool hasAvx512Z() const noexcept { return hasFlag(kFlagAvx512Z); }
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//! Tests whether the instruction supports AVX512 embedded-rounding {er}.
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inline bool hasAvx512ER() const noexcept { return hasFlag(kFlagAvx512ER); }
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//! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
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inline bool hasAvx512SAE() const noexcept { return hasFlag(kFlagAvx512SAE); }
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//! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
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inline bool hasAvx512B() const noexcept { return hasFlag(kFlagAvx512B32 | kFlagAvx512B64); }
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//! Tests whether the instruction supports AVX512 broadcast (32-bit).
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inline bool hasAvx512B32() const noexcept { return hasFlag(kFlagAvx512B32); }
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//! Tests whether the instruction supports AVX512 broadcast (64-bit).
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inline bool hasAvx512B64() const noexcept { return hasFlag(kFlagAvx512B64); }
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inline uint32_t signatureIndex() const noexcept { return _iSignatureIndex; }
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inline uint32_t signatureCount() const noexcept { return _iSignatureCount; }
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inline const InstSignature* signatureData() const noexcept { return _instSignatureTable + _iSignatureIndex; }
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inline const InstSignature* signatureEnd() const noexcept { return _instSignatureTable + _iSignatureIndex + _iSignatureCount; }
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//! Returns the control-flow type of the instruction.
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inline uint32_t controlType() const noexcept { return _controlType; }
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inline uint32_t singleRegCase() const noexcept { return _singleRegCase; }
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};
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ASMJIT_VARAPI const CommonInfo _commonInfoTable[];
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// ============================================================================
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// [asmjit::x86::InstDB::InstInfo]
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// ============================================================================
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//! Instruction information (X86).
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struct InstInfo {
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//! Index to \ref _nameData.
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uint32_t _nameDataIndex : 14;
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//! Index to \ref _commonInfoTable.
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uint32_t _commonInfoIndex : 10;
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//! Index to \ref _commonInfoTableB.
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uint32_t _commonInfoIndexB : 8;
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//! Instruction encoding (internal encoding identifier used by \ref Assembler).
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uint8_t _encoding;
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//! Main opcode value (0..255).
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uint8_t _mainOpcodeValue;
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//! Index to \ref _mainOpcodeTable` that is combined with \ref _mainOpcodeValue
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//! to form the final opcode.
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uint8_t _mainOpcodeIndex;
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//! Index to \ref _altOpcodeTable that contains a full alternative opcode.
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uint8_t _altOpcodeIndex;
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// --------------------------------------------------------------------------
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// [Accessors]
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// --------------------------------------------------------------------------
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//! Returns common information, see `CommonInfo`.
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inline const CommonInfo& commonInfo() const noexcept { return _commonInfoTable[_commonInfoIndex]; }
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//! Tests whether the instruction has flag `flag`, see `Flags`.
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inline bool hasFlag(uint32_t flag) const noexcept { return commonInfo().hasFlag(flag); }
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//! Returns instruction flags, see `Flags`.
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inline uint32_t flags() const noexcept { return commonInfo().flags(); }
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//! Tests whether the instruction is FPU instruction.
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inline bool isFpu() const noexcept { return commonInfo().isFpu(); }
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//! Tests whether the instruction is MMX/3DNOW instruction that accesses MMX registers (includes EMMS and FEMMS).
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inline bool isMmx() const noexcept { return commonInfo().isMmx(); }
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//! Tests whether the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
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inline bool isVec() const noexcept { return commonInfo().isVec(); }
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//! Tests whether the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
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inline bool isSse() const noexcept { return commonInfo().isSse(); }
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//! Tests whether the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
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inline bool isAvx() const noexcept { return commonInfo().isAvx(); }
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//! Tests whether the instruction can be prefixed with LOCK prefix.
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inline bool hasLockPrefix() const noexcept { return commonInfo().hasLockPrefix(); }
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//! Tests whether the instruction can be prefixed with REP (REPE|REPZ) prefix.
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inline bool hasRepPrefix() const noexcept { return commonInfo().hasRepPrefix(); }
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//! Tests whether the instruction can be prefixed with XACQUIRE prefix.
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inline bool hasXAcquirePrefix() const noexcept { return commonInfo().hasXAcquirePrefix(); }
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//! Tests whether the instruction can be prefixed with XRELEASE prefix.
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inline bool hasXReleasePrefix() const noexcept { return commonInfo().hasXReleasePrefix(); }
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//! Tests whether the rep prefix is supported by the instruction, but ignored (has no effect).
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inline bool isRepIgnored() const noexcept { return commonInfo().isRepIgnored(); }
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//! Tests whether the instruction uses MIB.
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inline bool isMibOp() const noexcept { return hasFlag(kFlagMib); }
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//! Tests whether the instruction uses VSIB.
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inline bool isVsibOp() const noexcept { return hasFlag(kFlagVsib); }
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//! Tests whether the instruction uses VEX (can be set together with EVEX if both are encodable).
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inline bool isVex() const noexcept { return hasFlag(kFlagVex); }
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//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
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inline bool isEvex() const noexcept { return hasFlag(kFlagEvex); }
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//! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable).
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inline bool isVexOrEvex() const noexcept { return hasFlag(kFlagVex | kFlagEvex); }
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//! Tests whether the instruction supports AVX512 masking {k}.
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inline bool hasAvx512K() const noexcept { return hasFlag(kFlagAvx512K); }
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//! Tests whether the instruction supports AVX512 zeroing {k}{z}.
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inline bool hasAvx512Z() const noexcept { return hasFlag(kFlagAvx512Z); }
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//! Tests whether the instruction supports AVX512 embedded-rounding {er}.
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inline bool hasAvx512ER() const noexcept { return hasFlag(kFlagAvx512ER); }
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//! Tests whether the instruction supports AVX512 suppress-all-exceptions {sae}.
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inline bool hasAvx512SAE() const noexcept { return hasFlag(kFlagAvx512SAE); }
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//! Tests whether the instruction supports AVX512 broadcast (either 32-bit or 64-bit).
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inline bool hasAvx512B() const noexcept { return hasFlag(kFlagAvx512B32 | kFlagAvx512B64); }
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//! Tests whether the instruction supports AVX512 broadcast (32-bit).
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inline bool hasAvx512B32() const noexcept { return hasFlag(kFlagAvx512B32); }
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//! Tests whether the instruction supports AVX512 broadcast (64-bit).
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inline bool hasAvx512B64() const noexcept { return hasFlag(kFlagAvx512B64); }
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//! Gets the control-flow type of the instruction.
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inline uint32_t controlType() const noexcept { return commonInfo().controlType(); }
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inline uint32_t singleRegCase() const noexcept { return commonInfo().singleRegCase(); }
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inline uint32_t signatureIndex() const noexcept { return commonInfo().signatureIndex(); }
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inline uint32_t signatureCount() const noexcept { return commonInfo().signatureCount(); }
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inline const InstSignature* signatureData() const noexcept { return commonInfo().signatureData(); }
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inline const InstSignature* signatureEnd() const noexcept { return commonInfo().signatureEnd(); }
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};
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ASMJIT_VARAPI const InstInfo _instInfoTable[];
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static inline const InstInfo& infoById(uint32_t instId) noexcept {
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ASMJIT_ASSERT(Inst::isDefinedId(instId));
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return _instInfoTable[instId];
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}
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} // {InstDB}
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//! \}
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ASMJIT_END_SUB_NAMESPACE
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#endif // ASMJIT_X86_X86INSTDB_H_INCLUDED
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