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483 lines
21 KiB
483 lines
21 KiB
// AsmJit - Machine code generation for C++
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//
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// * Official AsmJit Home Page: https://asmjit.com
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// * Official Github Repository: https://github.com/asmjit/asmjit
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//
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// Copyright (c) 2008-2020 The AsmJit Authors
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//
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// This software is provided 'as-is', without any express or implied
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// warranty. In no event will the authors be held liable for any damages
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// arising from the use of this software.
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//
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// Permission is granted to anyone to use this software for any purpose,
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// including commercial applications, and to alter it and redistribute it
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// freely, subject to the following restrictions:
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//
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// 1. The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software. If you use this software
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// in a product, an acknowledgment in the product documentation would be
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// appreciated but is not required.
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// 2. Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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// 3. This notice may not be removed or altered from any source distribution.
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#ifndef ASMJIT_X86_X86OPCODE_P_H_INCLUDED
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#define ASMJIT_X86_X86OPCODE_P_H_INCLUDED
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#include "../x86/x86globals.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(x86)
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//! \cond INTERNAL
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//! \addtogroup asmjit_x86
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//! \{
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// ============================================================================
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// [asmjit::x86::Opcode]
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// ============================================================================
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//! Helper class to store and manipulate X86 opcodes.
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//!
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//! The first 8 least significant bits describe the opcode byte as defined in
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//! ISA manuals, all other bits describe other properties like prefixes, see
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//! `Opcode::Bits` for more information.
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struct Opcode {
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uint32_t v;
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//! Describes a meaning of all bits of AsmJit's 32-bit opcode value.
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//!
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//! This schema is AsmJit specific and has been designed to allow encoding of
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//! all X86 instructions available. X86, MMX, and SSE+ instructions always use
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//! `MM` and `PP` fields, which are encoded to corresponding prefixes needed
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//! by X86 or SIMD instructions. AVX+ instructions embed `MMMMM` and `PP` fields
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//! in a VEX prefix, and AVX-512 instructions embed `MM` and `PP` in EVEX prefix.
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//!
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//! The instruction opcode definition uses 1 or 2 bytes as an opcode value. 1
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//! byte is needed by most of the instructions, 2 bytes are only used by legacy
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//! X87-FPU instructions. This means that a second byte is free to by used by
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//! instructions encoded by using VEX and/or EVEX prefix.
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//!
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//! The fields description:
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//!
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//! - `MM` field is used to encode prefixes needed by the instruction or as
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//! a part of VEX/EVEX prefix. Described as `mm` and `mmmmm` in instruction
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//! manuals.
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//!
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//! NOTE: Since `MM` field is defined as `mmmmm` (5 bits), but only 2 least
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//! significant bits are used by VEX and EVEX prefixes, and additional 4th
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//! bit is used by XOP prefix, AsmJit uses the 3rd and 5th bit for it's own
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//! purposes. These bits will probably never be used in future encodings as
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//! AVX512 uses only `000mm` from `mmmmm`.
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//!
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//! - `PP` field is used to encode prefixes needed by the instruction or as a
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//! part of VEX/EVEX prefix. Described as `pp` in instruction manuals.
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//!
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//! - `LL` field is used exclusively by AVX+ and AVX512+ instruction sets. It
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//! describes vector size, which is `L.128` for XMM register, `L.256` for
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//! for YMM register, and `L.512` for ZMM register. The `LL` field is omitted
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//! in case that instruction supports multiple vector lengths, however, if the
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//! instruction requires specific `L` value it must be specified as a part of
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//! the opcode.
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//!
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//! NOTE: `LL` having value `11` is not defined yet.
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//!
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//! - `W` field is the most complicated. It was added by 64-bit architecture
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//! to promote default operation width (instructions that perform 32-bit
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//! operation by default require to override the width to 64-bit explicitly).
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//! There is nothing wrong on this, however, some instructions introduced
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//! implicit `W` override, for example a `cdqe` instruction is basically a
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//! `cwde` instruction with overridden `W` (set to 1). There are some others
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//! in the base X86 instruction set. More recent instruction sets started
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//! using `W` field more often:
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//!
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//! - AVX instructions started using `W` field as an extended opcode for FMA,
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//! GATHER, PERM, and other instructions. It also uses `W` field to override
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//! the default operation width in instructions like `vmovq`.
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//!
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//! - AVX-512 instructions started using `W` field as an extended opcode for
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//! all new instructions. This wouldn't have been an issue if the `W` field
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//! of AVX-512 have matched AVX, but this is not always the case.
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//!
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//! - `O` field is an extended opcode field (3 bits) embedded in ModR/M BYTE.
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//!
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//! - `CDSHL` and `CDTT` fields describe 'compressed-displacement'. `CDSHL` is
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//! defined for each instruction that is AVX-512 encodable (EVEX) and contains
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//! a base N shift (base shift to perform the calculation). The `CDTT` field
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//! is derived from instruction specification and describes additional shift
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//! to calculate the final `CDSHL` that will be used in SIB byte.
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//!
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//! \note Don't reorder any fields here, the shifts and masks were defined
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//! carefully to make encoding of X86 instructions fast, especially to construct
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//! REX, VEX, and EVEX prefixes in the most efficient way. Changing values defined
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//! by these enums many cause AsmJit to emit invalid binary representations of
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//! instructions passed to `x86::Assembler::_emit`.
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enum Bits : uint32_t {
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// MM & VEX & EVEX & XOP
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// ---------------------
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//
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// Two meanings:
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// * Part of a legacy opcode (prefixes emitted before the main opcode byte).
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// * `MMMMM` field in VEX|EVEX|XOP instruction.
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//
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// AVX reserves 5 bits for `MMMMM` field, however AVX instructions only use
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// 2 bits and XOP 3 bits. AVX-512 shrinks `MMMMM` field into `MM` so it's
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// safe to assume that bits [4:2] of `MM` field won't be used in future
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// extensions, which will most probably use EVEX encoding. AsmJit divides
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// MM field into this layout:
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//
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// [1:0] - Used to describe 0F, 0F38 and 0F3A legacy prefix bytes and
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// 2 bits of MM field.
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// [2] - Used to force 3-BYTE VEX prefix, but then cleared to zero before
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// the prefix is emitted. This bit is not used by any instruction
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// so it can be used for any purpose by AsmJit. Also, this bit is
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// used as an extension to `MM` field describing 0F|0F38|0F3A to also
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// describe 0F01 as used by some legacy instructions (instructions
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// not using VEX/EVEX prefix).
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// [3] - Required by XOP instructions, so we use this bit also to indicate
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// that this is a XOP opcode.
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kMM_Shift = 8,
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kMM_Mask = 0x1Fu << kMM_Shift,
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kMM_00 = 0x00u << kMM_Shift,
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kMM_0F = 0x01u << kMM_Shift,
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kMM_0F38 = 0x02u << kMM_Shift,
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kMM_0F3A = 0x03u << kMM_Shift, // Described also as XOP.M3 in AMD manuals.
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kMM_0F01 = 0x04u << kMM_Shift, // AsmJit way to describe 0F01 (never VEX/EVEX).
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// `XOP` field is only used to force XOP prefix instead of VEX3 prefix. We
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// know that only XOP encoding uses bit 0b1000 of MM field and that no VEX
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// and EVEX instruction uses such bit, so we can use this bit to force XOP
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// prefix to be emitted instead of VEX3 prefix. See `x86VEXPrefix` defined
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// in `x86assembler.cpp`.
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kMM_XOP08 = 0x08u << kMM_Shift, // XOP.M8.
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kMM_XOP09 = 0x09u << kMM_Shift, // XOP.M9.
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kMM_XOP0A = 0x0Au << kMM_Shift, // XOP.MA.
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kMM_IsXOP_Shift= kMM_Shift + 3,
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kMM_IsXOP = kMM_XOP08,
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// NOTE: Force VEX3 allows to force to emit VEX3 instead of VEX2 in some
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// cases (similar to forcing REX prefix). Force EVEX will force emitting
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// EVEX prefix instead of VEX2|VEX3. EVEX-only instructions will have
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// ForceEvex always set, however. instructions that can be encoded by
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// either VEX or EVEX prefix should not have ForceEvex set.
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kMM_ForceVex3 = 0x04u << kMM_Shift, // Force 3-BYTE VEX prefix.
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kMM_ForceEvex = 0x10u << kMM_Shift, // Force 4-BYTE EVEX prefix.
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// FPU_2B - Second-Byte of the Opcode used by FPU
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// ----------------------------------------------
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//
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// Second byte opcode. This BYTE is ONLY used by FPU instructions and
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// collides with 3 bits from `MM` and 5 bits from 'CDSHL' and 'CDTT'.
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// It's fine as FPU and AVX512 flags are never used at the same time.
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kFPU_2B_Shift = 10,
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kFPU_2B_Mask = 0xFF << kFPU_2B_Shift,
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// CDSHL & CDTT
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// ------------
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//
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// Compressed displacement bits.
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//
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// Each opcode defines the base size (N) shift:
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// [0]: BYTE (1 byte).
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// [1]: WORD (2 bytes).
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// [2]: DWORD (4 bytes - float/int32).
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// [3]: QWORD (8 bytes - double/int64).
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// [4]: OWORD (16 bytes - used by FV|FVM|M128).
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//
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// Which is then scaled by the instruction's TT (TupleType) into possible:
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// [5]: YWORD (32 bytes)
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// [6]: ZWORD (64 bytes)
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//
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// These bits are then adjusted before calling EmitModSib or EmitModVSib.
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kCDSHL_Shift = 13,
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kCDSHL_Mask = 0x7u << kCDSHL_Shift,
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kCDSHL__ = 0x0u << kCDSHL_Shift, // Base element size not used.
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kCDSHL_0 = 0x0u << kCDSHL_Shift, // N << 0.
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kCDSHL_1 = 0x1u << kCDSHL_Shift, // N << 1.
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kCDSHL_2 = 0x2u << kCDSHL_Shift, // N << 2.
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kCDSHL_3 = 0x3u << kCDSHL_Shift, // N << 3.
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kCDSHL_4 = 0x4u << kCDSHL_Shift, // N << 4.
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kCDSHL_5 = 0x5u << kCDSHL_Shift, // N << 5.
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// Compressed displacement tuple-type (specific to AsmJit).
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//
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// Since we store the base offset independently of CDTT we can simplify the
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// number of 'TUPLE_TYPE' groups significantly and just handle special cases.
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kCDTT_Shift = 16,
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kCDTT_Mask = 0x3u << kCDTT_Shift,
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kCDTT_None = 0x0u << kCDTT_Shift, // Does nothing.
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kCDTT_ByLL = 0x1u << kCDTT_Shift, // Scales by LL (1x 2x 4x).
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kCDTT_T1W = 0x2u << kCDTT_Shift, // Used to add 'W' to the shift.
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kCDTT_DUP = 0x3u << kCDTT_Shift, // Special 'VMOVDDUP' case.
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// Aliases that match names used in instruction manuals.
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kCDTT__ = kCDTT_None,
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kCDTT_FV = kCDTT_ByLL,
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kCDTT_HV = kCDTT_ByLL,
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kCDTT_FVM = kCDTT_ByLL,
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kCDTT_T1S = kCDTT_None,
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kCDTT_T1F = kCDTT_None,
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kCDTT_T1_4X = kCDTT_None,
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kCDTT_T2 = kCDTT_None,
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kCDTT_T4 = kCDTT_None,
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kCDTT_T8 = kCDTT_None,
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kCDTT_HVM = kCDTT_ByLL,
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kCDTT_QVM = kCDTT_ByLL,
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kCDTT_OVM = kCDTT_ByLL,
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kCDTT_128 = kCDTT_None,
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kCDTT_T4X = kCDTT_T1_4X, // Alias to have only 3 letters.
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// `O` Field in ModR/M (??:xxx:???)
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// --------------------------------
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kModO_Shift = 18,
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kModO_Mask = 0x7u << kModO_Shift,
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kModO__ = 0x0u,
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kModO_0 = 0x0u << kModO_Shift,
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kModO_1 = 0x1u << kModO_Shift,
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kModO_2 = 0x2u << kModO_Shift,
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kModO_3 = 0x3u << kModO_Shift,
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kModO_4 = 0x4u << kModO_Shift,
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kModO_5 = 0x5u << kModO_Shift,
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kModO_6 = 0x6u << kModO_Shift,
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kModO_7 = 0x7u << kModO_Shift,
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// `RM` Field in ModR/M (??:???:xxx)
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// ---------------------------------
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//
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// Second data field used by ModR/M byte. This is only used by few
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// instructions that use OPCODE+MOD/RM where both values in Mod/RM
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// are part of the opcode.
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kModRM_Shift = 13,
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kModRM_Mask = 0x7u << kModRM_Shift,
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kModRM__ = 0x0u,
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kModRM_0 = 0x0u << kModRM_Shift,
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kModRM_1 = 0x1u << kModRM_Shift,
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kModRM_2 = 0x2u << kModRM_Shift,
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kModRM_3 = 0x3u << kModRM_Shift,
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kModRM_4 = 0x4u << kModRM_Shift,
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kModRM_5 = 0x5u << kModRM_Shift,
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kModRM_6 = 0x6u << kModRM_Shift,
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kModRM_7 = 0x7u << kModRM_Shift,
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// `PP` Field
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// ----------
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//
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// These fields are stored deliberately right after each other as it makes
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// it easier to construct VEX prefix from the opcode value stored in the
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// instruction database.
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//
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// Two meanings:
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// * "PP" field in AVX/XOP/AVX-512 instruction.
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// * Mandatory Prefix in legacy encoding.
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//
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// AVX reserves 2 bits for `PP` field, but AsmJit extends the storage by 1
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// more bit that is used to emit 9B prefix for some X87-FPU instructions.
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kPP_Shift = 21,
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kPP_VEXMask = 0x03u << kPP_Shift, // PP field mask used by VEX/EVEX.
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kPP_FPUMask = 0x07u << kPP_Shift, // Mask used by EMIT_PP, also includes '0x9B'.
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kPP_00 = 0x00u << kPP_Shift,
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kPP_66 = 0x01u << kPP_Shift,
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kPP_F3 = 0x02u << kPP_Shift,
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kPP_F2 = 0x03u << kPP_Shift,
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kPP_9B = 0x07u << kPP_Shift, // AsmJit specific to emit FPU's '9B' byte.
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// REX|VEX|EVEX B|X|R|W Bits
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// -------------------------
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//
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// NOTE: REX.[B|X|R] are never stored within the opcode itself, they are
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// reserved by AsmJit are are added dynamically to the opcode to represent
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// [REX|VEX|EVEX].[B|X|R] bits. REX.W can be stored in DB as it's sometimes
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// part of the opcode itself.
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// These must be binary compatible with instruction options.
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kREX_Shift = 24,
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kREX_Mask = 0x0Fu << kREX_Shift,
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kB = 0x01u << kREX_Shift, // Never stored in DB, used by encoder.
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kX = 0x02u << kREX_Shift, // Never stored in DB, used by encoder.
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kR = 0x04u << kREX_Shift, // Never stored in DB, used by encoder.
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kW = 0x08u << kREX_Shift,
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kW_Shift = kREX_Shift + 3,
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kW__ = 0u << kW_Shift, // REX.W/VEX.W is unspecified.
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kW_x = 0u << kW_Shift, // REX.W/VEX.W is based on instruction operands.
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kW_I = 0u << kW_Shift, // REX.W/VEX.W is ignored (WIG).
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kW_0 = 0u << kW_Shift, // REX.W/VEX.W is 0 (W0).
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kW_1 = 1u << kW_Shift, // REX.W/VEX.W is 1 (W1).
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// EVEX.W Field
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// ------------
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//
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// `W` field used by EVEX instruction encoding.
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kEvex_W_Shift = 28,
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kEvex_W_Mask = 1u << kEvex_W_Shift,
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kEvex_W__ = 0u << kEvex_W_Shift, // EVEX.W is unspecified (not EVEX instruction).
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kEvex_W_x = 0u << kEvex_W_Shift, // EVEX.W is based on instruction operands.
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kEvex_W_I = 0u << kEvex_W_Shift, // EVEX.W is ignored (WIG).
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kEvex_W_0 = 0u << kEvex_W_Shift, // EVEX.W is 0 (W0).
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kEvex_W_1 = 1u << kEvex_W_Shift, // EVEX.W is 1 (W1).
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// `L` or `LL` field in AVX/XOP/AVX-512
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// ------------------------------------
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//
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// VEX/XOP prefix can only use the first bit `L.128` or `L.256`. EVEX prefix
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// prefix makes it possible to use also `L.512`.
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//
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// If the instruction set manual describes an instruction by `LIG` it means
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// that the `L` field is ignored and AsmJit defaults to `0` in such case.
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kLL_Shift = 29,
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kLL_Mask = 0x3u << kLL_Shift,
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kLL__ = 0x0u << kLL_Shift, // LL is unspecified.
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kLL_x = 0x0u << kLL_Shift, // LL is based on instruction operands.
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kLL_I = 0x0u << kLL_Shift, // LL is ignored (LIG).
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kLL_0 = 0x0u << kLL_Shift, // LL is 0 (L.128).
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kLL_1 = 0x1u << kLL_Shift, // LL is 1 (L.256).
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kLL_2 = 0x2u << kLL_Shift, // LL is 2 (L.512).
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// Opcode Combinations
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// -------------------
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k0 = 0, // '__' (no prefix, used internally).
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k000000 = kPP_00 | kMM_00, // '__' (no prefix, to be the same width as others).
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k000F00 = kPP_00 | kMM_0F, // '0F'
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k000F01 = kPP_00 | kMM_0F01, // '0F01'
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k000F0F = kPP_00 | kMM_0F, // '0F0F' - 3DNOW, equal to 0x0F, must have special encoding to take effect.
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k000F38 = kPP_00 | kMM_0F38, // '0F38'
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k000F3A = kPP_00 | kMM_0F3A, // '0F3A'
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k660000 = kPP_66 | kMM_00, // '66'
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k660F00 = kPP_66 | kMM_0F, // '660F'
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k660F01 = kPP_66 | kMM_0F01, // '660F01'
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k660F38 = kPP_66 | kMM_0F38, // '660F38'
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k660F3A = kPP_66 | kMM_0F3A, // '660F3A'
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kF20000 = kPP_F2 | kMM_00, // 'F2'
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kF20F00 = kPP_F2 | kMM_0F, // 'F20F'
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kF20F01 = kPP_F2 | kMM_0F01, // 'F20F01'
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kF20F38 = kPP_F2 | kMM_0F38, // 'F20F38'
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kF20F3A = kPP_F2 | kMM_0F3A, // 'F20F3A'
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kF30000 = kPP_F3 | kMM_00, // 'F3'
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kF30F00 = kPP_F3 | kMM_0F, // 'F30F'
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kF30F01 = kPP_F3 | kMM_0F01, // 'F30F01'
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kF30F38 = kPP_F3 | kMM_0F38, // 'F30F38'
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kF30F3A = kPP_F3 | kMM_0F3A, // 'F30F3A'
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kFPU_00 = kPP_00 | kMM_00, // '__' (FPU)
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kFPU_9B = kPP_9B | kMM_00, // '9B' (FPU)
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kXOP_M8 = kPP_00 | kMM_XOP08, // 'M8' (XOP)
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kXOP_M9 = kPP_00 | kMM_XOP09, // 'M9' (XOP)
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kXOP_MA = kPP_00 | kMM_XOP0A // 'MA' (XOP)
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};
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// --------------------------------------------------------------------------
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// [Opcode Builder]
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// --------------------------------------------------------------------------
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ASMJIT_INLINE uint32_t get() const noexcept { return v; }
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ASMJIT_INLINE bool hasW() const noexcept { return (v & kW) != 0; }
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ASMJIT_INLINE bool has66h() const noexcept { return (v & kPP_66) != 0; }
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ASMJIT_INLINE Opcode& add(uint32_t x) noexcept { return operator+=(x); }
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ASMJIT_INLINE Opcode& add66h() noexcept { return operator|=(kPP_66); }
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template<typename T>
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ASMJIT_INLINE Opcode& add66hIf(T exp) noexcept { return operator|=(uint32_t(exp) << kPP_Shift); }
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template<typename T>
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ASMJIT_INLINE Opcode& add66hBySize(T size) noexcept { return add66hIf(size == 2); }
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ASMJIT_INLINE Opcode& addW() noexcept { return operator|=(kW); }
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template<typename T>
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ASMJIT_INLINE Opcode& addWIf(T exp) noexcept { return operator|=(uint32_t(exp) << kW_Shift); }
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|
template<typename T>
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ASMJIT_INLINE Opcode& addWBySize(T size) noexcept { return addWIf(size == 8); }
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|
|
|
template<typename T>
|
|
ASMJIT_INLINE Opcode& addPrefixBySize(T size) noexcept {
|
|
static const uint32_t mask[16] = {
|
|
0, // #0
|
|
0, // #1 -> nothing (already handled or not possible)
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|
kPP_66, // #2 -> 66H
|
|
0, // #3
|
|
0, // #4 -> nothing
|
|
0, // #5
|
|
0, // #6
|
|
0, // #7
|
|
kW // #8 -> REX.W
|
|
};
|
|
return operator|=(mask[size & 0xF]);
|
|
}
|
|
|
|
template<typename T>
|
|
ASMJIT_INLINE Opcode& addArithBySize(T size) noexcept {
|
|
static const uint32_t mask[16] = {
|
|
0, // #0
|
|
0, // #1 -> nothing
|
|
1 | kPP_66, // #2 -> NOT_BYTE_OP(1) and 66H
|
|
0, // #3
|
|
1, // #4 -> NOT_BYTE_OP(1)
|
|
0, // #5
|
|
0, // #6
|
|
0, // #7
|
|
1 | kW // #8 -> NOT_BYTE_OP(1) and REX.W
|
|
};
|
|
return operator|=(mask[size & 0xF]);
|
|
}
|
|
|
|
ASMJIT_INLINE Opcode& forceEvex() noexcept { return operator|=(kMM_ForceEvex); }
|
|
template<typename T>
|
|
ASMJIT_INLINE Opcode& forceEvexIf(T exp) noexcept { return operator|=(uint32_t(exp) << Support::constCtz(uint32_t(kMM_ForceEvex))); }
|
|
|
|
//! Extract `O` field (R) from the opcode (specified as /0..7 in instruction manuals).
|
|
ASMJIT_INLINE uint32_t extractModO() const noexcept {
|
|
return (v >> kModO_Shift) & 0x07;
|
|
}
|
|
|
|
//! Extract `RM` field (RM) from the opcode (usually specified as another opcode value).
|
|
ASMJIT_INLINE uint32_t extractModRM() const noexcept {
|
|
return (v >> kModRM_Shift) & 0x07;
|
|
}
|
|
|
|
//! Extract `REX` prefix from opcode combined with `options`.
|
|
ASMJIT_INLINE uint32_t extractRex(uint32_t options) const noexcept {
|
|
// kREX was designed in a way that when shifted there will be no bytes
|
|
// set except REX.[B|X|R|W]. The returned value forms a real REX prefix byte.
|
|
// This case should be unit-tested as well.
|
|
return (v | options) >> kREX_Shift;
|
|
}
|
|
|
|
ASMJIT_INLINE uint32_t extractLLMM(uint32_t options) const noexcept {
|
|
uint32_t x = v & (kLL_Mask | kMM_Mask);
|
|
uint32_t y = options & (Inst::kOptionVex3 | Inst::kOptionEvex);
|
|
return (x | y) >> kMM_Shift;
|
|
}
|
|
|
|
ASMJIT_INLINE Opcode& operator=(uint32_t x) noexcept { v = x; return *this; }
|
|
ASMJIT_INLINE Opcode& operator+=(uint32_t x) noexcept { v += x; return *this; }
|
|
ASMJIT_INLINE Opcode& operator-=(uint32_t x) noexcept { v -= x; return *this; }
|
|
ASMJIT_INLINE Opcode& operator&=(uint32_t x) noexcept { v &= x; return *this; }
|
|
ASMJIT_INLINE Opcode& operator|=(uint32_t x) noexcept { v |= x; return *this; }
|
|
ASMJIT_INLINE Opcode& operator^=(uint32_t x) noexcept { v ^= x; return *this; }
|
|
|
|
ASMJIT_INLINE uint32_t operator&(uint32_t x) const noexcept { return v & x; }
|
|
ASMJIT_INLINE uint32_t operator|(uint32_t x) const noexcept { return v | x; }
|
|
ASMJIT_INLINE uint32_t operator^(uint32_t x) const noexcept { return v ^ x; }
|
|
ASMJIT_INLINE uint32_t operator<<(uint32_t x) const noexcept { return v << x; }
|
|
ASMJIT_INLINE uint32_t operator>>(uint32_t x) const noexcept { return v >> x; }
|
|
};
|
|
|
|
//! \}
|
|
//! \endcond
|
|
|
|
ASMJIT_END_SUB_NAMESPACE
|
|
|
|
#endif // ASMJIT_X86_X86OPCODE_P_H_INCLUDED
|