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225 lines
8.0 KiB
225 lines
8.0 KiB
// AsmJit - Machine code generation for C++
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//
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// * Official AsmJit Home Page: https://asmjit.com
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// * Official Github Repository: https://github.com/asmjit/asmjit
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//
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// Copyright (c) 2008-2020 The AsmJit Authors
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//
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// This software is provided 'as-is', without any express or implied
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// warranty. In no event will the authors be held liable for any damages
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// arising from the use of this software.
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//
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// Permission is granted to anyone to use this software for any purpose,
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// including commercial applications, and to alter it and redistribute it
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// freely, subject to the following restrictions:
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//
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// 1. The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software. If you use this software
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// in a product, an acknowledgment in the product documentation would be
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// appreciated but is not required.
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// 2. Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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// 3. This notice may not be removed or altered from any source distribution.
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#ifndef ASMJIT_CORE_FUNCARGSCONTEXT_P_H_INCLUDED
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#define ASMJIT_CORE_FUNCARGSCONTEXT_P_H_INCLUDED
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#include "../core/archtraits.h"
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#include "../core/environment.h"
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#include "../core/func.h"
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#include "../core/operand.h"
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#include "../core/radefs_p.h"
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#include "../core/support.h"
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ASMJIT_BEGIN_NAMESPACE
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//! \cond INTERNAL
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//! \addtogroup asmjit_core
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//! \{
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// ============================================================================
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// [TODO: Place somewhere else]
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// ============================================================================
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static inline RegInfo getSuitableRegForMemToMemMove(uint32_t arch, uint32_t dstTypeId, uint32_t srcTypeId) noexcept {
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const ArchTraits& archTraits = ArchTraits::byArch(arch);
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uint32_t dstSize = Type::sizeOf(dstTypeId);
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uint32_t srcSize = Type::sizeOf(srcTypeId);
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uint32_t maxSize = Support::max<uint32_t>(dstSize, srcSize);
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uint32_t regSize = Environment::registerSizeFromArch(arch);
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uint32_t signature = 0;
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if (maxSize <= regSize || (Type::isInt(dstTypeId) && Type::isInt(srcTypeId)))
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signature = maxSize <= 4 ? archTraits.regTypeToSignature(BaseReg::kTypeGp32)
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: archTraits.regTypeToSignature(BaseReg::kTypeGp64);
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else if (maxSize <= 8 && archTraits.hasRegType(BaseReg::kTypeVec64))
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signature = archTraits.regTypeToSignature(BaseReg::kTypeVec64);
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else if (maxSize <= 16 && archTraits.hasRegType(BaseReg::kTypeVec128))
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signature = archTraits.regTypeToSignature(BaseReg::kTypeVec128);
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else if (maxSize <= 32 && archTraits.hasRegType(BaseReg::kTypeVec256))
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signature = archTraits.regTypeToSignature(BaseReg::kTypeVec256);
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else if (maxSize <= 64 && archTraits.hasRegType(BaseReg::kTypeVec512))
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signature = archTraits.regTypeToSignature(BaseReg::kTypeVec512);
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return RegInfo { signature };
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}
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// ============================================================================
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// [asmjit::FuncArgsContext]
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// ============================================================================
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class FuncArgsContext {
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public:
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enum VarId : uint32_t {
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kVarIdNone = 0xFF
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};
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//! Contains information about a single argument or SA register that may need shuffling.
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struct Var {
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FuncValue cur;
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FuncValue out;
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inline void init(const FuncValue& cur_, const FuncValue& out_) noexcept {
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cur = cur_;
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out = out_;
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}
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//! Reset the value to its unassigned state.
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inline void reset() noexcept {
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cur.reset();
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out.reset();
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}
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inline bool isDone() const noexcept { return cur.isDone(); }
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inline void markDone() noexcept { cur.addFlags(FuncValue::kFlagIsDone); }
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};
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struct WorkData {
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//! All allocable registers provided by the architecture.
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uint32_t _archRegs;
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//! All registers that can be used by the shuffler.
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uint32_t _workRegs;
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//! Registers used by the shuffler (all).
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uint32_t _usedRegs;
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//! Assigned registers.
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uint32_t _assignedRegs;
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//! Destination registers assigned to arguments or SA.
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uint32_t _dstRegs;
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//! Destination registers that require shuffling.
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uint32_t _dstShuf;
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//! Number of register swaps.
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uint8_t _numSwaps;
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//! Number of stack loads.
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uint8_t _numStackArgs;
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//! Reserved (only used as padding).
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uint8_t _reserved[6];
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//! Physical ID to variable ID mapping.
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uint8_t _physToVarId[32];
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inline void reset() noexcept {
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_archRegs = 0;
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_workRegs = 0;
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_usedRegs = 0;
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_assignedRegs = 0;
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_dstRegs = 0;
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_dstShuf = 0;
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_numSwaps = 0;
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_numStackArgs = 0;
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memset(_reserved, 0, sizeof(_reserved));
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memset(_physToVarId, kVarIdNone, 32);
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}
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inline bool isAssigned(uint32_t regId) const noexcept {
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ASMJIT_ASSERT(regId < 32);
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return Support::bitTest(_assignedRegs, regId);
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}
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inline void assign(uint32_t varId, uint32_t regId) noexcept {
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ASMJIT_ASSERT(!isAssigned(regId));
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ASMJIT_ASSERT(_physToVarId[regId] == kVarIdNone);
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_physToVarId[regId] = uint8_t(varId);
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_assignedRegs ^= Support::bitMask(regId);
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}
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inline void reassign(uint32_t varId, uint32_t newId, uint32_t oldId) noexcept {
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ASMJIT_ASSERT( isAssigned(oldId));
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ASMJIT_ASSERT(!isAssigned(newId));
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ASMJIT_ASSERT(_physToVarId[oldId] == varId);
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ASMJIT_ASSERT(_physToVarId[newId] == kVarIdNone);
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_physToVarId[oldId] = uint8_t(kVarIdNone);
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_physToVarId[newId] = uint8_t(varId);
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_assignedRegs ^= Support::bitMask(newId) ^ Support::bitMask(oldId);
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}
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inline void swap(uint32_t aVarId, uint32_t aRegId, uint32_t bVarId, uint32_t bRegId) noexcept {
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ASMJIT_ASSERT(isAssigned(aRegId));
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ASMJIT_ASSERT(isAssigned(bRegId));
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ASMJIT_ASSERT(_physToVarId[aRegId] == aVarId);
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ASMJIT_ASSERT(_physToVarId[bRegId] == bVarId);
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_physToVarId[aRegId] = uint8_t(bVarId);
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_physToVarId[bRegId] = uint8_t(aVarId);
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}
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inline void unassign(uint32_t varId, uint32_t regId) noexcept {
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ASMJIT_ASSERT(isAssigned(regId));
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ASMJIT_ASSERT(_physToVarId[regId] == varId);
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DebugUtils::unused(varId);
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_physToVarId[regId] = uint8_t(kVarIdNone);
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_assignedRegs ^= Support::bitMask(regId);
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}
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inline uint32_t archRegs() const noexcept { return _archRegs; }
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inline uint32_t workRegs() const noexcept { return _workRegs; }
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inline uint32_t usedRegs() const noexcept { return _usedRegs; }
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inline uint32_t assignedRegs() const noexcept { return _assignedRegs; }
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inline uint32_t dstRegs() const noexcept { return _dstRegs; }
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inline uint32_t availableRegs() const noexcept { return _workRegs & ~_assignedRegs; }
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};
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//! Architecture traits.
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const ArchTraits* _archTraits = nullptr;
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const RAConstraints* _constraints = nullptr;
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//! Architecture identifier.
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uint8_t _arch = 0;
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//! Has arguments passed via stack (SRC).
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bool _hasStackSrc = false;
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//! Has preserved frame-pointer (FP).
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bool _hasPreservedFP = false;
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//! Has arguments assigned to stack (DST).
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uint8_t _stackDstMask = 0;
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//! Register swap groups (bit-mask).
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uint8_t _regSwapsMask = 0;
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uint8_t _saVarId = kVarIdNone;
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uint32_t _varCount = 0;
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WorkData _workData[BaseReg::kGroupVirt];
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Var _vars[Globals::kMaxFuncArgs * Globals::kMaxValuePack + 1];
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FuncArgsContext() noexcept;
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inline const ArchTraits& archTraits() const noexcept { return *_archTraits; }
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inline uint32_t arch() const noexcept { return _arch; }
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inline uint32_t varCount() const noexcept { return _varCount; }
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inline size_t indexOf(const Var* var) const noexcept { return (size_t)(var - _vars); }
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inline Var& var(size_t varId) noexcept { return _vars[varId]; }
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inline const Var& var(size_t varId) const noexcept { return _vars[varId]; }
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Error initWorkData(const FuncFrame& frame, const FuncArgsAssignment& args, const RAConstraints* constraints) noexcept;
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Error markScratchRegs(FuncFrame& frame) noexcept;
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Error markDstRegsDirty(FuncFrame& frame) noexcept;
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Error markStackArgsReg(FuncFrame& frame) noexcept;
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};
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//! \}
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//! \endcond
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ASMJIT_END_NAMESPACE
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#endif // ASMJIT_CORE_FUNCARGSCONTEXT_P_H_INCLUDED
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