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75 lines
2.8 KiB
75 lines
2.8 KiB
4 years ago
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/** @file
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This file contains definitions for the SPD fields on an SDRAM.
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Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _SDRAM_SPD_H_
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#define _SDRAM_SPD_H_
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#include <IndustryStandard/SdramSpdDdr3.h>
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#include <IndustryStandard/SdramSpdDdr4.h>
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#include <IndustryStandard/SdramSpdLpDdr.h>
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//
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// SDRAM SPD field definitions
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//
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#define SPD_MEMORY_TYPE 2
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#define SPD_SDRAM_ROW_ADDR 3
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#define SPD_SDRAM_COL_ADDR 4
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#define SPD_SDRAM_MODULE_ROWS 5
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#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
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#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
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#define SPD_SDRAM_ECC_SUPPORT 11
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#define SPD_SDRAM_REFRESH 12
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#define SPD_SDRAM_WIDTH 13
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#define SPD_SDRAM_ERROR_WIDTH 14
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#define SPD_SDRAM_BURST_LENGTH 16
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#define SPD_SDRAM_NO_OF_BANKS 17
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#define SPD_SDRAM_CAS_LATENCY 18
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#define SPD_SDRAM_MODULE_ATTR 21
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#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency
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#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency
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#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency
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#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency
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#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency
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#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency
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#define SPD_SDRAM_MIN_PRECHARGE 27
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#define SPD_SDRAM_ACTIVE_MIN 28
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#define SPD_SDRAM_RAS_CAS 29
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#define SPD_SDRAM_RAS_PULSE 30
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#define SPD_SDRAM_DENSITY 31
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//
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// Memory Type Definitions
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//
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#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory
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#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory
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#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory
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#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory
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#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory
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#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory
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#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory
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//
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// ECC Type Definitions
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//
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#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking
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#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking
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#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only
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//
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// Module Attributes (Bit positions)
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//
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#define SPD_BUFFERED 0x01
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#define SPD_REGISTERED 0x02
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#endif
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