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285 lines
9.5 KiB
285 lines
9.5 KiB
//
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// Copyright (c) 2012 - 2016, Linaro Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the Linaro nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Copyright (c) 2015 ARM Ltd
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3. The name of the company may not be used to endorse or promote
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// products derived from this software without specific prior written
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// permission.
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//
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// THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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// IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Assumptions:
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//
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// ARMv8-a, AArch64, unaligned accesses.
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//
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//
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#define dstin x0
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#define src x1
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#define count x2
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#define dst x3
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#define srcend x4
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#define dstend x5
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#define A_l x6
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#define A_lw w6
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#define A_h x7
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#define A_hw w7
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#define B_l x8
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#define B_lw w8
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#define B_h x9
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#define C_l x10
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#define C_h x11
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#define D_l x12
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#define D_h x13
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#define E_l x14
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#define E_h x15
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#define F_l srcend
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#define F_h dst
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#define tmp1 x9
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#define tmp2 x3
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#define L(l) .L ## l
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// Copies are split into 3 main cases: small copies of up to 16 bytes,
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// medium copies of 17..96 bytes which are fully unrolled. Large copies
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// of more than 96 bytes align the destination and use an unrolled loop
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// processing 64 bytes per iteration.
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// Small and medium copies read all data before writing, allowing any
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// kind of overlap, and memmove tailcalls memcpy for these cases as
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// well as non-overlapping copies.
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__memcpy:
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prfm PLDL1KEEP, [src]
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add srcend, src, count
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add dstend, dstin, count
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cmp count, 16
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b.ls L(copy16)
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cmp count, 96
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b.hi L(copy_long)
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// Medium copies: 17..96 bytes.
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sub tmp1, count, 1
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ldp A_l, A_h, [src]
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tbnz tmp1, 6, L(copy96)
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ldp D_l, D_h, [srcend, -16]
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tbz tmp1, 5, 1f
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ldp B_l, B_h, [src, 16]
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ldp C_l, C_h, [srcend, -32]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstend, -32]
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1:
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stp A_l, A_h, [dstin]
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stp D_l, D_h, [dstend, -16]
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ret
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.p2align 4
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// Small copies: 0..16 bytes.
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L(copy16):
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cmp count, 8
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b.lo 1f
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ldr A_l, [src]
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ldr A_h, [srcend, -8]
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str A_l, [dstin]
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str A_h, [dstend, -8]
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ret
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.p2align 4
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1:
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tbz count, 2, 1f
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ldr A_lw, [src]
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ldr A_hw, [srcend, -4]
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str A_lw, [dstin]
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str A_hw, [dstend, -4]
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ret
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// Copy 0..3 bytes. Use a branchless sequence that copies the same
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// byte 3 times if count==1, or the 2nd byte twice if count==2.
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1:
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cbz count, 2f
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lsr tmp1, count, 1
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ldrb A_lw, [src]
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ldrb A_hw, [srcend, -1]
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ldrb B_lw, [src, tmp1]
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strb A_lw, [dstin]
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strb B_lw, [dstin, tmp1]
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strb A_hw, [dstend, -1]
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2: ret
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.p2align 4
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// Copy 64..96 bytes. Copy 64 bytes from the start and
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// 32 bytes from the end.
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L(copy96):
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ldp B_l, B_h, [src, 16]
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ldp C_l, C_h, [src, 32]
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ldp D_l, D_h, [src, 48]
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ldp E_l, E_h, [srcend, -32]
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ldp F_l, F_h, [srcend, -16]
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stp A_l, A_h, [dstin]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstin, 32]
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stp D_l, D_h, [dstin, 48]
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stp E_l, E_h, [dstend, -32]
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stp F_l, F_h, [dstend, -16]
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ret
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// Align DST to 16 byte alignment so that we don't cross cache line
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// boundaries on both loads and stores. There are at least 96 bytes
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// to copy, so copy 16 bytes unaligned and then align. The loop
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// copies 64 bytes per iteration and prefetches one iteration ahead.
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.p2align 4
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L(copy_long):
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and tmp1, dstin, 15
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bic dst, dstin, 15
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ldp D_l, D_h, [src]
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sub src, src, tmp1
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add count, count, tmp1 // Count is now 16 too large.
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ldp A_l, A_h, [src, 16]
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stp D_l, D_h, [dstin]
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ldp B_l, B_h, [src, 32]
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ldp C_l, C_h, [src, 48]
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ldp D_l, D_h, [src, 64]!
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subs count, count, 128 + 16 // Test and readjust count.
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b.ls 2f
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1:
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stp A_l, A_h, [dst, 16]
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ldp A_l, A_h, [src, 16]
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stp B_l, B_h, [dst, 32]
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ldp B_l, B_h, [src, 32]
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stp C_l, C_h, [dst, 48]
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ldp C_l, C_h, [src, 48]
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stp D_l, D_h, [dst, 64]!
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ldp D_l, D_h, [src, 64]!
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subs count, count, 64
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b.hi 1b
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// Write the last full set of 64 bytes. The remainder is at most 64
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// bytes, so it is safe to always copy 64 bytes from the end even if
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// there is just 1 byte left.
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2:
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ldp E_l, E_h, [srcend, -64]
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stp A_l, A_h, [dst, 16]
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ldp A_l, A_h, [srcend, -48]
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stp B_l, B_h, [dst, 32]
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ldp B_l, B_h, [srcend, -32]
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stp C_l, C_h, [dst, 48]
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ldp C_l, C_h, [srcend, -16]
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stp D_l, D_h, [dst, 64]
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stp E_l, E_h, [dstend, -64]
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stp A_l, A_h, [dstend, -48]
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stp B_l, B_h, [dstend, -32]
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stp C_l, C_h, [dstend, -16]
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ret
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//
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// All memmoves up to 96 bytes are done by memcpy as it supports overlaps.
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// Larger backwards copies are also handled by memcpy. The only remaining
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// case is forward large copies. The destination is aligned, and an
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// unrolled loop processes 64 bytes per iteration.
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//
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ASM_GLOBAL ASM_PFX(InternalMemCopyMem)
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ASM_PFX(InternalMemCopyMem):
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sub tmp2, dstin, src
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cmp count, 96
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ccmp tmp2, count, 2, hi
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b.hs __memcpy
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cbz tmp2, 3f
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add dstend, dstin, count
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add srcend, src, count
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// Align dstend to 16 byte alignment so that we don't cross cache line
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// boundaries on both loads and stores. There are at least 96 bytes
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// to copy, so copy 16 bytes unaligned and then align. The loop
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// copies 64 bytes per iteration and prefetches one iteration ahead.
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and tmp2, dstend, 15
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ldp D_l, D_h, [srcend, -16]
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sub srcend, srcend, tmp2
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sub count, count, tmp2
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ldp A_l, A_h, [srcend, -16]
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stp D_l, D_h, [dstend, -16]
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ldp B_l, B_h, [srcend, -32]
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ldp C_l, C_h, [srcend, -48]
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ldp D_l, D_h, [srcend, -64]!
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sub dstend, dstend, tmp2
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subs count, count, 128
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b.ls 2f
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nop
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1:
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stp A_l, A_h, [dstend, -16]
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ldp A_l, A_h, [srcend, -16]
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stp B_l, B_h, [dstend, -32]
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ldp B_l, B_h, [srcend, -32]
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stp C_l, C_h, [dstend, -48]
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ldp C_l, C_h, [srcend, -48]
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stp D_l, D_h, [dstend, -64]!
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ldp D_l, D_h, [srcend, -64]!
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subs count, count, 64
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b.hi 1b
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// Write the last full set of 64 bytes. The remainder is at most 64
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// bytes, so it is safe to always copy 64 bytes from the start even if
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// there is just 1 byte left.
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2:
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ldp E_l, E_h, [src, 48]
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stp A_l, A_h, [dstend, -16]
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ldp A_l, A_h, [src, 32]
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stp B_l, B_h, [dstend, -32]
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ldp B_l, B_h, [src, 16]
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stp C_l, C_h, [dstend, -48]
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ldp C_l, C_h, [src]
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stp D_l, D_h, [dstend, -64]
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stp E_l, E_h, [dstin, 48]
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stp A_l, A_h, [dstin, 32]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstin]
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3: ret
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