From 23eb8b5f138a34bcec6f243b6824841b9a247eda Mon Sep 17 00:00:00 2001
From: _xeroxz <xerox@back.engineering>
Date: Sat, 6 Feb 2021 02:54:35 +0000
Subject: [PATCH] Update VMCS-GUEST.md

---
 VMCS-GUEST.md | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/VMCS-GUEST.md b/VMCS-GUEST.md
index ef660f5..330153c 100644
--- a/VMCS-GUEST.md
+++ b/VMCS-GUEST.md
@@ -8,7 +8,9 @@ Processors: (two xeon cpus)
 
 # VMCS - Guest Fields
 
-#### Control Registers
+#### 26.3.1.1 Checks on Guest Control Registers, Debug Registers, and MSRs
+
+##### Checks on Guest Control Registers
 
 * The CR0 field must not set any bit to a value not supported in VMX operation (see Section 23.8). The following
 are exceptions:
@@ -30,8 +32,20 @@ must be 0.
     - The CR3 field must be such that bits 63:52 and bits in the range 51:32 beyond the processor’s physicaladdress
 width are 0. :white_check_mark:
 
+* The CR4 field must not set any bit to a value not supported in VMX operation (see Section 23.8). :white_check_mark:
+
 ```
 guest cr0: 0x0000000080050033 0b1000 0000 0000 0101 0000 0000 0011 0011
 guest cr3: 0x00000000001AD000
 guest cr4: 0x00000000000026F8 0b0010 0110 1111 1000
-```
\ No newline at end of file
+```
+
+##### Checks on Guest MSRs
+
+* If the “load debug controls” VM-entry control is 1, bits reserved in the IA32_DEBUGCTL MSR must be 0 in the
+field for that register. The first processors to support the virtual-machine extensions supported only the 1-
+setting of this control and thus performed this check unconditionally.
+
+
+
+#### 26.3.1.2 Checks on Guest Segment Registers
\ No newline at end of file