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_xeroxz
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4 years ago | |
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64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf | 4 years ago | |
README.md | 4 years ago | |
VMCS-CONTROLS.md | 4 years ago | |
VMCS-GUEST.md | 4 years ago | |
bluepill.sln | 4 years ago | |
bluepill.vcxproj | 4 years ago | |
bluepill.vcxproj.filters | 4 years ago | |
bluepill.vcxproj.user | 4 years ago | |
entry.cpp | 4 years ago | |
exit_handler.cpp | 4 years ago | |
hv_types.hpp | 4 years ago | |
ia32.hpp | 4 years ago | |
segment.cpp | 4 years ago | |
segment_intrin.asm | 4 years ago | |
segment_intrin.h | 4 years ago | |
vmcs.cpp | 4 years ago | |
vmcs.hpp | 4 years ago | |
vmxexit_handler.asm | 4 years ago | |
vmxexit_handler.h | 4 years ago | |
vmxlaunch.cpp | 4 years ago | |
vmxlaunch.hpp | 4 years ago | |
vmxon.cpp | 4 years ago | |
vmxon.hpp | 4 years ago |
README.md
Figure 1. First ever vmexit...
Bluepill
Bluepill is an Intel type-2 research hypervisor written with no access to github.com. This project is purely for educational purposes and is designed to run on Windows 10 systems. This project uses WDK and thus Windows Kernel functions to facilitate vmxlaunch.
VMCS
This section of the readme just contains notes and a list of things I stumbled on and took me a while to figure out and fix.
VMCS Controls
- One of the mistakes I made early on was setting bits high after applying high/low MSR values. For example my xeons dont support Intel Processor Trace (Intel PT) and I was setting
entry_ctls.conceal_vmx_from_pt = true
after applying the MSR high/low masks. This caused vmxerror #7 (invalid vmcs controls). Now i set the bit high before i apply the high/low bit mask so if my hypervisor runs on a cpu that has Intel PT support it will be concealed from Intel PT. - My xeons also dont support xsave/xrstor and I was setting enable_xsave in secondary processor based vmexit controls after applying
IA32_VMX_PROCBASED_CTLS2
high/low bitmask. Which caused vmxerror #7 (invalid vmcs controls).
Dump of VMCS control fields can be found here. This is not required, but for learning its nice to see exactly what the MSR masks are, and what VMCS field's are enabled after you apply high/low bit masks.