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452 lines
13 KiB
452 lines
13 KiB
3 years ago
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|*Target Register Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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enum {
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SP_NoRegister,
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SP_ICC = 1,
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SP_Y = 2,
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SP_D0 = 3,
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SP_D1 = 4,
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SP_D2 = 5,
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SP_D3 = 6,
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SP_D4 = 7,
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SP_D5 = 8,
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SP_D6 = 9,
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SP_D7 = 10,
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SP_D8 = 11,
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SP_D9 = 12,
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SP_D10 = 13,
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SP_D11 = 14,
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SP_D12 = 15,
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SP_D13 = 16,
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SP_D14 = 17,
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SP_D15 = 18,
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SP_D16 = 19,
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SP_D17 = 20,
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SP_D18 = 21,
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SP_D19 = 22,
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SP_D20 = 23,
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SP_D21 = 24,
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SP_D22 = 25,
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SP_D23 = 26,
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SP_D24 = 27,
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SP_D25 = 28,
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SP_D26 = 29,
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SP_D27 = 30,
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SP_D28 = 31,
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SP_D29 = 32,
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SP_D30 = 33,
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SP_D31 = 34,
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SP_F0 = 35,
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SP_F1 = 36,
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SP_F2 = 37,
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SP_F3 = 38,
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SP_F4 = 39,
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SP_F5 = 40,
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SP_F6 = 41,
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SP_F7 = 42,
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SP_F8 = 43,
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SP_F9 = 44,
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SP_F10 = 45,
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SP_F11 = 46,
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SP_F12 = 47,
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SP_F13 = 48,
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SP_F14 = 49,
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SP_F15 = 50,
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SP_F16 = 51,
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SP_F17 = 52,
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SP_F18 = 53,
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SP_F19 = 54,
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SP_F20 = 55,
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SP_F21 = 56,
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SP_F22 = 57,
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SP_F23 = 58,
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SP_F24 = 59,
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SP_F25 = 60,
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SP_F26 = 61,
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SP_F27 = 62,
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SP_F28 = 63,
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SP_F29 = 64,
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SP_F30 = 65,
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SP_F31 = 66,
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SP_FCC0 = 67,
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SP_FCC1 = 68,
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SP_FCC2 = 69,
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SP_FCC3 = 70,
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SP_G0 = 71,
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SP_G1 = 72,
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SP_G2 = 73,
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SP_G3 = 74,
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SP_G4 = 75,
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SP_G5 = 76,
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SP_G6 = 77,
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SP_G7 = 78,
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SP_I0 = 79,
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SP_I1 = 80,
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SP_I2 = 81,
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SP_I3 = 82,
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SP_I4 = 83,
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SP_I5 = 84,
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SP_I6 = 85,
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SP_I7 = 86,
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SP_L0 = 87,
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SP_L1 = 88,
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SP_L2 = 89,
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SP_L3 = 90,
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SP_L4 = 91,
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SP_L5 = 92,
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SP_L6 = 93,
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SP_L7 = 94,
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SP_O0 = 95,
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SP_O1 = 96,
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SP_O2 = 97,
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SP_O3 = 98,
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SP_O4 = 99,
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SP_O5 = 100,
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SP_O6 = 101,
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SP_O7 = 102,
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SP_Q0 = 103,
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SP_Q1 = 104,
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SP_Q2 = 105,
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SP_Q3 = 106,
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SP_Q4 = 107,
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SP_Q5 = 108,
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SP_Q6 = 109,
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SP_Q7 = 110,
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SP_Q8 = 111,
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SP_Q9 = 112,
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SP_Q10 = 113,
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SP_Q11 = 114,
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SP_Q12 = 115,
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SP_Q13 = 116,
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SP_Q14 = 117,
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SP_Q15 = 118,
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SP_NUM_TARGET_REGS // 119
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};
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// Register classes
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enum {
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SP_FCCRegsRegClassID = 0,
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SP_FPRegsRegClassID = 1,
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SP_IntRegsRegClassID = 2,
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SP_DFPRegsRegClassID = 3,
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SP_I64RegsRegClassID = 4,
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SP_DFPRegs_with_sub_evenRegClassID = 5,
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SP_QFPRegsRegClassID = 6,
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SP_QFPRegs_with_sub_evenRegClassID = 7
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};
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|*MC Register Information *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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static const MCPhysReg SparcRegDiffLists[] = {
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/* 0 */ 65126, 1, 1, 1, 0,
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/* 5 */ 32, 1, 0,
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/* 8 */ 65436, 32, 1, 65504, 33, 1, 0,
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/* 15 */ 34, 1, 0,
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/* 18 */ 65437, 34, 1, 65502, 35, 1, 0,
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/* 25 */ 36, 1, 0,
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/* 28 */ 65438, 36, 1, 65500, 37, 1, 0,
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/* 35 */ 38, 1, 0,
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/* 38 */ 65439, 38, 1, 65498, 39, 1, 0,
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/* 45 */ 40, 1, 0,
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/* 48 */ 65440, 40, 1, 65496, 41, 1, 0,
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/* 55 */ 42, 1, 0,
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/* 58 */ 65441, 42, 1, 65494, 43, 1, 0,
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/* 65 */ 44, 1, 0,
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/* 68 */ 65442, 44, 1, 65492, 45, 1, 0,
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/* 75 */ 46, 1, 0,
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/* 78 */ 65443, 46, 1, 65490, 47, 1, 0,
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/* 85 */ 65348, 1, 0,
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/* 88 */ 65444, 1, 0,
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/* 91 */ 65445, 1, 0,
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/* 94 */ 65446, 1, 0,
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/* 97 */ 65447, 1, 0,
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/* 100 */ 65448, 1, 0,
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/* 103 */ 65449, 1, 0,
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/* 106 */ 65450, 1, 0,
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/* 109 */ 65451, 1, 0,
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/* 112 */ 65532, 1, 0,
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/* 115 */ 15, 0,
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/* 117 */ 84, 0,
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/* 119 */ 85, 0,
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/* 121 */ 86, 0,
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/* 123 */ 87, 0,
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/* 125 */ 88, 0,
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/* 127 */ 89, 0,
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/* 129 */ 90, 0,
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/* 131 */ 91, 0,
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/* 133 */ 65488, 92, 0,
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/* 136 */ 65489, 92, 0,
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/* 139 */ 65489, 93, 0,
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/* 142 */ 65490, 93, 0,
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/* 145 */ 65491, 93, 0,
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/* 148 */ 65491, 94, 0,
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/* 151 */ 65492, 94, 0,
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/* 154 */ 65493, 94, 0,
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/* 157 */ 65493, 95, 0,
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/* 160 */ 65494, 95, 0,
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/* 163 */ 65495, 95, 0,
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/* 166 */ 65495, 96, 0,
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/* 169 */ 65496, 96, 0,
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/* 172 */ 65497, 96, 0,
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/* 175 */ 65497, 97, 0,
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/* 178 */ 65498, 97, 0,
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/* 181 */ 65499, 97, 0,
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/* 184 */ 65499, 98, 0,
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/* 187 */ 65500, 98, 0,
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/* 190 */ 65501, 98, 0,
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/* 193 */ 65501, 99, 0,
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/* 196 */ 65502, 99, 0,
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/* 199 */ 65503, 99, 0,
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/* 202 */ 65503, 100, 0,
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/* 205 */ 65504, 100, 0,
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/* 208 */ 65503, 0,
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/* 210 */ 65519, 0,
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/* 212 */ 65535, 0,
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};
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static const uint16_t SparcSubRegIdxLists[] = {
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/* 0 */ 1, 3, 0,
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/* 3 */ 2, 4, 0,
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/* 6 */ 2, 1, 3, 4, 5, 6, 0,
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};
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static MCRegisterDesc SparcRegDesc[] = { // Descriptors
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{ 3, 0, 0, 0, 0, 0 },
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{ 406, 4, 4, 2, 3393, 0 },
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{ 410, 4, 4, 2, 3393, 0 },
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{ 33, 5, 203, 0, 1794, 2 },
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{ 87, 12, 194, 0, 1794, 2 },
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{ 133, 15, 194, 0, 1794, 2 },
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{ 179, 22, 185, 0, 1794, 2 },
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{ 220, 25, 185, 0, 1794, 2 },
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{ 261, 32, 176, 0, 1794, 2 },
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{ 298, 35, 176, 0, 1794, 2 },
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{ 335, 42, 167, 0, 1794, 2 },
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{ 372, 45, 167, 0, 1794, 2 },
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{ 397, 52, 158, 0, 1794, 2 },
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{ 0, 55, 158, 0, 1794, 2 },
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{ 54, 62, 149, 0, 1794, 2 },
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{ 108, 65, 149, 0, 1794, 2 },
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{ 154, 72, 140, 0, 1794, 2 },
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{ 200, 75, 140, 0, 1794, 2 },
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{ 241, 82, 134, 0, 1794, 2 },
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{ 282, 4, 134, 2, 1841, 0 },
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{ 319, 4, 131, 2, 1841, 0 },
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{ 356, 4, 131, 2, 1841, 0 },
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{ 381, 4, 129, 2, 1841, 0 },
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{ 12, 4, 129, 2, 1841, 0 },
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{ 66, 4, 127, 2, 1841, 0 },
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{ 120, 4, 127, 2, 1841, 0 },
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{ 166, 4, 125, 2, 1841, 0 },
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{ 212, 4, 125, 2, 1841, 0 },
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{ 253, 4, 123, 2, 1841, 0 },
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{ 290, 4, 123, 2, 1841, 0 },
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{ 327, 4, 121, 2, 1841, 0 },
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{ 364, 4, 121, 2, 1841, 0 },
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{ 389, 4, 119, 2, 1841, 0 },
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{ 20, 4, 119, 2, 1841, 0 },
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{ 74, 4, 117, 2, 1841, 0 },
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{ 36, 4, 205, 2, 3329, 0 },
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{ 90, 4, 202, 2, 3329, 0 },
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{ 136, 4, 199, 2, 3329, 0 },
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{ 182, 4, 196, 2, 3329, 0 },
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{ 223, 4, 196, 2, 3329, 0 },
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{ 264, 4, 193, 2, 3329, 0 },
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{ 301, 4, 190, 2, 3329, 0 },
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{ 338, 4, 187, 2, 3329, 0 },
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{ 375, 4, 187, 2, 3329, 0 },
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{ 400, 4, 184, 2, 3329, 0 },
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{ 4, 4, 181, 2, 3329, 0 },
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{ 58, 4, 178, 2, 3329, 0 },
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{ 112, 4, 178, 2, 3329, 0 },
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{ 158, 4, 175, 2, 3329, 0 },
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{ 204, 4, 172, 2, 3329, 0 },
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{ 245, 4, 169, 2, 3329, 0 },
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{ 286, 4, 169, 2, 3329, 0 },
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{ 323, 4, 166, 2, 3329, 0 },
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{ 360, 4, 163, 2, 3329, 0 },
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{ 385, 4, 160, 2, 3329, 0 },
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{ 16, 4, 160, 2, 3329, 0 },
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{ 70, 4, 157, 2, 3329, 0 },
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{ 124, 4, 154, 2, 3329, 0 },
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{ 170, 4, 151, 2, 3329, 0 },
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{ 216, 4, 151, 2, 3329, 0 },
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{ 257, 4, 148, 2, 3329, 0 },
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{ 294, 4, 145, 2, 3329, 0 },
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{ 331, 4, 142, 2, 3329, 0 },
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{ 368, 4, 142, 2, 3329, 0 },
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{ 393, 4, 139, 2, 3329, 0 },
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{ 24, 4, 136, 2, 3329, 0 },
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{ 78, 4, 133, 2, 3329, 0 },
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{ 28, 4, 4, 2, 3361, 0 },
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{ 82, 4, 4, 2, 3361, 0 },
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{ 128, 4, 4, 2, 3361, 0 },
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{ 174, 4, 4, 2, 3361, 0 },
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{ 39, 4, 4, 2, 3361, 0 },
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{ 93, 4, 4, 2, 3361, 0 },
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{ 139, 4, 4, 2, 3361, 0 },
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{ 185, 4, 4, 2, 3361, 0 },
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{ 226, 4, 4, 2, 3361, 0 },
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{ 267, 4, 4, 2, 3361, 0 },
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{ 304, 4, 4, 2, 3361, 0 },
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{ 341, 4, 4, 2, 3361, 0 },
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{ 42, 4, 4, 2, 3361, 0 },
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{ 96, 4, 4, 2, 3361, 0 },
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{ 142, 4, 4, 2, 3361, 0 },
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{ 188, 4, 4, 2, 3361, 0 },
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{ 229, 4, 4, 2, 3361, 0 },
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{ 270, 4, 4, 2, 3361, 0 },
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{ 307, 4, 4, 2, 3361, 0 },
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{ 344, 4, 4, 2, 3361, 0 },
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{ 45, 4, 4, 2, 3361, 0 },
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{ 99, 4, 4, 2, 3361, 0 },
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{ 145, 4, 4, 2, 3361, 0 },
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{ 191, 4, 4, 2, 3361, 0 },
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{ 232, 4, 4, 2, 3361, 0 },
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{ 273, 4, 4, 2, 3361, 0 },
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{ 310, 4, 4, 2, 3361, 0 },
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{ 347, 4, 4, 2, 3361, 0 },
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{ 48, 4, 4, 2, 3361, 0 },
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{ 102, 4, 4, 2, 3361, 0 },
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{ 148, 4, 4, 2, 3361, 0 },
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{ 194, 4, 4, 2, 3361, 0 },
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{ 235, 4, 4, 2, 3361, 0 },
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{ 276, 4, 4, 2, 3361, 0 },
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{ 313, 4, 4, 2, 3361, 0 },
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{ 350, 4, 4, 2, 3361, 0 },
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{ 51, 8, 4, 6, 4, 5 },
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|
|
{ 105, 18, 4, 6, 4, 5 },
|
||
|
|
{ 151, 28, 4, 6, 4, 5 },
|
||
|
|
{ 197, 38, 4, 6, 4, 5 },
|
||
|
|
{ 238, 48, 4, 6, 4, 5 },
|
||
|
|
{ 279, 58, 4, 6, 4, 5 },
|
||
|
|
{ 316, 68, 4, 6, 4, 5 },
|
||
|
|
{ 353, 78, 4, 6, 4, 5 },
|
||
|
|
{ 378, 88, 4, 3, 1362, 10 },
|
||
|
|
{ 403, 91, 4, 3, 1362, 10 },
|
||
|
|
{ 8, 94, 4, 3, 1362, 10 },
|
||
|
|
{ 62, 97, 4, 3, 1362, 10 },
|
||
|
|
{ 116, 100, 4, 3, 1362, 10 },
|
||
|
|
{ 162, 103, 4, 3, 1362, 10 },
|
||
|
|
{ 208, 106, 4, 3, 1362, 10 },
|
||
|
|
{ 249, 109, 4, 3, 1362, 10 },
|
||
|
|
};
|
||
|
|
|
||
|
|
// FCCRegs Register Class...
|
||
|
|
static const MCPhysReg FCCRegs[] = {
|
||
|
|
SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3,
|
||
|
|
};
|
||
|
|
|
||
|
|
// FCCRegs Bit set.
|
||
|
|
static const uint8_t FCCRegsBits[] = {
|
||
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
||
|
|
};
|
||
|
|
|
||
|
|
// FPRegs Register Class...
|
||
|
|
static const MCPhysReg FPRegs[] = {
|
||
|
|
SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31,
|
||
|
|
};
|
||
|
|
|
||
|
|
// FPRegs Bit set.
|
||
|
|
static const uint8_t FPRegsBits[] = {
|
||
|
|
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
|
};
|
||
|
|
|
||
|
|
// IntRegs Register Class...
|
||
|
|
static const MCPhysReg IntRegs[] = {
|
||
|
|
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
|
||
|
|
};
|
||
|
|
|
||
|
|
// IntRegs Bit set.
|
||
|
|
static const uint8_t IntRegsBits[] = {
|
||
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
|
||
|
|
};
|
||
|
|
|
||
|
|
// DFPRegs Register Class...
|
||
|
|
static const MCPhysReg DFPRegs[] = {
|
||
|
|
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31,
|
||
|
|
};
|
||
|
|
|
||
|
|
// DFPRegs Bit set.
|
||
|
|
static const uint8_t DFPRegsBits[] = {
|
||
|
|
0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
|
};
|
||
|
|
|
||
|
|
// I64Regs Register Class...
|
||
|
|
static const MCPhysReg I64Regs[] = {
|
||
|
|
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
|
||
|
|
};
|
||
|
|
|
||
|
|
// I64Regs Bit set.
|
||
|
|
static const uint8_t I64RegsBits[] = {
|
||
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
|
||
|
|
};
|
||
|
|
|
||
|
|
// DFPRegs_with_sub_even Register Class...
|
||
|
|
static const MCPhysReg DFPRegs_with_sub_even[] = {
|
||
|
|
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15,
|
||
|
|
};
|
||
|
|
|
||
|
|
// DFPRegs_with_sub_even Bit set.
|
||
|
|
static const uint8_t DFPRegs_with_sub_evenBits[] = {
|
||
|
|
0xf8, 0xff, 0x07,
|
||
|
|
};
|
||
|
|
|
||
|
|
// QFPRegs Register Class...
|
||
|
|
static const MCPhysReg QFPRegs[] = {
|
||
|
|
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15,
|
||
|
|
};
|
||
|
|
|
||
|
|
// QFPRegs Bit set.
|
||
|
|
static const uint8_t QFPRegsBits[] = {
|
||
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
|
||
|
|
};
|
||
|
|
|
||
|
|
// QFPRegs_with_sub_even Register Class...
|
||
|
|
static const MCPhysReg QFPRegs_with_sub_even[] = {
|
||
|
|
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7,
|
||
|
|
};
|
||
|
|
|
||
|
|
// QFPRegs_with_sub_even Bit set.
|
||
|
|
static const uint8_t QFPRegs_with_sub_evenBits[] = {
|
||
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
|
||
|
|
};
|
||
|
|
|
||
|
|
static MCRegisterClass SparcMCRegisterClasses[] = {
|
||
|
|
{ FCCRegs, FCCRegsBits, 52, 4, sizeof(FCCRegsBits), SP_FCCRegsRegClassID, 0, 0, 1, 1 },
|
||
|
|
{ FPRegs, FPRegsBits, 61, 32, sizeof(FPRegsBits), SP_FPRegsRegClassID, 4, 4, 1, 1 },
|
||
|
|
{ IntRegs, IntRegsBits, 76, 32, sizeof(IntRegsBits), SP_IntRegsRegClassID, 4, 4, 1, 1 },
|
||
|
|
{ DFPRegs, DFPRegsBits, 60, 32, sizeof(DFPRegsBits), SP_DFPRegsRegClassID, 8, 8, 1, 1 },
|
||
|
|
{ I64Regs, I64RegsBits, 44, 32, sizeof(I64RegsBits), SP_I64RegsRegClassID, 8, 8, 1, 1 },
|
||
|
|
{ DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, 0, 16, sizeof(DFPRegs_with_sub_evenBits), SP_DFPRegs_with_sub_evenRegClassID, 8, 8, 1, 1 },
|
||
|
|
{ QFPRegs, QFPRegsBits, 68, 16, sizeof(QFPRegsBits), SP_QFPRegsRegClassID, 16, 16, 1, 1 },
|
||
|
|
{ QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, 22, 8, sizeof(QFPRegs_with_sub_evenBits), SP_QFPRegs_with_sub_evenRegClassID, 16, 16, 1, 1 },
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif // GET_REGINFO_MC_DESC
|