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299 lines
9.5 KiB
299 lines
9.5 KiB
3 years ago
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|*Target Instruction Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_INSTRINFO_ENUM
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#undef GET_INSTRINFO_ENUM
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enum {
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TMS320C64x_PHI = 0,
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TMS320C64x_INLINEASM = 1,
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TMS320C64x_CFI_INSTRUCTION = 2,
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TMS320C64x_EH_LABEL = 3,
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TMS320C64x_GC_LABEL = 4,
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TMS320C64x_KILL = 5,
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TMS320C64x_EXTRACT_SUBREG = 6,
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TMS320C64x_INSERT_SUBREG = 7,
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TMS320C64x_IMPLICIT_DEF = 8,
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TMS320C64x_SUBREG_TO_REG = 9,
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TMS320C64x_COPY_TO_REGCLASS = 10,
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TMS320C64x_DBG_VALUE = 11,
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TMS320C64x_REG_SEQUENCE = 12,
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TMS320C64x_COPY = 13,
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TMS320C64x_BUNDLE = 14,
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TMS320C64x_LIFETIME_START = 15,
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TMS320C64x_LIFETIME_END = 16,
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TMS320C64x_STACKMAP = 17,
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TMS320C64x_PATCHPOINT = 18,
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TMS320C64x_LOAD_STACK_GUARD = 19,
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TMS320C64x_STATEPOINT = 20,
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TMS320C64x_FRAME_ALLOC = 21,
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TMS320C64x_ABS2_l2_rr = 22,
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TMS320C64x_ABS_l1_pp = 23,
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TMS320C64x_ABS_l1_rr = 24,
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TMS320C64x_ADD2_d2_rrr = 25,
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TMS320C64x_ADD2_l1_rrr_x2 = 26,
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TMS320C64x_ADD2_s1_rrr = 27,
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TMS320C64x_ADD4_l1_rrr_x2 = 28,
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TMS320C64x_ADDAB_d1_rir = 29,
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TMS320C64x_ADDAB_d1_rrr = 30,
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TMS320C64x_ADDAD_d1_rir = 31,
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TMS320C64x_ADDAD_d1_rrr = 32,
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TMS320C64x_ADDAH_d1_rir = 33,
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TMS320C64x_ADDAH_d1_rrr = 34,
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TMS320C64x_ADDAW_d1_rir = 35,
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TMS320C64x_ADDAW_d1_rrr = 36,
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TMS320C64x_ADDKPC_s3_iir = 37,
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TMS320C64x_ADDK_s2_ir = 38,
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TMS320C64x_ADDU_l1_rpp = 39,
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TMS320C64x_ADDU_l1_rrp_x2 = 40,
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TMS320C64x_ADD_d1_rir = 41,
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TMS320C64x_ADD_d1_rrr = 42,
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TMS320C64x_ADD_d2_rir = 43,
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TMS320C64x_ADD_d2_rrr = 44,
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TMS320C64x_ADD_l1_ipp = 45,
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TMS320C64x_ADD_l1_irr = 46,
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TMS320C64x_ADD_l1_rpp = 47,
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TMS320C64x_ADD_l1_rrp_x2 = 48,
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TMS320C64x_ADD_l1_rrr_x2 = 49,
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TMS320C64x_ADD_s1_irr = 50,
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TMS320C64x_ADD_s1_rrr = 51,
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TMS320C64x_ANDN_d2_rrr = 52,
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TMS320C64x_ANDN_l1_rrr_x2 = 53,
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TMS320C64x_ANDN_s4_rrr = 54,
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TMS320C64x_AND_d2_rir = 55,
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TMS320C64x_AND_d2_rrr = 56,
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TMS320C64x_AND_l1_irr = 57,
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TMS320C64x_AND_l1_rrr_x2 = 58,
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TMS320C64x_AND_s1_irr = 59,
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TMS320C64x_AND_s1_rrr = 60,
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TMS320C64x_AVG2_m1_rrr = 61,
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TMS320C64x_AVGU4_m1_rrr = 62,
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TMS320C64x_BDEC_s8_ir = 63,
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TMS320C64x_BITC4_m2_rr = 64,
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TMS320C64x_BNOP_s10_ri = 65,
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TMS320C64x_BNOP_s9_ii = 66,
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TMS320C64x_BPOS_s8_ir = 67,
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TMS320C64x_B_s5_i = 68,
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TMS320C64x_B_s6_r = 69,
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TMS320C64x_B_s7_irp = 70,
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TMS320C64x_B_s7_nrp = 71,
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TMS320C64x_CLR_s15_riir = 72,
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TMS320C64x_CLR_s1_rrr = 73,
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TMS320C64x_CMPEQ2_s1_rrr = 74,
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TMS320C64x_CMPEQ4_s1_rrr = 75,
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TMS320C64x_CMPEQ_l1_ipr = 76,
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TMS320C64x_CMPEQ_l1_irr = 77,
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TMS320C64x_CMPEQ_l1_rpr = 78,
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TMS320C64x_CMPEQ_l1_rrr_x2 = 79,
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TMS320C64x_CMPGT2_s1_rrr = 80,
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TMS320C64x_CMPGTU4_s1_rrr = 81,
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TMS320C64x_CMPGT_l1_ipr = 82,
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TMS320C64x_CMPGT_l1_irr = 83,
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TMS320C64x_CMPGT_l1_rpr = 84,
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TMS320C64x_CMPGT_l1_rrr_x2 = 85,
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TMS320C64x_CMPLTU_l1_ipr = 86,
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TMS320C64x_CMPLTU_l1_irr = 87,
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TMS320C64x_CMPLTU_l1_rpr = 88,
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TMS320C64x_CMPLTU_l1_rrr_x2 = 89,
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TMS320C64x_CMPLT_l1_ipr = 90,
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TMS320C64x_CMPLT_l1_irr = 91,
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TMS320C64x_CMPLT_l1_rpr = 92,
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TMS320C64x_CMPLT_l1_rrr_x2 = 93,
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TMS320C64x_DEAL_m2_rr = 94,
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TMS320C64x_DOTP2_m1_rrp = 95,
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TMS320C64x_DOTP2_m1_rrr = 96,
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TMS320C64x_DOTPN2_m1_rrr = 97,
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TMS320C64x_DOTPNRSU2_m1_rrr = 98,
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TMS320C64x_DOTPRSU2_m1_rrr = 99,
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TMS320C64x_DOTPSU4_m1_rrr = 100,
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TMS320C64x_DOTPU4_m1_rrr = 101,
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TMS320C64x_EXTU_s15_riir = 102,
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TMS320C64x_EXTU_s1_rrr = 103,
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TMS320C64x_EXT_s15_riir = 104,
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TMS320C64x_EXT_s1_rrr = 105,
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TMS320C64x_GMPGTU_l1_ipr = 106,
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TMS320C64x_GMPGTU_l1_irr = 107,
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TMS320C64x_GMPGTU_l1_rpr = 108,
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TMS320C64x_GMPGTU_l1_rrr_x2 = 109,
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TMS320C64x_GMPY4_m1_rrr = 110,
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TMS320C64x_LDBU_d5_mr = 111,
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TMS320C64x_LDBU_d6_mr = 112,
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TMS320C64x_LDB_d5_mr = 113,
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TMS320C64x_LDB_d6_mr = 114,
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TMS320C64x_LDDW_d7_mp = 115,
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TMS320C64x_LDHU_d5_mr = 116,
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TMS320C64x_LDHU_d6_mr = 117,
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TMS320C64x_LDH_d5_mr = 118,
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TMS320C64x_LDH_d6_mr = 119,
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TMS320C64x_LDNDW_d8_mp = 120,
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TMS320C64x_LDNW_d5_mr = 121,
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TMS320C64x_LDW_d5_mr = 122,
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TMS320C64x_LDW_d6_mr = 123,
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TMS320C64x_LMBD_l1_irr = 124,
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TMS320C64x_LMBD_l1_rrr_x2 = 125,
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TMS320C64x_MAX2_l1_rrr_x2 = 126,
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TMS320C64x_MAXU4_l1_rrr_x2 = 127,
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TMS320C64x_MIN2_l1_rrr_x2 = 128,
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TMS320C64x_MINU4_l1_rrr_x2 = 129,
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TMS320C64x_MPY2_m1_rrp = 130,
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TMS320C64x_MPYHIR_m1_rrr = 131,
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TMS320C64x_MPYHI_m1_rrp = 132,
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TMS320C64x_MPYHLU_m4_rrr = 133,
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TMS320C64x_MPYHL_m4_rrr = 134,
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TMS320C64x_MPYHSLU_m4_rrr = 135,
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TMS320C64x_MPYHSU_m4_rrr = 136,
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TMS320C64x_MPYHULS_m4_rrr = 137,
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TMS320C64x_MPYHUS_m4_rrr = 138,
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TMS320C64x_MPYHU_m4_rrr = 139,
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TMS320C64x_MPYH_m4_rrr = 140,
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TMS320C64x_MPYLHU_m4_rrr = 141,
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TMS320C64x_MPYLH_m4_rrr = 142,
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TMS320C64x_MPYLIR_m1_rrr = 143,
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TMS320C64x_MPYLI_m1_rrp = 144,
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TMS320C64x_MPYLSHU_m4_rrr = 145,
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TMS320C64x_MPYLUHS_m4_rrr = 146,
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TMS320C64x_MPYSU4_m1_rrp = 147,
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TMS320C64x_MPYSU_m4_irr = 148,
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TMS320C64x_MPYSU_m4_rrr = 149,
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TMS320C64x_MPYU4_m1_rrp = 150,
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TMS320C64x_MPYUS_m4_rrr = 151,
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TMS320C64x_MPYU_m4_rrr = 152,
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TMS320C64x_MPY_m4_irr = 153,
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TMS320C64x_MPY_m4_rrr = 154,
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TMS320C64x_MVC_s1_rr = 155,
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TMS320C64x_MVC_s1_rr2 = 156,
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TMS320C64x_MVD_m2_rr = 157,
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TMS320C64x_MVKLH_s12_ir = 158,
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TMS320C64x_MVKL_s12_ir = 159,
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TMS320C64x_MVK_d1_rr = 160,
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TMS320C64x_MVK_l2_ir = 161,
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TMS320C64x_NOP_n = 162,
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TMS320C64x_NORM_l1_pr = 163,
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TMS320C64x_NORM_l1_rr = 164,
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TMS320C64x_OR_d2_rir = 165,
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TMS320C64x_OR_d2_rrr = 166,
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TMS320C64x_OR_l1_irr = 167,
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TMS320C64x_OR_l1_rrr_x2 = 168,
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TMS320C64x_OR_s1_irr = 169,
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TMS320C64x_OR_s1_rrr = 170,
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TMS320C64x_PACK2_l1_rrr_x2 = 171,
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TMS320C64x_PACK2_s4_rrr = 172,
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TMS320C64x_PACKH2_l1_rrr_x2 = 173,
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TMS320C64x_PACKH2_s1_rrr = 174,
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TMS320C64x_PACKH4_l1_rrr_x2 = 175,
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TMS320C64x_PACKHL2_l1_rrr_x2 = 176,
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TMS320C64x_PACKHL2_s1_rrr = 177,
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TMS320C64x_PACKL4_l1_rrr_x2 = 178,
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TMS320C64x_PACKLH2_l1_rrr_x2 = 179,
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TMS320C64x_PACKLH2_s1_rrr = 180,
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TMS320C64x_ROTL_m1_rir = 181,
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TMS320C64x_ROTL_m1_rrr = 182,
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TMS320C64x_SADD2_s4_rrr = 183,
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TMS320C64x_SADDU4_s4_rrr = 184,
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TMS320C64x_SADDUS2_s4_rrr = 185,
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TMS320C64x_SADD_l1_ipp = 186,
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TMS320C64x_SADD_l1_irr = 187,
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TMS320C64x_SADD_l1_rpp = 188,
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TMS320C64x_SADD_l1_rrr_x2 = 189,
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TMS320C64x_SADD_s1_rrr = 190,
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TMS320C64x_SAT_l1_pr = 191,
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TMS320C64x_SET_s15_riir = 192,
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TMS320C64x_SET_s1_rrr = 193,
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TMS320C64x_SHFL_m2_rr = 194,
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TMS320C64x_SHLMB_l1_rrr_x2 = 195,
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TMS320C64x_SHLMB_s4_rrr = 196,
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TMS320C64x_SHL_s1_pip = 197,
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TMS320C64x_SHL_s1_prp = 198,
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TMS320C64x_SHL_s1_rip = 199,
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TMS320C64x_SHL_s1_rir = 200,
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TMS320C64x_SHL_s1_rrp = 201,
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TMS320C64x_SHL_s1_rrr = 202,
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TMS320C64x_SHR2_s1_rir = 203,
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TMS320C64x_SHR2_s4_rrr = 204,
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TMS320C64x_SHRMB_l1_rrr_x2 = 205,
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TMS320C64x_SHRMB_s4_rrr = 206,
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TMS320C64x_SHRU2_s1_rir = 207,
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TMS320C64x_SHRU2_s4_rrr = 208,
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TMS320C64x_SHRU_s1_pip = 209,
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TMS320C64x_SHRU_s1_prp = 210,
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TMS320C64x_SHRU_s1_rir = 211,
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TMS320C64x_SHRU_s1_rrr = 212,
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TMS320C64x_SHR_s1_pip = 213,
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TMS320C64x_SHR_s1_prp = 214,
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TMS320C64x_SHR_s1_rir = 215,
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TMS320C64x_SHR_s1_rrr = 216,
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TMS320C64x_SMPY2_m1_rrp = 217,
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TMS320C64x_SMPYHL_m4_rrr = 218,
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TMS320C64x_SMPYH_m4_rrr = 219,
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TMS320C64x_SMPYLH_m4_rrr = 220,
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TMS320C64x_SMPY_m4_rrr = 221,
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TMS320C64x_SPACK2_s4_rrr = 222,
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TMS320C64x_SPACKU4_s4_rrr = 223,
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TMS320C64x_SSHL_s1_rir = 224,
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TMS320C64x_SSHL_s1_rrr = 225,
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TMS320C64x_SSHVL_m1_rrr = 226,
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TMS320C64x_SSHVR_m1_rrr = 227,
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TMS320C64x_SSUB_l1_ipp = 228,
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TMS320C64x_SSUB_l1_irr = 229,
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TMS320C64x_SSUB_l1_rrr_x1 = 230,
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TMS320C64x_SSUB_l1_rrr_x2 = 231,
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TMS320C64x_STB_d5_rm = 232,
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TMS320C64x_STB_d6_rm = 233,
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TMS320C64x_STDW_d7_pm = 234,
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TMS320C64x_STH_d5_rm = 235,
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TMS320C64x_STH_d6_rm = 236,
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TMS320C64x_STNDW_d8_pm = 237,
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TMS320C64x_STNW_d5_rm = 238,
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TMS320C64x_STW_d5_rm = 239,
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TMS320C64x_STW_d6_rm = 240,
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TMS320C64x_SUB2_d2_rrr = 241,
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TMS320C64x_SUB2_l1_rrr_x2 = 242,
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TMS320C64x_SUB2_s1_rrr = 243,
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TMS320C64x_SUB4_l1_rrr_x2 = 244,
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TMS320C64x_SUBABS4_l1_rrr_x2 = 245,
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TMS320C64x_SUBAB_d1_rir = 246,
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TMS320C64x_SUBAB_d1_rrr = 247,
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TMS320C64x_SUBAH_d1_rir = 248,
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TMS320C64x_SUBAH_d1_rrr = 249,
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TMS320C64x_SUBAW_d1_rir = 250,
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TMS320C64x_SUBAW_d1_rrr = 251,
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TMS320C64x_SUBC_l1_rrr_x2 = 252,
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TMS320C64x_SUBU_l1_rrp_x1 = 253,
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TMS320C64x_SUBU_l1_rrp_x2 = 254,
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TMS320C64x_SUB_d1_rir = 255,
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TMS320C64x_SUB_d1_rrr = 256,
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TMS320C64x_SUB_d2_rrr = 257,
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TMS320C64x_SUB_l1_ipp = 258,
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TMS320C64x_SUB_l1_irr = 259,
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TMS320C64x_SUB_l1_rrp_x1 = 260,
|
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|
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TMS320C64x_SUB_l1_rrp_x2 = 261,
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||
|
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TMS320C64x_SUB_l1_rrr_x1 = 262,
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TMS320C64x_SUB_l1_rrr_x2 = 263,
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TMS320C64x_SUB_s1_irr = 264,
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TMS320C64x_SUB_s1_rrr = 265,
|
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|
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TMS320C64x_SUB_s4_rrr = 266,
|
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|
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TMS320C64x_SWAP4_l2_rr = 267,
|
||
|
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TMS320C64x_UNPKHU4_l2_rr = 268,
|
||
|
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TMS320C64x_UNPKHU4_s14_rr = 269,
|
||
|
|
TMS320C64x_UNPKLU4_l2_rr = 270,
|
||
|
|
TMS320C64x_UNPKLU4_s14_rr = 271,
|
||
|
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TMS320C64x_XOR_d2_rir = 272,
|
||
|
|
TMS320C64x_XOR_d2_rrr = 273,
|
||
|
|
TMS320C64x_XOR_l1_irr = 274,
|
||
|
|
TMS320C64x_XOR_l1_rrr_x2 = 275,
|
||
|
|
TMS320C64x_XOR_s1_irr = 276,
|
||
|
|
TMS320C64x_XOR_s1_rrr = 277,
|
||
|
|
TMS320C64x_XPND2_m2_rr = 278,
|
||
|
|
TMS320C64x_XPND4_m2_rr = 279,
|
||
|
|
TMS320C64x_INSTRUCTION_LIST_END = 280
|
||
|
|
};
|
||
|
|
|
||
|
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#endif // GET_INSTRINFO_ENUM
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