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427 lines
14 KiB
427 lines
14 KiB
3 years ago
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#!/usr/bin/env python
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from __future__ import print_function
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import sys
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import bitstring
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from capstone import *
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from capstone.m68k import *
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#
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# Objdump with the same output as his binary cousin
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#
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TODO = """
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TODO :
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o need more testing on M68K_AM_*_DISP
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o cleanup, etc ...
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"""
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objdump_cmd_example = 'm68k-atari-mint-objdump -b binary -D -mm68k --adjust-vma 0x30664 u/m68k.bin'
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objdump_dumpheader_fmt = """
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%s: file format binary
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Disassembly of section .data:
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%08x <.data>:"""
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M68000_CODE = b"\x04\x40\x00\x40"
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all_tests = (
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(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_060, M68000_CODE, "M68060-32 (Big-endian)"),
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)
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def dump_bytes(b, len):
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str = ''
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i = 0
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while i < len:
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str += format("%02x%02x " % (b[i], b[i+1]))
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i += 2
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return str[:-1]
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def dump_op_reg(insn, op_reg):
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if op_reg == M68K_REG_A7:
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return "%sp"
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if op_reg == M68K_REG_A6:
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return "%fp"
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return '%' + insn.reg_name(op_reg)
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def s8(value):
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return bitstring.Bits(uint=value, length=8).unpack('int')[0]
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def s16(value):
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return bitstring.Bits(uint=value, length=16).unpack('int')[0]
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def extsign8(value):
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if value & 0x80:
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return 0xffffffffffffff00 + value
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return value
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def extsign1616(value):
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if value & 0x8000:
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return 0xffff0000 + value
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return value
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def extsign1632(value):
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if value & 0x8000:
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return 0xffffffffffff0000 + value
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return value
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def printRegbitsRange(buffer, data, prefix):
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str = ''
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first = 0
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run_length = 0
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i = 0
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while i < 8:
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if (data & (1 << i)):
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first = i
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run_length = 0
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while (i < 7 and (data & (1 << (i + 1)))):
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i += 1
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run_length += 1
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if len(buffer) or len(str):
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str += "/"
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str += format("%%%s%d" % (prefix, first))
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if run_length > 0:
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str += format("-%%%s%d" % (prefix, first + run_length))
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i += 1
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return str
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def registerBits(op):
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str = ''
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data = op.register_bits
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str += printRegbitsRange(str, data & 0xff, "d")
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str += printRegbitsRange(str, (data >> 8) & 0xff, "a")
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str += printRegbitsRange(str, (data >> 16) & 0xff, "fp")
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return str
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def dump_op_ea(insn, op):
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s_spacing = " "
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map_index_size_str = { 0: 'w', 1 : 'l' }
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str = ''
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if op.address_mode == M68K_AM_NONE:
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if op.type == M68K_OP_REG_BITS:
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return registerBits(op)
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if op.type == M68K_OP_REG_PAIR:
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return registerPair(op)
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if op.type == M68K_OP_REG:
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return dump_op_reg(insn, op.reg)
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if op.address_mode == M68K_AM_REG_DIRECT_DATA:
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return dump_op_reg(insn, op.reg)
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if op.address_mode == M68K_AM_REG_DIRECT_ADDR:
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return dump_op_reg(insn, op.reg) + "@"
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if op.address_mode == M68K_AM_REGI_ADDR:
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return dump_op_reg(insn, op.reg) + "@"
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if op.address_mode == M68K_AM_REGI_ADDR_POST_INC:
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return dump_op_reg(insn, op.reg) + "@+"
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if op.address_mode == M68K_AM_REGI_ADDR_PRE_DEC:
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return dump_op_reg(insn, op.reg) + "@-"
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if op.address_mode == M68K_AM_REGI_ADDR_DISP:
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# str = dump_op_reg(insn, op.mem.base_reg - M68K_REG_A0 + 1) #double check and fixme '+1' : 02af 899f 2622
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str = dump_op_reg(insn, op.mem.base_reg)
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if op.mem.disp:
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str += format("@(%d)" % s16(op.mem.disp))
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return str
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if op.address_mode == M68K_AM_PCI_DISP:
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return format("%%pc@(0x%x)" % ( extsign1616(op.mem.disp + 2)))
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if op.address_mode == M68K_AM_ABSOLUTE_DATA_SHORT:
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return format("0x%x" % (extsign1616(op.imm & 0xffff)))
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if op.address_mode == M68K_AM_ABSOLUTE_DATA_LONG:
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return format("0x%x" % (op.imm & 0xffffffff))
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if op.address_mode == M68K_AM_IMMEDIATE:
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if insn.op_size.type == M68K_SIZE_TYPE_FPU:
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map_fpu_size_str = { M68K_FPU_SIZE_SINGLE : op.simm, M68K_FPU_SIZE_DOUBLE : op.dimm }
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return format("#%f" % (insn.op_size.fpu_size[map_fpu_size_str]))
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return format("#$%x" % (op.imm))
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if op.address_mode in [ M68K_AM_PCI_INDEX_8_BIT_DISP, M68K_AM_AREGI_INDEX_8_BIT_DISP ]:
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disp = op.mem.disp
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if op.register_bits == 2:
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disp = extsign8(op.mem.disp)
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if op.register_bits == 4:
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disp = extsign1632(op.mem.disp)
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str = dump_op_reg(insn, op.mem.base_reg) + "@(" + "{0:016x}".format(disp) + "," + dump_op_reg(insn, op.mem.index_reg) + ":" + map_index_size_str[op.mem.index_size]
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if op.register_bits:
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str += format(":%u" % (op.register_bits))
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return str + ")"
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if op.address_mode in [ M68K_AM_PCI_INDEX_BASE_DISP, M68K_AM_AREGI_INDEX_BASE_DISP ]:
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str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg) ))
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str += format("@(%016x)@(%016x" % (extsign1632(op.mem.in_disp), extsign1632(op.mem.out_disp)))
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if op.mem.index_reg:
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str += "," + dump_op_reg(insn, op.mem.index_reg) + ":" + map_index_size_str[op.mem.index_size]
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if op.register_bits:
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str += format(":%u" % (op.register_bits))
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str += ")"
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return str
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if op.mem.in_disp > 0:
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str += format("$%x" % ( op.mem.in_disp))
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str += format("(")
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if op.address_mode == M68K_AM_PCI_INDEX_BASE_DISP:
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str_size = ''
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if op.mem.index_size:
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str_size = "l"
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else:
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str_size = "w"
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str += format("pc,%s%s.%s" % ( dump_op_reg(insn, op.mem.index_reg)), s_spacing, str_size)
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else:
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if op.mem.base_reg != M68K_REG_INVALID:
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str += format("a%d,%s" % ( op.mem.base_reg - M68K_REG_A0, s_spacing))
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str_size = ''
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if op.mem.index_size:
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str_size = "l"
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else:
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str_size = "w"
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str += format("%s.%s" % ( dump_op_reg(insn, op.mem.index_reg), str_size))
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if op.mem.scale > 0:
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str += format("%s*%s%d)" % ( s_spacing, s_spacing, op.mem.scale))
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else:
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str += ")"
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return str
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# It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler.
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# While this is not strictly correct it makes the code
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# easier and that is what actually happens when the code is executed anyway.
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if op.address_mode in [ M68K_AM_PC_MEMI_POST_INDEX, M68K_AM_PC_MEMI_PRE_INDEX, M68K_AM_MEMI_PRE_INDEX, M68K_AM_MEMI_POST_INDEX]:
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if op.mem.base_reg:
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str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg) ))
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if op.mem.in_disp:
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value = op.mem.in_disp
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if op.mem.in_disp & 0x8000:
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value = 0xffffffffffff0000 + op.mem.in_disp
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str += format("@(%016x)@(%016x)" % (value, op.mem.out_disp))
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return str
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str += format("([")
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if op.mem.in_disp > 0:
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str += format("$%x" % ( op.mem.in_disp))
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if op.mem.base_reg != M68K_REG_INVALID:
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if op.mem.in_disp > 0:
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str += format(",%s%s" % ( s_spacing, dump_op_reg(insn, op.mem.base_reg)))
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else:
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str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg)))
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if op.address_mode in [ M68K_AM_MEMI_POST_INDEX, M68K_AM_PC_MEMI_POST_INDEX]:
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str += format("]")
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if op.mem.index_reg != M68K_REG_INVALID:
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str_size = ''
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if op.mem.index_size:
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str_size = "l"
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else:
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str_size = "w"
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str += format(",%s%s.%s" % ( s_spacing, dump_op_reg(insn, op.mem.index_reg), str_size))
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if op.mem.scale > 0:
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str += format("%s*%s%d" % ( s_spacing, s_spacing, op.mem.scale))
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if op.address_mode in [ M68K_AM_MEMI_PRE_INDEX, M68K_AM_PC_MEMI_PRE_INDEX]:
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str += format("]")
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if op.mem.out_disp > 0:
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str += format(",%s$%x" % ( s_spacing, op.mem.out_disp))
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str += format(")")
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return str
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if op.mem.bitfield:
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return format("%d:%d" % ( op.mem.offset, op.mem.width))
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############# OK
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if op.address_mode == M68K_AM_AREGI_INDEX_BASE_DISP:
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if op.mem.index_size:
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str_size = "l"
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else:
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str_size = "w"
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bits = op.mem.disp
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return dump_op_reg(insn, op.mem.base_reg) + "@(" + "{0:016b}".format(bits) + "," + dump_op_reg(insn, op.mem.index_reg) + ":" + str_size + ")"
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return ''
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# M68K Addressing Modes
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map_address_mode_str = {
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0 : "M68K_AM_NONE",
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1 : "M68K_AM_REG_DIRECT_DATA",
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2 : "M68K_AM_REG_DIRECT_ADDR",
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3 : "M68K_AM_REGI_ADDR",
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4 : "M68K_AM_REGI_ADDR_POST_INC",
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5 : "M68K_AM_REGI_ADDR_PRE_DEC",
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6 : "M68K_AM_REGI_ADDR_DISP",
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7 : "M68K_AM_AREGI_INDEX_8_BIT_DISP",
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8 : "M68K_AM_AREGI_INDEX_BASE_DISP",
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9 : "M68K_AM_MEMI_POST_INDEX",
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10 : "M68K_AM_MEMI_PRE_INDEX",
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11 : "M68K_AM_PCI_DISP",
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12 : "M68K_AM_PCI_INDEX_8_BIT_DISP",
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13 : "M68K_AM_PCI_INDEX_BASE_DISP",
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14 : "M68K_AM_PC_MEMI_POST_INDEX",
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15 : "M68K_AM_PC_MEMI_PRE_INDEX",
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16 : "M68K_AM_ABSOLUTE_DATA_SHORT",
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17 : "M68K_AM_ABSOLUTE_DATA_LONG",
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18 : "M68K_AM_IMMEDIATE",
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}
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# Operand type for instruction's operands
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map_op_str = {
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0 : "M68K_OP_INVALID",
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1 : "M68K_OP_REG",
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2 : "M68K_OP_IMM",
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3 : "M68K_OP_MEM",
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4 : "M68K_OP_FP",
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5 : "M68K_OP_REG_BITS",
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6 : "M68K_OP_REG_PAIR",
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}
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def debug(insn, op):
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if len(sys.argv) > 3:
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print("id %d type %s address_mode %s" % (insn.id, map_op_str[op.type], map_address_mode_str[op.address_mode]))
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def dump_ops(insn):
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str = ''
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mnemonic = insn.insn_name()
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i = 0
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while i < len(insn.operands):
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if i > 0:
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str += ','
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op = insn.operands[i]
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debug(insn, op)
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# "data" instruction generated by SKIPDATA option has no detail
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if insn.id == M68K_INS_INVALID:
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return format("0x%04x" % (op.imm))
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if op.type == M68K_OP_REG:
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str_op_reg = dump_op_ea(insn, op)
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if str_op_reg == '' or op.address_mode == M68K_AM_REG_DIRECT_ADDR:
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str_op_reg = dump_op_reg(insn, op.reg)
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str += str_op_reg
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if op.type == M68K_OP_IMM:
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str_op_imm = format("#%u" % (op.imm))
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if mnemonic in ["bkpt"]:
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str_op_imm = format("%u" % (op.imm))
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signed_insn = [ "move", "moveq", "cmp", "cmpi", "ori", "bclr", "pack", "unpk", "sub", "add" ]
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if mnemonic in signed_insn:
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if insn.op_size.size == 1 or mnemonic == "moveq":
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str_op_imm = format("#%d" % s8(op.imm))
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if insn.op_size.size == 2 or mnemonic == "pack":
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str_op_imm = format("#%d" % s16(op.imm))
|
||
|
|
if insn.op_size.size == 4:
|
||
|
|
str_op_imm = format("#%d" % (op.imm))
|
||
|
|
|
||
|
|
dbxx_insn = [ "dbt", "dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne", "dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge", "dblt", "dbgt", "dble", "dbra" ]
|
||
|
|
if is_branch(insn) or mnemonic in dbxx_insn:
|
||
|
|
str_op_imm = format("0x%x" % (op.imm & 0xffffffff))
|
||
|
|
str += str_op_imm
|
||
|
|
if op.type == M68K_OP_MEM:
|
||
|
|
str_op_mem = dump_op_ea(insn, op)
|
||
|
|
if str_op_mem == '':
|
||
|
|
str_op_mem = format("0x%x" % (op.imm))
|
||
|
|
str += str_op_mem
|
||
|
|
if op.type in [ M68K_OP_REG_BITS, M68K_OP_REG_PAIR ]:
|
||
|
|
str += dump_op_ea(insn, op)
|
||
|
|
|
||
|
|
# if insn.address == 0x3127c:
|
||
|
|
# import pdb;pdb.set_trace()
|
||
|
|
# print("type %u am %u\n" % (op.type, op.address_mode))
|
||
|
|
i += 1
|
||
|
|
return str
|
||
|
|
|
||
|
|
|
||
|
|
def is_branch(insn):
|
||
|
|
mnemonic = insn.insn_name()
|
||
|
|
branch_insn = [ "bsr", "bra", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc", "bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble" ];
|
||
|
|
return mnemonic in branch_insn
|
||
|
|
|
||
|
|
def dump_mnemonic(insn):
|
||
|
|
# "data" instruction generated by SKIPDATA option has no detail
|
||
|
|
if insn.id == M68K_INS_INVALID:
|
||
|
|
return ".short"
|
||
|
|
mnemonic = insn.insn_name()
|
||
|
|
ext = { 0: '', 1:'b', 2:'w', 4:'l' }
|
||
|
|
if is_branch(insn):
|
||
|
|
ext.update({ 1:'s', 2:'w', 4:'l' })
|
||
|
|
|
||
|
|
no_size = [ "pea", "lea", "bset", "bclr", "bchg", "btst", "nbcd", "abcd", "sbcd", "exg", "scc", "sls", "scs", "shi" ]
|
||
|
|
sxx_insn = [ "st", "sf", "shi", "sls", "scc", "scs", "sne", "seq", "svc", "svs", "spl", "smi", "sge", "slt", "sgt", "sle", "stop" ]
|
||
|
|
no_size += sxx_insn
|
||
|
|
no_size += [ "tas" ]
|
||
|
|
if mnemonic in no_size:
|
||
|
|
ext.update({ 0:'', 1:'', 2:'', 4:'' })
|
||
|
|
return mnemonic + ext[insn.op_size.size]
|
||
|
|
|
||
|
|
def print_insn_detail_np(insn):
|
||
|
|
# objdump format hack
|
||
|
|
if insn.size == 2:
|
||
|
|
space = ' ' * 11
|
||
|
|
if insn.size == 4:
|
||
|
|
space = ' ' * 6
|
||
|
|
if insn.size >= 6:
|
||
|
|
space = ' '
|
||
|
|
space_ops = ''
|
||
|
|
if len(insn.operands) > 0:
|
||
|
|
space_ops = ' '
|
||
|
|
|
||
|
|
print(" %x:\t%s%s\t%s%s%s" % (insn.address, dump_bytes(insn._raw.bytes, min(insn.size, 6)), space, dump_mnemonic(insn), space_ops, dump_ops(insn)))
|
||
|
|
|
||
|
|
if insn.size > 6:
|
||
|
|
delta = min(insn.size, 6)
|
||
|
|
print(" %x:\t%s " % (insn.address+delta, dump_bytes(insn._raw.bytes[delta:], min(insn.size-delta, 6))))
|
||
|
|
|
||
|
|
|
||
|
|
def print_objdump_dumpheader(filename='', address=0):
|
||
|
|
print(objdump_dumpheader_fmt % (filename, address))
|
||
|
|
|
||
|
|
# ## Test class Cs
|
||
|
|
def test_class():
|
||
|
|
for (arch, mode, code, comment) in all_tests:
|
||
|
|
filename = "/dev/stdin"
|
||
|
|
address = 0
|
||
|
|
if len(sys.argv) > 1:
|
||
|
|
filename = sys.argv[1]
|
||
|
|
if len(sys.argv) > 2:
|
||
|
|
address = int(sys.argv[2],16)
|
||
|
|
if len(sys.argv) > 3:
|
||
|
|
debug_mode = True
|
||
|
|
|
||
|
|
with open(filename, "rb") as f:
|
||
|
|
code = f.read()
|
||
|
|
|
||
|
|
try:
|
||
|
|
md = Cs(arch, mode)
|
||
|
|
md.detail = True
|
||
|
|
|
||
|
|
print_objdump_dumpheader(filename, address)
|
||
|
|
|
||
|
|
for insn in md.disasm(code, address):
|
||
|
|
print_insn_detail_np(insn)
|
||
|
|
|
||
|
|
except CsError as e:
|
||
|
|
print("ERROR: %s" % e)
|
||
|
|
|
||
|
|
|
||
|
|
if __name__ == '__main__':
|
||
|
|
test_class()
|