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445 lines
12 KiB
445 lines
12 KiB
//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_POWERPC
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#include <stdio.h> // DEBUG
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#include <stdlib.h>
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#include <string.h>
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "PPCDisassembler.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCDisassembler.h"
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#include "../../MathExtras.h"
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#define GET_REGINFO_ENUM
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#include "PPCGenRegisterInfo.inc"
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// FIXME: These can be generated by TableGen from the existing register
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// encoding values!
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static const unsigned CRRegs[] = {
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PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3,
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PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7
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};
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static const unsigned CRBITRegs[] = {
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PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN,
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PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN,
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PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN,
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PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN,
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PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN,
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PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN,
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PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN,
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PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN
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};
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static const unsigned FRegs[] = {
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PPC_F0, PPC_F1, PPC_F2, PPC_F3,
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PPC_F4, PPC_F5, PPC_F6, PPC_F7,
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PPC_F8, PPC_F9, PPC_F10, PPC_F11,
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PPC_F12, PPC_F13, PPC_F14, PPC_F15,
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PPC_F16, PPC_F17, PPC_F18, PPC_F19,
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PPC_F20, PPC_F21, PPC_F22, PPC_F23,
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PPC_F24, PPC_F25, PPC_F26, PPC_F27,
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PPC_F28, PPC_F29, PPC_F30, PPC_F31
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};
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static const unsigned VRegs[] = {
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PPC_V0, PPC_V1, PPC_V2, PPC_V3,
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PPC_V4, PPC_V5, PPC_V6, PPC_V7,
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PPC_V8, PPC_V9, PPC_V10, PPC_V11,
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PPC_V12, PPC_V13, PPC_V14, PPC_V15,
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PPC_V16, PPC_V17, PPC_V18, PPC_V19,
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PPC_V20, PPC_V21, PPC_V22, PPC_V23,
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PPC_V24, PPC_V25, PPC_V26, PPC_V27,
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PPC_V28, PPC_V29, PPC_V30, PPC_V31
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};
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static const unsigned VSRegs[] = {
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PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3,
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PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7,
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PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11,
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PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15,
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PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19,
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PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23,
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PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27,
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PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31,
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PPC_VSH0, PPC_VSH1, PPC_VSH2, PPC_VSH3,
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PPC_VSH4, PPC_VSH5, PPC_VSH6, PPC_VSH7,
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PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11,
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PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15,
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PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19,
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PPC_VSH20, PPC_VSH21, PPC_VSH22, PPC_VSH23,
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PPC_VSH24, PPC_VSH25, PPC_VSH26, PPC_VSH27,
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PPC_VSH28, PPC_VSH29, PPC_VSH30, PPC_VSH31
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};
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static const unsigned VSFRegs[] = {
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PPC_F0, PPC_F1, PPC_F2, PPC_F3,
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PPC_F4, PPC_F5, PPC_F6, PPC_F7,
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PPC_F8, PPC_F9, PPC_F10, PPC_F11,
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PPC_F12, PPC_F13, PPC_F14, PPC_F15,
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PPC_F16, PPC_F17, PPC_F18, PPC_F19,
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PPC_F20, PPC_F21, PPC_F22, PPC_F23,
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PPC_F24, PPC_F25, PPC_F26, PPC_F27,
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PPC_F28, PPC_F29, PPC_F30, PPC_F31,
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PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3,
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PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7,
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PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11,
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PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15,
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PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
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PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23,
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PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27,
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PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31
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};
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static const unsigned GPRegs[] = {
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PPC_R0, PPC_R1, PPC_R2, PPC_R3,
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PPC_R4, PPC_R5, PPC_R6, PPC_R7,
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PPC_R8, PPC_R9, PPC_R10, PPC_R11,
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PPC_R12, PPC_R13, PPC_R14, PPC_R15,
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PPC_R16, PPC_R17, PPC_R18, PPC_R19,
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PPC_R20, PPC_R21, PPC_R22, PPC_R23,
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PPC_R24, PPC_R25, PPC_R26, PPC_R27,
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PPC_R28, PPC_R29, PPC_R30, PPC_R31
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};
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static const unsigned GP0Regs[] = {
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PPC_ZERO, PPC_R1, PPC_R2, PPC_R3,
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PPC_R4, PPC_R5, PPC_R6, PPC_R7,
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PPC_R8, PPC_R9, PPC_R10, PPC_R11,
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PPC_R12, PPC_R13, PPC_R14, PPC_R15,
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PPC_R16, PPC_R17, PPC_R18, PPC_R19,
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PPC_R20, PPC_R21, PPC_R22, PPC_R23,
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PPC_R24, PPC_R25, PPC_R26, PPC_R27,
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PPC_R28, PPC_R29, PPC_R30, PPC_R31
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};
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static const unsigned G8Regs[] = {
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PPC_X0, PPC_X1, PPC_X2, PPC_X3,
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PPC_X4, PPC_X5, PPC_X6, PPC_X7,
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PPC_X8, PPC_X9, PPC_X10, PPC_X11,
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PPC_X12, PPC_X13, PPC_X14, PPC_X15,
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PPC_X16, PPC_X17, PPC_X18, PPC_X19,
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PPC_X20, PPC_X21, PPC_X22, PPC_X23,
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PPC_X24, PPC_X25, PPC_X26, PPC_X27,
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PPC_X28, PPC_X29, PPC_X30, PPC_X31
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};
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static const unsigned QFRegs[] = {
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PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3,
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PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7,
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PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11,
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PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15,
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PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19,
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PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23,
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PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
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PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
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};
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static uint64_t getFeatureBits(int feature)
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{
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// enable all features
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return (uint64_t)-1;
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}
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static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
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const unsigned *Regs, size_t RegsLen)
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{
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if (RegNo >= RegsLen / sizeof(unsigned)) {
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return MCDisassembler_Fail;
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}
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MCOperand_CreateReg0(Inst, Regs[RegNo]);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, CRRegs, sizeof(CRRegs));
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}
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static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, CRBITRegs, sizeof(CRBITRegs));
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}
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static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs));
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}
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static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, FRegs, sizeof(FRegs));
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}
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static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, VRegs, sizeof(VRegs));
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}
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static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, VSRegs, sizeof(VSRegs));
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}
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static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, VSFRegs, sizeof(VSFRegs));
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, GPRegs, sizeof(GPRegs));
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}
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static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, GP0Regs, sizeof(GP0Regs));
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}
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static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, G8Regs, sizeof(G8Regs));
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}
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#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
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#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
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static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, QFRegs, sizeof(QFRegs));
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}
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#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
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#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
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static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address, const void *Decoder, unsigned N)
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{
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//assert(isUInt<N>(Imm) && "Invalid immediate");
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MCOperand_CreateImm0(Inst, Imm);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address, const void *Decoder, unsigned N)
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{
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// assert(isUInt<N>(Imm) && "Invalid immediate");
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MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
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return MCDisassembler_Success;
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}
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#define GET_INSTRINFO_ENUM
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#include "PPCGenInstrInfo.inc"
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static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
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int64_t Address, const void *Decoder)
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{
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// Decode the memri field (imm, reg), which has the low 16-bits as the
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// displacement and the next 5 bits as the register #.
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uint64_t Base = Imm >> 16;
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uint64_t Disp = Imm & 0xFFFF;
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// assert(Base < 32 && "Invalid base register");
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if (Base >= 32)
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return MCDisassembler_Fail;
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switch (MCInst_getOpcode(Inst)) {
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default: break;
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case PPC_LBZU:
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case PPC_LHAU:
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case PPC_LHZU:
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case PPC_LWZU:
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case PPC_LFSU:
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case PPC_LFDU:
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// Add the tied output operand.
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MCOperand_CreateReg0(Inst, GP0Regs[Base]);
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break;
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case PPC_STBU:
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case PPC_STHU:
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case PPC_STWU:
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case PPC_STFSU:
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case PPC_STFDU:
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MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
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break;
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}
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MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16));
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MCOperand_CreateReg0(Inst, GP0Regs[Base]);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
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int64_t Address, const void *Decoder)
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{
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// Decode the memrix field (imm, reg), which has the low 14-bits as the
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// displacement and the next 5 bits as the register #.
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uint64_t Base = Imm >> 14;
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uint64_t Disp = Imm & 0x3FFF;
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// assert(Base < 32 && "Invalid base register");
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if (MCInst_getOpcode(Inst) == PPC_LDU)
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// Add the tied output operand.
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MCOperand_CreateReg0(Inst, GP0Regs[Base]);
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else if (MCInst_getOpcode(Inst) == PPC_STDU)
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MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
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MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16));
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MCOperand_CreateReg0(Inst, GP0Regs[Base]);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address, const void *Decoder)
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{
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// The cr bit encoding is 0x80 >> cr_reg_num.
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unsigned Zeros = CountTrailingZeros_64(Imm);
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// assert(Zeros < 8 && "Invalid CR bit value");
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if (Zeros >=8)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]);
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return MCDisassembler_Success;
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}
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#include "PPCGenDisassemblerTables.inc"
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static DecodeStatus getInstruction(MCInst *MI,
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const uint8_t *code, size_t code_len,
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uint16_t *Size,
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uint64_t Address, MCRegisterInfo *MRI)
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{
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uint32_t insn;
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DecodeStatus result;
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// Get the four bytes of the instruction.
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if (code_len < 4) {
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// not enough data
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*Size = 0;
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return MCDisassembler_Fail;
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}
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// The instruction is big-endian encoded.
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if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
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insn = ((uint32_t) code[0] << 24) | (code[1] << 16) |
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(code[2] << 8) | (code[3] << 0);
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else
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insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
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(code[1] << 8) | (code[0] << 0);
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if (MI->flat_insn->detail) {
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memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc)+sizeof(cs_ppc));
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}
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if (MI->csh->mode & CS_MODE_QPX) {
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result = decodeInstruction_4(DecoderTableQPX32, MI, insn, Address, 4);
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if (result != MCDisassembler_Fail) {
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*Size = 4;
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return result;
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}
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MCInst_clear(MI);
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}
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result = decodeInstruction_4(DecoderTable32, MI, insn, Address, 4);
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if (result != MCDisassembler_Fail) {
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*Size = 4;
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return result;
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}
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// report error
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MCInst_clear(MI);
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*Size = 0;
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return MCDisassembler_Fail;
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}
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bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len,
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MCInst *instr, uint16_t *size, uint64_t address, void *info)
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{
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DecodeStatus status = getInstruction(instr,
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code, code_len,
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size,
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address, (MCRegisterInfo *)info);
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return status == MCDisassembler_Success;
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}
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#define GET_REGINFO_MC_DESC
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#include "PPCGenRegisterInfo.inc"
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void PPC_init(MCRegisterInfo *MRI)
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{
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/*
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InitMCRegisterInfo(PPCRegDesc, 310, RA, PC,
|
|
PPCMCRegisterClasses, 23,
|
|
PPCRegUnitRoots,
|
|
138,
|
|
PPCRegDiffLists,
|
|
PPCLaneMaskLists,
|
|
PPCRegStrings,
|
|
PPCRegClassStrings,
|
|
PPCSubRegIdxLists,
|
|
8,
|
|
PPCSubRegIdxRanges,
|
|
PPCRegEncodingTable);
|
|
*/
|
|
|
|
|
|
MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 310,
|
|
0, 0,
|
|
PPCMCRegisterClasses, 23,
|
|
0, 0,
|
|
PPCRegDiffLists,
|
|
0,
|
|
PPCSubRegIdxLists, 8,
|
|
0);
|
|
}
|
|
|
|
#endif
|