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1003 lines
28 KiB
1003 lines
28 KiB
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an PPC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_POWERPC
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "PPCInstPrinter.h"
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#include "PPCPredicates.h"
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#include "../../MCInst.h"
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#include "../../utils.h"
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#include "../../SStream.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MathExtras.h"
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#include "PPCMapping.h"
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#ifndef CAPSTONE_DIET
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static const char *getRegisterName(unsigned RegNo);
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#endif
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static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
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static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
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static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
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static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
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static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info);
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static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
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unsigned PrintMethodIdx, SStream *OS);
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#if 0
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static void printRegName(SStream *OS, unsigned RegNo)
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{
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char *RegName = getRegisterName(RegNo);
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if (RegName[0] == 'q' /* QPX */) {
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// The system toolchain on the BG/Q does not understand QPX register names
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// in .cfi_* directives, so print the name of the floating-point
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// subregister instead.
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RegName[0] = 'f';
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}
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SStream_concat0(OS, RegName);
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}
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#endif
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static void set_mem_access(MCInst *MI, bool status)
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{
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if (MI->csh->detail != CS_OPT_ON)
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return;
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MI->csh->doing_mem = status;
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if (status) {
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
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} else {
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// done, create the next operand slot
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MI->flat_insn->detail->ppc.op_count++;
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}
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}
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void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
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{
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if (((cs_struct *)ud)->detail != CS_OPT_ON)
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return;
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// check if this insn has branch hint
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if (strrchr(insn_asm, '+') != NULL && !strstr(insn_asm, ".+")) {
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insn->detail->ppc.bh = PPC_BH_PLUS;
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} else if (strrchr(insn_asm, '-') != NULL) {
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insn->detail->ppc.bh = PPC_BH_MINUS;
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}
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}
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#define GET_INSTRINFO_ENUM
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#include "PPCGenInstrInfo.inc"
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static int isBOCTRBranch(unsigned int op)
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{
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return ((op >= PPC_BDNZ) && (op <= PPC_BDZp));
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}
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void PPC_printInst(MCInst *MI, SStream *O, void *Info)
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{
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char *mnem;
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// Check for slwi/srwi mnemonics.
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if (MCInst_getOpcode(MI) == PPC_RLWINM) {
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unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
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unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
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unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
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bool useSubstituteMnemonic = false;
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if (SH <= 31 && MB == 0 && ME == (31-SH)) {
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SStream_concat0(O, "slwi\t");
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MCInst_setOpcodePub(MI, PPC_INS_SLWI);
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useSubstituteMnemonic = true;
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}
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if (SH <= 31 && MB == (32-SH) && ME == 31) {
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SStream_concat0(O, "srwi\t");
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MCInst_setOpcodePub(MI, PPC_INS_SRWI);
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useSubstituteMnemonic = true;
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SH = 32-SH;
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}
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if (useSubstituteMnemonic) {
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printOperand(MI, 0, O);
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SStream_concat0(O, ", ");
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printOperand(MI, 1, O);
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if (SH > HEX_THRESHOLD)
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SStream_concat(O, ", 0x%x", (unsigned int)SH);
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else
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SStream_concat(O, ", %u", (unsigned int)SH);
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if (MI->csh->detail) {
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cs_ppc *ppc = &MI->flat_insn->detail->ppc;
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ppc->operands[ppc->op_count].type = PPC_OP_IMM;
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ppc->operands[ppc->op_count].imm = SH;
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++ppc->op_count;
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}
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return;
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}
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}
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if ((MCInst_getOpcode(MI) == PPC_OR || MCInst_getOpcode(MI) == PPC_OR8) &&
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MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) {
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SStream_concat0(O, "mr\t");
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MCInst_setOpcodePub(MI, PPC_INS_MR);
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printOperand(MI, 0, O);
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SStream_concat0(O, ", ");
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printOperand(MI, 1, O);
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return;
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}
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if (MCInst_getOpcode(MI) == PPC_RLDICR) {
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unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
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unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
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// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
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if (63-SH == ME) {
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SStream_concat0(O, "sldi\t");
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MCInst_setOpcodePub(MI, PPC_INS_SLDI);
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printOperand(MI, 0, O);
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SStream_concat0(O, ", ");
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printOperand(MI, 1, O);
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if (SH > HEX_THRESHOLD)
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SStream_concat(O, ", 0x%x", (unsigned int)SH);
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else
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SStream_concat(O, ", %u", (unsigned int)SH);
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return;
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}
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}
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if ((MCInst_getOpcode(MI) == PPC_gBC)||(MCInst_getOpcode(MI) == PPC_gBCA)||
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(MCInst_getOpcode(MI) == PPC_gBCL)||(MCInst_getOpcode(MI) == PPC_gBCLA)) {
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int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2));
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bd = SignExtend64(bd, 14);
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MCOperand_setImm(MCInst_getOperand(MI, 2),bd);
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}
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if (isBOCTRBranch(MCInst_getOpcode(MI))) {
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if (MCOperand_isImm(MCInst_getOperand(MI,0)))
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{
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int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
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bd = SignExtend64(bd, 14);
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MCOperand_setImm(MCInst_getOperand(MI, 0),bd);
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}
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}
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if ((MCInst_getOpcode(MI) == PPC_B)||(MCInst_getOpcode(MI) == PPC_BA)||
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(MCInst_getOpcode(MI) == PPC_BL)||(MCInst_getOpcode(MI) == PPC_BLA)) {
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int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
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bd = SignExtend64(bd, 24);
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MCOperand_setImm(MCInst_getOperand(MI, 0),bd);
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}
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// consider our own alias instructions first
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mnem = printAliasInstrEx(MI, O, Info);
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if (!mnem)
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mnem = printAliasInstr(MI, O, Info);
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if (mnem != NULL) {
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if (strlen(mnem) > 0) {
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struct ppc_alias alias;
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// check to remove the last letter of ('.', '-', '+')
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if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.')
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mnem[strlen(mnem) - 1] = '\0';
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if (PPC_alias_insn(mnem, &alias)) {
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MCInst_setOpcodePub(MI, alias.id);
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if (MI->csh->detail) {
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MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc;
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}
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}
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}
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cs_mem_free(mnem);
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} else
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printInstruction(MI, O, NULL);
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}
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enum ppc_bc_hint {
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PPC_BC_LT_MINUS = (0 << 5) | 14,
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PPC_BC_LE_MINUS = (1 << 5) | 6,
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PPC_BC_EQ_MINUS = (2 << 5) | 14,
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PPC_BC_GE_MINUS = (0 << 5) | 6,
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PPC_BC_GT_MINUS = (1 << 5) | 14,
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PPC_BC_NE_MINUS = (2 << 5) | 6,
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PPC_BC_UN_MINUS = (3 << 5) | 14,
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PPC_BC_NU_MINUS = (3 << 5) | 6,
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PPC_BC_LT_PLUS = (0 << 5) | 15,
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PPC_BC_LE_PLUS = (1 << 5) | 7,
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PPC_BC_EQ_PLUS = (2 << 5) | 15,
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PPC_BC_GE_PLUS = (0 << 5) | 7,
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PPC_BC_GT_PLUS = (1 << 5) | 15,
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PPC_BC_NE_PLUS = (2 << 5) | 7,
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PPC_BC_UN_PLUS = (3 << 5) | 15,
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PPC_BC_NU_PLUS = (3 << 5) | 7,
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};
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// normalize CC to remove _MINUS & _PLUS
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static int cc_normalize(int cc)
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{
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switch(cc) {
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default: return cc;
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case PPC_BC_LT_MINUS: return PPC_BC_LT;
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case PPC_BC_LE_MINUS: return PPC_BC_LE;
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case PPC_BC_EQ_MINUS: return PPC_BC_EQ;
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case PPC_BC_GE_MINUS: return PPC_BC_GE;
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case PPC_BC_GT_MINUS: return PPC_BC_GT;
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case PPC_BC_NE_MINUS: return PPC_BC_NE;
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case PPC_BC_UN_MINUS: return PPC_BC_UN;
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case PPC_BC_NU_MINUS: return PPC_BC_NU;
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case PPC_BC_LT_PLUS : return PPC_BC_LT;
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case PPC_BC_LE_PLUS : return PPC_BC_LE;
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case PPC_BC_EQ_PLUS : return PPC_BC_EQ;
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case PPC_BC_GE_PLUS : return PPC_BC_GE;
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case PPC_BC_GT_PLUS : return PPC_BC_GT;
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case PPC_BC_NE_PLUS : return PPC_BC_NE;
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case PPC_BC_UN_PLUS : return PPC_BC_UN;
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case PPC_BC_NU_PLUS : return PPC_BC_NU;
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}
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}
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static void printPredicateOperand(MCInst *MI, unsigned OpNo,
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SStream *O, const char *Modifier)
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{
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unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
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MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code);
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if (!strcmp(Modifier, "cc")) {
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switch ((ppc_predicate)Code) {
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default: // unreachable
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case PPC_PRED_LT_MINUS:
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case PPC_PRED_LT_PLUS:
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case PPC_PRED_LT:
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SStream_concat0(O, "lt");
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return;
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case PPC_PRED_LE_MINUS:
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case PPC_PRED_LE_PLUS:
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case PPC_PRED_LE:
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SStream_concat0(O, "le");
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return;
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case PPC_PRED_EQ_MINUS:
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case PPC_PRED_EQ_PLUS:
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case PPC_PRED_EQ:
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SStream_concat0(O, "eq");
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return;
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case PPC_PRED_GE_MINUS:
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case PPC_PRED_GE_PLUS:
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case PPC_PRED_GE:
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SStream_concat0(O, "ge");
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return;
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case PPC_PRED_GT_MINUS:
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case PPC_PRED_GT_PLUS:
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case PPC_PRED_GT:
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SStream_concat0(O, "gt");
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return;
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case PPC_PRED_NE_MINUS:
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case PPC_PRED_NE_PLUS:
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case PPC_PRED_NE:
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SStream_concat0(O, "ne");
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return;
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case PPC_PRED_UN_MINUS:
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case PPC_PRED_UN_PLUS:
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case PPC_PRED_UN:
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SStream_concat0(O, "un");
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return;
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case PPC_PRED_NU_MINUS:
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case PPC_PRED_NU_PLUS:
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case PPC_PRED_NU:
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SStream_concat0(O, "nu");
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return;
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case PPC_PRED_BIT_SET:
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case PPC_PRED_BIT_UNSET:
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// llvm_unreachable("Invalid use of bit predicate code");
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SStream_concat0(O, "invalid-predicate");
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return;
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}
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}
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if (!strcmp(Modifier, "pm")) {
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switch ((ppc_predicate)Code) {
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case PPC_PRED_LT:
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case PPC_PRED_LE:
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case PPC_PRED_EQ:
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case PPC_PRED_GE:
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case PPC_PRED_GT:
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case PPC_PRED_NE:
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case PPC_PRED_UN:
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case PPC_PRED_NU:
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return;
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case PPC_PRED_LT_MINUS:
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case PPC_PRED_LE_MINUS:
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case PPC_PRED_EQ_MINUS:
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case PPC_PRED_GE_MINUS:
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case PPC_PRED_GT_MINUS:
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case PPC_PRED_NE_MINUS:
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case PPC_PRED_UN_MINUS:
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case PPC_PRED_NU_MINUS:
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SStream_concat0(O, "-");
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return;
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case PPC_PRED_LT_PLUS:
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case PPC_PRED_LE_PLUS:
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case PPC_PRED_EQ_PLUS:
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case PPC_PRED_GE_PLUS:
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case PPC_PRED_GT_PLUS:
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case PPC_PRED_NE_PLUS:
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case PPC_PRED_UN_PLUS:
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case PPC_PRED_NU_PLUS:
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SStream_concat0(O, "+");
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return;
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case PPC_PRED_BIT_SET:
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case PPC_PRED_BIT_UNSET:
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// llvm_unreachable("Invalid use of bit predicate code");
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SStream_concat0(O, "invalid-predicate");
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return;
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default: // unreachable
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return;
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}
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// llvm_unreachable("Invalid predicate code");
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}
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//assert(StringRef(Modifier) == "reg" &&
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// "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
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printOperand(MI, OpNo + 1, O);
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}
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static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
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//assert(Value <= 3 && "Invalid u2imm argument!");
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if (Value > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", Value);
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else
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SStream_concat(O, "%u", Value);
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if (MI->csh->detail) {
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
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MI->flat_insn->detail->ppc.op_count++;
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}
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}
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static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
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//assert(Value <= 15 && "Invalid u4imm argument!");
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if (Value > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", Value);
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else
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SStream_concat(O, "%u", Value);
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if (MI->csh->detail) {
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
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MI->flat_insn->detail->ppc.op_count++;
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}
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}
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static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
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Value = SignExtend32(Value, 5);
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printInt32(O, Value);
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if (MI->csh->detail) {
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
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MI->flat_insn->detail->ppc.op_count++;
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}
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}
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static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
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//assert(Value <= 31 && "Invalid u5imm argument!");
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printUInt32(O, Value);
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if (MI->csh->detail) {
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
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MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
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MI->flat_insn->detail->ppc.op_count++;
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}
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}
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static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
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//assert(Value <= 63 && "Invalid u6imm argument!");
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printUInt32(O, Value);
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|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
|
|
static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
unsigned short Value = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
|
|
|
// assert(Value <= 4095 && "Invalid u12imm argument!");
|
|
|
|
if (Value > HEX_THRESHOLD)
|
|
SStream_concat(O, "0x%x", Value);
|
|
else
|
|
SStream_concat(O, "%u", Value);
|
|
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
|
|
static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
|
|
unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
|
if (Imm > HEX_THRESHOLD)
|
|
SStream_concat(O, "0x%x", Imm);
|
|
else
|
|
SStream_concat(O, "%u", Imm);
|
|
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
} else
|
|
printOperand(MI, OpNo, O);
|
|
}
|
|
|
|
static void printS16ImmOperand_Mem(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
|
|
short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
|
|
|
if (Imm >= 0) {
|
|
if (Imm > HEX_THRESHOLD)
|
|
SStream_concat(O, "0x%x", Imm);
|
|
else
|
|
SStream_concat(O, "%u", Imm);
|
|
} else {
|
|
if (Imm < -HEX_THRESHOLD)
|
|
SStream_concat(O, "-0x%x", -Imm);
|
|
else
|
|
SStream_concat(O, "-%u", -Imm);
|
|
}
|
|
|
|
if (MI->csh->detail) {
|
|
if (MI->csh->doing_mem) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
|
|
} else {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
} else
|
|
printOperand(MI, OpNo, O);
|
|
}
|
|
|
|
static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
|
|
unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
|
if (Imm > HEX_THRESHOLD)
|
|
SStream_concat(O, "0x%x", Imm);
|
|
else
|
|
SStream_concat(O, "%u", Imm);
|
|
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
} else
|
|
printOperand(MI, OpNo, O);
|
|
}
|
|
|
|
static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
|
|
printOperand(MI, OpNo, O);
|
|
return;
|
|
}
|
|
|
|
// Branches can take an immediate operand. This is used by the branch
|
|
// selection pass to print .+8, an eight byte displacement from the PC.
|
|
printAbsBranchOperand(MI, OpNo, O);
|
|
}
|
|
|
|
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
int64_t imm;
|
|
|
|
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
|
|
printOperand(MI, OpNo, O);
|
|
return;
|
|
}
|
|
|
|
imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
|
|
|
|
if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) {
|
|
imm = MI->address + imm;
|
|
}
|
|
|
|
SStream_concat(O, "0x%"PRIx64, imm);
|
|
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
|
|
|
|
#define GET_REGINFO_ENUM
|
|
#include "PPCGenRegisterInfo.inc"
|
|
|
|
static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
unsigned RegNo, tmp;
|
|
unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo));
|
|
|
|
switch (CCReg) {
|
|
default: // llvm_unreachable("Unknown CR register");
|
|
case PPC_CR0: RegNo = 0; break;
|
|
case PPC_CR1: RegNo = 1; break;
|
|
case PPC_CR2: RegNo = 2; break;
|
|
case PPC_CR3: RegNo = 3; break;
|
|
case PPC_CR4: RegNo = 4; break;
|
|
case PPC_CR5: RegNo = 5; break;
|
|
case PPC_CR6: RegNo = 6; break;
|
|
case PPC_CR7: RegNo = 7; break;
|
|
}
|
|
|
|
tmp = 0x80 >> RegNo;
|
|
if (tmp > HEX_THRESHOLD)
|
|
SStream_concat(O, "0x%x", tmp);
|
|
else
|
|
SStream_concat(O, "%u", tmp);
|
|
}
|
|
|
|
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
set_mem_access(MI, true);
|
|
|
|
printS16ImmOperand_Mem(MI, OpNo, O);
|
|
|
|
SStream_concat0(O, "(");
|
|
|
|
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
|
|
SStream_concat0(O, "0");
|
|
else
|
|
printOperand(MI, OpNo + 1, O);
|
|
|
|
SStream_concat0(O, ")");
|
|
set_mem_access(MI, false);
|
|
}
|
|
|
|
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
// When used as the base register, r0 reads constant zero rather than
|
|
// the value contained in the register. For this reason, the darwin
|
|
// assembler requires that we print r0 as 0 (no r) when used as the base.
|
|
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0)
|
|
SStream_concat0(O, "0");
|
|
else
|
|
printOperand(MI, OpNo, O);
|
|
SStream_concat0(O, ", ");
|
|
|
|
printOperand(MI, OpNo + 1, O);
|
|
}
|
|
|
|
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
set_mem_access(MI, true);
|
|
//printBranchOperand(MI, OpNo, O);
|
|
|
|
// On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
|
|
// come at the _end_ of the expression.
|
|
|
|
SStream_concat0(O, "(");
|
|
printOperand(MI, OpNo + 1, O);
|
|
SStream_concat0(O, ")");
|
|
set_mem_access(MI, false);
|
|
}
|
|
|
|
#ifndef CAPSTONE_DIET
|
|
/// stripRegisterPrefix - This method strips the character prefix from a
|
|
/// register name so that only the number is left. Used by for linux asm.
|
|
static const char *stripRegisterPrefix(const char *RegName)
|
|
{
|
|
switch (RegName[0]) {
|
|
case 'r':
|
|
case 'f':
|
|
case 'q': // for QPX
|
|
case 'v':
|
|
if (RegName[1] == 's')
|
|
return RegName + 2;
|
|
return RegName + 1;
|
|
case 'c':
|
|
if (RegName[1] == 'r')
|
|
return RegName + 2;
|
|
}
|
|
|
|
return RegName;
|
|
}
|
|
#endif
|
|
|
|
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|
{
|
|
MCOperand *Op = MCInst_getOperand(MI, OpNo);
|
|
if (MCOperand_isReg(Op)) {
|
|
unsigned reg = MCOperand_getReg(Op);
|
|
#ifndef CAPSTONE_DIET
|
|
const char *RegName = getRegisterName(reg);
|
|
#endif
|
|
// map to public register
|
|
reg = PPC_map_register(reg);
|
|
#ifndef CAPSTONE_DIET
|
|
// The linux and AIX assembler does not take register prefixes.
|
|
if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME)
|
|
RegName = stripRegisterPrefix(RegName);
|
|
|
|
SStream_concat0(O, RegName);
|
|
#endif
|
|
|
|
if (MI->csh->detail) {
|
|
if (MI->csh->doing_mem) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
|
|
} else {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (MCOperand_isImm(Op)) {
|
|
int32_t imm = (int32_t)MCOperand_getImm(Op);
|
|
printInt32(O, imm);
|
|
|
|
if (MI->csh->detail) {
|
|
if (MI->csh->doing_mem) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = (int32_t)imm;
|
|
} else {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void op_addImm(MCInst *MI, int v)
|
|
{
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = v;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
|
|
static void op_addReg(MCInst *MI, unsigned int reg)
|
|
{
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
|
|
static void op_addBC(MCInst *MI, unsigned int bc)
|
|
{
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.bc = (ppc_bc)bc;
|
|
}
|
|
}
|
|
|
|
#define CREQ (0)
|
|
#define CRGT (1)
|
|
#define CRLT (2)
|
|
#define CRUN (3)
|
|
|
|
static int getBICRCond(int bi)
|
|
{
|
|
return (bi-PPC_CR0EQ) >> 3;
|
|
}
|
|
|
|
static int getBICR(int bi)
|
|
{
|
|
return ((bi - PPC_CR0EQ) & 7) + PPC_CR0;
|
|
}
|
|
|
|
static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info)
|
|
{
|
|
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
|
|
SStream ss;
|
|
const char *opCode;
|
|
char *tmp, *AsmMnem, *AsmOps, *c;
|
|
int OpIdx, PrintMethodIdx;
|
|
int decCtr = false, needComma = false;
|
|
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
|
|
|
|
SStream_Init(&ss);
|
|
switch (MCInst_getOpcode(MI)) {
|
|
default: return NULL;
|
|
case PPC_gBC:
|
|
opCode = "b%s";
|
|
break;
|
|
case PPC_gBCA:
|
|
opCode = "b%sa";
|
|
break;
|
|
case PPC_gBCCTR:
|
|
opCode = "b%sctr";
|
|
break;
|
|
case PPC_gBCCTRL:
|
|
opCode = "b%sctrl";
|
|
break;
|
|
case PPC_gBCL:
|
|
opCode = "b%sl";
|
|
break;
|
|
case PPC_gBCLA:
|
|
opCode = "b%sla";
|
|
break;
|
|
case PPC_gBCLR:
|
|
opCode = "b%slr";
|
|
break;
|
|
case PPC_gBCLRL:
|
|
opCode = "b%slrl";
|
|
break;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) {
|
|
SStream_concat(&ss, opCode, "dnzf");
|
|
decCtr = true;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) {
|
|
SStream_concat(&ss, opCode, "dzf");
|
|
decCtr = true;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
|
|
switch(cr) {
|
|
case CREQ:
|
|
SStream_concat(&ss, opCode, "ne");
|
|
break;
|
|
case CRGT:
|
|
SStream_concat(&ss, opCode, "le");
|
|
break;
|
|
case CRLT:
|
|
SStream_concat(&ss, opCode, "ge");
|
|
break;
|
|
case CRUN:
|
|
SStream_concat(&ss, opCode, "ns");
|
|
break;
|
|
}
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6)
|
|
SStream_concat0(&ss, "-");
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7)
|
|
SStream_concat0(&ss, "+");
|
|
|
|
decCtr = false;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) {
|
|
SStream_concat(&ss, opCode, "dnzt");
|
|
decCtr = true;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) {
|
|
SStream_concat(&ss, opCode, "dzt");
|
|
decCtr = true;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) &&
|
|
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
|
|
int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
|
|
switch(cr) {
|
|
case CREQ:
|
|
SStream_concat(&ss, opCode, "eq");
|
|
break;
|
|
case CRGT:
|
|
SStream_concat(&ss, opCode, "gt");
|
|
break;
|
|
case CRLT:
|
|
SStream_concat(&ss, opCode, "lt");
|
|
break;
|
|
case CRUN:
|
|
SStream_concat(&ss, opCode, "so");
|
|
break;
|
|
}
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14)
|
|
SStream_concat0(&ss, "-");
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15)
|
|
SStream_concat0(&ss, "+");
|
|
|
|
decCtr = false;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) {
|
|
SStream_concat(&ss, opCode, "dnz");
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24)
|
|
SStream_concat0(&ss, "-");
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25)
|
|
SStream_concat0(&ss, "+");
|
|
|
|
needComma = false;
|
|
}
|
|
|
|
if (MCInst_getNumOperands(MI) == 3 &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) {
|
|
SStream_concat(&ss, opCode, "dz");
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26)
|
|
SStream_concat0(&ss, "-");
|
|
|
|
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27)
|
|
SStream_concat0(&ss, "+");
|
|
|
|
needComma = false;
|
|
}
|
|
|
|
if (MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
|
|
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
|
|
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
|
|
(MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) {
|
|
int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
|
|
|
|
if (decCtr) {
|
|
needComma = true;
|
|
SStream_concat0(&ss, " ");
|
|
|
|
if (cr > PPC_CR0) {
|
|
SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0);
|
|
}
|
|
|
|
cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
|
|
switch(cr) {
|
|
case CREQ:
|
|
SStream_concat0(&ss, "eq");
|
|
op_addBC(MI, PPC_BC_EQ);
|
|
break;
|
|
case CRGT:
|
|
SStream_concat0(&ss, "gt");
|
|
op_addBC(MI, PPC_BC_GT);
|
|
break;
|
|
case CRLT:
|
|
SStream_concat0(&ss, "lt");
|
|
op_addBC(MI, PPC_BC_LT);
|
|
break;
|
|
case CRUN:
|
|
SStream_concat0(&ss, "so");
|
|
op_addBC(MI, PPC_BC_SO);
|
|
break;
|
|
}
|
|
|
|
cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
|
|
if (cr > PPC_CR0) {
|
|
if (MI->csh->detail) {
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_CRX;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.scale = 4;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.reg = PPC_REG_CR0 + cr - PPC_CR0;
|
|
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.cond = MI->flat_insn->detail->ppc.bc;
|
|
MI->flat_insn->detail->ppc.op_count++;
|
|
}
|
|
}
|
|
} else {
|
|
if (cr > PPC_CR0) {
|
|
needComma = true;
|
|
SStream_concat(&ss, " cr%d", cr - PPC_CR0);
|
|
op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
|
|
MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) {
|
|
if (needComma)
|
|
SStream_concat0(&ss, ",");
|
|
|
|
SStream_concat0(&ss, " $\xFF\x03\x01");
|
|
}
|
|
|
|
tmp = cs_strdup(ss.buffer);
|
|
AsmMnem = tmp;
|
|
for(AsmOps = tmp; *AsmOps; AsmOps++) {
|
|
if (*AsmOps == ' ' || *AsmOps == '\t') {
|
|
*AsmOps = '\0';
|
|
AsmOps++;
|
|
break;
|
|
}
|
|
}
|
|
|
|
SStream_concat0(OS, AsmMnem);
|
|
if (*AsmOps) {
|
|
SStream_concat0(OS, "\t");
|
|
for (c = AsmOps; *c; c++) {
|
|
if (*c == '$') {
|
|
c += 1;
|
|
if (*c == (char)0xff) {
|
|
c += 1;
|
|
OpIdx = *c - 1;
|
|
c += 1;
|
|
PrintMethodIdx = *c - 1;
|
|
printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
|
|
} else
|
|
printOperand(MI, *c - 1, OS);
|
|
} else {
|
|
SStream_concat(OS, "%c", *c);
|
|
}
|
|
}
|
|
}
|
|
|
|
return tmp;
|
|
}
|
|
|
|
#define PRINT_ALIAS_INSTR
|
|
#include "PPCGenAsmWriter.inc"
|
|
|
|
#endif
|