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450 lines
13 KiB
450 lines
13 KiB
//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Sparc MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_SPARC
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#ifdef _MSC_VER
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#define _CRT_SECURE_NO_WARNINGS
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#endif
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#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
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#pragma warning(disable:28719) // disable MSVC's warning on strncpy()
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#endif
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <limits.h>
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#include "SparcInstPrinter.h"
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#include "../../MCInst.h"
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#include "../../utils.h"
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#include "../../SStream.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MathExtras.h"
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#include "SparcMapping.h"
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#include "Sparc.h"
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static const char *getRegisterName(unsigned RegNo);
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static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
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static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
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static void printOperand(MCInst *MI, int opNum, SStream *O);
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static void Sparc_add_hint(MCInst *MI, unsigned int hint)
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{
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if (MI->csh->detail) {
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MI->flat_insn->detail->sparc.hint = hint;
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}
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}
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static void Sparc_add_reg(MCInst *MI, unsigned int reg)
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{
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if (MI->csh->detail) {
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
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MI->flat_insn->detail->sparc.op_count++;
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}
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}
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static void set_mem_access(MCInst *MI, bool status)
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{
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if (MI->csh->detail != CS_OPT_ON)
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return;
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MI->csh->doing_mem = status;
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if (status) {
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
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} else {
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// done, create the next operand slot
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MI->flat_insn->detail->sparc.op_count++;
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}
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}
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void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
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{
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if (((cs_struct *)ud)->detail != CS_OPT_ON)
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return;
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// fix up some instructions
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if (insn->id == SPARC_INS_CASX) {
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// first op is actually a memop, not regop
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insn->detail->sparc.operands[0].type = SPARC_OP_MEM;
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insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg;
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insn->detail->sparc.operands[0].mem.disp = 0;
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}
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}
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static void printRegName(SStream *OS, unsigned RegNo)
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{
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SStream_concat0(OS, "%");
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SStream_concat0(OS, getRegisterName(RegNo));
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}
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#define GET_INSTRINFO_ENUM
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#include "SparcGenInstrInfo.inc"
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#define GET_REGINFO_ENUM
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#include "SparcGenRegisterInfo.inc"
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static bool printSparcAliasInstr(MCInst *MI, SStream *O)
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{
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switch (MCInst_getOpcode(MI)) {
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default: return false;
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case SP_JMPLrr:
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case SP_JMPLri:
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if (MCInst_getNumOperands(MI) != 3)
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return false;
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if (!MCOperand_isReg(MCInst_getOperand(MI, 0)))
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return false;
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switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) {
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default: return false;
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case SP_G0: // jmp $addr | ret | retl
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if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
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MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
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switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) {
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default: break;
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case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true;
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case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true;
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}
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}
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SStream_concat0(O, "jmp\t");
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MCInst_setOpcodePub(MI, SPARC_INS_JMP);
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printMemOperand(MI, 1, O, NULL);
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return true;
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case SP_O7: // call $addr
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SStream_concat0(O, "call ");
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MCInst_setOpcodePub(MI, SPARC_INS_CALL);
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printMemOperand(MI, 1, O, NULL);
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return true;
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}
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case SP_V9FCMPS:
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case SP_V9FCMPD:
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case SP_V9FCMPQ:
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case SP_V9FCMPES:
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case SP_V9FCMPED:
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case SP_V9FCMPEQ:
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if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) ||
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(!MCOperand_isReg(MCInst_getOperand(MI, 0))) ||
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(MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0))
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return false;
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// if V8, skip printing %fcc0.
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switch(MCInst_getOpcode(MI)) {
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default:
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case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break;
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case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break;
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case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break;
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case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break;
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case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break;
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case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break;
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}
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printOperand(MI, 1, O);
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SStream_concat0(O, ", ");
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printOperand(MI, 2, O);
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return true;
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}
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}
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static void printOperand(MCInst *MI, int opNum, SStream *O)
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{
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int64_t Imm;
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unsigned reg;
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MCOperand *MO = MCInst_getOperand(MI, opNum);
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if (MCOperand_isReg(MO)) {
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reg = MCOperand_getReg(MO);
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printRegName(O, reg);
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reg = Sparc_map_register(reg);
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if (MI->csh->detail) {
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if (MI->csh->doing_mem) {
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if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
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else
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg;
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} else {
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
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MI->flat_insn->detail->sparc.op_count++;
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}
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}
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return;
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}
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if (MCOperand_isImm(MO)) {
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Imm = (int)MCOperand_getImm(MO);
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// Conditional branches displacements needs to be signextended to be
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// able to jump backwards.
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//
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// Displacements are measured as the number of instructions forward or
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// backward, so they need to be multiplied by 4
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switch (MI->Opcode) {
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case SP_CALL:
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// Imm = SignExtend32(Imm, 30);
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Imm += MI->address;
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break;
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// Branch on integer condition with prediction (BPcc)
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// Branch on floating point condition with prediction (FBPfcc)
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case SP_BPICC:
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case SP_BPICCA:
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case SP_BPICCANT:
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case SP_BPICCNT:
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case SP_BPXCC:
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case SP_BPXCCA:
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case SP_BPXCCANT:
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case SP_BPXCCNT:
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case SP_BPFCC:
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case SP_BPFCCA:
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case SP_BPFCCANT:
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case SP_BPFCCNT:
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Imm = SignExtend32((uint32_t)Imm, 19);
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Imm = MI->address + Imm * 4;
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break;
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// Branch on integer condition (Bicc)
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// Branch on floating point condition (FBfcc)
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case SP_BA:
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case SP_BCOND:
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case SP_BCONDA:
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case SP_FBCOND:
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case SP_FBCONDA:
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Imm = SignExtend32((uint32_t)Imm, 22);
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Imm = MI->address + Imm * 4;
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break;
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// Branch on integer register with prediction (BPr)
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case SP_BPGEZapn:
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case SP_BPGEZapt:
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case SP_BPGEZnapn:
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case SP_BPGEZnapt:
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case SP_BPGZapn:
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case SP_BPGZapt:
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case SP_BPGZnapn:
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case SP_BPGZnapt:
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case SP_BPLEZapn:
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case SP_BPLEZapt:
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case SP_BPLEZnapn:
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case SP_BPLEZnapt:
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case SP_BPLZapn:
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case SP_BPLZapt:
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case SP_BPLZnapn:
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case SP_BPLZnapt:
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case SP_BPNZapn:
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case SP_BPNZapt:
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case SP_BPNZnapn:
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case SP_BPNZnapt:
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case SP_BPZapn:
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case SP_BPZapt:
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case SP_BPZnapn:
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case SP_BPZnapt:
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Imm = SignExtend32((uint32_t)Imm, 16);
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Imm = MI->address + Imm * 4;
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break;
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}
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printInt64(O, Imm);
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if (MI->csh->detail) {
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if (MI->csh->doing_mem) {
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = (uint32_t)Imm;
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} else {
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
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MI->flat_insn->detail->sparc.op_count++;
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}
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}
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}
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return;
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}
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static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier)
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{
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MCOperand *MO;
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set_mem_access(MI, true);
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printOperand(MI, opNum, O);
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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SStream_concat0(O, ", ");
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printOperand(MI, opNum + 1, O);
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set_mem_access(MI, false);
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return;
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}
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MO = MCInst_getOperand(MI, opNum + 1);
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if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
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set_mem_access(MI, false);
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return; // don't print "+%g0"
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}
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if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
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set_mem_access(MI, false);
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return; // don't print "+0"
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}
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SStream_concat0(O, "+"); // qq
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printOperand(MI, opNum + 1, O);
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set_mem_access(MI, false);
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}
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static void printCCOperand(MCInst *MI, int opNum, SStream *O)
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{
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int CC = (int)MCOperand_getImm(MCInst_getOperand(MI, opNum)) + 256;
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switch (MCInst_getOpcode(MI)) {
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default: break;
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case SP_FBCOND:
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case SP_FBCONDA:
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case SP_BPFCC:
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case SP_BPFCCA:
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case SP_BPFCCNT:
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case SP_BPFCCANT:
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case SP_MOVFCCrr: case SP_V9MOVFCCrr:
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case SP_MOVFCCri: case SP_V9MOVFCCri:
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case SP_FMOVS_FCC: case SP_V9FMOVS_FCC:
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case SP_FMOVD_FCC: case SP_V9FMOVD_FCC:
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case SP_FMOVQ_FCC: case SP_V9FMOVQ_FCC:
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// Make sure CC is a fp conditional flag.
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CC = (CC < 16+256) ? (CC + 16) : CC;
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break;
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}
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SStream_concat0(O, SPARCCondCodeToString((sparc_cc)CC));
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if (MI->csh->detail)
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MI->flat_insn->detail->sparc.cc = (sparc_cc)CC;
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}
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static bool printGetPCX(MCInst *MI, unsigned opNum, SStream *O)
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{
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return true;
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}
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#define PRINT_ALIAS_INSTR
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#include "SparcGenAsmWriter.inc"
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void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
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{
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char *mnem, *p;
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char instr[64]; // Sparc has no instruction this long
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mnem = printAliasInstr(MI, O, Info);
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if (mnem) {
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// fixup instruction id due to the change in alias instruction
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strncpy(instr, mnem, sizeof(instr));
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instr[sizeof(instr) - 1] = '\0';
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// does this contains hint with a coma?
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p = strchr(instr, ',');
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if (p)
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*p = '\0'; // now instr only has instruction mnemonic
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MCInst_setOpcodePub(MI, Sparc_map_insn(instr));
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switch(MCInst_getOpcode(MI)) {
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case SP_BCOND:
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case SP_BCONDA:
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case SP_BPICCANT:
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case SP_BPICCNT:
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case SP_BPXCCANT:
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case SP_BPXCCNT:
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case SP_TXCCri:
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case SP_TXCCrr:
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if (MI->csh->detail) {
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// skip 'b', 't'
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MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 1);
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MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
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}
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break;
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case SP_BPFCCANT:
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case SP_BPFCCNT:
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if (MI->csh->detail) {
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// skip 'fb'
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MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 2);
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MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
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}
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break;
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case SP_FMOVD_ICC:
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case SP_FMOVD_XCC:
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case SP_FMOVQ_ICC:
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case SP_FMOVQ_XCC:
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case SP_FMOVS_ICC:
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case SP_FMOVS_XCC:
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if (MI->csh->detail) {
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// skip 'fmovd', 'fmovq', 'fmovs'
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MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 5);
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MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
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}
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break;
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case SP_MOVICCri:
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case SP_MOVICCrr:
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case SP_MOVXCCri:
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case SP_MOVXCCrr:
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if (MI->csh->detail) {
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// skip 'mov'
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MI->flat_insn->detail->sparc.cc = Sparc_map_ICC(instr + 3);
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MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
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}
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break;
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case SP_V9FMOVD_FCC:
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case SP_V9FMOVQ_FCC:
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case SP_V9FMOVS_FCC:
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if (MI->csh->detail) {
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// skip 'fmovd', 'fmovq', 'fmovs'
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MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 5);
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MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
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}
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break;
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case SP_V9MOVFCCri:
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case SP_V9MOVFCCrr:
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if (MI->csh->detail) {
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// skip 'mov'
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MI->flat_insn->detail->sparc.cc = Sparc_map_FCC(instr + 3);
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MI->flat_insn->detail->sparc.hint = Sparc_map_hint(mnem);
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}
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break;
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default:
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break;
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}
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cs_mem_free(mnem);
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} else {
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if (!printSparcAliasInstr(MI, O))
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printInstruction(MI, O, NULL);
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}
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}
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void Sparc_addReg(MCInst *MI, int reg)
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{
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if (MI->csh->detail) {
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
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MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
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MI->flat_insn->detail->sparc.op_count++;
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}
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}
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#endif
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