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795 lines
24 KiB
795 lines
24 KiB
//===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_XCORE
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#include <stdio.h> // DEBUG
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#include <stdlib.h>
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#include <string.h>
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "XCoreDisassembler.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCDisassembler.h"
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#include "../../MathExtras.h"
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static uint64_t getFeatureBits(int mode)
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{
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// support everything
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return (uint64_t)-1;
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}
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static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn)
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{
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if (code_len < 2)
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// insufficient data
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return false;
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// Encoded as a little-endian 16-bit word in the stream.
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*insn = (code[0] << 0) | (code[1] << 8);
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return true;
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}
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static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn)
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{
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if (code_len < 4)
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// insufficient data
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return false;
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// Encoded as a little-endian 32-bit word in the stream.
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*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24);
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return true;
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}
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static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
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{
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const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
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return rc->RegsBegin[RegNo];
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}
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_MC_DESC
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#include "XCoreGenRegisterInfo.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg;
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if (RegNo > 11)
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return MCDisassembler_Fail;
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Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo);
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg;
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if (RegNo > 15)
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return MCDisassembler_Fail;
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Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo);
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
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uint64_t Address, const void *Decoder)
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{
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static const unsigned Values[] = {
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32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
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};
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if (Val > 11)
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return MCDisassembler_Fail;
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MCOperand_CreateImm0(Inst, Values[Val]);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
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uint64_t Address, const void *Decoder)
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{
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MCOperand_CreateImm0(Inst, -(int64_t)Val);
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return MCDisassembler_Success;
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}
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static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2)
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{
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unsigned Op1High, Op2High;
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unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
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if (Combined < 27)
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return MCDisassembler_Fail;
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if (fieldFromInstruction_4(Insn, 5, 1)) {
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if (Combined == 31)
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return MCDisassembler_Fail;
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Combined += 5;
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}
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Combined -= 27;
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Op1High = Combined % 3;
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Op2High = Combined / 3;
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*Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2);
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*Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2);
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return MCDisassembler_Success;
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}
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static DecodeStatus Decode3OpInstruction(unsigned Insn,
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unsigned *Op1, unsigned *Op2, unsigned *Op3)
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{
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unsigned Op1High, Op2High, Op3High;
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unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
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if (Combined >= 27)
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return MCDisassembler_Fail;
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Op1High = Combined % 3;
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Op2High = (Combined / 3) % 3;
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Op3High = Combined / 9;
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*Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2);
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*Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2);
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*Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2);
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return MCDisassembler_Success;
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}
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#define GET_INSTRINFO_ENUM
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#include "XCoreGenInstrInfo.inc"
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static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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// Try and decode as a 3R instruction.
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unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
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switch (Opcode) {
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case 0x0:
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MCInst_setOpcode(Inst, XCore_STW_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x1:
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MCInst_setOpcode(Inst, XCore_LDW_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x2:
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MCInst_setOpcode(Inst, XCore_ADD_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x3:
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MCInst_setOpcode(Inst, XCore_SUB_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x4:
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MCInst_setOpcode(Inst, XCore_SHL_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x5:
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MCInst_setOpcode(Inst, XCore_SHR_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x6:
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MCInst_setOpcode(Inst, XCore_EQ_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x7:
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MCInst_setOpcode(Inst, XCore_AND_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x8:
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MCInst_setOpcode(Inst, XCore_OR_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x9:
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MCInst_setOpcode(Inst, XCore_LDW_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x10:
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MCInst_setOpcode(Inst, XCore_LD16S_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x11:
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MCInst_setOpcode(Inst, XCore_LD8U_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x12:
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MCInst_setOpcode(Inst, XCore_ADD_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x13:
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MCInst_setOpcode(Inst, XCore_SUB_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x14:
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MCInst_setOpcode(Inst, XCore_SHL_2rus);
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return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
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case 0x15:
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MCInst_setOpcode(Inst, XCore_SHR_2rus);
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return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
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case 0x16:
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MCInst_setOpcode(Inst, XCore_EQ_2rus);
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return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
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case 0x17:
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MCInst_setOpcode(Inst, XCore_TSETR_3r);
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return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
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case 0x18:
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MCInst_setOpcode(Inst, XCore_LSS_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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case 0x19:
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MCInst_setOpcode(Inst, XCore_LSU_3r);
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return Decode3RInstruction(Inst, Insn, Address, Decoder);
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}
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return MCDisassembler_Fail;
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}
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static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
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if (S != MCDisassembler_Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
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if (S != MCDisassembler_Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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MCOperand_CreateImm0(Inst, Op1);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
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if (S != MCDisassembler_Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
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if (S != MCDisassembler_Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
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if (S != MCDisassembler_Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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MCOperand_CreateImm0(Inst, Op2);
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return S;
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}
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static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
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if (S != MCDisassembler_Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
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if (S != MCDisassembler_Success)
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return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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return S;
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}
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static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
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const void *Decoder)
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{
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// Try and decode as a L3R / L2RUS instruction.
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unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
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fieldFromInstruction_4(Insn, 27, 5) << 4;
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switch (Opcode) {
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case 0x0c:
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MCInst_setOpcode(Inst, XCore_STW_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x1c:
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MCInst_setOpcode(Inst, XCore_XOR_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x2c:
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MCInst_setOpcode(Inst, XCore_ASHR_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x3c:
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MCInst_setOpcode(Inst, XCore_LDAWF_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x4c:
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MCInst_setOpcode(Inst, XCore_LDAWB_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x5c:
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MCInst_setOpcode(Inst, XCore_LDA16F_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x6c:
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MCInst_setOpcode(Inst, XCore_LDA16B_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x7c:
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MCInst_setOpcode(Inst, XCore_MUL_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x8c:
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MCInst_setOpcode(Inst, XCore_DIVS_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x9c:
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MCInst_setOpcode(Inst, XCore_DIVU_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x10c:
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MCInst_setOpcode(Inst, XCore_ST16_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x11c:
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MCInst_setOpcode(Inst, XCore_ST8_l3r);
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return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
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case 0x12c:
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MCInst_setOpcode(Inst, XCore_ASHR_l2rus);
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|
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x12d:
|
|
MCInst_setOpcode(Inst, XCore_OUTPW_l2rus);
|
|
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x12e:
|
|
MCInst_setOpcode(Inst, XCore_INPW_l2rus);
|
|
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x13c:
|
|
MCInst_setOpcode(Inst, XCore_LDAWF_l2rus);
|
|
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x14c:
|
|
MCInst_setOpcode(Inst, XCore_LDAWB_l2rus);
|
|
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x15c:
|
|
MCInst_setOpcode(Inst, XCore_CRC_l3r);
|
|
return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x18c:
|
|
MCInst_setOpcode(Inst, XCore_REMS_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
case 0x19c:
|
|
MCInst_setOpcode(Inst, XCore_REMU_l3r);
|
|
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
|
|
}
|
|
|
|
return MCDisassembler_Fail;
|
|
}
|
|
|
|
static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2;
|
|
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
|
|
if (S != MCDisassembler_Success)
|
|
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
|
|
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2;
|
|
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
|
|
if (S != MCDisassembler_Success)
|
|
return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
|
|
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
MCOperand_CreateImm0(Inst, Op1);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
MCOperand_CreateImm0(Inst, Op3);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeBitpOperand(Inst, Op3, Address, Decoder);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
MCOperand_CreateImm0(Inst, Op3);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeBitpOperand(Inst, Op3, Address, Decoder);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3, Op4, Op5, Op6;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S != MCDisassembler_Success)
|
|
return S;
|
|
|
|
S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6);
|
|
if (S != MCDisassembler_Success)
|
|
return S;
|
|
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Opcode;
|
|
|
|
// Try and decode as a L6R instruction.
|
|
MCInst_clear(Inst);
|
|
Opcode = fieldFromInstruction_4(Insn, 27, 5);
|
|
switch (Opcode) {
|
|
default:
|
|
break;
|
|
case 0x00:
|
|
MCInst_setOpcode(Inst, XCore_LMUL_l6r);
|
|
return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
|
|
}
|
|
|
|
return MCDisassembler_Fail;
|
|
}
|
|
|
|
static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3, Op4, Op5;
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S != MCDisassembler_Success)
|
|
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
|
|
|
|
S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5);
|
|
if (S != MCDisassembler_Success)
|
|
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
|
|
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
}
|
|
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
return S;
|
|
}
|
|
|
|
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
unsigned Op1, Op2, Op3;
|
|
unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
|
|
DecodeStatus S =
|
|
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
}
|
|
|
|
if (S == MCDisassembler_Success) {
|
|
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
|
|
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
|
|
}
|
|
|
|
return S;
|
|
}
|
|
|
|
#define GET_SUBTARGETINFO_ENUM
|
|
#include "XCoreGenInstrInfo.inc"
|
|
bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
|
|
uint16_t *size, uint64_t address, void *info)
|
|
{
|
|
uint16_t insn16;
|
|
uint32_t insn32;
|
|
DecodeStatus Result;
|
|
|
|
if (!readInstruction16(code, code_len, &insn16)) {
|
|
return false;
|
|
}
|
|
|
|
if (MI->flat_insn->detail) {
|
|
memset(MI->flat_insn->detail, 0, offsetof(cs_detail, xcore)+sizeof(cs_xcore));
|
|
}
|
|
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0);
|
|
if (Result != MCDisassembler_Fail) {
|
|
*size = 2;
|
|
return true;
|
|
}
|
|
|
|
if (!readInstruction32(code, code_len, &insn32)) {
|
|
return false;
|
|
}
|
|
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0);
|
|
if (Result != MCDisassembler_Fail) {
|
|
*size = 4;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void XCore_init(MCRegisterInfo *MRI)
|
|
{
|
|
/*
|
|
InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
|
|
XCoreMCRegisterClasses, 2,
|
|
XCoreRegUnitRoots,
|
|
16,
|
|
XCoreRegDiffLists,
|
|
XCoreRegStrings,
|
|
XCoreSubRegIdxLists,
|
|
1,
|
|
XCoreSubRegIdxRanges,
|
|
XCoreRegEncodingTable);
|
|
*/
|
|
|
|
|
|
MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17,
|
|
0, 0,
|
|
XCoreMCRegisterClasses, 2,
|
|
0, 0,
|
|
XCoreRegDiffLists,
|
|
0,
|
|
XCoreSubRegIdxLists, 1,
|
|
0);
|
|
}
|
|
|
|
#endif
|