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215 lines
7.2 KiB
215 lines
7.2 KiB
(* Capstone Disassembly Engine
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* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 *)
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open Arm
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open Arm64
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open Mips
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open Ppc
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open X86
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open Sparc
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open Systemz
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open Xcore
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open M680x
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open Printf (* debug *)
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(* Hardware architectures *)
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type arch =
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| CS_ARCH_ARM
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| CS_ARCH_ARM64
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| CS_ARCH_MIPS
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| CS_ARCH_X86
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| CS_ARCH_PPC
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| CS_ARCH_SPARC
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| CS_ARCH_SYSZ
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| CS_ARCH_XCORE
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| CS_ARCH_M68K
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| CS_ARCH_TMS320C64X
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| CS_ARCH_M680X
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(* Hardware modes *)
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type mode =
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| CS_MODE_LITTLE_ENDIAN (* little-endian mode (default mode) *)
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| CS_MODE_ARM (* ARM mode *)
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| CS_MODE_16 (* 16-bit mode (for X86) *)
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| CS_MODE_32 (* 32-bit mode (for X86) *)
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| CS_MODE_64 (* 64-bit mode (for X86, PPC) *)
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| CS_MODE_THUMB (* ARM's Thumb mode, including Thumb-2 *)
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| CS_MODE_MCLASS (* ARM's MClass mode *)
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| CS_MODE_V8 (* ARMv8 A32 encodings for ARM *)
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| CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *)
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| CS_MODE_MIPS3 (* Mips3 mode (MIPS architecture) *)
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| CS_MODE_MIPS32R6 (* Mips32-R6 mode (MIPS architecture) *)
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| CS_MODE_MIPS2 (* Mips2 mode (MIPS architecture) *)
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| CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *)
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| CS_MODE_BIG_ENDIAN (* big-endian mode *)
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| CS_MODE_MIPS32 (* Mips32 mode (for Mips) *)
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| CS_MODE_MIPS64 (* Mips64 mode (for Mips) *)
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| CS_MODE_QPX (* Quad Processing eXtensions mode (PowerPC) *)
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| CS_MODE_M680X_6301 (* M680X Hitachi 6301,6303 mode *)
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| CS_MODE_M680X_6309 (* M680X Hitachi 6309 mode *)
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| CS_MODE_M680X_6800 (* M680X Motorola 6800,6802 mode *)
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| CS_MODE_M680X_6801 (* M680X Motorola 6801,6803 mode *)
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| CS_MODE_M680X_6805 (* M680X Motorola 6805 mode *)
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| CS_MODE_M680X_6808 (* M680X Motorola 6808 mode *)
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| CS_MODE_M680X_6809 (* M680X Motorola 6809 mode *)
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| CS_MODE_M680X_6811 (* M680X Motorola/Freescale 68HC11 mode *)
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| CS_MODE_M680X_CPU12 (* M680X Motorola/Freescale/NXP CPU12 mode *)
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| CS_MODE_M680X_HCS08 (* M680X Freescale HCS08 mode *)
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(* Runtime option for the disassembled engine *)
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type opt_type =
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| CS_OPT_SYNTAX (* Asssembly output syntax *)
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| CS_OPT_DETAIL (* Break down instruction structure into details *)
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| CS_OPT_MODE (* Change engine's mode at run-time *)
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| CS_OPT_MEM (* User-defined dynamic memory related functions *)
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| CS_OPT_SKIPDATA (* Skip data when disassembling. Then engine is in SKIPDATA mode. *)
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| CS_OPT_SKIPDATA_SETUP (* Setup user-defined function for SKIPDATA option *)
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(* Common instruction operand access types - to be consistent across all architectures. *)
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(* It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE *)
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let _CS_AC_INVALID = 0;; (* Uninitialized/invalid access type. *)
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let _CS_AC_READ = 1 lsl 0;; (* Operand read from memory or register. *)
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let _CS_AC_WRITE = 1 lsl 1;; (* Operand write to memory or register. *)
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(* Runtime option value (associated with option type above) *)
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let _CS_OPT_OFF = 0L;; (* Turn OFF an option - default option of CS_OPT_DETAIL, CS_OPT_SKIPDATA. *)
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let _CS_OPT_ON = 3L;; (* Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA). *)
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let _CS_OPT_SYNTAX_DEFAULT = 0L;; (* Default asm syntax (CS_OPT_SYNTAX). *)
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let _CS_OPT_SYNTAX_INTEL = 1L;; (* X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX). *)
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let _CS_OPT_SYNTAX_ATT = 2L;; (* X86 ATT asm syntax (CS_OPT_SYNTAX). *)
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let _CS_OPT_SYNTAX_NOREGNAME = 3L;; (* Prints register name with only number (CS_OPT_SYNTAX) *)
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(* Common instruction operand types - to be consistent across all architectures. *)
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let _CS_OP_INVALID = 0;; (* uninitialized/invalid operand. *)
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let _CS_OP_REG = 1;; (* Register operand. *)
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let _CS_OP_IMM = 2;; (* Immediate operand. *)
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let _CS_OP_MEM = 3;; (* Memory operand. *)
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let _CS_OP_FP = 4;; (* Floating-Point operand. *)
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(* Common instruction groups - to be consistent across all architectures. *)
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let _CS_GRP_INVALID = 0;; (* uninitialized/invalid group. *)
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let _CS_GRP_JUMP = 1;; (* all jump instructions (conditional+direct+indirect jumps) *)
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let _CS_GRP_CALL = 2;; (* all call instructions *)
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let _CS_GRP_RET = 3;; (* all return instructions *)
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let _CS_GRP_INT = 4;; (* all interrupt instructions (int+syscall) *)
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let _CS_GRP_IRET = 5;; (* all interrupt return instructions *)
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let _CS_GRP_PRIVILEGE = 6;; (* all privileged instructions *)
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type cs_arch =
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| CS_INFO_ARM of cs_arm
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| CS_INFO_ARM64 of cs_arm64
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| CS_INFO_MIPS of cs_mips
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| CS_INFO_X86 of cs_x86
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| CS_INFO_PPC of cs_ppc
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| CS_INFO_SPARC of cs_sparc
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| CS_INFO_SYSZ of cs_sysz
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| CS_INFO_XCORE of cs_xcore
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| CS_INFO_M680X of cs_m680x
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type csh = {
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h: Int64.t;
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a: arch;
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}
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type cs_insn0 = {
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id: int;
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address: int;
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size: int;
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bytes: int array;
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mnemonic: string;
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op_str: string;
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regs_read: int array;
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regs_write: int array;
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groups: int array;
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arch: cs_arch;
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}
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external _cs_open: arch -> mode list -> Int64.t option = "ocaml_open"
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external cs_disasm_quick: arch -> mode list -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm"
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external _cs_disasm_internal: arch -> Int64.t -> string -> Int64.t -> Int64.t -> cs_insn0 list = "ocaml_cs_disasm_internal"
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external _cs_reg_name: Int64.t -> int -> string = "ocaml_register_name"
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external _cs_insn_name: Int64.t -> int -> string = "ocaml_instruction_name"
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external _cs_group_name: Int64.t -> int -> string = "ocaml_group_name"
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external cs_version: unit -> int = "ocaml_version"
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external _cs_option: Int64.t -> opt_type -> Int64.t -> int = "ocaml_option"
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external _cs_close: Int64.t -> int = "ocaml_close"
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let cs_open _arch _mode: csh = (
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let _handle = _cs_open _arch _mode in (
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match _handle with
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| None -> { h = 0L; a = _arch }
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| Some v -> { h = v; a = _arch }
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);
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);;
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let cs_close handle = (
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_cs_close handle.h;
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)
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let cs_option handle opt value = (
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_cs_option handle.h opt value;
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);;
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let cs_disasm handle code address count = (
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_cs_disasm_internal handle.a handle.h code address count;
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);;
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let cs_reg_name handle id = (
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_cs_reg_name handle.h id;
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);;
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let cs_insn_name handle id = (
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_cs_insn_name handle.h id;
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);;
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let cs_group_name handle id = (
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_cs_group_name handle.h id;
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);;
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class cs_insn c a =
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let csh = c in
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let (id, address, size, bytes, mnemonic, op_str, regs_read,
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regs_write, groups, arch) =
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(a.id, a.address, a.size, a.bytes, a.mnemonic, a.op_str,
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a.regs_read, a.regs_write, a.groups, a.arch) in
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object
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method id = id;
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method address = address;
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method size = size;
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method bytes = bytes;
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method mnemonic = mnemonic;
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method op_str = op_str;
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method regs_read = regs_read;
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method regs_write = regs_write;
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method groups = groups;
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method arch = arch;
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method reg_name id = _cs_reg_name csh.h id;
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method insn_name id = _cs_insn_name csh.h id;
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method group_name id = _cs_group_name csh.h id;
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end;;
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let cs_insn_group handle insn group_id =
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List.exists (fun g -> g == group_id) (Array.to_list insn.groups);;
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let cs_reg_read handle insn reg_id =
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List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_read);;
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let cs_reg_write handle insn reg_id =
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List.exists (fun g -> g == reg_id) (Array.to_list insn.regs_write);;
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class cs a m =
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let mode = m and arch = a in
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let handle = cs_open arch mode in
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object
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method disasm code offset count =
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let insns = (_cs_disasm_internal arch handle.h code offset count) in
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List.map (fun x -> new cs_insn handle x) insns;
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end;;
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