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339 lines
10 KiB
339 lines
10 KiB
From 5d631cb16e7ba5dd0380ff1ee9dda192b1cdad18 Mon Sep 17 00:00:00 2001
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From: mephi42 <mephi42@gmail.com>
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Date: Tue, 7 Aug 2018 17:02:40 +0200
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Subject: [PATCH 1/7] capstone: generate *GenRegisterInfo.inc
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---
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utils/TableGen/RegisterInfoEmitter.cpp | 130 ++++++++++++++++++++++---
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1 file changed, 115 insertions(+), 15 deletions(-)
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diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
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index 49016cca799..6ebb7148b1b 100644
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--- a/utils/TableGen/RegisterInfoEmitter.cpp
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+++ b/utils/TableGen/RegisterInfoEmitter.cpp
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@@ -99,6 +99,12 @@ private:
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} // end anonymous namespace
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+#ifdef CAPSTONE
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+#define NAME_PREFIX Target.getName() << "_" <<
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+#else
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+#define NAME_PREFIX
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+#endif
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+
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// runEnums - Print out enum values for all of the registers.
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void RegisterInfoEmitter::runEnums(raw_ostream &OS,
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CodeGenTarget &Target, CodeGenRegBank &Bank) {
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@@ -107,13 +113,22 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
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// Register enums are stored as uint16_t in the tables. Make sure we'll fit.
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assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
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+#ifndef CAPSTONE
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StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace");
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+#endif
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emitSourceFileHeader("Target Register Enum Values", OS);
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+#ifdef CAPSTONE
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+ OS << "/* Capstone Disassembly Engine */\n"
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+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n"
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+ "\n";
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+#endif
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+
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OS << "\n#ifdef GET_REGINFO_ENUM\n";
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OS << "#undef GET_REGINFO_ENUM\n\n";
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+#ifndef CAPSTONE
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OS << "namespace llvm {\n\n";
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OS << "class MCRegisterClass;\n"
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@@ -122,16 +137,20 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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- OS << "enum {\n NoRegister,\n";
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+#endif
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+
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+ OS << "enum {\n " << NAME_PREFIX "NoRegister,\n";
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for (const auto &Reg : Registers)
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- OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
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+ OS << " " << NAME_PREFIX Reg.getName() << " = " << Reg.EnumValue << ",\n";
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assert(Registers.size() == Registers.back().EnumValue &&
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"Register enum value mismatch!");
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- OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
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+ OS << " " << NAME_PREFIX "NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
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OS << "};\n";
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+#ifndef CAPSTONE
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if (!Namespace.empty())
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OS << "} // end namespace " << Namespace << "\n";
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+#endif
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const auto &RegisterClasses = Bank.getRegClasses();
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if (!RegisterClasses.empty()) {
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@@ -140,18 +159,29 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
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assert(RegisterClasses.size() <= 0xffff &&
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"Too many register classes to fit in tables");
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- OS << "\n// Register classes\n\n";
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+ OS << "\n// Register classes\n";
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+#ifndef CAPSTONE
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+ OS << "\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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+#endif
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OS << "enum {\n";
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for (const auto &RC : RegisterClasses)
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- OS << " " << RC.getName() << "RegClassID"
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+ OS << " " << NAME_PREFIX RC.getName() << "RegClassID"
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<< " = " << RC.EnumValue << ",\n";
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- OS << "\n };\n";
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+#ifdef CAPSTONE
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+ OS
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+#else
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+ OS << "\n "
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+#endif
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+ << "};\n";
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+#ifndef CAPSTONE
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if (!Namespace.empty())
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OS << "} // end namespace " << Namespace << "\n\n";
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+#endif
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}
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+#ifndef CAPSTONE
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const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
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// If the only definition is the default NoRegAltName, we don't need to
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// emit anything.
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@@ -182,8 +212,11 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS,
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if (!Namespace.empty())
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OS << "} // end namespace " << Namespace << "\n\n";
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}
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+#endif
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+#ifndef CAPSTONE
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OS << "} // end namespace llvm\n\n";
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+#endif
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OS << "#endif // GET_REGINFO_ENUM\n\n";
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}
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@@ -830,7 +863,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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const auto &Regs = RegBank.getRegisters();
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+#ifndef CAPSTONE
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auto &SubRegIndices = RegBank.getSubRegIndices();
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+#endif
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// The lists of sub-registers and super-registers go in the same array. That
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// allows us to share suffixes.
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typedef std::vector<const CodeGenRegister*> RegVec;
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@@ -922,25 +957,40 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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LaneMaskSeqs.layout();
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SubRegIdxSeqs.layout();
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+#ifndef CAPSTONE
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OS << "namespace llvm {\n\n";
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+#endif
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const std::string &TargetName = Target.getName();
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// Emit the shared table of differential lists.
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- OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
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+#ifdef CAPSTONE
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+ OS << "static"
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+#else
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+ OS << "extern"
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+#endif
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+ << " const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
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DiffSeqs.emit(OS, printDiff16);
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OS << "};\n\n";
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+#ifndef CAPSTONE
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// Emit the shared table of regunit lane mask sequences.
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OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n";
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LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()");
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OS << "};\n\n";
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+#endif
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// Emit the table of sub-register indexes.
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- OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
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+#ifdef CAPSTONE
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+ OS << "static"
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+#else
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+ OS << "extern"
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+#endif
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+ << " const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
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SubRegIdxSeqs.emit(OS, printSubRegIndex);
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OS << "};\n\n";
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+#ifndef CAPSTONE
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// Emit the table of sub-register index sizes.
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OS << "extern const MCRegisterInfo::SubRegCoveredBits "
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<< TargetName << "SubRegIdxRanges[] = {\n";
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@@ -950,14 +1000,22 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< Idx.getName() << "\n";
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}
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OS << "};\n\n";
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+#endif
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// Emit the string table.
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RegStrings.layout();
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+#ifndef CAPSTONE
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OS << "extern const char " << TargetName << "RegStrings[] = {\n";
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RegStrings.emit(OS, printChar);
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OS << "};\n\n";
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+#endif
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- OS << "extern const MCRegisterDesc " << TargetName
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+#ifdef CAPSTONE
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+ OS << "static"
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+#else
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+ OS << "extern"
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+#endif
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+ << " const MCRegisterDesc " << TargetName
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<< "RegDesc[] = { // Descriptors\n";
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OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n";
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@@ -973,6 +1031,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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}
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OS << "};\n\n"; // End of register descriptors...
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+#ifndef CAPSTONE
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// Emit the table of register unit roots. Each regunit has one or two root
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// registers.
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OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
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@@ -986,11 +1045,14 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << " },\n";
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}
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OS << "};\n\n";
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+#endif
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const auto &RegisterClasses = RegBank.getRegClasses();
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// Loop over all of the register classes... emitting each one.
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+#ifndef CAPSTONE
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OS << "namespace { // Register classes...\n";
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+#endif
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SequenceToOffsetTable<std::string> RegClassStrings;
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@@ -1005,15 +1067,28 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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// Emit the register list now.
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OS << " // " << Name << " Register Class...\n"
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- << " const MCPhysReg " << Name
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+ << " "
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+#ifdef CAPSTONE
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+ << "static "
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+#endif
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+ << "const MCPhysReg " << Name
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<< "[] = {\n ";
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for (Record *Reg : Order) {
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- OS << getQualifiedName(Reg) << ", ";
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+#ifdef CAPSTONE
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+ OS << NAME_PREFIX Reg->getName()
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+#else
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+ OS << getQualifiedName(Reg)
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+#endif
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+ << ", ";
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}
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OS << "\n };\n\n";
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OS << " // " << Name << " Bit set.\n"
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- << " const uint8_t " << Name
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+ << " "
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+#ifdef CAPSTONE
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+ << "static "
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+#endif
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+ << "const uint8_t " << Name
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<< "Bits[] = {\n ";
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BitVectorEmitter BVE;
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for (Record *Reg : Order) {
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@@ -1023,14 +1098,23 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << "\n };\n\n";
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}
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+#ifndef CAPSTONE
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OS << "} // end anonymous namespace\n\n";
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+#endif
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RegClassStrings.layout();
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+#ifndef CAPSTONE
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OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
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RegClassStrings.emit(OS, printChar);
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OS << "};\n\n";
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+#endif
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- OS << "extern const MCRegisterClass " << TargetName
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+#ifdef CAPSTONE
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+ OS << "static"
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+#else
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+ OS << "extern"
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+#endif
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+ << " const MCRegisterClass " << TargetName
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<< "MCRegisterClasses[] = {\n";
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for (const auto &RC : RegisterClasses) {
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@@ -1041,7 +1125,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
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<< RegClassStrings.get(RC.getName()) << ", "
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<< RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
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- << RC.getQualifiedName() + "RegClassID" << ", "
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+#ifdef CAPSTONE
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+ << NAME_PREFIX RC.getName()
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+#else
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+ << RC.getQualifiedName()
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+#endif
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+ << "RegClassID" << ", "
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<< RegSize/8 << ", "
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<< RC.CopyCost << ", "
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<< ( RC.Allocatable ? "true" : "false" ) << " },\n";
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@@ -1049,6 +1138,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << "};\n\n";
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+#ifndef CAPSTONE
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EmitRegMappingTables(OS, Regs, false);
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// Emit Reg encoding table
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@@ -1067,7 +1157,9 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << " " << Value << ",\n";
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}
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OS << "};\n"; // End of HW encoding table
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+#endif
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+#ifndef CAPSTONE
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// MCRegisterInfo initialization routine.
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OS << "static inline void Init" << TargetName
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<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
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@@ -1088,7 +1180,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << "}\n\n";
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OS << "} // end namespace llvm\n\n";
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- OS << "#endif // GET_REGINFO_MC_DESC\n\n";
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+#endif
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+ OS << "#endif // GET_REGINFO_MC_DESC\n"
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+#ifndef CAPSTONE
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+ << "\n"
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+#endif
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+ ;
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}
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void
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@@ -1568,10 +1665,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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void RegisterInfoEmitter::run(raw_ostream &OS) {
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CodeGenRegBank &RegBank = Target.getRegBank();
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+
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runEnums(OS, Target, RegBank);
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runMCDesc(OS, Target, RegBank);
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+#ifndef CAPSTONE
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runTargetHeader(OS, Target, RegBank);
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runTargetDesc(OS, Target, RegBank);
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+#endif
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if (RegisterInfoDebug)
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debugDump(errs());
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--
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2.19.1
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