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226 lines
7.3 KiB
226 lines
7.3 KiB
From 5569e48b9cb34a33910e1e850fbfabc999f016a2 Mon Sep 17 00:00:00 2001
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From: mephi42 <mephi42@gmail.com>
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Date: Tue, 7 Aug 2018 20:00:08 +0200
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Subject: [PATCH 5/7] capstone: generate *GenAsmWriter.inc
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---
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utils/TableGen/AsmWriterEmitter.cpp | 89 +++++++++++++++++++++++++++--
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utils/TableGen/AsmWriterInst.cpp | 4 ++
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2 files changed, 87 insertions(+), 6 deletions(-)
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diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
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index 3c4c9c8e5c6..133800d217c 100644
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--- a/utils/TableGen/AsmWriterEmitter.cpp
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+++ b/utils/TableGen/AsmWriterEmitter.cpp
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@@ -272,16 +272,22 @@ static void UnescapeString(std::string &Str) {
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/// clearing the Instructions vector.
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void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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Record *AsmWriter = Target.getAsmWriter();
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+#ifndef CAPSTONE
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StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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+#endif
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bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
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O <<
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"/// printInstruction - This method is automatically generated by tablegen\n"
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"/// from the instruction set description.\n"
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+#ifdef CAPSTONE
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+ "static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)\n{\n";
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+#else
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"void " << Target.getName() << ClassName
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<< "::printInstruction(const MCInst *MI, "
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<< (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
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<< "raw_ostream &O) {\n";
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+#endif
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// Build an aggregate string, and build a table of offsets into it.
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SequenceToOffsetTable<std::string> StringTable;
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@@ -379,9 +385,16 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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}
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// Emit the string table itself.
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+#ifdef CAPSTONE
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+ O << "#ifndef CAPSTONE_DIET\n";
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+#endif
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O << " static const char AsmStrs[] = {\n";
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StringTable.emit(O, printChar);
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- O << " };\n\n";
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+ O << " };\n"
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+#ifdef CAPSTONE
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+ << "#endif\n"
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+#endif
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+ << "\n";
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// Emit the lookup tables in pieces to minimize wasted bytes.
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unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8;
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@@ -409,21 +422,45 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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// If the total bits is more than 32-bits we need to use a 64-bit type.
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if (BitsLeft < (OpcodeInfoBits - 32))
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BitsOS << "(uint64_t)";
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- BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n";
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+ BitsOS << "OpInfo" << Table << "["
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+#ifdef CAPSTONE
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+ << "MCInst_getOpcode(MI)"
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+#else
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+ << "MI->getOpcode()"
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+#endif
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+ << "] << " << Shift << ";\n";
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// Prepare the shift for the next iteration and increment the table count.
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Shift += TableSize;
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++Table;
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}
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// Emit the initial tab character.
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+#ifndef CAPSTONE
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O << " O << \"\\t\";\n\n";
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+#endif
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O << " // Emit the opcode for the instruction.\n";
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O << BitsString;
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// Emit the starting string.
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- O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"
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- << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n";
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+ O << " "
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+#ifdef CAPSTONE
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+ << "// "
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+#endif
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+ << "assert(Bits != 0 && \"Cannot print this instruction.\");\n"
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+#ifdef CAPSTONE
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+ << "#ifndef CAPSTONE_DIET\n"
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+ << " SStream_concat0(O, "
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+#else
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+ << " O << "
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+#endif
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+ << "AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1"
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+#ifdef CAPSTONE
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+ << ");\n"
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+ << "#endif\n\n";
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+#else
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+ << ");\n\n";
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+#endif
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// Output the table driven operand information.
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BitsLeft = OpcodeInfoBits-AsmStrBits;
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@@ -455,7 +492,11 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
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O << " switch ((Bits >> "
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<< (OpcodeInfoBits-BitsLeft) << ") & "
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<< ((1 << NumBits)-1) << ") {\n"
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- << " default: llvm_unreachable(\"Invalid command number.\");\n";
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+ << " default: "
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+#ifdef CAPSTONE
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+ << "// "
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+#endif
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+ << "llvm_unreachable(\"Invalid command number.\");\n";
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// Print out all the cases.
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for (unsigned j = 0, e = Commands.size(); j != e; ++j) {
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@@ -536,6 +577,9 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
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}
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StringTable.layout();
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+#ifdef CAPSTONE
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+ O << "#ifndef CAPSTONE_DIET\n";
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+#endif
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O << " static const char AsmStrs" << AltName << "[] = {\n";
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StringTable.emit(O, printChar);
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O << " };\n\n";
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@@ -552,8 +596,10 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
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}
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void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
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+#ifndef CAPSTONE
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Record *AsmWriter = Target.getAsmWriter();
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StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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+#endif
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const auto &Registers = Target.getRegBank().getRegisters();
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const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices();
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bool hasAltNames = AltNameIndices.size() > 1;
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@@ -563,12 +609,20 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
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"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
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"/// from the register set description. This returns the assembler name\n"
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"/// for the specified register.\n"
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+#ifdef CAPSTONE
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+ "static const char *getRegisterName(unsigned RegNo)\n{\n";
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+#else
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"const char *" << Target.getName() << ClassName << "::";
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if (hasAltNames)
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O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n";
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else
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O << "getRegisterName(unsigned RegNo) {\n";
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- O << " assert(RegNo && RegNo < " << (Registers.size()+1)
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+#endif
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+ O << " "
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+#ifdef CAPSTONE
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+ << "// "
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+#endif
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+ << "assert(RegNo && RegNo < " << (Registers.size()+1)
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<< " && \"Invalid register number!\");\n"
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<< "\n";
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@@ -595,10 +649,22 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
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}
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O << " }\n";
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} else {
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+#ifdef CAPSTONE
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+ O << " //int i;\n"
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+ << " //for (i = 0; i < sizeof(RegAsmOffset); i++)\n"
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+ << " // printf(\"%s = %u\\n\", AsmStrs+RegAsmOffset[i], i + 1);\n"
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+ << " //printf(\"*************************\\n\");\n"
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+#else
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O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
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<< " \"Invalid alt name index for register!\");\n"
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+#endif
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<< " return AsmStrs+RegAsmOffset[RegNo-1];\n";
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}
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+#ifdef CAPSTONE
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+ O << "#else\n"
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+ << " return NULL;\n"
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+ << "#endif\n";
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+#endif
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O << "}\n";
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}
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@@ -1135,9 +1201,20 @@ AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
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}
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void AsmWriterEmitter::run(raw_ostream &O) {
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+#ifdef CAPSTONE
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+ O << "/* Capstone Disassembly Engine */\n"
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+ "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */\n"
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+ "\n"
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+ "#include <stdio.h>\t// debug\n"
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+ "#include <capstone/platform.h>\n"
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+ "\n"
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+ "\n";
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+#endif
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EmitPrintInstruction(O);
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EmitGetRegisterName(O);
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+#ifndef CAPSTONE
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EmitPrintAliasInstruction(O);
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+#endif
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}
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namespace llvm {
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diff --git a/utils/TableGen/AsmWriterInst.cpp b/utils/TableGen/AsmWriterInst.cpp
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index 2c19e5d663d..6fa751e50df 100644
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--- a/utils/TableGen/AsmWriterInst.cpp
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+++ b/utils/TableGen/AsmWriterInst.cpp
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@@ -28,9 +28,13 @@ static bool isIdentChar(char C) {
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std::string AsmWriterOperand::getCode(bool PassSubtarget) const {
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if (OperandType == isLiteralTextOperand) {
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+#ifdef CAPSTONE
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+ return "SStream_concat0(O, \"" + Str + "\");";
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+#else
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if (Str.size() == 1)
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return "O << '" + Str + "';";
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return "O << \"" + Str + "\";";
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+#endif
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}
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if (OperandType == isLiteralStatementOperand)
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--
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2.19.1
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