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485 lines
13 KiB
485 lines
13 KiB
//===------ SystemZDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_SYSZ
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#include <stdio.h> // DEBUG
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#include <stdlib.h>
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#include <string.h>
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "SystemZDisassembler.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCDisassembler.h"
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#include "../../MathExtras.h"
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#include "SystemZMCTargetDesc.h"
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static uint64_t getFeatureBits(int mode)
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{
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// support everything
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return (uint64_t)-1;
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}
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static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs)
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{
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//assert(RegNo < 16 && "Invalid register");
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RegNo = Regs[RegNo];
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if (RegNo == 0)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, (unsigned)RegNo);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeGR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR32Regs);
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}
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static DecodeStatus DecodeGRH32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GRH32Regs);
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}
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static DecodeStatus DecodeGR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs);
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}
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static DecodeStatus DecodeGR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR128Regs);
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}
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static DecodeStatus DecodeADDR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_GR64Regs);
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}
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static DecodeStatus DecodeFP32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_FP32Regs);
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}
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static DecodeStatus DecodeFP64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_FP64Regs);
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}
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static DecodeStatus DecodeFP128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_FP128Regs);
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}
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static DecodeStatus DecodeVR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_VR32Regs);
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}
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static DecodeStatus DecodeVR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_VR64Regs);
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}
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static DecodeStatus DecodeVR128BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_VR128Regs);
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}
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static DecodeStatus DecodeAR32BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_AR32Regs);
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}
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static DecodeStatus DecodeCR64BitRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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return decodeRegisterClass(Inst, RegNo, SystemZMC_CR64Regs);
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}
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static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm)
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{
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//assert(isUInt<N>(Imm) && "Invalid immediate");
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MCOperand_CreateImm0(Inst, Imm);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N)
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{
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//assert(isUInt<N>(Imm) && "Invalid immediate");
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MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeU1ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU2ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU3ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU8ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU12ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU16ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeU32ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeUImmOperand(Inst, Imm);
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}
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static DecodeStatus decodeS8ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeSImmOperand(Inst, Imm, 8);
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}
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static DecodeStatus decodeS16ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeSImmOperand(Inst, Imm, 16);
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}
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static DecodeStatus decodeS32ImmOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder)
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{
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return decodeSImmOperand(Inst, Imm, 32);
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}
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static DecodeStatus decodePCDBLOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address, unsigned N)
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{
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//assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
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MCOperand_CreateImm0(Inst, SignExtend64(Imm, N) * 2 + Address);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodePC12DBLBranchOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder)
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{
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return decodePCDBLOperand(Inst, Imm, Address, 12);
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}
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static DecodeStatus decodePC16DBLBranchOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder)
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{
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return decodePCDBLOperand(Inst, Imm, Address, 16);
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}
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static DecodeStatus decodePC24DBLBranchOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder)
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{
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return decodePCDBLOperand(Inst, Imm, Address, 24);
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}
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static DecodeStatus decodePC32DBLBranchOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder)
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{
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return decodePCDBLOperand(Inst, Imm, Address, 32);
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}
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static DecodeStatus decodePC32DBLOperand(MCInst *Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder)
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{
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return decodePCDBLOperand(Inst, Imm, Address, 32);
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}
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static DecodeStatus decodeBDAddr12Operand(MCInst *Inst, uint64_t Field,
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const unsigned *Regs)
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{
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uint64_t Base = Field >> 12;
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uint64_t Disp = Field & 0xfff;
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//assert(Base < 16 && "Invalid BDAddr12");
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MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
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MCOperand_CreateImm0(Inst, Disp);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeBDAddr20Operand(MCInst *Inst, uint64_t Field,
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const unsigned *Regs)
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{
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uint64_t Base = Field >> 20;
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uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
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//assert(Base < 16 && "Invalid BDAddr20");
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MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
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MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeBDXAddr12Operand(MCInst *Inst, uint64_t Field,
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const unsigned *Regs)
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{
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uint64_t Index = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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//assert(Index < 16 && "Invalid BDXAddr12");
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MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
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MCOperand_CreateImm0(Inst, Disp);
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MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeBDXAddr20Operand(MCInst *Inst, uint64_t Field,
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const unsigned *Regs)
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{
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uint64_t Index = Field >> 24;
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uint64_t Base = (Field >> 20) & 0xf;
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uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
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//assert(Index < 16 && "Invalid BDXAddr20");
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MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
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MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
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MCOperand_CreateReg0(Inst, Index == 0 ? 0 : Regs[Index]);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeBDLAddr12Len8Operand(MCInst *Inst, uint64_t Field,
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const unsigned *Regs)
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{
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uint64_t Length = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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//assert(Length < 256 && "Invalid BDLAddr12Len8");
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MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
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MCOperand_CreateImm0(Inst, Disp);
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MCOperand_CreateImm0(Inst, Length + 1);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeBDRAddr12Operand(MCInst *Inst, uint64_t Field,
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const unsigned *Regs)
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{
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uint64_t Length = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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//assert(Length < 16 && "Invalid BDRAddr12");
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MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
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MCOperand_CreateImm0(Inst, Disp);
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MCOperand_CreateReg0(Inst, Regs[Length]);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeBDVAddr12Operand(MCInst *Inst, uint64_t Field,
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const unsigned *Regs)
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{
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uint64_t Index = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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//assert(Index < 32 && "Invalid BDVAddr12");
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MCOperand_CreateReg0(Inst, Base == 0 ? 0 : Regs[Base]);
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MCOperand_CreateImm0(Inst, Disp);
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MCOperand_CreateReg0(Inst, SystemZMC_VR128Regs[Index]);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeBDAddr32Disp12Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR32Regs);
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}
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static DecodeStatus decodeBDAddr32Disp20Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR32Regs);
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}
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static DecodeStatus decodeBDAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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static DecodeStatus decodeBDAddr64Disp20Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDAddr20Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDXAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDXAddr20Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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static DecodeStatus decodeBDLAddr64Disp12Len4Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDRAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst *Inst, uint64_t Field,
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uint64_t Address, const void *Decoder)
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{
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return decodeBDVAddr12Operand(Inst, Field, SystemZMC_GR64Regs);
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}
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#define GET_SUBTARGETINFO_ENUM
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#include "SystemZGenSubtargetInfo.inc"
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#include "SystemZGenDisassemblerTables.inc"
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bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
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uint16_t *size, uint64_t address, void *info)
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{
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uint64_t Inst;
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const uint8_t *Table;
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uint16_t I;
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// The top 2 bits of the first byte specify the size.
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if (*code < 0x40) {
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*size = 2;
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Table = DecoderTable16;
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} else if (*code < 0xc0) {
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*size = 4;
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Table = DecoderTable32;
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} else {
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*size = 6;
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Table = DecoderTable48;
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}
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if (code_len < *size)
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// short of input data
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return false;
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if (MI->flat_insn->detail) {
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memset(MI->flat_insn->detail, 0, offsetof(cs_detail, sysz)+sizeof(cs_sysz));
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}
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// Construct the instruction.
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Inst = 0;
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for (I = 0; I < *size; ++I)
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Inst = (Inst << 8) | code[I];
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return decodeInstruction(Table, MI, Inst, address, info, 0);
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}
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_MC_DESC
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#include "SystemZGenRegisterInfo.inc"
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void SystemZ_init(MCRegisterInfo *MRI)
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{
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/*
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InitMCRegisterInfo(SystemZRegDesc, 98, RA, PC,
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SystemZMCRegisterClasses, 12,
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SystemZRegUnitRoots,
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49,
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SystemZRegDiffLists,
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SystemZRegStrings,
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SystemZSubRegIdxLists,
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7,
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SystemZSubRegIdxRanges,
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SystemZRegEncodingTable);
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*/
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MCRegisterInfo_InitMCRegisterInfo(MRI, SystemZRegDesc, 194,
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0, 0,
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SystemZMCRegisterClasses, 21,
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0, 0,
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SystemZRegDiffLists,
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0,
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SystemZSubRegIdxLists, 7,
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0);
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}
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#endif
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