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279 lines
9.2 KiB
279 lines
9.2 KiB
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|*Target Register Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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enum {
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TMS320C64x_NoRegister,
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TMS320C64x_AMR = 1,
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TMS320C64x_CSR = 2,
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TMS320C64x_DIER = 3,
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TMS320C64x_DNUM = 4,
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TMS320C64x_ECR = 5,
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TMS320C64x_GFPGFR = 6,
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TMS320C64x_GPLYA = 7,
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TMS320C64x_GPLYB = 8,
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TMS320C64x_ICR = 9,
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TMS320C64x_IER = 10,
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TMS320C64x_IERR = 11,
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TMS320C64x_ILC = 12,
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TMS320C64x_IRP = 13,
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TMS320C64x_ISR = 14,
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TMS320C64x_ISTP = 15,
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TMS320C64x_ITSR = 16,
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TMS320C64x_NRP = 17,
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TMS320C64x_NTSR = 18,
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TMS320C64x_REP = 19,
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TMS320C64x_RILC = 20,
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TMS320C64x_SSR = 21,
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TMS320C64x_TSCH = 22,
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TMS320C64x_TSCL = 23,
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TMS320C64x_TSR = 24,
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TMS320C64x_A0 = 25,
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TMS320C64x_A1 = 26,
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TMS320C64x_A2 = 27,
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TMS320C64x_A3 = 28,
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TMS320C64x_A4 = 29,
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TMS320C64x_A5 = 30,
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TMS320C64x_A6 = 31,
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TMS320C64x_A7 = 32,
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TMS320C64x_A8 = 33,
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TMS320C64x_A9 = 34,
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TMS320C64x_A10 = 35,
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TMS320C64x_A11 = 36,
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TMS320C64x_A12 = 37,
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TMS320C64x_A13 = 38,
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TMS320C64x_A14 = 39,
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TMS320C64x_A15 = 40,
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TMS320C64x_A16 = 41,
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TMS320C64x_A17 = 42,
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TMS320C64x_A18 = 43,
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TMS320C64x_A19 = 44,
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TMS320C64x_A20 = 45,
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TMS320C64x_A21 = 46,
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TMS320C64x_A22 = 47,
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TMS320C64x_A23 = 48,
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TMS320C64x_A24 = 49,
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TMS320C64x_A25 = 50,
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TMS320C64x_A26 = 51,
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TMS320C64x_A27 = 52,
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TMS320C64x_A28 = 53,
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TMS320C64x_A29 = 54,
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TMS320C64x_A30 = 55,
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TMS320C64x_A31 = 56,
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TMS320C64x_B0 = 57,
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TMS320C64x_B1 = 58,
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TMS320C64x_B2 = 59,
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TMS320C64x_B3 = 60,
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TMS320C64x_B4 = 61,
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TMS320C64x_B5 = 62,
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TMS320C64x_B6 = 63,
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TMS320C64x_B7 = 64,
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TMS320C64x_B8 = 65,
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TMS320C64x_B9 = 66,
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TMS320C64x_B10 = 67,
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TMS320C64x_B11 = 68,
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TMS320C64x_B12 = 69,
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TMS320C64x_B13 = 70,
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TMS320C64x_B14 = 71,
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TMS320C64x_B15 = 72,
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TMS320C64x_B16 = 73,
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TMS320C64x_B17 = 74,
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TMS320C64x_B18 = 75,
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TMS320C64x_B19 = 76,
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TMS320C64x_B20 = 77,
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TMS320C64x_B21 = 78,
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TMS320C64x_B22 = 79,
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TMS320C64x_B23 = 80,
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TMS320C64x_B24 = 81,
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TMS320C64x_B25 = 82,
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TMS320C64x_B26 = 83,
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TMS320C64x_B27 = 84,
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TMS320C64x_B28 = 85,
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TMS320C64x_B29 = 86,
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TMS320C64x_B30 = 87,
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TMS320C64x_B31 = 88,
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TMS320C64x_PCE1 = 89,
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TMS320C64x_NUM_TARGET_REGS // 90
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};
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// Register classes
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enum {
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TMS320C64x_GPRegsRegClassID = 0,
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TMS320C64x_AFRegsRegClassID = 1,
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TMS320C64x_BFRegsRegClassID = 2,
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TMS320C64x_ControlRegsRegClassID = 3,
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};
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|*MC Register Information *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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static MCPhysReg TMS320C64xRegDiffLists[] = {
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/* 0 */ 65535, 0,
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};
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static uint16_t TMS320C64xSubRegIdxLists[] = {
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/* 0 */ 0,
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};
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static MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors
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{ 3, 0, 0, 0, 0 },
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{ 310, 1, 1, 0, 1 },
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{ 319, 1, 1, 0, 1 },
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{ 298, 1, 1, 0, 1 },
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{ 268, 1, 1, 0, 1 },
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{ 290, 1, 1, 0, 1 },
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{ 303, 1, 1, 0, 1 },
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{ 241, 1, 1, 0, 1 },
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{ 247, 1, 1, 0, 1 },
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{ 294, 1, 1, 0, 1 },
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{ 299, 1, 1, 0, 1 },
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{ 314, 1, 1, 0, 1 },
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{ 254, 1, 1, 0, 1 },
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{ 277, 1, 1, 0, 1 },
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{ 323, 1, 1, 0, 1 },
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{ 285, 1, 1, 0, 1 },
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{ 331, 1, 1, 0, 1 },
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{ 281, 1, 1, 0, 1 },
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{ 336, 1, 1, 0, 1 },
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{ 273, 1, 1, 0, 1 },
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{ 253, 1, 1, 0, 1 },
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{ 327, 1, 1, 0, 1 },
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{ 258, 1, 1, 0, 1 },
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{ 263, 1, 1, 0, 1 },
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{ 332, 1, 1, 0, 1 },
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{ 24, 1, 1, 0, 1 },
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{ 54, 1, 1, 0, 1 },
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{ 81, 1, 1, 0, 1 },
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{ 103, 1, 1, 0, 1 },
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{ 125, 1, 1, 0, 1 },
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{ 147, 1, 1, 0, 1 },
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{ 169, 1, 1, 0, 1 },
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{ 191, 1, 1, 0, 1 },
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{ 213, 1, 1, 0, 1 },
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{ 235, 1, 1, 0, 1 },
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{ 0, 1, 1, 0, 1 },
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{ 30, 1, 1, 0, 1 },
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{ 65, 1, 1, 0, 1 },
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{ 87, 1, 1, 0, 1 },
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{ 109, 1, 1, 0, 1 },
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{ 131, 1, 1, 0, 1 },
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{ 153, 1, 1, 0, 1 },
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{ 175, 1, 1, 0, 1 },
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{ 197, 1, 1, 0, 1 },
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{ 219, 1, 1, 0, 1 },
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{ 8, 1, 1, 0, 1 },
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{ 38, 1, 1, 0, 1 },
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{ 73, 1, 1, 0, 1 },
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{ 95, 1, 1, 0, 1 },
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{ 117, 1, 1, 0, 1 },
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{ 139, 1, 1, 0, 1 },
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{ 161, 1, 1, 0, 1 },
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{ 183, 1, 1, 0, 1 },
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{ 205, 1, 1, 0, 1 },
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{ 227, 1, 1, 0, 1 },
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{ 16, 1, 1, 0, 1 },
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{ 46, 1, 1, 0, 1 },
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{ 27, 1, 1, 0, 1 },
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{ 57, 1, 1, 0, 1 },
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{ 84, 1, 1, 0, 1 },
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{ 106, 1, 1, 0, 1 },
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{ 128, 1, 1, 0, 1 },
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{ 150, 1, 1, 0, 1 },
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{ 172, 1, 1, 0, 1 },
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{ 194, 1, 1, 0, 1 },
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{ 216, 1, 1, 0, 1 },
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{ 238, 1, 1, 0, 1 },
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{ 4, 1, 1, 0, 1 },
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{ 34, 1, 1, 0, 1 },
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{ 69, 1, 1, 0, 1 },
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{ 91, 1, 1, 0, 1 },
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{ 113, 1, 1, 0, 1 },
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{ 135, 1, 1, 0, 1 },
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{ 157, 1, 1, 0, 1 },
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{ 179, 1, 1, 0, 1 },
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{ 201, 1, 1, 0, 1 },
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{ 223, 1, 1, 0, 1 },
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{ 12, 1, 1, 0, 1 },
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{ 42, 1, 1, 0, 1 },
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{ 77, 1, 1, 0, 1 },
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{ 99, 1, 1, 0, 1 },
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{ 121, 1, 1, 0, 1 },
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{ 143, 1, 1, 0, 1 },
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{ 165, 1, 1, 0, 1 },
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{ 187, 1, 1, 0, 1 },
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{ 209, 1, 1, 0, 1 },
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{ 231, 1, 1, 0, 1 },
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{ 20, 1, 1, 0, 1 },
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{ 50, 1, 1, 0, 1 },
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{ 60, 1, 1, 0, 1 },
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};
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// GPRegs Register Class...
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static MCPhysReg GPRegs[] = {
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TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
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};
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// GPRegs Bit set.
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static uint8_t GPRegsBits[] = {
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0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
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};
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// AFRegs Register Class...
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static MCPhysReg AFRegs[] = {
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TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31,
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};
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// AFRegs Bit set.
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static uint8_t AFRegsBits[] = {
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0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
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};
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// BFRegs Register Class...
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static MCPhysReg BFRegs[] = {
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TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
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};
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// BFRegs Bit set.
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static uint8_t BFRegsBits[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
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};
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// ControlRegs Register Class...
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static MCPhysReg ControlRegs[] = {
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TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR,
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};
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// ControlRegs Bit set.
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static uint8_t ControlRegsBits[] = {
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0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
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};
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static MCRegisterClass TMS320C64xMCRegisterClasses[] = {
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{ GPRegs, GPRegsBits, 64, sizeof(GPRegsBits), TMS320C64x_GPRegsRegClassID, 4, 4, 1, 1 },
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{ AFRegs, AFRegsBits, 32, sizeof(AFRegsBits), TMS320C64x_AFRegsRegClassID, 4, 4, 1, 1 },
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{ BFRegs, BFRegsBits, 32, sizeof(BFRegsBits), TMS320C64x_BFRegsRegClassID, 4, 4, 1, 1 },
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{ ControlRegs, ControlRegsBits, 25, sizeof(ControlRegsBits), TMS320C64x_ControlRegsRegClassID, 4, 4, 1, 1 },
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};
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#endif // GET_REGINFO_MC_DESC
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