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3558 lines
109 KiB
3558 lines
109 KiB
3 years ago
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Target Register Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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namespace llvm_ks {
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class MCRegisterClass;
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extern const MCRegisterClass MipsMCRegisterClasses[];
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namespace Mips {
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enum {
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NoRegister,
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AT = 1,
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DSPCCond = 2,
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DSPCarry = 3,
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DSPEFI = 4,
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DSPOutFlag = 5,
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DSPPos = 6,
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DSPSCount = 7,
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FP = 8,
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GP = 9,
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MSAAccess = 10,
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MSACSR = 11,
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MSAIR = 12,
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MSAMap = 13,
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MSAModify = 14,
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MSARequest = 15,
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MSASave = 16,
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MSAUnmap = 17,
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PC = 18,
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RA = 19,
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SP = 20,
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ZERO = 21,
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A0 = 22,
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A1 = 23,
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A2 = 24,
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A3 = 25,
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AC0 = 26,
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AC1 = 27,
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AC2 = 28,
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AC3 = 29,
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AT_64 = 30,
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COP00 = 31,
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COP01 = 32,
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COP02 = 33,
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COP03 = 34,
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COP04 = 35,
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COP05 = 36,
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COP06 = 37,
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COP07 = 38,
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COP08 = 39,
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COP09 = 40,
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COP20 = 41,
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COP21 = 42,
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COP22 = 43,
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COP23 = 44,
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COP24 = 45,
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COP25 = 46,
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COP26 = 47,
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COP27 = 48,
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COP28 = 49,
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COP29 = 50,
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COP30 = 51,
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COP31 = 52,
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COP32 = 53,
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COP33 = 54,
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COP34 = 55,
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COP35 = 56,
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COP36 = 57,
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COP37 = 58,
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COP38 = 59,
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COP39 = 60,
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COP010 = 61,
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COP011 = 62,
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COP012 = 63,
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COP013 = 64,
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COP014 = 65,
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COP015 = 66,
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COP016 = 67,
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COP017 = 68,
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COP018 = 69,
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COP019 = 70,
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COP020 = 71,
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COP021 = 72,
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COP022 = 73,
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COP023 = 74,
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COP024 = 75,
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COP025 = 76,
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COP026 = 77,
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COP027 = 78,
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COP028 = 79,
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COP029 = 80,
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COP030 = 81,
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COP031 = 82,
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COP210 = 83,
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COP211 = 84,
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COP212 = 85,
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COP213 = 86,
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COP214 = 87,
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COP215 = 88,
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COP216 = 89,
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COP217 = 90,
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COP218 = 91,
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COP219 = 92,
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COP220 = 93,
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COP221 = 94,
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COP222 = 95,
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COP223 = 96,
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COP224 = 97,
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COP225 = 98,
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COP226 = 99,
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COP227 = 100,
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COP228 = 101,
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COP229 = 102,
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COP230 = 103,
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COP231 = 104,
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COP310 = 105,
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COP311 = 106,
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COP312 = 107,
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COP313 = 108,
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COP314 = 109,
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COP315 = 110,
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COP316 = 111,
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COP317 = 112,
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COP318 = 113,
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COP319 = 114,
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COP320 = 115,
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COP321 = 116,
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COP322 = 117,
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COP323 = 118,
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COP324 = 119,
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COP325 = 120,
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COP326 = 121,
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COP327 = 122,
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COP328 = 123,
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COP329 = 124,
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COP330 = 125,
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COP331 = 126,
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D0 = 127,
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D1 = 128,
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D2 = 129,
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D3 = 130,
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D4 = 131,
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D5 = 132,
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D6 = 133,
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D7 = 134,
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D8 = 135,
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D9 = 136,
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D10 = 137,
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D11 = 138,
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D12 = 139,
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D13 = 140,
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D14 = 141,
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D15 = 142,
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DSPOutFlag20 = 143,
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DSPOutFlag21 = 144,
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DSPOutFlag22 = 145,
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DSPOutFlag23 = 146,
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F0 = 147,
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F1 = 148,
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F2 = 149,
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F3 = 150,
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F4 = 151,
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F5 = 152,
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F6 = 153,
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F7 = 154,
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F8 = 155,
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F9 = 156,
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F10 = 157,
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F11 = 158,
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F12 = 159,
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F13 = 160,
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F14 = 161,
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F15 = 162,
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F16 = 163,
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F17 = 164,
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F18 = 165,
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F19 = 166,
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F20 = 167,
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F21 = 168,
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F22 = 169,
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F23 = 170,
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F24 = 171,
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F25 = 172,
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F26 = 173,
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F27 = 174,
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F28 = 175,
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F29 = 176,
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F30 = 177,
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F31 = 178,
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FCC0 = 179,
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FCC1 = 180,
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FCC2 = 181,
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FCC3 = 182,
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FCC4 = 183,
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FCC5 = 184,
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FCC6 = 185,
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FCC7 = 186,
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FCR0 = 187,
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FCR1 = 188,
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FCR2 = 189,
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FCR3 = 190,
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FCR4 = 191,
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FCR5 = 192,
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FCR6 = 193,
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FCR7 = 194,
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FCR8 = 195,
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FCR9 = 196,
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FCR10 = 197,
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FCR11 = 198,
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FCR12 = 199,
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FCR13 = 200,
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FCR14 = 201,
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FCR15 = 202,
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FCR16 = 203,
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FCR17 = 204,
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FCR18 = 205,
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FCR19 = 206,
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FCR20 = 207,
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FCR21 = 208,
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FCR22 = 209,
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FCR23 = 210,
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FCR24 = 211,
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FCR25 = 212,
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FCR26 = 213,
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FCR27 = 214,
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FCR28 = 215,
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FCR29 = 216,
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FCR30 = 217,
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FCR31 = 218,
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FP_64 = 219,
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F_HI0 = 220,
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F_HI1 = 221,
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F_HI2 = 222,
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F_HI3 = 223,
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F_HI4 = 224,
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F_HI5 = 225,
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F_HI6 = 226,
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F_HI7 = 227,
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F_HI8 = 228,
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F_HI9 = 229,
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F_HI10 = 230,
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F_HI11 = 231,
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F_HI12 = 232,
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F_HI13 = 233,
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F_HI14 = 234,
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F_HI15 = 235,
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F_HI16 = 236,
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F_HI17 = 237,
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F_HI18 = 238,
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F_HI19 = 239,
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F_HI20 = 240,
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F_HI21 = 241,
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F_HI22 = 242,
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F_HI23 = 243,
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F_HI24 = 244,
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F_HI25 = 245,
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F_HI26 = 246,
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F_HI27 = 247,
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F_HI28 = 248,
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F_HI29 = 249,
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F_HI30 = 250,
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F_HI31 = 251,
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GP_64 = 252,
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HI0 = 253,
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HI1 = 254,
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HI2 = 255,
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HI3 = 256,
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HWR0 = 257,
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HWR1 = 258,
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HWR2 = 259,
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HWR3 = 260,
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HWR4 = 261,
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HWR5 = 262,
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HWR6 = 263,
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HWR7 = 264,
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HWR8 = 265,
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HWR9 = 266,
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HWR10 = 267,
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HWR11 = 268,
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HWR12 = 269,
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HWR13 = 270,
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HWR14 = 271,
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HWR15 = 272,
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HWR16 = 273,
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HWR17 = 274,
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HWR18 = 275,
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HWR19 = 276,
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HWR20 = 277,
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HWR21 = 278,
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HWR22 = 279,
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HWR23 = 280,
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HWR24 = 281,
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HWR25 = 282,
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HWR26 = 283,
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HWR27 = 284,
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HWR28 = 285,
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HWR29 = 286,
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HWR30 = 287,
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HWR31 = 288,
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K0 = 289,
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K1 = 290,
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LO0 = 291,
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LO1 = 292,
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LO2 = 293,
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LO3 = 294,
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MPL0 = 295,
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MPL1 = 296,
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MPL2 = 297,
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P0 = 298,
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P1 = 299,
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P2 = 300,
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RA_64 = 301,
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S0 = 302,
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S1 = 303,
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S2 = 304,
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S3 = 305,
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S4 = 306,
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S5 = 307,
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S6 = 308,
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S7 = 309,
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SP_64 = 310,
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T0 = 311,
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T1 = 312,
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T2 = 313,
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T3 = 314,
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T4 = 315,
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T5 = 316,
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T6 = 317,
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T7 = 318,
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T8 = 319,
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T9 = 320,
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V0 = 321,
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V1 = 322,
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W0 = 323,
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W1 = 324,
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W2 = 325,
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W3 = 326,
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W4 = 327,
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W5 = 328,
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W6 = 329,
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W7 = 330,
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W8 = 331,
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W9 = 332,
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W10 = 333,
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W11 = 334,
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W12 = 335,
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W13 = 336,
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W14 = 337,
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W15 = 338,
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W16 = 339,
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W17 = 340,
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W18 = 341,
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W19 = 342,
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W20 = 343,
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W21 = 344,
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W22 = 345,
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W23 = 346,
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W24 = 347,
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W25 = 348,
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W26 = 349,
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W27 = 350,
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W28 = 351,
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W29 = 352,
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W30 = 353,
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W31 = 354,
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ZERO_64 = 355,
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A0_64 = 356,
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A1_64 = 357,
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A2_64 = 358,
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A3_64 = 359,
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AC0_64 = 360,
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D0_64 = 361,
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D1_64 = 362,
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D2_64 = 363,
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D3_64 = 364,
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D4_64 = 365,
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D5_64 = 366,
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D6_64 = 367,
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D7_64 = 368,
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D8_64 = 369,
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D9_64 = 370,
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D10_64 = 371,
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D11_64 = 372,
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D12_64 = 373,
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D13_64 = 374,
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D14_64 = 375,
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D15_64 = 376,
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D16_64 = 377,
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D17_64 = 378,
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D18_64 = 379,
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D19_64 = 380,
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|
D20_64 = 381,
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||
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D21_64 = 382,
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|
D22_64 = 383,
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|
D23_64 = 384,
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||
|
D24_64 = 385,
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|
D25_64 = 386,
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D26_64 = 387,
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D27_64 = 388,
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D28_64 = 389,
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D29_64 = 390,
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D30_64 = 391,
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D31_64 = 392,
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DSPOutFlag16_19 = 393,
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||
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HI0_64 = 394,
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||
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K0_64 = 395,
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K1_64 = 396,
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LO0_64 = 397,
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||
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S0_64 = 398,
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||
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S1_64 = 399,
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||
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S2_64 = 400,
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||
|
S3_64 = 401,
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||
|
S4_64 = 402,
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||
|
S5_64 = 403,
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||
|
S6_64 = 404,
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||
|
S7_64 = 405,
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T0_64 = 406,
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||
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T1_64 = 407,
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||
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T2_64 = 408,
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||
|
T3_64 = 409,
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||
|
T4_64 = 410,
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||
|
T5_64 = 411,
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||
|
T6_64 = 412,
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||
|
T7_64 = 413,
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||
|
T8_64 = 414,
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||
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T9_64 = 415,
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||
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V0_64 = 416,
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||
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V1_64 = 417,
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||
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NUM_TARGET_REGS // 418
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||
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};
|
||
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}
|
||
|
|
||
|
// Register classes
|
||
|
namespace Mips {
|
||
|
enum {
|
||
|
OddSPRegClassID = 0,
|
||
|
CCRRegClassID = 1,
|
||
|
COP0RegClassID = 2,
|
||
|
COP2RegClassID = 3,
|
||
|
COP3RegClassID = 4,
|
||
|
DSPRRegClassID = 5,
|
||
|
FGR32RegClassID = 6,
|
||
|
FGRCCRegClassID = 7,
|
||
|
FGRH32RegClassID = 8,
|
||
|
GPR32RegClassID = 9,
|
||
|
HWRegsRegClassID = 10,
|
||
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OddSP_with_sub_hiRegClassID = 11,
|
||
|
FGR32_and_OddSPRegClassID = 12,
|
||
|
FGRH32_and_OddSPRegClassID = 13,
|
||
|
OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 14,
|
||
|
CPU16RegsPlusSPRegClassID = 15,
|
||
|
CPU16RegsRegClassID = 16,
|
||
|
FCCRegClassID = 17,
|
||
|
GPRMM16RegClassID = 18,
|
||
|
GPRMM16MovePRegClassID = 19,
|
||
|
GPRMM16ZeroRegClassID = 20,
|
||
|
MSACtrlRegClassID = 21,
|
||
|
OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22,
|
||
|
CPU16Regs_and_GPRMM16ZeroRegClassID = 23,
|
||
|
CPU16Regs_and_GPRMM16MovePRegClassID = 24,
|
||
|
GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25,
|
||
|
HI32DSPRegClassID = 26,
|
||
|
LO32DSPRegClassID = 27,
|
||
|
GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28,
|
||
|
CPURARegRegClassID = 29,
|
||
|
CPUSPRegRegClassID = 30,
|
||
|
DSPCCRegClassID = 31,
|
||
|
HI32RegClassID = 32,
|
||
|
LO32RegClassID = 33,
|
||
|
FGR64RegClassID = 34,
|
||
|
GPR64RegClassID = 35,
|
||
|
AFGR64RegClassID = 36,
|
||
|
FGR64_and_OddSPRegClassID = 37,
|
||
|
GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38,
|
||
|
AFGR64_and_OddSPRegClassID = 39,
|
||
|
GPR64_with_sub_32_in_CPU16RegsRegClassID = 40,
|
||
|
GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41,
|
||
|
GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42,
|
||
|
GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43,
|
||
|
ACC64DSPRegClassID = 44,
|
||
|
GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45,
|
||
|
GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46,
|
||
|
GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47,
|
||
|
OCTEON_MPLRegClassID = 48,
|
||
|
OCTEON_PRegClassID = 49,
|
||
|
ACC64RegClassID = 50,
|
||
|
GPR64_with_sub_32_in_CPURARegRegClassID = 51,
|
||
|
GPR64_with_sub_32_in_CPUSPRegRegClassID = 52,
|
||
|
HI64RegClassID = 53,
|
||
|
LO64RegClassID = 54,
|
||
|
MSA128BRegClassID = 55,
|
||
|
MSA128DRegClassID = 56,
|
||
|
MSA128HRegClassID = 57,
|
||
|
MSA128WRegClassID = 58,
|
||
|
MSA128B_with_sub_64_in_OddSPRegClassID = 59,
|
||
|
MSA128WEvensRegClassID = 60,
|
||
|
ACC128RegClassID = 61,
|
||
|
|
||
|
};
|
||
|
}
|
||
|
|
||
|
// Subregister indices
|
||
|
namespace Mips {
|
||
|
enum {
|
||
|
NoSubRegister,
|
||
|
sub_32, // 1
|
||
|
sub_64, // 2
|
||
|
sub_dsp16_19, // 3
|
||
|
sub_dsp20, // 4
|
||
|
sub_dsp21, // 5
|
||
|
sub_dsp22, // 6
|
||
|
sub_dsp23, // 7
|
||
|
sub_hi, // 8
|
||
|
sub_lo, // 9
|
||
|
sub_hi_then_sub_32, // 10
|
||
|
sub_32_sub_hi_then_sub_32, // 11
|
||
|
NUM_TARGET_SUBREGS
|
||
|
};
|
||
|
}
|
||
|
} // End llvm namespace
|
||
|
#endif // GET_REGINFO_ENUM
|
||
|
|
||
|
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|
||
|
|* *|
|
||
|
|* MC Register Information *|
|
||
|
|* *|
|
||
|
|* Automatically generated file, do not edit! *|
|
||
|
|* *|
|
||
|
\*===----------------------------------------------------------------------===*/
|
||
|
|
||
|
|
||
|
#ifdef GET_REGINFO_MC_DESC
|
||
|
#undef GET_REGINFO_MC_DESC
|
||
|
namespace llvm_ks {
|
||
|
|
||
|
extern const MCPhysReg MipsRegDiffLists[] = {
|
||
|
/* 0 */ 0, 0,
|
||
|
/* 2 */ 4, 1, 1, 1, 1, 0,
|
||
|
/* 8 */ 388, 65286, 1, 1, 1, 0,
|
||
|
/* 14 */ 20, 1, 0,
|
||
|
/* 17 */ 21, 1, 0,
|
||
|
/* 20 */ 22, 1, 0,
|
||
|
/* 23 */ 23, 1, 0,
|
||
|
/* 26 */ 24, 1, 0,
|
||
|
/* 29 */ 25, 1, 0,
|
||
|
/* 32 */ 26, 1, 0,
|
||
|
/* 35 */ 27, 1, 0,
|
||
|
/* 38 */ 28, 1, 0,
|
||
|
/* 41 */ 29, 1, 0,
|
||
|
/* 44 */ 30, 1, 0,
|
||
|
/* 47 */ 31, 1, 0,
|
||
|
/* 50 */ 32, 1, 0,
|
||
|
/* 53 */ 33, 1, 0,
|
||
|
/* 56 */ 34, 1, 0,
|
||
|
/* 59 */ 35, 1, 0,
|
||
|
/* 62 */ 65415, 1, 0,
|
||
|
/* 65 */ 65513, 1, 0,
|
||
|
/* 68 */ 3, 0,
|
||
|
/* 70 */ 4, 0,
|
||
|
/* 72 */ 6, 0,
|
||
|
/* 74 */ 11, 0,
|
||
|
/* 76 */ 12, 0,
|
||
|
/* 78 */ 22, 0,
|
||
|
/* 80 */ 23, 0,
|
||
|
/* 82 */ 29, 0,
|
||
|
/* 84 */ 30, 0,
|
||
|
/* 86 */ 65308, 72, 0,
|
||
|
/* 89 */ 65346, 72, 0,
|
||
|
/* 92 */ 38, 65322, 73, 0,
|
||
|
/* 96 */ 95, 0,
|
||
|
/* 98 */ 96, 0,
|
||
|
/* 100 */ 106, 0,
|
||
|
/* 102 */ 211, 0,
|
||
|
/* 104 */ 243, 0,
|
||
|
/* 106 */ 282, 0,
|
||
|
/* 108 */ 290, 0,
|
||
|
/* 110 */ 334, 0,
|
||
|
/* 112 */ 64983, 0,
|
||
|
/* 114 */ 65060, 0,
|
||
|
/* 116 */ 65148, 0,
|
||
|
/* 118 */ 65202, 0,
|
||
|
/* 120 */ 65205, 0,
|
||
|
/* 122 */ 65246, 0,
|
||
|
/* 124 */ 65254, 0,
|
||
|
/* 126 */ 65271, 0,
|
||
|
/* 128 */ 65293, 0,
|
||
|
/* 130 */ 37, 65430, 103, 65395, 65309, 0,
|
||
|
/* 136 */ 65325, 0,
|
||
|
/* 138 */ 65395, 0,
|
||
|
/* 140 */ 65396, 0,
|
||
|
/* 142 */ 65397, 0,
|
||
|
/* 144 */ 65398, 0,
|
||
|
/* 146 */ 65410, 0,
|
||
|
/* 148 */ 65415, 0,
|
||
|
/* 150 */ 65430, 0,
|
||
|
/* 152 */ 65440, 0,
|
||
|
/* 154 */ 65441, 0,
|
||
|
/* 156 */ 141, 65498, 0,
|
||
|
/* 159 */ 65516, 234, 65498, 0,
|
||
|
/* 163 */ 65515, 235, 65498, 0,
|
||
|
/* 167 */ 65514, 236, 65498, 0,
|
||
|
/* 171 */ 65513, 237, 65498, 0,
|
||
|
/* 175 */ 65512, 238, 65498, 0,
|
||
|
/* 179 */ 65511, 239, 65498, 0,
|
||
|
/* 183 */ 65510, 240, 65498, 0,
|
||
|
/* 187 */ 65509, 241, 65498, 0,
|
||
|
/* 191 */ 65508, 242, 65498, 0,
|
||
|
/* 195 */ 65507, 243, 65498, 0,
|
||
|
/* 199 */ 65506, 244, 65498, 0,
|
||
|
/* 203 */ 65505, 245, 65498, 0,
|
||
|
/* 207 */ 65504, 246, 65498, 0,
|
||
|
/* 211 */ 65503, 247, 65498, 0,
|
||
|
/* 215 */ 65502, 248, 65498, 0,
|
||
|
/* 219 */ 65501, 249, 65498, 0,
|
||
|
/* 223 */ 65500, 250, 65498, 0,
|
||
|
/* 227 */ 265, 65498, 0,
|
||
|
/* 230 */ 65271, 371, 65499, 0,
|
||
|
/* 234 */ 65309, 368, 65502, 0,
|
||
|
/* 238 */ 65507, 0,
|
||
|
/* 240 */ 65510, 0,
|
||
|
/* 242 */ 65511, 0,
|
||
|
/* 244 */ 65512, 0,
|
||
|
/* 246 */ 65516, 0,
|
||
|
/* 248 */ 65521, 0,
|
||
|
/* 250 */ 65522, 0,
|
||
|
/* 252 */ 65535, 0,
|
||
|
};
|
||
|
|
||
|
extern const unsigned MipsLaneMaskLists[] = {
|
||
|
/* 0 */ 0x00000000, ~0u,
|
||
|
/* 2 */ 0x00000001, ~0u,
|
||
|
/* 4 */ 0x00000002, 0x00000004, 0x00000008, 0x00000010, 0x00000020, ~0u,
|
||
|
/* 10 */ 0x00000001, 0x00000040, ~0u,
|
||
|
};
|
||
|
|
||
|
extern const uint16_t MipsSubRegIdxLists[] = {
|
||
|
/* 0 */ 1, 0,
|
||
|
/* 2 */ 3, 4, 5, 6, 7, 0,
|
||
|
/* 8 */ 2, 9, 8, 0,
|
||
|
/* 12 */ 9, 1, 8, 10, 11, 0,
|
||
|
};
|
||
|
|
||
|
extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
|
||
|
{ 65535, 65535 },
|
||
|
{ 0, 32 }, // sub_32
|
||
|
{ 0, 64 }, // sub_64
|
||
|
{ 16, 4 }, // sub_dsp16_19
|
||
|
{ 20, 1 }, // sub_dsp20
|
||
|
{ 21, 1 }, // sub_dsp21
|
||
|
{ 22, 1 }, // sub_dsp22
|
||
|
{ 23, 1 }, // sub_dsp23
|
||
|
{ 32, 32 }, // sub_hi
|
||
|
{ 0, 32 }, // sub_lo
|
||
|
{ 32, 32 }, // sub_hi_then_sub_32
|
||
|
{ 0, 64 }, // sub_32_sub_hi_then_sub_32
|
||
|
};
|
||
|
|
||
|
extern const char MipsRegStrings[] = {
|
||
|
/* 0 */ 'C', 'O', 'P', '0', '0', 0,
|
||
|
/* 6 */ 'C', 'O', 'P', '0', '1', '0', 0,
|
||
|
/* 13 */ 'C', 'O', 'P', '2', '1', '0', 0,
|
||
|
/* 20 */ 'C', 'O', 'P', '3', '1', '0', 0,
|
||
|
/* 27 */ 'D', '1', '0', 0,
|
||
|
/* 31 */ 'F', '1', '0', 0,
|
||
|
/* 35 */ 'F', '_', 'H', 'I', '1', '0', 0,
|
||
|
/* 42 */ 'F', 'C', 'R', '1', '0', 0,
|
||
|
/* 48 */ 'H', 'W', 'R', '1', '0', 0,
|
||
|
/* 54 */ 'W', '1', '0', 0,
|
||
|
/* 58 */ 'C', 'O', 'P', '0', '2', '0', 0,
|
||
|
/* 65 */ 'C', 'O', 'P', '2', '2', '0', 0,
|
||
|
/* 72 */ 'C', 'O', 'P', '3', '2', '0', 0,
|
||
|
/* 79 */ 'F', '2', '0', 0,
|
||
|
/* 83 */ 'F', '_', 'H', 'I', '2', '0', 0,
|
||
|
/* 90 */ 'C', 'O', 'P', '2', '0', 0,
|
||
|
/* 96 */ 'F', 'C', 'R', '2', '0', 0,
|
||
|
/* 102 */ 'H', 'W', 'R', '2', '0', 0,
|
||
|
/* 108 */ 'W', '2', '0', 0,
|
||
|
/* 112 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
|
||
|
/* 125 */ 'C', 'O', 'P', '0', '3', '0', 0,
|
||
|
/* 132 */ 'C', 'O', 'P', '2', '3', '0', 0,
|
||
|
/* 139 */ 'C', 'O', 'P', '3', '3', '0', 0,
|
||
|
/* 146 */ 'F', '3', '0', 0,
|
||
|
/* 150 */ 'F', '_', 'H', 'I', '3', '0', 0,
|
||
|
/* 157 */ 'C', 'O', 'P', '3', '0', 0,
|
||
|
/* 163 */ 'F', 'C', 'R', '3', '0', 0,
|
||
|
/* 169 */ 'H', 'W', 'R', '3', '0', 0,
|
||
|
/* 175 */ 'W', '3', '0', 0,
|
||
|
/* 179 */ 'A', '0', 0,
|
||
|
/* 182 */ 'A', 'C', '0', 0,
|
||
|
/* 186 */ 'F', 'C', 'C', '0', 0,
|
||
|
/* 191 */ 'D', '0', 0,
|
||
|
/* 194 */ 'F', '0', 0,
|
||
|
/* 197 */ 'F', '_', 'H', 'I', '0', 0,
|
||
|
/* 203 */ 'K', '0', 0,
|
||
|
/* 206 */ 'M', 'P', 'L', '0', 0,
|
||
|
/* 211 */ 'L', 'O', '0', 0,
|
||
|
/* 215 */ 'P', '0', 0,
|
||
|
/* 218 */ 'F', 'C', 'R', '0', 0,
|
||
|
/* 223 */ 'H', 'W', 'R', '0', 0,
|
||
|
/* 228 */ 'S', '0', 0,
|
||
|
/* 231 */ 'T', '0', 0,
|
||
|
/* 234 */ 'V', '0', 0,
|
||
|
/* 237 */ 'W', '0', 0,
|
||
|
/* 240 */ 'C', 'O', 'P', '0', '1', 0,
|
||
|
/* 246 */ 'C', 'O', 'P', '0', '1', '1', 0,
|
||
|
/* 253 */ 'C', 'O', 'P', '2', '1', '1', 0,
|
||
|
/* 260 */ 'C', 'O', 'P', '3', '1', '1', 0,
|
||
|
/* 267 */ 'D', '1', '1', 0,
|
||
|
/* 271 */ 'F', '1', '1', 0,
|
||
|
/* 275 */ 'F', '_', 'H', 'I', '1', '1', 0,
|
||
|
/* 282 */ 'F', 'C', 'R', '1', '1', 0,
|
||
|
/* 288 */ 'H', 'W', 'R', '1', '1', 0,
|
||
|
/* 294 */ 'W', '1', '1', 0,
|
||
|
/* 298 */ 'C', 'O', 'P', '0', '2', '1', 0,
|
||
|
/* 305 */ 'C', 'O', 'P', '2', '2', '1', 0,
|
||
|
/* 312 */ 'C', 'O', 'P', '3', '2', '1', 0,
|
||
|
/* 319 */ 'F', '2', '1', 0,
|
||
|
/* 323 */ 'F', '_', 'H', 'I', '2', '1', 0,
|
||
|
/* 330 */ 'C', 'O', 'P', '2', '1', 0,
|
||
|
/* 336 */ 'F', 'C', 'R', '2', '1', 0,
|
||
|
/* 342 */ 'H', 'W', 'R', '2', '1', 0,
|
||
|
/* 348 */ 'W', '2', '1', 0,
|
||
|
/* 352 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
|
||
|
/* 365 */ 'C', 'O', 'P', '0', '3', '1', 0,
|
||
|
/* 372 */ 'C', 'O', 'P', '2', '3', '1', 0,
|
||
|
/* 379 */ 'C', 'O', 'P', '3', '3', '1', 0,
|
||
|
/* 386 */ 'F', '3', '1', 0,
|
||
|
/* 390 */ 'F', '_', 'H', 'I', '3', '1', 0,
|
||
|
/* 397 */ 'C', 'O', 'P', '3', '1', 0,
|
||
|
/* 403 */ 'F', 'C', 'R', '3', '1', 0,
|
||
|
/* 409 */ 'H', 'W', 'R', '3', '1', 0,
|
||
|
/* 415 */ 'W', '3', '1', 0,
|
||
|
/* 419 */ 'A', '1', 0,
|
||
|
/* 422 */ 'A', 'C', '1', 0,
|
||
|
/* 426 */ 'F', 'C', 'C', '1', 0,
|
||
|
/* 431 */ 'D', '1', 0,
|
||
|
/* 434 */ 'F', '1', 0,
|
||
|
/* 437 */ 'F', '_', 'H', 'I', '1', 0,
|
||
|
/* 443 */ 'K', '1', 0,
|
||
|
/* 446 */ 'M', 'P', 'L', '1', 0,
|
||
|
/* 451 */ 'L', 'O', '1', 0,
|
||
|
/* 455 */ 'P', '1', 0,
|
||
|
/* 458 */ 'F', 'C', 'R', '1', 0,
|
||
|
/* 463 */ 'H', 'W', 'R', '1', 0,
|
||
|
/* 468 */ 'S', '1', 0,
|
||
|
/* 471 */ 'T', '1', 0,
|
||
|
/* 474 */ 'V', '1', 0,
|
||
|
/* 477 */ 'W', '1', 0,
|
||
|
/* 480 */ 'C', 'O', 'P', '0', '2', 0,
|
||
|
/* 486 */ 'C', 'O', 'P', '0', '1', '2', 0,
|
||
|
/* 493 */ 'C', 'O', 'P', '2', '1', '2', 0,
|
||
|
/* 500 */ 'C', 'O', 'P', '3', '1', '2', 0,
|
||
|
/* 507 */ 'D', '1', '2', 0,
|
||
|
/* 511 */ 'F', '1', '2', 0,
|
||
|
/* 515 */ 'F', '_', 'H', 'I', '1', '2', 0,
|
||
|
/* 522 */ 'F', 'C', 'R', '1', '2', 0,
|
||
|
/* 528 */ 'H', 'W', 'R', '1', '2', 0,
|
||
|
/* 534 */ 'W', '1', '2', 0,
|
||
|
/* 538 */ 'C', 'O', 'P', '0', '2', '2', 0,
|
||
|
/* 545 */ 'C', 'O', 'P', '2', '2', '2', 0,
|
||
|
/* 552 */ 'C', 'O', 'P', '3', '2', '2', 0,
|
||
|
/* 559 */ 'F', '2', '2', 0,
|
||
|
/* 563 */ 'F', '_', 'H', 'I', '2', '2', 0,
|
||
|
/* 570 */ 'C', 'O', 'P', '2', '2', 0,
|
||
|
/* 576 */ 'F', 'C', 'R', '2', '2', 0,
|
||
|
/* 582 */ 'H', 'W', 'R', '2', '2', 0,
|
||
|
/* 588 */ 'W', '2', '2', 0,
|
||
|
/* 592 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
|
||
|
/* 605 */ 'C', 'O', 'P', '3', '2', 0,
|
||
|
/* 611 */ 'A', '2', 0,
|
||
|
/* 614 */ 'A', 'C', '2', 0,
|
||
|
/* 618 */ 'F', 'C', 'C', '2', 0,
|
||
|
/* 623 */ 'D', '2', 0,
|
||
|
/* 626 */ 'F', '2', 0,
|
||
|
/* 629 */ 'F', '_', 'H', 'I', '2', 0,
|
||
|
/* 635 */ 'M', 'P', 'L', '2', 0,
|
||
|
/* 640 */ 'L', 'O', '2', 0,
|
||
|
/* 644 */ 'P', '2', 0,
|
||
|
/* 647 */ 'F', 'C', 'R', '2', 0,
|
||
|
/* 652 */ 'H', 'W', 'R', '2', 0,
|
||
|
/* 657 */ 'S', '2', 0,
|
||
|
/* 660 */ 'T', '2', 0,
|
||
|
/* 663 */ 'W', '2', 0,
|
||
|
/* 666 */ 'C', 'O', 'P', '0', '3', 0,
|
||
|
/* 672 */ 'C', 'O', 'P', '0', '1', '3', 0,
|
||
|
/* 679 */ 'C', 'O', 'P', '2', '1', '3', 0,
|
||
|
/* 686 */ 'C', 'O', 'P', '3', '1', '3', 0,
|
||
|
/* 693 */ 'D', '1', '3', 0,
|
||
|
/* 697 */ 'F', '1', '3', 0,
|
||
|
/* 701 */ 'F', '_', 'H', 'I', '1', '3', 0,
|
||
|
/* 708 */ 'F', 'C', 'R', '1', '3', 0,
|
||
|
/* 714 */ 'H', 'W', 'R', '1', '3', 0,
|
||
|
/* 720 */ 'W', '1', '3', 0,
|
||
|
/* 724 */ 'C', 'O', 'P', '0', '2', '3', 0,
|
||
|
/* 731 */ 'C', 'O', 'P', '2', '2', '3', 0,
|
||
|
/* 738 */ 'C', 'O', 'P', '3', '2', '3', 0,
|
||
|
/* 745 */ 'F', '2', '3', 0,
|
||
|
/* 749 */ 'F', '_', 'H', 'I', '2', '3', 0,
|
||
|
/* 756 */ 'C', 'O', 'P', '2', '3', 0,
|
||
|
/* 762 */ 'F', 'C', 'R', '2', '3', 0,
|
||
|
/* 768 */ 'H', 'W', 'R', '2', '3', 0,
|
||
|
/* 774 */ 'W', '2', '3', 0,
|
||
|
/* 778 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
|
||
|
/* 791 */ 'C', 'O', 'P', '3', '3', 0,
|
||
|
/* 797 */ 'A', '3', 0,
|
||
|
/* 800 */ 'A', 'C', '3', 0,
|
||
|
/* 804 */ 'F', 'C', 'C', '3', 0,
|
||
|
/* 809 */ 'D', '3', 0,
|
||
|
/* 812 */ 'F', '3', 0,
|
||
|
/* 815 */ 'F', '_', 'H', 'I', '3', 0,
|
||
|
/* 821 */ 'L', 'O', '3', 0,
|
||
|
/* 825 */ 'F', 'C', 'R', '3', 0,
|
||
|
/* 830 */ 'H', 'W', 'R', '3', 0,
|
||
|
/* 835 */ 'S', '3', 0,
|
||
|
/* 838 */ 'T', '3', 0,
|
||
|
/* 841 */ 'W', '3', 0,
|
||
|
/* 844 */ 'C', 'O', 'P', '0', '4', 0,
|
||
|
/* 850 */ 'C', 'O', 'P', '0', '1', '4', 0,
|
||
|
/* 857 */ 'C', 'O', 'P', '2', '1', '4', 0,
|
||
|
/* 864 */ 'C', 'O', 'P', '3', '1', '4', 0,
|
||
|
/* 871 */ 'D', '1', '4', 0,
|
||
|
/* 875 */ 'F', '1', '4', 0,
|
||
|
/* 879 */ 'F', '_', 'H', 'I', '1', '4', 0,
|
||
|
/* 886 */ 'F', 'C', 'R', '1', '4', 0,
|
||
|
/* 892 */ 'H', 'W', 'R', '1', '4', 0,
|
||
|
/* 898 */ 'W', '1', '4', 0,
|
||
|
/* 902 */ 'C', 'O', 'P', '0', '2', '4', 0,
|
||
|
/* 909 */ 'C', 'O', 'P', '2', '2', '4', 0,
|
||
|
/* 916 */ 'C', 'O', 'P', '3', '2', '4', 0,
|
||
|
/* 923 */ 'F', '2', '4', 0,
|
||
|
/* 927 */ 'F', '_', 'H', 'I', '2', '4', 0,
|
||
|
/* 934 */ 'C', 'O', 'P', '2', '4', 0,
|
||
|
/* 940 */ 'F', 'C', 'R', '2', '4', 0,
|
||
|
/* 946 */ 'H', 'W', 'R', '2', '4', 0,
|
||
|
/* 952 */ 'W', '2', '4', 0,
|
||
|
/* 956 */ 'C', 'O', 'P', '3', '4', 0,
|
||
|
/* 962 */ 'D', '1', '0', '_', '6', '4', 0,
|
||
|
/* 969 */ 'D', '2', '0', '_', '6', '4', 0,
|
||
|
/* 976 */ 'D', '3', '0', '_', '6', '4', 0,
|
||
|
/* 983 */ 'A', '0', '_', '6', '4', 0,
|
||
|
/* 989 */ 'A', 'C', '0', '_', '6', '4', 0,
|
||
|
/* 996 */ 'D', '0', '_', '6', '4', 0,
|
||
|
/* 1002 */ 'H', 'I', '0', '_', '6', '4', 0,
|
||
|
/* 1009 */ 'K', '0', '_', '6', '4', 0,
|
||
|
/* 1015 */ 'L', 'O', '0', '_', '6', '4', 0,
|
||
|
/* 1022 */ 'S', '0', '_', '6', '4', 0,
|
||
|
/* 1028 */ 'T', '0', '_', '6', '4', 0,
|
||
|
/* 1034 */ 'V', '0', '_', '6', '4', 0,
|
||
|
/* 1040 */ 'D', '1', '1', '_', '6', '4', 0,
|
||
|
/* 1047 */ 'D', '2', '1', '_', '6', '4', 0,
|
||
|
/* 1054 */ 'D', '3', '1', '_', '6', '4', 0,
|
||
|
/* 1061 */ 'A', '1', '_', '6', '4', 0,
|
||
|
/* 1067 */ 'D', '1', '_', '6', '4', 0,
|
||
|
/* 1073 */ 'K', '1', '_', '6', '4', 0,
|
||
|
/* 1079 */ 'S', '1', '_', '6', '4', 0,
|
||
|
/* 1085 */ 'T', '1', '_', '6', '4', 0,
|
||
|
/* 1091 */ 'V', '1', '_', '6', '4', 0,
|
||
|
/* 1097 */ 'D', '1', '2', '_', '6', '4', 0,
|
||
|
/* 1104 */ 'D', '2', '2', '_', '6', '4', 0,
|
||
|
/* 1111 */ 'A', '2', '_', '6', '4', 0,
|
||
|
/* 1117 */ 'D', '2', '_', '6', '4', 0,
|
||
|
/* 1123 */ 'S', '2', '_', '6', '4', 0,
|
||
|
/* 1129 */ 'T', '2', '_', '6', '4', 0,
|
||
|
/* 1135 */ 'D', '1', '3', '_', '6', '4', 0,
|
||
|
/* 1142 */ 'D', '2', '3', '_', '6', '4', 0,
|
||
|
/* 1149 */ 'A', '3', '_', '6', '4', 0,
|
||
|
/* 1155 */ 'D', '3', '_', '6', '4', 0,
|
||
|
/* 1161 */ 'S', '3', '_', '6', '4', 0,
|
||
|
/* 1167 */ 'T', '3', '_', '6', '4', 0,
|
||
|
/* 1173 */ 'D', '1', '4', '_', '6', '4', 0,
|
||
|
/* 1180 */ 'D', '2', '4', '_', '6', '4', 0,
|
||
|
/* 1187 */ 'D', '4', '_', '6', '4', 0,
|
||
|
/* 1193 */ 'S', '4', '_', '6', '4', 0,
|
||
|
/* 1199 */ 'T', '4', '_', '6', '4', 0,
|
||
|
/* 1205 */ 'D', '1', '5', '_', '6', '4', 0,
|
||
|
/* 1212 */ 'D', '2', '5', '_', '6', '4', 0,
|
||
|
/* 1219 */ 'D', '5', '_', '6', '4', 0,
|
||
|
/* 1225 */ 'S', '5', '_', '6', '4', 0,
|
||
|
/* 1231 */ 'T', '5', '_', '6', '4', 0,
|
||
|
/* 1237 */ 'D', '1', '6', '_', '6', '4', 0,
|
||
|
/* 1244 */ 'D', '2', '6', '_', '6', '4', 0,
|
||
|
/* 1251 */ 'D', '6', '_', '6', '4', 0,
|
||
|
/* 1257 */ 'S', '6', '_', '6', '4', 0,
|
||
|
/* 1263 */ 'T', '6', '_', '6', '4', 0,
|
||
|
/* 1269 */ 'D', '1', '7', '_', '6', '4', 0,
|
||
|
/* 1276 */ 'D', '2', '7', '_', '6', '4', 0,
|
||
|
/* 1283 */ 'D', '7', '_', '6', '4', 0,
|
||
|
/* 1289 */ 'S', '7', '_', '6', '4', 0,
|
||
|
/* 1295 */ 'T', '7', '_', '6', '4', 0,
|
||
|
/* 1301 */ 'D', '1', '8', '_', '6', '4', 0,
|
||
|
/* 1308 */ 'D', '2', '8', '_', '6', '4', 0,
|
||
|
/* 1315 */ 'D', '8', '_', '6', '4', 0,
|
||
|
/* 1321 */ 'T', '8', '_', '6', '4', 0,
|
||
|
/* 1327 */ 'D', '1', '9', '_', '6', '4', 0,
|
||
|
/* 1334 */ 'D', '2', '9', '_', '6', '4', 0,
|
||
|
/* 1341 */ 'D', '9', '_', '6', '4', 0,
|
||
|
/* 1347 */ 'T', '9', '_', '6', '4', 0,
|
||
|
/* 1353 */ 'R', 'A', '_', '6', '4', 0,
|
||
|
/* 1359 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0,
|
||
|
/* 1367 */ 'F', 'P', '_', '6', '4', 0,
|
||
|
/* 1373 */ 'G', 'P', '_', '6', '4', 0,
|
||
|
/* 1379 */ 'S', 'P', '_', '6', '4', 0,
|
||
|
/* 1385 */ 'A', 'T', '_', '6', '4', 0,
|
||
|
/* 1391 */ 'F', 'C', 'C', '4', 0,
|
||
|
/* 1396 */ 'D', '4', 0,
|
||
|
/* 1399 */ 'F', '4', 0,
|
||
|
/* 1402 */ 'F', '_', 'H', 'I', '4', 0,
|
||
|
/* 1408 */ 'F', 'C', 'R', '4', 0,
|
||
|
/* 1413 */ 'H', 'W', 'R', '4', 0,
|
||
|
/* 1418 */ 'S', '4', 0,
|
||
|
/* 1421 */ 'T', '4', 0,
|
||
|
/* 1424 */ 'W', '4', 0,
|
||
|
/* 1427 */ 'C', 'O', 'P', '0', '5', 0,
|
||
|
/* 1433 */ 'C', 'O', 'P', '0', '1', '5', 0,
|
||
|
/* 1440 */ 'C', 'O', 'P', '2', '1', '5', 0,
|
||
|
/* 1447 */ 'C', 'O', 'P', '3', '1', '5', 0,
|
||
|
/* 1454 */ 'D', '1', '5', 0,
|
||
|
/* 1458 */ 'F', '1', '5', 0,
|
||
|
/* 1462 */ 'F', '_', 'H', 'I', '1', '5', 0,
|
||
|
/* 1469 */ 'F', 'C', 'R', '1', '5', 0,
|
||
|
/* 1475 */ 'H', 'W', 'R', '1', '5', 0,
|
||
|
/* 1481 */ 'W', '1', '5', 0,
|
||
|
/* 1485 */ 'C', 'O', 'P', '0', '2', '5', 0,
|
||
|
/* 1492 */ 'C', 'O', 'P', '2', '2', '5', 0,
|
||
|
/* 1499 */ 'C', 'O', 'P', '3', '2', '5', 0,
|
||
|
/* 1506 */ 'F', '2', '5', 0,
|
||
|
/* 1510 */ 'F', '_', 'H', 'I', '2', '5', 0,
|
||
|
/* 1517 */ 'C', 'O', 'P', '2', '5', 0,
|
||
|
/* 1523 */ 'F', 'C', 'R', '2', '5', 0,
|
||
|
/* 1529 */ 'H', 'W', 'R', '2', '5', 0,
|
||
|
/* 1535 */ 'W', '2', '5', 0,
|
||
|
/* 1539 */ 'C', 'O', 'P', '3', '5', 0,
|
||
|
/* 1545 */ 'F', 'C', 'C', '5', 0,
|
||
|
/* 1550 */ 'D', '5', 0,
|
||
|
/* 1553 */ 'F', '5', 0,
|
||
|
/* 1556 */ 'F', '_', 'H', 'I', '5', 0,
|
||
|
/* 1562 */ 'F', 'C', 'R', '5', 0,
|
||
|
/* 1567 */ 'H', 'W', 'R', '5', 0,
|
||
|
/* 1572 */ 'S', '5', 0,
|
||
|
/* 1575 */ 'T', '5', 0,
|
||
|
/* 1578 */ 'W', '5', 0,
|
||
|
/* 1581 */ 'C', 'O', 'P', '0', '6', 0,
|
||
|
/* 1587 */ 'C', 'O', 'P', '0', '1', '6', 0,
|
||
|
/* 1594 */ 'C', 'O', 'P', '2', '1', '6', 0,
|
||
|
/* 1601 */ 'C', 'O', 'P', '3', '1', '6', 0,
|
||
|
/* 1608 */ 'F', '1', '6', 0,
|
||
|
/* 1612 */ 'F', '_', 'H', 'I', '1', '6', 0,
|
||
|
/* 1619 */ 'F', 'C', 'R', '1', '6', 0,
|
||
|
/* 1625 */ 'H', 'W', 'R', '1', '6', 0,
|
||
|
/* 1631 */ 'W', '1', '6', 0,
|
||
|
/* 1635 */ 'C', 'O', 'P', '0', '2', '6', 0,
|
||
|
/* 1642 */ 'C', 'O', 'P', '2', '2', '6', 0,
|
||
|
/* 1649 */ 'C', 'O', 'P', '3', '2', '6', 0,
|
||
|
/* 1656 */ 'F', '2', '6', 0,
|
||
|
/* 1660 */ 'F', '_', 'H', 'I', '2', '6', 0,
|
||
|
/* 1667 */ 'C', 'O', 'P', '2', '6', 0,
|
||
|
/* 1673 */ 'F', 'C', 'R', '2', '6', 0,
|
||
|
/* 1679 */ 'H', 'W', 'R', '2', '6', 0,
|
||
|
/* 1685 */ 'W', '2', '6', 0,
|
||
|
/* 1689 */ 'C', 'O', 'P', '3', '6', 0,
|
||
|
/* 1695 */ 'F', 'C', 'C', '6', 0,
|
||
|
/* 1700 */ 'D', '6', 0,
|
||
|
/* 1703 */ 'F', '6', 0,
|
||
|
/* 1706 */ 'F', '_', 'H', 'I', '6', 0,
|
||
|
/* 1712 */ 'F', 'C', 'R', '6', 0,
|
||
|
/* 1717 */ 'H', 'W', 'R', '6', 0,
|
||
|
/* 1722 */ 'S', '6', 0,
|
||
|
/* 1725 */ 'T', '6', 0,
|
||
|
/* 1728 */ 'W', '6', 0,
|
||
|
/* 1731 */ 'C', 'O', 'P', '0', '7', 0,
|
||
|
/* 1737 */ 'C', 'O', 'P', '0', '1', '7', 0,
|
||
|
/* 1744 */ 'C', 'O', 'P', '2', '1', '7', 0,
|
||
|
/* 1751 */ 'C', 'O', 'P', '3', '1', '7', 0,
|
||
|
/* 1758 */ 'F', '1', '7', 0,
|
||
|
/* 1762 */ 'F', '_', 'H', 'I', '1', '7', 0,
|
||
|
/* 1769 */ 'F', 'C', 'R', '1', '7', 0,
|
||
|
/* 1775 */ 'H', 'W', 'R', '1', '7', 0,
|
||
|
/* 1781 */ 'W', '1', '7', 0,
|
||
|
/* 1785 */ 'C', 'O', 'P', '0', '2', '7', 0,
|
||
|
/* 1792 */ 'C', 'O', 'P', '2', '2', '7', 0,
|
||
|
/* 1799 */ 'C', 'O', 'P', '3', '2', '7', 0,
|
||
|
/* 1806 */ 'F', '2', '7', 0,
|
||
|
/* 1810 */ 'F', '_', 'H', 'I', '2', '7', 0,
|
||
|
/* 1817 */ 'C', 'O', 'P', '2', '7', 0,
|
||
|
/* 1823 */ 'F', 'C', 'R', '2', '7', 0,
|
||
|
/* 1829 */ 'H', 'W', 'R', '2', '7', 0,
|
||
|
/* 1835 */ 'W', '2', '7', 0,
|
||
|
/* 1839 */ 'C', 'O', 'P', '3', '7', 0,
|
||
|
/* 1845 */ 'F', 'C', 'C', '7', 0,
|
||
|
/* 1850 */ 'D', '7', 0,
|
||
|
/* 1853 */ 'F', '7', 0,
|
||
|
/* 1856 */ 'F', '_', 'H', 'I', '7', 0,
|
||
|
/* 1862 */ 'F', 'C', 'R', '7', 0,
|
||
|
/* 1867 */ 'H', 'W', 'R', '7', 0,
|
||
|
/* 1872 */ 'S', '7', 0,
|
||
|
/* 1875 */ 'T', '7', 0,
|
||
|
/* 1878 */ 'W', '7', 0,
|
||
|
/* 1881 */ 'C', 'O', 'P', '0', '8', 0,
|
||
|
/* 1887 */ 'C', 'O', 'P', '0', '1', '8', 0,
|
||
|
/* 1894 */ 'C', 'O', 'P', '2', '1', '8', 0,
|
||
|
/* 1901 */ 'C', 'O', 'P', '3', '1', '8', 0,
|
||
|
/* 1908 */ 'F', '1', '8', 0,
|
||
|
/* 1912 */ 'F', '_', 'H', 'I', '1', '8', 0,
|
||
|
/* 1919 */ 'F', 'C', 'R', '1', '8', 0,
|
||
|
/* 1925 */ 'H', 'W', 'R', '1', '8', 0,
|
||
|
/* 1931 */ 'W', '1', '8', 0,
|
||
|
/* 1935 */ 'C', 'O', 'P', '0', '2', '8', 0,
|
||
|
/* 1942 */ 'C', 'O', 'P', '2', '2', '8', 0,
|
||
|
/* 1949 */ 'C', 'O', 'P', '3', '2', '8', 0,
|
||
|
/* 1956 */ 'F', '2', '8', 0,
|
||
|
/* 1960 */ 'F', '_', 'H', 'I', '2', '8', 0,
|
||
|
/* 1967 */ 'C', 'O', 'P', '2', '8', 0,
|
||
|
/* 1973 */ 'F', 'C', 'R', '2', '8', 0,
|
||
|
/* 1979 */ 'H', 'W', 'R', '2', '8', 0,
|
||
|
/* 1985 */ 'W', '2', '8', 0,
|
||
|
/* 1989 */ 'C', 'O', 'P', '3', '8', 0,
|
||
|
/* 1995 */ 'D', '8', 0,
|
||
|
/* 1998 */ 'F', '8', 0,
|
||
|
/* 2001 */ 'F', '_', 'H', 'I', '8', 0,
|
||
|
/* 2007 */ 'F', 'C', 'R', '8', 0,
|
||
|
/* 2012 */ 'H', 'W', 'R', '8', 0,
|
||
|
/* 2017 */ 'T', '8', 0,
|
||
|
/* 2020 */ 'W', '8', 0,
|
||
|
/* 2023 */ 'C', 'O', 'P', '0', '9', 0,
|
||
|
/* 2029 */ 'C', 'O', 'P', '0', '1', '9', 0,
|
||
|
/* 2036 */ 'C', 'O', 'P', '2', '1', '9', 0,
|
||
|
/* 2043 */ 'C', 'O', 'P', '3', '1', '9', 0,
|
||
|
/* 2050 */ 'F', '1', '9', 0,
|
||
|
/* 2054 */ 'F', '_', 'H', 'I', '1', '9', 0,
|
||
|
/* 2061 */ 'F', 'C', 'R', '1', '9', 0,
|
||
|
/* 2067 */ 'H', 'W', 'R', '1', '9', 0,
|
||
|
/* 2073 */ 'W', '1', '9', 0,
|
||
|
/* 2077 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
|
||
|
/* 2093 */ 'C', 'O', 'P', '0', '2', '9', 0,
|
||
|
/* 2100 */ 'C', 'O', 'P', '2', '2', '9', 0,
|
||
|
/* 2107 */ 'C', 'O', 'P', '3', '2', '9', 0,
|
||
|
/* 2114 */ 'F', '2', '9', 0,
|
||
|
/* 2118 */ 'F', '_', 'H', 'I', '2', '9', 0,
|
||
|
/* 2125 */ 'C', 'O', 'P', '2', '9', 0,
|
||
|
/* 2131 */ 'F', 'C', 'R', '2', '9', 0,
|
||
|
/* 2137 */ 'H', 'W', 'R', '2', '9', 0,
|
||
|
/* 2143 */ 'W', '2', '9', 0,
|
||
|
/* 2147 */ 'C', 'O', 'P', '3', '9', 0,
|
||
|
/* 2153 */ 'D', '9', 0,
|
||
|
/* 2156 */ 'F', '9', 0,
|
||
|
/* 2159 */ 'F', '_', 'H', 'I', '9', 0,
|
||
|
/* 2165 */ 'F', 'C', 'R', '9', 0,
|
||
|
/* 2170 */ 'H', 'W', 'R', '9', 0,
|
||
|
/* 2175 */ 'T', '9', 0,
|
||
|
/* 2178 */ 'W', '9', 0,
|
||
|
/* 2181 */ 'R', 'A', 0,
|
||
|
/* 2184 */ 'P', 'C', 0,
|
||
|
/* 2187 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
|
||
|
/* 2194 */ 'Z', 'E', 'R', 'O', 0,
|
||
|
/* 2199 */ 'F', 'P', 0,
|
||
|
/* 2202 */ 'G', 'P', 0,
|
||
|
/* 2205 */ 'S', 'P', 0,
|
||
|
/* 2208 */ 'M', 'S', 'A', 'I', 'R', 0,
|
||
|
/* 2214 */ 'M', 'S', 'A', 'C', 'S', 'R', 0,
|
||
|
/* 2221 */ 'A', 'T', 0,
|
||
|
/* 2224 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
|
||
|
/* 2233 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0,
|
||
|
/* 2241 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
|
||
|
/* 2252 */ 'M', 'S', 'A', 'M', 'a', 'p', 0,
|
||
|
/* 2259 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0,
|
||
|
/* 2268 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
|
||
|
/* 2275 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0,
|
||
|
/* 2285 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
|
||
|
/* 2295 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0,
|
||
|
/* 2306 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0,
|
||
|
/* 2316 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
|
||
|
};
|
||
|
|
||
|
extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
|
||
|
{ 5, 0, 0, 0, 0, 0 },
|
||
|
{ 2221, 1, 82, 1, 4033, 0 },
|
||
|
{ 2224, 1, 1, 1, 4033, 0 },
|
||
|
{ 2316, 1, 1, 1, 4033, 0 },
|
||
|
{ 2187, 1, 1, 1, 4033, 0 },
|
||
|
{ 2241, 8, 1, 2, 32, 4 },
|
||
|
{ 2268, 1, 1, 1, 1089, 0 },
|
||
|
{ 2285, 1, 1, 1, 1089, 0 },
|
||
|
{ 2199, 1, 102, 1, 1089, 0 },
|
||
|
{ 2202, 1, 104, 1, 1089, 0 },
|
||
|
{ 2275, 1, 1, 1, 1089, 0 },
|
||
|
{ 2214, 1, 1, 1, 1089, 0 },
|
||
|
{ 2208, 1, 1, 1, 1089, 0 },
|
||
|
{ 2252, 1, 1, 1, 1089, 0 },
|
||
|
{ 2306, 1, 1, 1, 1089, 0 },
|
||
|
{ 2295, 1, 1, 1, 1089, 0 },
|
||
|
{ 2233, 1, 1, 1, 1089, 0 },
|
||
|
{ 2259, 1, 1, 1, 1089, 0 },
|
||
|
{ 2184, 1, 1, 1, 1089, 0 },
|
||
|
{ 2181, 1, 106, 1, 1089, 0 },
|
||
|
{ 2205, 1, 108, 1, 1089, 0 },
|
||
|
{ 2194, 1, 110, 1, 1089, 0 },
|
||
|
{ 179, 1, 110, 1, 1089, 0 },
|
||
|
{ 419, 1, 110, 1, 1089, 0 },
|
||
|
{ 611, 1, 110, 1, 1089, 0 },
|
||
|
{ 797, 1, 110, 1, 1089, 0 },
|
||
|
{ 182, 227, 110, 9, 1042, 10 },
|
||
|
{ 422, 227, 1, 9, 1042, 10 },
|
||
|
{ 614, 227, 1, 9, 1042, 10 },
|
||
|
{ 800, 227, 1, 9, 1042, 10 },
|
||
|
{ 1385, 238, 1, 0, 0, 2 },
|
||
|
{ 0, 1, 1, 1, 1153, 0 },
|
||
|
{ 240, 1, 1, 1, 1153, 0 },
|
||
|
{ 480, 1, 1, 1, 1153, 0 },
|
||
|
{ 666, 1, 1, 1, 1153, 0 },
|
||
|
{ 844, 1, 1, 1, 1153, 0 },
|
||
|
{ 1427, 1, 1, 1, 1153, 0 },
|
||
|
{ 1581, 1, 1, 1, 1153, 0 },
|
||
|
{ 1731, 1, 1, 1, 1153, 0 },
|
||
|
{ 1881, 1, 1, 1, 1153, 0 },
|
||
|
{ 2023, 1, 1, 1, 1153, 0 },
|
||
|
{ 90, 1, 1, 1, 1153, 0 },
|
||
|
{ 330, 1, 1, 1, 1153, 0 },
|
||
|
{ 570, 1, 1, 1, 1153, 0 },
|
||
|
{ 756, 1, 1, 1, 1153, 0 },
|
||
|
{ 934, 1, 1, 1, 1153, 0 },
|
||
|
{ 1517, 1, 1, 1, 1153, 0 },
|
||
|
{ 1667, 1, 1, 1, 1153, 0 },
|
||
|
{ 1817, 1, 1, 1, 1153, 0 },
|
||
|
{ 1967, 1, 1, 1, 1153, 0 },
|
||
|
{ 2125, 1, 1, 1, 1153, 0 },
|
||
|
{ 157, 1, 1, 1, 1153, 0 },
|
||
|
{ 397, 1, 1, 1, 1153, 0 },
|
||
|
{ 605, 1, 1, 1, 1153, 0 },
|
||
|
{ 791, 1, 1, 1, 1153, 0 },
|
||
|
{ 956, 1, 1, 1, 1153, 0 },
|
||
|
{ 1539, 1, 1, 1, 1153, 0 },
|
||
|
{ 1689, 1, 1, 1, 1153, 0 },
|
||
|
{ 1839, 1, 1, 1, 1153, 0 },
|
||
|
{ 1989, 1, 1, 1, 1153, 0 },
|
||
|
{ 2147, 1, 1, 1, 1153, 0 },
|
||
|
{ 6, 1, 1, 1, 1153, 0 },
|
||
|
{ 246, 1, 1, 1, 1153, 0 },
|
||
|
{ 486, 1, 1, 1, 1153, 0 },
|
||
|
{ 672, 1, 1, 1, 1153, 0 },
|
||
|
{ 850, 1, 1, 1, 1153, 0 },
|
||
|
{ 1433, 1, 1, 1, 1153, 0 },
|
||
|
{ 1587, 1, 1, 1, 1153, 0 },
|
||
|
{ 1737, 1, 1, 1, 1153, 0 },
|
||
|
{ 1887, 1, 1, 1, 1153, 0 },
|
||
|
{ 2029, 1, 1, 1, 1153, 0 },
|
||
|
{ 58, 1, 1, 1, 1153, 0 },
|
||
|
{ 298, 1, 1, 1, 1153, 0 },
|
||
|
{ 538, 1, 1, 1, 1153, 0 },
|
||
|
{ 724, 1, 1, 1, 1153, 0 },
|
||
|
{ 902, 1, 1, 1, 1153, 0 },
|
||
|
{ 1485, 1, 1, 1, 1153, 0 },
|
||
|
{ 1635, 1, 1, 1, 1153, 0 },
|
||
|
{ 1785, 1, 1, 1, 1153, 0 },
|
||
|
{ 1935, 1, 1, 1, 1153, 0 },
|
||
|
{ 2093, 1, 1, 1, 1153, 0 },
|
||
|
{ 125, 1, 1, 1, 1153, 0 },
|
||
|
{ 365, 1, 1, 1, 1153, 0 },
|
||
|
{ 13, 1, 1, 1, 1153, 0 },
|
||
|
{ 253, 1, 1, 1, 1153, 0 },
|
||
|
{ 493, 1, 1, 1, 1153, 0 },
|
||
|
{ 679, 1, 1, 1, 1153, 0 },
|
||
|
{ 857, 1, 1, 1, 1153, 0 },
|
||
|
{ 1440, 1, 1, 1, 1153, 0 },
|
||
|
{ 1594, 1, 1, 1, 1153, 0 },
|
||
|
{ 1744, 1, 1, 1, 1153, 0 },
|
||
|
{ 1894, 1, 1, 1, 1153, 0 },
|
||
|
{ 2036, 1, 1, 1, 1153, 0 },
|
||
|
{ 65, 1, 1, 1, 1153, 0 },
|
||
|
{ 305, 1, 1, 1, 1153, 0 },
|
||
|
{ 545, 1, 1, 1, 1153, 0 },
|
||
|
{ 731, 1, 1, 1, 1153, 0 },
|
||
|
{ 909, 1, 1, 1, 1153, 0 },
|
||
|
{ 1492, 1, 1, 1, 1153, 0 },
|
||
|
{ 1642, 1, 1, 1, 1153, 0 },
|
||
|
{ 1792, 1, 1, 1, 1153, 0 },
|
||
|
{ 1942, 1, 1, 1, 1153, 0 },
|
||
|
{ 2100, 1, 1, 1, 1153, 0 },
|
||
|
{ 132, 1, 1, 1, 1153, 0 },
|
||
|
{ 372, 1, 1, 1, 1153, 0 },
|
||
|
{ 20, 1, 1, 1, 1153, 0 },
|
||
|
{ 260, 1, 1, 1, 1153, 0 },
|
||
|
{ 500, 1, 1, 1, 1153, 0 },
|
||
|
{ 686, 1, 1, 1, 1153, 0 },
|
||
|
{ 864, 1, 1, 1, 1153, 0 },
|
||
|
{ 1447, 1, 1, 1, 1153, 0 },
|
||
|
{ 1601, 1, 1, 1, 1153, 0 },
|
||
|
{ 1751, 1, 1, 1, 1153, 0 },
|
||
|
{ 1901, 1, 1, 1, 1153, 0 },
|
||
|
{ 2043, 1, 1, 1, 1153, 0 },
|
||
|
{ 72, 1, 1, 1, 1153, 0 },
|
||
|
{ 312, 1, 1, 1, 1153, 0 },
|
||
|
{ 552, 1, 1, 1, 1153, 0 },
|
||
|
{ 738, 1, 1, 1, 1153, 0 },
|
||
|
{ 916, 1, 1, 1, 1153, 0 },
|
||
|
{ 1499, 1, 1, 1, 1153, 0 },
|
||
|
{ 1649, 1, 1, 1, 1153, 0 },
|
||
|
{ 1799, 1, 1, 1, 1153, 0 },
|
||
|
{ 1949, 1, 1, 1, 1153, 0 },
|
||
|
{ 2107, 1, 1, 1, 1153, 0 },
|
||
|
{ 139, 1, 1, 1, 1153, 0 },
|
||
|
{ 379, 1, 1, 1, 1153, 0 },
|
||
|
{ 191, 14, 1, 9, 994, 10 },
|
||
|
{ 431, 17, 1, 9, 994, 10 },
|
||
|
{ 623, 20, 1, 9, 994, 10 },
|
||
|
{ 809, 23, 1, 9, 994, 10 },
|
||
|
{ 1396, 26, 1, 9, 994, 10 },
|
||
|
{ 1550, 29, 1, 9, 994, 10 },
|
||
|
{ 1700, 32, 1, 9, 994, 10 },
|
||
|
{ 1850, 35, 1, 9, 994, 10 },
|
||
|
{ 1995, 38, 1, 9, 994, 10 },
|
||
|
{ 2153, 41, 1, 9, 994, 10 },
|
||
|
{ 27, 44, 1, 9, 994, 10 },
|
||
|
{ 267, 47, 1, 9, 994, 10 },
|
||
|
{ 507, 50, 1, 9, 994, 10 },
|
||
|
{ 693, 53, 1, 9, 994, 10 },
|
||
|
{ 871, 56, 1, 9, 994, 10 },
|
||
|
{ 1454, 59, 1, 9, 994, 10 },
|
||
|
{ 112, 1, 144, 1, 2305, 0 },
|
||
|
{ 352, 1, 142, 1, 2305, 0 },
|
||
|
{ 592, 1, 140, 1, 2305, 0 },
|
||
|
{ 778, 1, 138, 1, 2305, 0 },
|
||
|
{ 194, 1, 159, 1, 4001, 0 },
|
||
|
{ 434, 1, 163, 1, 4001, 0 },
|
||
|
{ 626, 1, 163, 1, 4001, 0 },
|
||
|
{ 812, 1, 167, 1, 4001, 0 },
|
||
|
{ 1399, 1, 167, 1, 4001, 0 },
|
||
|
{ 1553, 1, 171, 1, 4001, 0 },
|
||
|
{ 1703, 1, 171, 1, 4001, 0 },
|
||
|
{ 1853, 1, 175, 1, 4001, 0 },
|
||
|
{ 1998, 1, 175, 1, 4001, 0 },
|
||
|
{ 2156, 1, 179, 1, 4001, 0 },
|
||
|
{ 31, 1, 179, 1, 4001, 0 },
|
||
|
{ 271, 1, 183, 1, 4001, 0 },
|
||
|
{ 511, 1, 183, 1, 4001, 0 },
|
||
|
{ 697, 1, 187, 1, 4001, 0 },
|
||
|
{ 875, 1, 187, 1, 4001, 0 },
|
||
|
{ 1458, 1, 191, 1, 4001, 0 },
|
||
|
{ 1608, 1, 191, 1, 4001, 0 },
|
||
|
{ 1758, 1, 195, 1, 4001, 0 },
|
||
|
{ 1908, 1, 195, 1, 4001, 0 },
|
||
|
{ 2050, 1, 199, 1, 4001, 0 },
|
||
|
{ 79, 1, 199, 1, 4001, 0 },
|
||
|
{ 319, 1, 203, 1, 4001, 0 },
|
||
|
{ 559, 1, 203, 1, 4001, 0 },
|
||
|
{ 745, 1, 207, 1, 4001, 0 },
|
||
|
{ 923, 1, 207, 1, 4001, 0 },
|
||
|
{ 1506, 1, 211, 1, 4001, 0 },
|
||
|
{ 1656, 1, 211, 1, 4001, 0 },
|
||
|
{ 1806, 1, 215, 1, 4001, 0 },
|
||
|
{ 1956, 1, 215, 1, 4001, 0 },
|
||
|
{ 2114, 1, 219, 1, 4001, 0 },
|
||
|
{ 146, 1, 219, 1, 4001, 0 },
|
||
|
{ 386, 1, 223, 1, 4001, 0 },
|
||
|
{ 186, 1, 1, 1, 4001, 0 },
|
||
|
{ 426, 1, 1, 1, 4001, 0 },
|
||
|
{ 618, 1, 1, 1, 4001, 0 },
|
||
|
{ 804, 1, 1, 1, 4001, 0 },
|
||
|
{ 1391, 1, 1, 1, 4001, 0 },
|
||
|
{ 1545, 1, 1, 1, 4001, 0 },
|
||
|
{ 1695, 1, 1, 1, 4001, 0 },
|
||
|
{ 1845, 1, 1, 1, 4001, 0 },
|
||
|
{ 218, 1, 1, 1, 4001, 0 },
|
||
|
{ 458, 1, 1, 1, 4001, 0 },
|
||
|
{ 647, 1, 1, 1, 4001, 0 },
|
||
|
{ 825, 1, 1, 1, 4001, 0 },
|
||
|
{ 1408, 1, 1, 1, 4001, 0 },
|
||
|
{ 1562, 1, 1, 1, 4001, 0 },
|
||
|
{ 1712, 1, 1, 1, 4001, 0 },
|
||
|
{ 1862, 1, 1, 1, 4001, 0 },
|
||
|
{ 2007, 1, 1, 1, 4001, 0 },
|
||
|
{ 2165, 1, 1, 1, 4001, 0 },
|
||
|
{ 42, 1, 1, 1, 4001, 0 },
|
||
|
{ 282, 1, 1, 1, 4001, 0 },
|
||
|
{ 522, 1, 1, 1, 4001, 0 },
|
||
|
{ 708, 1, 1, 1, 4001, 0 },
|
||
|
{ 886, 1, 1, 1, 4001, 0 },
|
||
|
{ 1469, 1, 1, 1, 4001, 0 },
|
||
|
{ 1619, 1, 1, 1, 4001, 0 },
|
||
|
{ 1769, 1, 1, 1, 4001, 0 },
|
||
|
{ 1919, 1, 1, 1, 4001, 0 },
|
||
|
{ 2061, 1, 1, 1, 4001, 0 },
|
||
|
{ 96, 1, 1, 1, 4001, 0 },
|
||
|
{ 336, 1, 1, 1, 4001, 0 },
|
||
|
{ 576, 1, 1, 1, 4001, 0 },
|
||
|
{ 762, 1, 1, 1, 4001, 0 },
|
||
|
{ 940, 1, 1, 1, 4001, 0 },
|
||
|
{ 1523, 1, 1, 1, 4001, 0 },
|
||
|
{ 1673, 1, 1, 1, 4001, 0 },
|
||
|
{ 1823, 1, 1, 1, 4001, 0 },
|
||
|
{ 1973, 1, 1, 1, 4001, 0 },
|
||
|
{ 2131, 1, 1, 1, 4001, 0 },
|
||
|
{ 163, 1, 1, 1, 4001, 0 },
|
||
|
{ 403, 1, 1, 1, 4001, 0 },
|
||
|
{ 1367, 136, 1, 0, 1184, 2 },
|
||
|
{ 197, 1, 156, 1, 3969, 0 },
|
||
|
{ 437, 1, 156, 1, 3969, 0 },
|
||
|
{ 629, 1, 156, 1, 3969, 0 },
|
||
|
{ 815, 1, 156, 1, 3969, 0 },
|
||
|
{ 1402, 1, 156, 1, 3969, 0 },
|
||
|
{ 1556, 1, 156, 1, 3969, 0 },
|
||
|
{ 1706, 1, 156, 1, 3969, 0 },
|
||
|
{ 1856, 1, 156, 1, 3969, 0 },
|
||
|
{ 2001, 1, 156, 1, 3969, 0 },
|
||
|
{ 2159, 1, 156, 1, 3969, 0 },
|
||
|
{ 35, 1, 156, 1, 3969, 0 },
|
||
|
{ 275, 1, 156, 1, 3969, 0 },
|
||
|
{ 515, 1, 156, 1, 3969, 0 },
|
||
|
{ 701, 1, 156, 1, 3969, 0 },
|
||
|
{ 879, 1, 156, 1, 3969, 0 },
|
||
|
{ 1462, 1, 156, 1, 3969, 0 },
|
||
|
{ 1612, 1, 156, 1, 3969, 0 },
|
||
|
{ 1762, 1, 156, 1, 3969, 0 },
|
||
|
{ 1912, 1, 156, 1, 3969, 0 },
|
||
|
{ 2054, 1, 156, 1, 3969, 0 },
|
||
|
{ 83, 1, 156, 1, 3969, 0 },
|
||
|
{ 323, 1, 156, 1, 3969, 0 },
|
||
|
{ 563, 1, 156, 1, 3969, 0 },
|
||
|
{ 749, 1, 156, 1, 3969, 0 },
|
||
|
{ 927, 1, 156, 1, 3969, 0 },
|
||
|
{ 1510, 1, 156, 1, 3969, 0 },
|
||
|
{ 1660, 1, 156, 1, 3969, 0 },
|
||
|
{ 1810, 1, 156, 1, 3969, 0 },
|
||
|
{ 1960, 1, 156, 1, 3969, 0 },
|
||
|
{ 2118, 1, 156, 1, 3969, 0 },
|
||
|
{ 150, 1, 156, 1, 3969, 0 },
|
||
|
{ 390, 1, 156, 1, 3969, 0 },
|
||
|
{ 1373, 128, 1, 0, 1216, 2 },
|
||
|
{ 199, 1, 234, 1, 1826, 0 },
|
||
|
{ 439, 1, 134, 1, 1826, 0 },
|
||
|
{ 631, 1, 134, 1, 1826, 0 },
|
||
|
{ 817, 1, 134, 1, 1826, 0 },
|
||
|
{ 223, 1, 1, 1, 3937, 0 },
|
||
|
{ 463, 1, 1, 1, 3937, 0 },
|
||
|
{ 652, 1, 1, 1, 3937, 0 },
|
||
|
{ 830, 1, 1, 1, 3937, 0 },
|
||
|
{ 1413, 1, 1, 1, 3937, 0 },
|
||
|
{ 1567, 1, 1, 1, 3937, 0 },
|
||
|
{ 1717, 1, 1, 1, 3937, 0 },
|
||
|
{ 1867, 1, 1, 1, 3937, 0 },
|
||
|
{ 2012, 1, 1, 1, 3937, 0 },
|
||
|
{ 2170, 1, 1, 1, 3937, 0 },
|
||
|
{ 48, 1, 1, 1, 3937, 0 },
|
||
|
{ 288, 1, 1, 1, 3937, 0 },
|
||
|
{ 528, 1, 1, 1, 3937, 0 },
|
||
|
{ 714, 1, 1, 1, 3937, 0 },
|
||
|
{ 892, 1, 1, 1, 3937, 0 },
|
||
|
{ 1475, 1, 1, 1, 3937, 0 },
|
||
|
{ 1625, 1, 1, 1, 3937, 0 },
|
||
|
{ 1775, 1, 1, 1, 3937, 0 },
|
||
|
{ 1925, 1, 1, 1, 3937, 0 },
|
||
|
{ 2067, 1, 1, 1, 3937, 0 },
|
||
|
{ 102, 1, 1, 1, 3937, 0 },
|
||
|
{ 342, 1, 1, 1, 3937, 0 },
|
||
|
{ 582, 1, 1, 1, 3937, 0 },
|
||
|
{ 768, 1, 1, 1, 3937, 0 },
|
||
|
{ 946, 1, 1, 1, 3937, 0 },
|
||
|
{ 1529, 1, 1, 1, 3937, 0 },
|
||
|
{ 1679, 1, 1, 1, 3937, 0 },
|
||
|
{ 1829, 1, 1, 1, 3937, 0 },
|
||
|
{ 1979, 1, 1, 1, 3937, 0 },
|
||
|
{ 2137, 1, 1, 1, 3937, 0 },
|
||
|
{ 169, 1, 1, 1, 3937, 0 },
|
||
|
{ 409, 1, 1, 1, 3937, 0 },
|
||
|
{ 203, 1, 100, 1, 3937, 0 },
|
||
|
{ 443, 1, 100, 1, 3937, 0 },
|
||
|
{ 211, 1, 230, 1, 1794, 0 },
|
||
|
{ 451, 1, 126, 1, 1794, 0 },
|
||
|
{ 640, 1, 126, 1, 1794, 0 },
|
||
|
{ 821, 1, 126, 1, 1794, 0 },
|
||
|
{ 206, 1, 1, 1, 3905, 0 },
|
||
|
{ 446, 1, 1, 1, 3905, 0 },
|
||
|
{ 635, 1, 1, 1, 3905, 0 },
|
||
|
{ 215, 1, 1, 1, 3905, 0 },
|
||
|
{ 455, 1, 1, 1, 3905, 0 },
|
||
|
{ 644, 1, 1, 1, 3905, 0 },
|
||
|
{ 1353, 124, 1, 0, 1248, 2 },
|
||
|
{ 228, 1, 98, 1, 3873, 0 },
|
||
|
{ 468, 1, 98, 1, 3873, 0 },
|
||
|
{ 657, 1, 98, 1, 3873, 0 },
|
||
|
{ 835, 1, 98, 1, 3873, 0 },
|
||
|
{ 1418, 1, 98, 1, 3873, 0 },
|
||
|
{ 1572, 1, 98, 1, 3873, 0 },
|
||
|
{ 1722, 1, 98, 1, 3873, 0 },
|
||
|
{ 1872, 1, 98, 1, 3873, 0 },
|
||
|
{ 1379, 122, 1, 0, 1280, 2 },
|
||
|
{ 231, 1, 96, 1, 3841, 0 },
|
||
|
{ 471, 1, 96, 1, 3841, 0 },
|
||
|
{ 660, 1, 96, 1, 3841, 0 },
|
||
|
{ 838, 1, 96, 1, 3841, 0 },
|
||
|
{ 1421, 1, 96, 1, 3841, 0 },
|
||
|
{ 1575, 1, 96, 1, 3841, 0 },
|
||
|
{ 1725, 1, 96, 1, 3841, 0 },
|
||
|
{ 1875, 1, 96, 1, 3841, 0 },
|
||
|
{ 2017, 1, 96, 1, 3841, 0 },
|
||
|
{ 2175, 1, 96, 1, 3841, 0 },
|
||
|
{ 234, 1, 96, 1, 3841, 0 },
|
||
|
{ 474, 1, 96, 1, 3841, 0 },
|
||
|
{ 237, 92, 1, 8, 1425, 10 },
|
||
|
{ 477, 92, 1, 8, 1425, 10 },
|
||
|
{ 663, 92, 1, 8, 1425, 10 },
|
||
|
{ 841, 92, 1, 8, 1425, 10 },
|
||
|
{ 1424, 92, 1, 8, 1425, 10 },
|
||
|
{ 1578, 92, 1, 8, 1425, 10 },
|
||
|
{ 1728, 92, 1, 8, 1425, 10 },
|
||
|
{ 1878, 92, 1, 8, 1425, 10 },
|
||
|
{ 2020, 92, 1, 8, 1425, 10 },
|
||
|
{ 2178, 92, 1, 8, 1425, 10 },
|
||
|
{ 54, 92, 1, 8, 1425, 10 },
|
||
|
{ 294, 92, 1, 8, 1425, 10 },
|
||
|
{ 534, 92, 1, 8, 1425, 10 },
|
||
|
{ 720, 92, 1, 8, 1425, 10 },
|
||
|
{ 898, 92, 1, 8, 1425, 10 },
|
||
|
{ 1481, 92, 1, 8, 1425, 10 },
|
||
|
{ 1631, 92, 1, 8, 1425, 10 },
|
||
|
{ 1781, 92, 1, 8, 1425, 10 },
|
||
|
{ 1931, 92, 1, 8, 1425, 10 },
|
||
|
{ 2073, 92, 1, 8, 1425, 10 },
|
||
|
{ 108, 92, 1, 8, 1425, 10 },
|
||
|
{ 348, 92, 1, 8, 1425, 10 },
|
||
|
{ 588, 92, 1, 8, 1425, 10 },
|
||
|
{ 774, 92, 1, 8, 1425, 10 },
|
||
|
{ 952, 92, 1, 8, 1425, 10 },
|
||
|
{ 1535, 92, 1, 8, 1425, 10 },
|
||
|
{ 1685, 92, 1, 8, 1425, 10 },
|
||
|
{ 1835, 92, 1, 8, 1425, 10 },
|
||
|
{ 1985, 92, 1, 8, 1425, 10 },
|
||
|
{ 2143, 92, 1, 8, 1425, 10 },
|
||
|
{ 175, 92, 1, 8, 1425, 10 },
|
||
|
{ 415, 92, 1, 8, 1425, 10 },
|
||
|
{ 1359, 118, 1, 0, 1921, 2 },
|
||
|
{ 983, 118, 1, 0, 1921, 2 },
|
||
|
{ 1061, 118, 1, 0, 1921, 2 },
|
||
|
{ 1111, 118, 1, 0, 1921, 2 },
|
||
|
{ 1149, 118, 1, 0, 1921, 2 },
|
||
|
{ 989, 130, 1, 12, 656, 10 },
|
||
|
{ 996, 93, 157, 9, 1377, 10 },
|
||
|
{ 1067, 93, 157, 9, 1377, 10 },
|
||
|
{ 1117, 93, 157, 9, 1377, 10 },
|
||
|
{ 1155, 93, 157, 9, 1377, 10 },
|
||
|
{ 1187, 93, 157, 9, 1377, 10 },
|
||
|
{ 1219, 93, 157, 9, 1377, 10 },
|
||
|
{ 1251, 93, 157, 9, 1377, 10 },
|
||
|
{ 1283, 93, 157, 9, 1377, 10 },
|
||
|
{ 1315, 93, 157, 9, 1377, 10 },
|
||
|
{ 1341, 93, 157, 9, 1377, 10 },
|
||
|
{ 962, 93, 157, 9, 1377, 10 },
|
||
|
{ 1040, 93, 157, 9, 1377, 10 },
|
||
|
{ 1097, 93, 157, 9, 1377, 10 },
|
||
|
{ 1135, 93, 157, 9, 1377, 10 },
|
||
|
{ 1173, 93, 157, 9, 1377, 10 },
|
||
|
{ 1205, 93, 157, 9, 1377, 10 },
|
||
|
{ 1237, 93, 157, 9, 1377, 10 },
|
||
|
{ 1269, 93, 157, 9, 1377, 10 },
|
||
|
{ 1301, 93, 157, 9, 1377, 10 },
|
||
|
{ 1327, 93, 157, 9, 1377, 10 },
|
||
|
{ 969, 93, 157, 9, 1377, 10 },
|
||
|
{ 1047, 93, 157, 9, 1377, 10 },
|
||
|
{ 1104, 93, 157, 9, 1377, 10 },
|
||
|
{ 1142, 93, 157, 9, 1377, 10 },
|
||
|
{ 1180, 93, 157, 9, 1377, 10 },
|
||
|
{ 1212, 93, 157, 9, 1377, 10 },
|
||
|
{ 1244, 93, 157, 9, 1377, 10 },
|
||
|
{ 1276, 93, 157, 9, 1377, 10 },
|
||
|
{ 1308, 93, 157, 9, 1377, 10 },
|
||
|
{ 1334, 93, 157, 9, 1377, 10 },
|
||
|
{ 976, 93, 157, 9, 1377, 10 },
|
||
|
{ 1054, 93, 157, 9, 1377, 10 },
|
||
|
{ 2077, 1, 116, 1, 1120, 0 },
|
||
|
{ 1002, 138, 236, 0, 1344, 2 },
|
||
|
{ 1009, 150, 1, 0, 2337, 2 },
|
||
|
{ 1073, 150, 1, 0, 2337, 2 },
|
||
|
{ 1015, 150, 232, 0, 1312, 2 },
|
||
|
{ 1022, 152, 1, 0, 2369, 2 },
|
||
|
{ 1079, 152, 1, 0, 2369, 2 },
|
||
|
{ 1123, 152, 1, 0, 2369, 2 },
|
||
|
{ 1161, 152, 1, 0, 2369, 2 },
|
||
|
{ 1193, 152, 1, 0, 2369, 2 },
|
||
|
{ 1225, 152, 1, 0, 2369, 2 },
|
||
|
{ 1257, 152, 1, 0, 2369, 2 },
|
||
|
{ 1289, 152, 1, 0, 2369, 2 },
|
||
|
{ 1028, 154, 1, 0, 2369, 2 },
|
||
|
{ 1085, 154, 1, 0, 2369, 2 },
|
||
|
{ 1129, 154, 1, 0, 2369, 2 },
|
||
|
{ 1167, 154, 1, 0, 2369, 2 },
|
||
|
{ 1199, 154, 1, 0, 2369, 2 },
|
||
|
{ 1231, 154, 1, 0, 2369, 2 },
|
||
|
{ 1263, 154, 1, 0, 2369, 2 },
|
||
|
{ 1295, 154, 1, 0, 2369, 2 },
|
||
|
{ 1321, 154, 1, 0, 2369, 2 },
|
||
|
{ 1347, 154, 1, 0, 2369, 2 },
|
||
|
{ 1034, 154, 1, 0, 2369, 2 },
|
||
|
{ 1091, 154, 1, 0, 2369, 2 },
|
||
|
};
|
||
|
|
||
|
extern const MCPhysReg MipsRegUnitRoots[][2] = {
|
||
|
{ Mips::AT },
|
||
|
{ Mips::DSPCCond },
|
||
|
{ Mips::DSPCarry },
|
||
|
{ Mips::DSPEFI },
|
||
|
{ Mips::DSPOutFlag16_19 },
|
||
|
{ Mips::DSPOutFlag20 },
|
||
|
{ Mips::DSPOutFlag21 },
|
||
|
{ Mips::DSPOutFlag22 },
|
||
|
{ Mips::DSPOutFlag23 },
|
||
|
{ Mips::DSPPos },
|
||
|
{ Mips::DSPSCount },
|
||
|
{ Mips::FP },
|
||
|
{ Mips::GP },
|
||
|
{ Mips::MSAAccess },
|
||
|
{ Mips::MSACSR },
|
||
|
{ Mips::MSAIR },
|
||
|
{ Mips::MSAMap },
|
||
|
{ Mips::MSAModify },
|
||
|
{ Mips::MSARequest },
|
||
|
{ Mips::MSASave },
|
||
|
{ Mips::MSAUnmap },
|
||
|
{ Mips::PC },
|
||
|
{ Mips::RA },
|
||
|
{ Mips::SP },
|
||
|
{ Mips::ZERO },
|
||
|
{ Mips::A0 },
|
||
|
{ Mips::A1 },
|
||
|
{ Mips::A2 },
|
||
|
{ Mips::A3 },
|
||
|
{ Mips::LO0 },
|
||
|
{ Mips::HI0 },
|
||
|
{ Mips::LO1 },
|
||
|
{ Mips::HI1 },
|
||
|
{ Mips::LO2 },
|
||
|
{ Mips::HI2 },
|
||
|
{ Mips::LO3 },
|
||
|
{ Mips::HI3 },
|
||
|
{ Mips::COP00 },
|
||
|
{ Mips::COP01 },
|
||
|
{ Mips::COP02 },
|
||
|
{ Mips::COP03 },
|
||
|
{ Mips::COP04 },
|
||
|
{ Mips::COP05 },
|
||
|
{ Mips::COP06 },
|
||
|
{ Mips::COP07 },
|
||
|
{ Mips::COP08 },
|
||
|
{ Mips::COP09 },
|
||
|
{ Mips::COP20 },
|
||
|
{ Mips::COP21 },
|
||
|
{ Mips::COP22 },
|
||
|
{ Mips::COP23 },
|
||
|
{ Mips::COP24 },
|
||
|
{ Mips::COP25 },
|
||
|
{ Mips::COP26 },
|
||
|
{ Mips::COP27 },
|
||
|
{ Mips::COP28 },
|
||
|
{ Mips::COP29 },
|
||
|
{ Mips::COP30 },
|
||
|
{ Mips::COP31 },
|
||
|
{ Mips::COP32 },
|
||
|
{ Mips::COP33 },
|
||
|
{ Mips::COP34 },
|
||
|
{ Mips::COP35 },
|
||
|
{ Mips::COP36 },
|
||
|
{ Mips::COP37 },
|
||
|
{ Mips::COP38 },
|
||
|
{ Mips::COP39 },
|
||
|
{ Mips::COP010 },
|
||
|
{ Mips::COP011 },
|
||
|
{ Mips::COP012 },
|
||
|
{ Mips::COP013 },
|
||
|
{ Mips::COP014 },
|
||
|
{ Mips::COP015 },
|
||
|
{ Mips::COP016 },
|
||
|
{ Mips::COP017 },
|
||
|
{ Mips::COP018 },
|
||
|
{ Mips::COP019 },
|
||
|
{ Mips::COP020 },
|
||
|
{ Mips::COP021 },
|
||
|
{ Mips::COP022 },
|
||
|
{ Mips::COP023 },
|
||
|
{ Mips::COP024 },
|
||
|
{ Mips::COP025 },
|
||
|
{ Mips::COP026 },
|
||
|
{ Mips::COP027 },
|
||
|
{ Mips::COP028 },
|
||
|
{ Mips::COP029 },
|
||
|
{ Mips::COP030 },
|
||
|
{ Mips::COP031 },
|
||
|
{ Mips::COP210 },
|
||
|
{ Mips::COP211 },
|
||
|
{ Mips::COP212 },
|
||
|
{ Mips::COP213 },
|
||
|
{ Mips::COP214 },
|
||
|
{ Mips::COP215 },
|
||
|
{ Mips::COP216 },
|
||
|
{ Mips::COP217 },
|
||
|
{ Mips::COP218 },
|
||
|
{ Mips::COP219 },
|
||
|
{ Mips::COP220 },
|
||
|
{ Mips::COP221 },
|
||
|
{ Mips::COP222 },
|
||
|
{ Mips::COP223 },
|
||
|
{ Mips::COP224 },
|
||
|
{ Mips::COP225 },
|
||
|
{ Mips::COP226 },
|
||
|
{ Mips::COP227 },
|
||
|
{ Mips::COP228 },
|
||
|
{ Mips::COP229 },
|
||
|
{ Mips::COP230 },
|
||
|
{ Mips::COP231 },
|
||
|
{ Mips::COP310 },
|
||
|
{ Mips::COP311 },
|
||
|
{ Mips::COP312 },
|
||
|
{ Mips::COP313 },
|
||
|
{ Mips::COP314 },
|
||
|
{ Mips::COP315 },
|
||
|
{ Mips::COP316 },
|
||
|
{ Mips::COP317 },
|
||
|
{ Mips::COP318 },
|
||
|
{ Mips::COP319 },
|
||
|
{ Mips::COP320 },
|
||
|
{ Mips::COP321 },
|
||
|
{ Mips::COP322 },
|
||
|
{ Mips::COP323 },
|
||
|
{ Mips::COP324 },
|
||
|
{ Mips::COP325 },
|
||
|
{ Mips::COP326 },
|
||
|
{ Mips::COP327 },
|
||
|
{ Mips::COP328 },
|
||
|
{ Mips::COP329 },
|
||
|
{ Mips::COP330 },
|
||
|
{ Mips::COP331 },
|
||
|
{ Mips::F0 },
|
||
|
{ Mips::F1 },
|
||
|
{ Mips::F2 },
|
||
|
{ Mips::F3 },
|
||
|
{ Mips::F4 },
|
||
|
{ Mips::F5 },
|
||
|
{ Mips::F6 },
|
||
|
{ Mips::F7 },
|
||
|
{ Mips::F8 },
|
||
|
{ Mips::F9 },
|
||
|
{ Mips::F10 },
|
||
|
{ Mips::F11 },
|
||
|
{ Mips::F12 },
|
||
|
{ Mips::F13 },
|
||
|
{ Mips::F14 },
|
||
|
{ Mips::F15 },
|
||
|
{ Mips::F16 },
|
||
|
{ Mips::F17 },
|
||
|
{ Mips::F18 },
|
||
|
{ Mips::F19 },
|
||
|
{ Mips::F20 },
|
||
|
{ Mips::F21 },
|
||
|
{ Mips::F22 },
|
||
|
{ Mips::F23 },
|
||
|
{ Mips::F24 },
|
||
|
{ Mips::F25 },
|
||
|
{ Mips::F26 },
|
||
|
{ Mips::F27 },
|
||
|
{ Mips::F28 },
|
||
|
{ Mips::F29 },
|
||
|
{ Mips::F30 },
|
||
|
{ Mips::F31 },
|
||
|
{ Mips::FCC0 },
|
||
|
{ Mips::FCC1 },
|
||
|
{ Mips::FCC2 },
|
||
|
{ Mips::FCC3 },
|
||
|
{ Mips::FCC4 },
|
||
|
{ Mips::FCC5 },
|
||
|
{ Mips::FCC6 },
|
||
|
{ Mips::FCC7 },
|
||
|
{ Mips::FCR0 },
|
||
|
{ Mips::FCR1 },
|
||
|
{ Mips::FCR2 },
|
||
|
{ Mips::FCR3 },
|
||
|
{ Mips::FCR4 },
|
||
|
{ Mips::FCR5 },
|
||
|
{ Mips::FCR6 },
|
||
|
{ Mips::FCR7 },
|
||
|
{ Mips::FCR8 },
|
||
|
{ Mips::FCR9 },
|
||
|
{ Mips::FCR10 },
|
||
|
{ Mips::FCR11 },
|
||
|
{ Mips::FCR12 },
|
||
|
{ Mips::FCR13 },
|
||
|
{ Mips::FCR14 },
|
||
|
{ Mips::FCR15 },
|
||
|
{ Mips::FCR16 },
|
||
|
{ Mips::FCR17 },
|
||
|
{ Mips::FCR18 },
|
||
|
{ Mips::FCR19 },
|
||
|
{ Mips::FCR20 },
|
||
|
{ Mips::FCR21 },
|
||
|
{ Mips::FCR22 },
|
||
|
{ Mips::FCR23 },
|
||
|
{ Mips::FCR24 },
|
||
|
{ Mips::FCR25 },
|
||
|
{ Mips::FCR26 },
|
||
|
{ Mips::FCR27 },
|
||
|
{ Mips::FCR28 },
|
||
|
{ Mips::FCR29 },
|
||
|
{ Mips::FCR30 },
|
||
|
{ Mips::FCR31 },
|
||
|
{ Mips::F_HI0 },
|
||
|
{ Mips::F_HI1 },
|
||
|
{ Mips::F_HI2 },
|
||
|
{ Mips::F_HI3 },
|
||
|
{ Mips::F_HI4 },
|
||
|
{ Mips::F_HI5 },
|
||
|
{ Mips::F_HI6 },
|
||
|
{ Mips::F_HI7 },
|
||
|
{ Mips::F_HI8 },
|
||
|
{ Mips::F_HI9 },
|
||
|
{ Mips::F_HI10 },
|
||
|
{ Mips::F_HI11 },
|
||
|
{ Mips::F_HI12 },
|
||
|
{ Mips::F_HI13 },
|
||
|
{ Mips::F_HI14 },
|
||
|
{ Mips::F_HI15 },
|
||
|
{ Mips::F_HI16 },
|
||
|
{ Mips::F_HI17 },
|
||
|
{ Mips::F_HI18 },
|
||
|
{ Mips::F_HI19 },
|
||
|
{ Mips::F_HI20 },
|
||
|
{ Mips::F_HI21 },
|
||
|
{ Mips::F_HI22 },
|
||
|
{ Mips::F_HI23 },
|
||
|
{ Mips::F_HI24 },
|
||
|
{ Mips::F_HI25 },
|
||
|
{ Mips::F_HI26 },
|
||
|
{ Mips::F_HI27 },
|
||
|
{ Mips::F_HI28 },
|
||
|
{ Mips::F_HI29 },
|
||
|
{ Mips::F_HI30 },
|
||
|
{ Mips::F_HI31 },
|
||
|
{ Mips::HWR0 },
|
||
|
{ Mips::HWR1 },
|
||
|
{ Mips::HWR2 },
|
||
|
{ Mips::HWR3 },
|
||
|
{ Mips::HWR4 },
|
||
|
{ Mips::HWR5 },
|
||
|
{ Mips::HWR6 },
|
||
|
{ Mips::HWR7 },
|
||
|
{ Mips::HWR8 },
|
||
|
{ Mips::HWR9 },
|
||
|
{ Mips::HWR10 },
|
||
|
{ Mips::HWR11 },
|
||
|
{ Mips::HWR12 },
|
||
|
{ Mips::HWR13 },
|
||
|
{ Mips::HWR14 },
|
||
|
{ Mips::HWR15 },
|
||
|
{ Mips::HWR16 },
|
||
|
{ Mips::HWR17 },
|
||
|
{ Mips::HWR18 },
|
||
|
{ Mips::HWR19 },
|
||
|
{ Mips::HWR20 },
|
||
|
{ Mips::HWR21 },
|
||
|
{ Mips::HWR22 },
|
||
|
{ Mips::HWR23 },
|
||
|
{ Mips::HWR24 },
|
||
|
{ Mips::HWR25 },
|
||
|
{ Mips::HWR26 },
|
||
|
{ Mips::HWR27 },
|
||
|
{ Mips::HWR28 },
|
||
|
{ Mips::HWR29 },
|
||
|
{ Mips::HWR30 },
|
||
|
{ Mips::HWR31 },
|
||
|
{ Mips::K0 },
|
||
|
{ Mips::K1 },
|
||
|
{ Mips::MPL0 },
|
||
|
{ Mips::MPL1 },
|
||
|
{ Mips::MPL2 },
|
||
|
{ Mips::P0 },
|
||
|
{ Mips::P1 },
|
||
|
{ Mips::P2 },
|
||
|
{ Mips::S0 },
|
||
|
{ Mips::S1 },
|
||
|
{ Mips::S2 },
|
||
|
{ Mips::S3 },
|
||
|
{ Mips::S4 },
|
||
|
{ Mips::S5 },
|
||
|
{ Mips::S6 },
|
||
|
{ Mips::S7 },
|
||
|
{ Mips::T0 },
|
||
|
{ Mips::T1 },
|
||
|
{ Mips::T2 },
|
||
|
{ Mips::T3 },
|
||
|
{ Mips::T4 },
|
||
|
{ Mips::T5 },
|
||
|
{ Mips::T6 },
|
||
|
{ Mips::T7 },
|
||
|
{ Mips::T8 },
|
||
|
{ Mips::T9 },
|
||
|
{ Mips::V0 },
|
||
|
{ Mips::V1 },
|
||
|
};
|
||
|
|
||
|
namespace { // Register classes...
|
||
|
// OddSP Register Class...
|
||
|
const MCPhysReg OddSP[] = {
|
||
|
Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
|
||
|
};
|
||
|
|
||
|
// OddSP Bit set.
|
||
|
const uint8_t OddSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||
|
};
|
||
|
|
||
|
// CCR Register Class...
|
||
|
const MCPhysReg CCR[] = {
|
||
|
Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
|
||
|
};
|
||
|
|
||
|
// CCR Bit set.
|
||
|
const uint8_t CCRBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// COP0 Register Class...
|
||
|
const MCPhysReg COP0[] = {
|
||
|
Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
|
||
|
};
|
||
|
|
||
|
// COP0 Bit set.
|
||
|
const uint8_t COP0Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// COP2 Register Class...
|
||
|
const MCPhysReg COP2[] = {
|
||
|
Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
|
||
|
};
|
||
|
|
||
|
// COP2 Bit set.
|
||
|
const uint8_t COP2Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
|
||
|
};
|
||
|
|
||
|
// COP3 Register Class...
|
||
|
const MCPhysReg COP3[] = {
|
||
|
Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
|
||
|
};
|
||
|
|
||
|
// COP3 Bit set.
|
||
|
const uint8_t COP3Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
|
||
|
};
|
||
|
|
||
|
// DSPR Register Class...
|
||
|
const MCPhysReg DSPR[] = {
|
||
|
Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
|
||
|
};
|
||
|
|
||
|
// DSPR Bit set.
|
||
|
const uint8_t DSPRBits[] = {
|
||
|
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// FGR32 Register Class...
|
||
|
const MCPhysReg FGR32[] = {
|
||
|
Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
|
||
|
};
|
||
|
|
||
|
// FGR32 Bit set.
|
||
|
const uint8_t FGR32Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// FGRCC Register Class...
|
||
|
const MCPhysReg FGRCC[] = {
|
||
|
Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
|
||
|
};
|
||
|
|
||
|
// FGRCC Bit set.
|
||
|
const uint8_t FGRCCBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// FGRH32 Register Class...
|
||
|
const MCPhysReg FGRH32[] = {
|
||
|
Mips::F_HI0, Mips::F_HI1, Mips::F_HI2, Mips::F_HI3, Mips::F_HI4, Mips::F_HI5, Mips::F_HI6, Mips::F_HI7, Mips::F_HI8, Mips::F_HI9, Mips::F_HI10, Mips::F_HI11, Mips::F_HI12, Mips::F_HI13, Mips::F_HI14, Mips::F_HI15, Mips::F_HI16, Mips::F_HI17, Mips::F_HI18, Mips::F_HI19, Mips::F_HI20, Mips::F_HI21, Mips::F_HI22, Mips::F_HI23, Mips::F_HI24, Mips::F_HI25, Mips::F_HI26, Mips::F_HI27, Mips::F_HI28, Mips::F_HI29, Mips::F_HI30, Mips::F_HI31,
|
||
|
};
|
||
|
|
||
|
// FGRH32 Bit set.
|
||
|
const uint8_t FGRH32Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||
|
};
|
||
|
|
||
|
// GPR32 Register Class...
|
||
|
const MCPhysReg GPR32[] = {
|
||
|
Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
|
||
|
};
|
||
|
|
||
|
// GPR32 Bit set.
|
||
|
const uint8_t GPR32Bits[] = {
|
||
|
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// HWRegs Register Class...
|
||
|
const MCPhysReg HWRegs[] = {
|
||
|
Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
|
||
|
};
|
||
|
|
||
|
// HWRegs Bit set.
|
||
|
const uint8_t HWRegsBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||
|
};
|
||
|
|
||
|
// OddSP_with_sub_hi Register Class...
|
||
|
const MCPhysReg OddSP_with_sub_hi[] = {
|
||
|
Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
|
||
|
};
|
||
|
|
||
|
// OddSP_with_sub_hi Bit set.
|
||
|
const uint8_t OddSP_with_sub_hiBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||
|
};
|
||
|
|
||
|
// FGR32_and_OddSP Register Class...
|
||
|
const MCPhysReg FGR32_and_OddSP[] = {
|
||
|
Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31,
|
||
|
};
|
||
|
|
||
|
// FGR32_and_OddSP Bit set.
|
||
|
const uint8_t FGR32_and_OddSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
||
|
};
|
||
|
|
||
|
// FGRH32_and_OddSP Register Class...
|
||
|
const MCPhysReg FGRH32_and_OddSP[] = {
|
||
|
Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31,
|
||
|
};
|
||
|
|
||
|
// FGRH32_and_OddSP Bit set.
|
||
|
const uint8_t FGRH32_and_OddSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
|
||
|
};
|
||
|
|
||
|
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
|
||
|
const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
|
||
|
Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
|
||
|
};
|
||
|
|
||
|
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
|
||
|
const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||
|
};
|
||
|
|
||
|
// CPU16RegsPlusSP Register Class...
|
||
|
const MCPhysReg CPU16RegsPlusSP[] = {
|
||
|
Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
|
||
|
};
|
||
|
|
||
|
// CPU16RegsPlusSP Bit set.
|
||
|
const uint8_t CPU16RegsPlusSPBits[] = {
|
||
|
0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// CPU16Regs Register Class...
|
||
|
const MCPhysReg CPU16Regs[] = {
|
||
|
Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
|
||
|
};
|
||
|
|
||
|
// CPU16Regs Bit set.
|
||
|
const uint8_t CPU16RegsBits[] = {
|
||
|
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// FCC Register Class...
|
||
|
const MCPhysReg FCC[] = {
|
||
|
Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
|
||
|
};
|
||
|
|
||
|
// FCC Bit set.
|
||
|
const uint8_t FCCBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
||
|
};
|
||
|
|
||
|
// GPRMM16 Register Class...
|
||
|
const MCPhysReg GPRMM16[] = {
|
||
|
Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
|
||
|
};
|
||
|
|
||
|
// GPRMM16 Bit set.
|
||
|
const uint8_t GPRMM16Bits[] = {
|
||
|
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// GPRMM16MoveP Register Class...
|
||
|
const MCPhysReg GPRMM16MoveP[] = {
|
||
|
Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
|
||
|
};
|
||
|
|
||
|
// GPRMM16MoveP Bit set.
|
||
|
const uint8_t GPRMM16MovePBits[] = {
|
||
|
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// GPRMM16Zero Register Class...
|
||
|
const MCPhysReg GPRMM16Zero[] = {
|
||
|
Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
|
||
|
};
|
||
|
|
||
|
// GPRMM16Zero Bit set.
|
||
|
const uint8_t GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// MSACtrl Register Class...
|
||
|
const MCPhysReg MSACtrl[] = {
|
||
|
Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap,
|
||
|
};
|
||
|
|
||
|
// MSACtrl Bit set.
|
||
|
const uint8_t MSACtrlBits[] = {
|
||
|
0x00, 0xfc, 0x03,
|
||
|
};
|
||
|
|
||
|
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
|
||
|
const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
|
||
|
Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15,
|
||
|
};
|
||
|
|
||
|
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
|
||
|
const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
||
|
};
|
||
|
|
||
|
// CPU16Regs_and_GPRMM16Zero Register Class...
|
||
|
const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
|
||
|
Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
|
||
|
};
|
||
|
|
||
|
// CPU16Regs_and_GPRMM16Zero Bit set.
|
||
|
const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// CPU16Regs_and_GPRMM16MoveP Register Class...
|
||
|
const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
|
||
|
Mips::S1, Mips::V0, Mips::V1, Mips::S0,
|
||
|
};
|
||
|
|
||
|
// CPU16Regs_and_GPRMM16MoveP Bit set.
|
||
|
const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// GPRMM16MoveP_and_GPRMM16Zero Register Class...
|
||
|
const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
|
||
|
Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
|
||
|
};
|
||
|
|
||
|
// GPRMM16MoveP_and_GPRMM16Zero Bit set.
|
||
|
const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// HI32DSP Register Class...
|
||
|
const MCPhysReg HI32DSP[] = {
|
||
|
Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
|
||
|
};
|
||
|
|
||
|
// HI32DSP Bit set.
|
||
|
const uint8_t HI32DSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
|
||
|
};
|
||
|
|
||
|
// LO32DSP Register Class...
|
||
|
const MCPhysReg LO32DSP[] = {
|
||
|
Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
|
||
|
};
|
||
|
|
||
|
// LO32DSP Bit set.
|
||
|
const uint8_t LO32DSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
||
|
};
|
||
|
|
||
|
// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
|
||
|
const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
|
||
|
Mips::S1, Mips::V0, Mips::V1,
|
||
|
};
|
||
|
|
||
|
// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
|
||
|
const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
|
||
|
};
|
||
|
|
||
|
// CPURAReg Register Class...
|
||
|
const MCPhysReg CPURAReg[] = {
|
||
|
Mips::RA,
|
||
|
};
|
||
|
|
||
|
// CPURAReg Bit set.
|
||
|
const uint8_t CPURARegBits[] = {
|
||
|
0x00, 0x00, 0x08,
|
||
|
};
|
||
|
|
||
|
// CPUSPReg Register Class...
|
||
|
const MCPhysReg CPUSPReg[] = {
|
||
|
Mips::SP,
|
||
|
};
|
||
|
|
||
|
// CPUSPReg Bit set.
|
||
|
const uint8_t CPUSPRegBits[] = {
|
||
|
0x00, 0x00, 0x10,
|
||
|
};
|
||
|
|
||
|
// DSPCC Register Class...
|
||
|
const MCPhysReg DSPCC[] = {
|
||
|
Mips::DSPCCond,
|
||
|
};
|
||
|
|
||
|
// DSPCC Bit set.
|
||
|
const uint8_t DSPCCBits[] = {
|
||
|
0x04,
|
||
|
};
|
||
|
|
||
|
// HI32 Register Class...
|
||
|
const MCPhysReg HI32[] = {
|
||
|
Mips::HI0,
|
||
|
};
|
||
|
|
||
|
// HI32 Bit set.
|
||
|
const uint8_t HI32Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||
|
};
|
||
|
|
||
|
// LO32 Register Class...
|
||
|
const MCPhysReg LO32[] = {
|
||
|
Mips::LO0,
|
||
|
};
|
||
|
|
||
|
// LO32 Bit set.
|
||
|
const uint8_t LO32Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
||
|
};
|
||
|
|
||
|
// FGR64 Register Class...
|
||
|
const MCPhysReg FGR64[] = {
|
||
|
Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
|
||
|
};
|
||
|
|
||
|
// FGR64 Bit set.
|
||
|
const uint8_t FGR64Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||
|
};
|
||
|
|
||
|
// GPR64 Register Class...
|
||
|
const MCPhysReg GPR64[] = {
|
||
|
Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
|
||
|
};
|
||
|
|
||
|
// GPR64 Bit set.
|
||
|
const uint8_t GPR64Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
|
||
|
};
|
||
|
|
||
|
// AFGR64 Register Class...
|
||
|
const MCPhysReg AFGR64[] = {
|
||
|
Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
|
||
|
};
|
||
|
|
||
|
// AFGR64 Bit set.
|
||
|
const uint8_t AFGR64Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
|
||
|
};
|
||
|
|
||
|
// FGR64_and_OddSP Register Class...
|
||
|
const MCPhysReg FGR64_and_OddSP[] = {
|
||
|
Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
|
||
|
};
|
||
|
|
||
|
// FGR64_and_OddSP Bit set.
|
||
|
const uint8_t FGR64_and_OddSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
|
||
|
Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// AFGR64_and_OddSP Register Class...
|
||
|
const MCPhysReg AFGR64_and_OddSP[] = {
|
||
|
Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15,
|
||
|
};
|
||
|
|
||
|
// AFGR64_and_OddSP Bit set.
|
||
|
const uint8_t AFGR64_and_OddSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16Regs Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
|
||
|
Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16Regs Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
|
||
|
Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16Zero Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
|
||
|
Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16Zero Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
|
||
|
Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// ACC64DSP Register Class...
|
||
|
const MCPhysReg ACC64DSP[] = {
|
||
|
Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
|
||
|
};
|
||
|
|
||
|
// ACC64DSP Bit set.
|
||
|
const uint8_t ACC64DSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x3c,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
|
||
|
Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
|
||
|
Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
|
||
|
Mips::V0_64, Mips::V1_64, Mips::S1_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
|
||
|
};
|
||
|
|
||
|
// OCTEON_MPL Register Class...
|
||
|
const MCPhysReg OCTEON_MPL[] = {
|
||
|
Mips::MPL0, Mips::MPL1, Mips::MPL2,
|
||
|
};
|
||
|
|
||
|
// OCTEON_MPL Bit set.
|
||
|
const uint8_t OCTEON_MPLBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
|
||
|
};
|
||
|
|
||
|
// OCTEON_P Register Class...
|
||
|
const MCPhysReg OCTEON_P[] = {
|
||
|
Mips::P0, Mips::P1, Mips::P2,
|
||
|
};
|
||
|
|
||
|
// OCTEON_P Bit set.
|
||
|
const uint8_t OCTEON_PBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
|
||
|
};
|
||
|
|
||
|
// ACC64 Register Class...
|
||
|
const MCPhysReg ACC64[] = {
|
||
|
Mips::AC0,
|
||
|
};
|
||
|
|
||
|
// ACC64 Bit set.
|
||
|
const uint8_t ACC64Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x04,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPURAReg Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
|
||
|
Mips::RA_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPURAReg Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPUSPReg Register Class...
|
||
|
const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
|
||
|
Mips::SP_64,
|
||
|
};
|
||
|
|
||
|
// GPR64_with_sub_32_in_CPUSPReg Bit set.
|
||
|
const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
||
|
};
|
||
|
|
||
|
// HI64 Register Class...
|
||
|
const MCPhysReg HI64[] = {
|
||
|
Mips::HI0_64,
|
||
|
};
|
||
|
|
||
|
// HI64 Bit set.
|
||
|
const uint8_t HI64Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
||
|
};
|
||
|
|
||
|
// LO64 Register Class...
|
||
|
const MCPhysReg LO64[] = {
|
||
|
Mips::LO0_64,
|
||
|
};
|
||
|
|
||
|
// LO64 Bit set.
|
||
|
const uint8_t LO64Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||
|
};
|
||
|
|
||
|
// MSA128B Register Class...
|
||
|
const MCPhysReg MSA128B[] = {
|
||
|
Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
|
||
|
};
|
||
|
|
||
|
// MSA128B Bit set.
|
||
|
const uint8_t MSA128BBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// MSA128D Register Class...
|
||
|
const MCPhysReg MSA128D[] = {
|
||
|
Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
|
||
|
};
|
||
|
|
||
|
// MSA128D Bit set.
|
||
|
const uint8_t MSA128DBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// MSA128H Register Class...
|
||
|
const MCPhysReg MSA128H[] = {
|
||
|
Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
|
||
|
};
|
||
|
|
||
|
// MSA128H Bit set.
|
||
|
const uint8_t MSA128HBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// MSA128W Register Class...
|
||
|
const MCPhysReg MSA128W[] = {
|
||
|
Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
|
||
|
};
|
||
|
|
||
|
// MSA128W Bit set.
|
||
|
const uint8_t MSA128WBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||
|
};
|
||
|
|
||
|
// MSA128B_with_sub_64_in_OddSP Register Class...
|
||
|
const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
|
||
|
Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31,
|
||
|
};
|
||
|
|
||
|
// MSA128B_with_sub_64_in_OddSP Bit set.
|
||
|
const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
||
|
};
|
||
|
|
||
|
// MSA128WEvens Register Class...
|
||
|
const MCPhysReg MSA128WEvens[] = {
|
||
|
Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
|
||
|
};
|
||
|
|
||
|
// MSA128WEvens Bit set.
|
||
|
const uint8_t MSA128WEvensBits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
|
||
|
};
|
||
|
|
||
|
// ACC128 Register Class...
|
||
|
const MCPhysReg ACC128[] = {
|
||
|
Mips::AC0_64,
|
||
|
};
|
||
|
|
||
|
// ACC128 Bit set.
|
||
|
const uint8_t ACC128Bits[] = {
|
||
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||
|
};
|
||
|
|
||
|
}
|
||
|
|
||
|
extern const char MipsRegClassStrings[] = {
|
||
|
/* 0 */ 'C', 'O', 'P', '0', 0,
|
||
|
/* 5 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', 'H', '3', '2', 0,
|
||
|
/* 45 */ 'H', 'I', '3', '2', 0,
|
||
|
/* 50 */ 'L', 'O', '3', '2', 0,
|
||
|
/* 55 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', '3', '2', 0,
|
||
|
/* 94 */ 'G', 'P', 'R', '3', '2', 0,
|
||
|
/* 100 */ 'C', 'O', 'P', '2', 0,
|
||
|
/* 105 */ 'C', 'O', 'P', '3', 0,
|
||
|
/* 110 */ 'A', 'C', 'C', '6', '4', 0,
|
||
|
/* 116 */ 'H', 'I', '6', '4', 0,
|
||
|
/* 121 */ 'L', 'O', '6', '4', 0,
|
||
|
/* 126 */ 'A', 'F', 'G', 'R', '6', '4', 0,
|
||
|
/* 133 */ 'G', 'P', 'R', '6', '4', 0,
|
||
|
/* 139 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0,
|
||
|
/* 147 */ 'A', 'C', 'C', '1', '2', '8', 0,
|
||
|
/* 154 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0,
|
||
|
/* 162 */ 'F', 'C', 'C', 0,
|
||
|
/* 166 */ 'D', 'S', 'P', 'C', 'C', 0,
|
||
|
/* 172 */ 'F', 'G', 'R', 'C', 'C', 0,
|
||
|
/* 178 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0,
|
||
|
/* 186 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0,
|
||
|
/* 194 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0,
|
||
|
/* 205 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0,
|
||
|
/* 213 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0,
|
||
|
/* 221 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
|
||
|
/* 230 */ 'F', 'G', 'R', 'H', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
|
||
|
/* 247 */ 'F', 'G', 'R', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
|
||
|
/* 263 */ 'A', 'F', 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
|
||
|
/* 280 */ 'M', 'S', 'A', '1', '2', '8', 'B', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
|
||
|
/* 309 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0,
|
||
|
/* 346 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0,
|
||
|
/* 355 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
|
||
|
/* 403 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
|
||
|
/* 437 */ 'C', 'C', 'R', 0,
|
||
|
/* 441 */ 'D', 'S', 'P', 'R', 0,
|
||
|
/* 446 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0,
|
||
|
/* 454 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0,
|
||
|
/* 484 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0,
|
||
|
/* 514 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', 0,
|
||
|
/* 532 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0,
|
||
|
/* 540 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
|
||
|
/* 590 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
|
||
|
/* 654 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
|
||
|
/* 701 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
|
||
|
/* 734 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0,
|
||
|
/* 765 */ 'H', 'W', 'R', 'e', 'g', 's', 0,
|
||
|
/* 772 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0,
|
||
|
};
|
||
|
|
||
|
extern const MCRegisterClass MipsMCRegisterClasses[] = {
|
||
|
{ OddSP, OddSPBits, 241, 56, sizeof(OddSPBits), Mips::OddSPRegClassID, 4, 4, 1, 0 },
|
||
|
{ CCR, CCRBits, 437, 32, sizeof(CCRBits), Mips::CCRRegClassID, 4, 4, 1, 0 },
|
||
|
{ COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 4, 4, 1, 0 },
|
||
|
{ COP2, COP2Bits, 100, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 4, 4, 1, 0 },
|
||
|
{ COP3, COP3Bits, 105, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 4, 4, 1, 0 },
|
||
|
{ DSPR, DSPRBits, 441, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 4, 4, 1, 1 },
|
||
|
{ FGR32, FGR32Bits, 88, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 4, 4, 1, 1 },
|
||
|
{ FGRCC, FGRCCBits, 172, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 4, 4, 1, 1 },
|
||
|
{ FGRH32, FGRH32Bits, 38, 32, sizeof(FGRH32Bits), Mips::FGRH32RegClassID, 4, 4, 1, 0 },
|
||
|
{ GPR32, GPR32Bits, 94, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 4, 4, 1, 1 },
|
||
|
{ HWRegs, HWRegsBits, 765, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 4, 4, 1, 0 },
|
||
|
{ OddSP_with_sub_hi, OddSP_with_sub_hiBits, 514, 24, sizeof(OddSP_with_sub_hiBits), Mips::OddSP_with_sub_hiRegClassID, 4, 4, 1, 0 },
|
||
|
{ FGR32_and_OddSP, FGR32_and_OddSPBits, 247, 16, sizeof(FGR32_and_OddSPBits), Mips::FGR32_and_OddSPRegClassID, 4, 4, 1, 1 },
|
||
|
{ FGRH32_and_OddSP, FGRH32_and_OddSPBits, 230, 16, sizeof(FGRH32_and_OddSPBits), Mips::FGRH32_and_OddSPRegClassID, 4, 4, 1, 0 },
|
||
|
{ OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 5, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 4, 1, 0 },
|
||
|
{ CPU16RegsPlusSP, CPU16RegsPlusSPBits, 330, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 4, 4, 1, 1 },
|
||
|
{ CPU16Regs, CPU16RegsBits, 755, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 4, 4, 1, 1 },
|
||
|
{ FCC, FCCBits, 162, 8, sizeof(FCCBits), Mips::FCCRegClassID, 4, 4, 1, 0 },
|
||
|
{ GPRMM16, GPRMM16Bits, 139, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 4, 4, 1, 1 },
|
||
|
{ GPRMM16MoveP, GPRMM16MovePBits, 390, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 4, 4, 1, 1 },
|
||
|
{ GPRMM16Zero, GPRMM16ZeroBits, 578, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
|
||
|
{ MSACtrl, MSACtrlBits, 532, 8, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 4, 4, 1, 1 },
|
||
|
{ OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 55, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 4, 1, 0 },
|
||
|
{ CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 628, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
|
||
|
{ CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 376, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 4, 4, 1, 1 },
|
||
|
{ GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 561, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
|
||
|
{ HI32DSP, HI32DSPBits, 205, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 4, 4, 1, 1 },
|
||
|
{ LO32DSP, LO32DSPBits, 213, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 4, 4, 1, 1 },
|
||
|
{ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 611, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
|
||
|
{ CPURAReg, CPURARegBits, 475, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 4, 4, 1, 0 },
|
||
|
{ CPUSPReg, CPUSPRegBits, 505, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 4, 4, 1, 0 },
|
||
|
{ DSPCC, DSPCCBits, 166, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 4, 4, 1, 1 },
|
||
|
{ HI32, HI32Bits, 45, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 4, 4, 1, 1 },
|
||
|
{ LO32, LO32Bits, 50, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 4, 4, 1, 1 },
|
||
|
{ FGR64, FGR64Bits, 127, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64, GPR64Bits, 133, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 8, 8, 1, 1 },
|
||
|
{ AFGR64, AFGR64Bits, 126, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 8, 8, 1, 1 },
|
||
|
{ FGR64_and_OddSP, FGR64_and_OddSPBits, 264, 16, sizeof(FGR64_and_OddSPBits), Mips::FGR64_and_OddSPRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 309, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 8, 1, 1 },
|
||
|
{ AFGR64_and_OddSP, AFGR64_and_OddSPBits, 263, 8, sizeof(AFGR64_and_OddSPBits), Mips::AFGR64_and_OddSPRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 734, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 403, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 701, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 654, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
|
||
|
{ ACC64DSP, ACC64DSPBits, 221, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 355, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 540, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 590, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
|
||
|
{ OCTEON_MPL, OCTEON_MPLBits, 194, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 8, 8, 1, 0 },
|
||
|
{ OCTEON_P, OCTEON_PBits, 346, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 8, 8, 1, 0 },
|
||
|
{ ACC64, ACC64Bits, 110, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 454, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 8, 8, 1, 1 },
|
||
|
{ GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, 484, 1, sizeof(GPR64_with_sub_32_in_CPUSPRegBits), Mips::GPR64_with_sub_32_in_CPUSPRegRegClassID, 8, 8, 1, 1 },
|
||
|
{ HI64, HI64Bits, 116, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 8, 8, 1, 1 },
|
||
|
{ LO64, LO64Bits, 121, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 8, 8, 1, 1 },
|
||
|
{ MSA128B, MSA128BBits, 154, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 16, 16, 1, 1 },
|
||
|
{ MSA128D, MSA128DBits, 178, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 16, 16, 1, 1 },
|
||
|
{ MSA128H, MSA128HBits, 186, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 16, 16, 1, 1 },
|
||
|
{ MSA128W, MSA128WBits, 446, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 16, 16, 1, 1 },
|
||
|
{ MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 280, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips::MSA128B_with_sub_64_in_OddSPRegClassID, 16, 16, 1, 1 },
|
||
|
{ MSA128WEvens, MSA128WEvensBits, 772, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 16, 16, 1, 1 },
|
||
|
{ ACC128, ACC128Bits, 147, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 16, 16, 1, 1 },
|
||
|
};
|
||
|
|
||
|
// Mips Dwarf<->LLVM register mappings.
|
||
|
extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
|
||
|
{ 0U, Mips::ZERO_64 },
|
||
|
{ 1U, Mips::AT_64 },
|
||
|
{ 2U, Mips::V0_64 },
|
||
|
{ 3U, Mips::V1_64 },
|
||
|
{ 4U, Mips::A0_64 },
|
||
|
{ 5U, Mips::A1_64 },
|
||
|
{ 6U, Mips::A2_64 },
|
||
|
{ 7U, Mips::A3_64 },
|
||
|
{ 8U, Mips::T0_64 },
|
||
|
{ 9U, Mips::T1_64 },
|
||
|
{ 10U, Mips::T2_64 },
|
||
|
{ 11U, Mips::T3_64 },
|
||
|
{ 12U, Mips::T4_64 },
|
||
|
{ 13U, Mips::T5_64 },
|
||
|
{ 14U, Mips::T6_64 },
|
||
|
{ 15U, Mips::T7_64 },
|
||
|
{ 16U, Mips::S0_64 },
|
||
|
{ 17U, Mips::S1_64 },
|
||
|
{ 18U, Mips::S2_64 },
|
||
|
{ 19U, Mips::S3_64 },
|
||
|
{ 20U, Mips::S4_64 },
|
||
|
{ 21U, Mips::S5_64 },
|
||
|
{ 22U, Mips::S6_64 },
|
||
|
{ 23U, Mips::S7_64 },
|
||
|
{ 24U, Mips::T8_64 },
|
||
|
{ 25U, Mips::T9_64 },
|
||
|
{ 26U, Mips::K0_64 },
|
||
|
{ 27U, Mips::K1_64 },
|
||
|
{ 28U, Mips::GP_64 },
|
||
|
{ 29U, Mips::SP_64 },
|
||
|
{ 30U, Mips::FP_64 },
|
||
|
{ 31U, Mips::RA_64 },
|
||
|
{ 32U, Mips::D0_64 },
|
||
|
{ 33U, Mips::D1_64 },
|
||
|
{ 34U, Mips::D2_64 },
|
||
|
{ 35U, Mips::D3_64 },
|
||
|
{ 36U, Mips::D4_64 },
|
||
|
{ 37U, Mips::D5_64 },
|
||
|
{ 38U, Mips::D6_64 },
|
||
|
{ 39U, Mips::D7_64 },
|
||
|
{ 40U, Mips::D8_64 },
|
||
|
{ 41U, Mips::D9_64 },
|
||
|
{ 42U, Mips::D10_64 },
|
||
|
{ 43U, Mips::D11_64 },
|
||
|
{ 44U, Mips::D12_64 },
|
||
|
{ 45U, Mips::D13_64 },
|
||
|
{ 46U, Mips::D14_64 },
|
||
|
{ 47U, Mips::D15_64 },
|
||
|
{ 48U, Mips::D16_64 },
|
||
|
{ 49U, Mips::D17_64 },
|
||
|
{ 50U, Mips::D18_64 },
|
||
|
{ 51U, Mips::D19_64 },
|
||
|
{ 52U, Mips::D20_64 },
|
||
|
{ 53U, Mips::D21_64 },
|
||
|
{ 54U, Mips::D22_64 },
|
||
|
{ 55U, Mips::D23_64 },
|
||
|
{ 56U, Mips::D24_64 },
|
||
|
{ 57U, Mips::D25_64 },
|
||
|
{ 58U, Mips::D26_64 },
|
||
|
{ 59U, Mips::D27_64 },
|
||
|
{ 60U, Mips::D28_64 },
|
||
|
{ 61U, Mips::D29_64 },
|
||
|
{ 62U, Mips::D30_64 },
|
||
|
{ 63U, Mips::D31_64 },
|
||
|
{ 64U, Mips::HI0 },
|
||
|
{ 65U, Mips::LO0 },
|
||
|
{ 176U, Mips::HI1 },
|
||
|
{ 177U, Mips::LO1 },
|
||
|
{ 178U, Mips::HI2 },
|
||
|
{ 179U, Mips::LO2 },
|
||
|
{ 180U, Mips::HI3 },
|
||
|
{ 181U, Mips::LO3 },
|
||
|
};
|
||
|
extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L);
|
||
|
|
||
|
extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
|
||
|
{ 0U, Mips::ZERO_64 },
|
||
|
{ 1U, Mips::AT_64 },
|
||
|
{ 2U, Mips::V0_64 },
|
||
|
{ 3U, Mips::V1_64 },
|
||
|
{ 4U, Mips::A0_64 },
|
||
|
{ 5U, Mips::A1_64 },
|
||
|
{ 6U, Mips::A2_64 },
|
||
|
{ 7U, Mips::A3_64 },
|
||
|
{ 8U, Mips::T0_64 },
|
||
|
{ 9U, Mips::T1_64 },
|
||
|
{ 10U, Mips::T2_64 },
|
||
|
{ 11U, Mips::T3_64 },
|
||
|
{ 12U, Mips::T4_64 },
|
||
|
{ 13U, Mips::T5_64 },
|
||
|
{ 14U, Mips::T6_64 },
|
||
|
{ 15U, Mips::T7_64 },
|
||
|
{ 16U, Mips::S0_64 },
|
||
|
{ 17U, Mips::S1_64 },
|
||
|
{ 18U, Mips::S2_64 },
|
||
|
{ 19U, Mips::S3_64 },
|
||
|
{ 20U, Mips::S4_64 },
|
||
|
{ 21U, Mips::S5_64 },
|
||
|
{ 22U, Mips::S6_64 },
|
||
|
{ 23U, Mips::S7_64 },
|
||
|
{ 24U, Mips::T8_64 },
|
||
|
{ 25U, Mips::T9_64 },
|
||
|
{ 26U, Mips::K0_64 },
|
||
|
{ 27U, Mips::K1_64 },
|
||
|
{ 28U, Mips::GP_64 },
|
||
|
{ 29U, Mips::SP_64 },
|
||
|
{ 30U, Mips::FP_64 },
|
||
|
{ 31U, Mips::RA_64 },
|
||
|
{ 32U, Mips::D0_64 },
|
||
|
{ 33U, Mips::D1_64 },
|
||
|
{ 34U, Mips::D2_64 },
|
||
|
{ 35U, Mips::D3_64 },
|
||
|
{ 36U, Mips::D4_64 },
|
||
|
{ 37U, Mips::D5_64 },
|
||
|
{ 38U, Mips::D6_64 },
|
||
|
{ 39U, Mips::D7_64 },
|
||
|
{ 40U, Mips::D8_64 },
|
||
|
{ 41U, Mips::D9_64 },
|
||
|
{ 42U, Mips::D10_64 },
|
||
|
{ 43U, Mips::D11_64 },
|
||
|
{ 44U, Mips::D12_64 },
|
||
|
{ 45U, Mips::D13_64 },
|
||
|
{ 46U, Mips::D14_64 },
|
||
|
{ 47U, Mips::D15_64 },
|
||
|
{ 48U, Mips::D16_64 },
|
||
|
{ 49U, Mips::D17_64 },
|
||
|
{ 50U, Mips::D18_64 },
|
||
|
{ 51U, Mips::D19_64 },
|
||
|
{ 52U, Mips::D20_64 },
|
||
|
{ 53U, Mips::D21_64 },
|
||
|
{ 54U, Mips::D22_64 },
|
||
|
{ 55U, Mips::D23_64 },
|
||
|
{ 56U, Mips::D24_64 },
|
||
|
{ 57U, Mips::D25_64 },
|
||
|
{ 58U, Mips::D26_64 },
|
||
|
{ 59U, Mips::D27_64 },
|
||
|
{ 60U, Mips::D28_64 },
|
||
|
{ 61U, Mips::D29_64 },
|
||
|
{ 62U, Mips::D30_64 },
|
||
|
{ 63U, Mips::D31_64 },
|
||
|
{ 64U, Mips::HI0 },
|
||
|
{ 65U, Mips::LO0 },
|
||
|
{ 176U, Mips::HI1 },
|
||
|
{ 177U, Mips::LO1 },
|
||
|
{ 178U, Mips::HI2 },
|
||
|
{ 179U, Mips::LO2 },
|
||
|
{ 180U, Mips::HI3 },
|
||
|
{ 181U, Mips::LO3 },
|
||
|
};
|
||
|
extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L);
|
||
|
|
||
|
extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
|
||
|
{ Mips::AT, 1U },
|
||
|
{ Mips::FP, 30U },
|
||
|
{ Mips::GP, 28U },
|
||
|
{ Mips::RA, 31U },
|
||
|
{ Mips::SP, 29U },
|
||
|
{ Mips::ZERO, 0U },
|
||
|
{ Mips::A0, 4U },
|
||
|
{ Mips::A1, 5U },
|
||
|
{ Mips::A2, 6U },
|
||
|
{ Mips::A3, 7U },
|
||
|
{ Mips::AT_64, 1U },
|
||
|
{ Mips::F0, 32U },
|
||
|
{ Mips::F1, 33U },
|
||
|
{ Mips::F2, 34U },
|
||
|
{ Mips::F3, 35U },
|
||
|
{ Mips::F4, 36U },
|
||
|
{ Mips::F5, 37U },
|
||
|
{ Mips::F6, 38U },
|
||
|
{ Mips::F7, 39U },
|
||
|
{ Mips::F8, 40U },
|
||
|
{ Mips::F9, 41U },
|
||
|
{ Mips::F10, 42U },
|
||
|
{ Mips::F11, 43U },
|
||
|
{ Mips::F12, 44U },
|
||
|
{ Mips::F13, 45U },
|
||
|
{ Mips::F14, 46U },
|
||
|
{ Mips::F15, 47U },
|
||
|
{ Mips::F16, 48U },
|
||
|
{ Mips::F17, 49U },
|
||
|
{ Mips::F18, 50U },
|
||
|
{ Mips::F19, 51U },
|
||
|
{ Mips::F20, 52U },
|
||
|
{ Mips::F21, 53U },
|
||
|
{ Mips::F22, 54U },
|
||
|
{ Mips::F23, 55U },
|
||
|
{ Mips::F24, 56U },
|
||
|
{ Mips::F25, 57U },
|
||
|
{ Mips::F26, 58U },
|
||
|
{ Mips::F27, 59U },
|
||
|
{ Mips::F28, 60U },
|
||
|
{ Mips::F29, 61U },
|
||
|
{ Mips::F30, 62U },
|
||
|
{ Mips::F31, 63U },
|
||
|
{ Mips::FP_64, 30U },
|
||
|
{ Mips::F_HI0, 32U },
|
||
|
{ Mips::F_HI1, 33U },
|
||
|
{ Mips::F_HI2, 34U },
|
||
|
{ Mips::F_HI3, 35U },
|
||
|
{ Mips::F_HI4, 36U },
|
||
|
{ Mips::F_HI5, 37U },
|
||
|
{ Mips::F_HI6, 38U },
|
||
|
{ Mips::F_HI7, 39U },
|
||
|
{ Mips::F_HI8, 40U },
|
||
|
{ Mips::F_HI9, 41U },
|
||
|
{ Mips::F_HI10, 42U },
|
||
|
{ Mips::F_HI11, 43U },
|
||
|
{ Mips::F_HI12, 44U },
|
||
|
{ Mips::F_HI13, 45U },
|
||
|
{ Mips::F_HI14, 46U },
|
||
|
{ Mips::F_HI15, 47U },
|
||
|
{ Mips::F_HI16, 48U },
|
||
|
{ Mips::F_HI17, 49U },
|
||
|
{ Mips::F_HI18, 50U },
|
||
|
{ Mips::F_HI19, 51U },
|
||
|
{ Mips::F_HI20, 52U },
|
||
|
{ Mips::F_HI21, 53U },
|
||
|
{ Mips::F_HI22, 54U },
|
||
|
{ Mips::F_HI23, 55U },
|
||
|
{ Mips::F_HI24, 56U },
|
||
|
{ Mips::F_HI25, 57U },
|
||
|
{ Mips::F_HI26, 58U },
|
||
|
{ Mips::F_HI27, 59U },
|
||
|
{ Mips::F_HI28, 60U },
|
||
|
{ Mips::F_HI29, 61U },
|
||
|
{ Mips::F_HI30, 62U },
|
||
|
{ Mips::F_HI31, 63U },
|
||
|
{ Mips::GP_64, 28U },
|
||
|
{ Mips::HI0, 64U },
|
||
|
{ Mips::HI1, 176U },
|
||
|
{ Mips::HI2, 178U },
|
||
|
{ Mips::HI3, 180U },
|
||
|
{ Mips::K0, 26U },
|
||
|
{ Mips::K1, 27U },
|
||
|
{ Mips::LO0, 65U },
|
||
|
{ Mips::LO1, 177U },
|
||
|
{ Mips::LO2, 179U },
|
||
|
{ Mips::LO3, 181U },
|
||
|
{ Mips::RA_64, 31U },
|
||
|
{ Mips::S0, 16U },
|
||
|
{ Mips::S1, 17U },
|
||
|
{ Mips::S2, 18U },
|
||
|
{ Mips::S3, 19U },
|
||
|
{ Mips::S4, 20U },
|
||
|
{ Mips::S5, 21U },
|
||
|
{ Mips::S6, 22U },
|
||
|
{ Mips::S7, 23U },
|
||
|
{ Mips::SP_64, 29U },
|
||
|
{ Mips::T0, 8U },
|
||
|
{ Mips::T1, 9U },
|
||
|
{ Mips::T2, 10U },
|
||
|
{ Mips::T3, 11U },
|
||
|
{ Mips::T4, 12U },
|
||
|
{ Mips::T5, 13U },
|
||
|
{ Mips::T6, 14U },
|
||
|
{ Mips::T7, 15U },
|
||
|
{ Mips::T8, 24U },
|
||
|
{ Mips::T9, 25U },
|
||
|
{ Mips::V0, 2U },
|
||
|
{ Mips::V1, 3U },
|
||
|
{ Mips::W0, 32U },
|
||
|
{ Mips::W1, 33U },
|
||
|
{ Mips::W2, 34U },
|
||
|
{ Mips::W3, 35U },
|
||
|
{ Mips::W4, 36U },
|
||
|
{ Mips::W5, 37U },
|
||
|
{ Mips::W6, 38U },
|
||
|
{ Mips::W7, 39U },
|
||
|
{ Mips::W8, 40U },
|
||
|
{ Mips::W9, 41U },
|
||
|
{ Mips::W10, 42U },
|
||
|
{ Mips::W11, 43U },
|
||
|
{ Mips::W12, 44U },
|
||
|
{ Mips::W13, 45U },
|
||
|
{ Mips::W14, 46U },
|
||
|
{ Mips::W15, 47U },
|
||
|
{ Mips::W16, 48U },
|
||
|
{ Mips::W17, 49U },
|
||
|
{ Mips::W18, 50U },
|
||
|
{ Mips::W19, 51U },
|
||
|
{ Mips::W20, 52U },
|
||
|
{ Mips::W21, 53U },
|
||
|
{ Mips::W22, 54U },
|
||
|
{ Mips::W23, 55U },
|
||
|
{ Mips::W24, 56U },
|
||
|
{ Mips::W25, 57U },
|
||
|
{ Mips::W26, 58U },
|
||
|
{ Mips::W27, 59U },
|
||
|
{ Mips::W28, 60U },
|
||
|
{ Mips::W29, 61U },
|
||
|
{ Mips::W30, 62U },
|
||
|
{ Mips::W31, 63U },
|
||
|
{ Mips::ZERO_64, 0U },
|
||
|
{ Mips::A0_64, 4U },
|
||
|
{ Mips::A1_64, 5U },
|
||
|
{ Mips::A2_64, 6U },
|
||
|
{ Mips::A3_64, 7U },
|
||
|
{ Mips::D0_64, 32U },
|
||
|
{ Mips::D1_64, 33U },
|
||
|
{ Mips::D2_64, 34U },
|
||
|
{ Mips::D3_64, 35U },
|
||
|
{ Mips::D4_64, 36U },
|
||
|
{ Mips::D5_64, 37U },
|
||
|
{ Mips::D6_64, 38U },
|
||
|
{ Mips::D7_64, 39U },
|
||
|
{ Mips::D8_64, 40U },
|
||
|
{ Mips::D9_64, 41U },
|
||
|
{ Mips::D10_64, 42U },
|
||
|
{ Mips::D11_64, 43U },
|
||
|
{ Mips::D12_64, 44U },
|
||
|
{ Mips::D13_64, 45U },
|
||
|
{ Mips::D14_64, 46U },
|
||
|
{ Mips::D15_64, 47U },
|
||
|
{ Mips::D16_64, 48U },
|
||
|
{ Mips::D17_64, 49U },
|
||
|
{ Mips::D18_64, 50U },
|
||
|
{ Mips::D19_64, 51U },
|
||
|
{ Mips::D20_64, 52U },
|
||
|
{ Mips::D21_64, 53U },
|
||
|
{ Mips::D22_64, 54U },
|
||
|
{ Mips::D23_64, 55U },
|
||
|
{ Mips::D24_64, 56U },
|
||
|
{ Mips::D25_64, 57U },
|
||
|
{ Mips::D26_64, 58U },
|
||
|
{ Mips::D27_64, 59U },
|
||
|
{ Mips::D28_64, 60U },
|
||
|
{ Mips::D29_64, 61U },
|
||
|
{ Mips::D30_64, 62U },
|
||
|
{ Mips::D31_64, 63U },
|
||
|
{ Mips::K0_64, 26U },
|
||
|
{ Mips::K1_64, 27U },
|
||
|
{ Mips::S0_64, 16U },
|
||
|
{ Mips::S1_64, 17U },
|
||
|
{ Mips::S2_64, 18U },
|
||
|
{ Mips::S3_64, 19U },
|
||
|
{ Mips::S4_64, 20U },
|
||
|
{ Mips::S5_64, 21U },
|
||
|
{ Mips::S6_64, 22U },
|
||
|
{ Mips::S7_64, 23U },
|
||
|
{ Mips::T0_64, 8U },
|
||
|
{ Mips::T1_64, 9U },
|
||
|
{ Mips::T2_64, 10U },
|
||
|
{ Mips::T3_64, 11U },
|
||
|
{ Mips::T4_64, 12U },
|
||
|
{ Mips::T5_64, 13U },
|
||
|
{ Mips::T6_64, 14U },
|
||
|
{ Mips::T7_64, 15U },
|
||
|
{ Mips::T8_64, 24U },
|
||
|
{ Mips::T9_64, 25U },
|
||
|
{ Mips::V0_64, 2U },
|
||
|
{ Mips::V1_64, 3U },
|
||
|
};
|
||
|
extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf);
|
||
|
|
||
|
extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
|
||
|
{ Mips::AT, 1U },
|
||
|
{ Mips::FP, 30U },
|
||
|
{ Mips::GP, 28U },
|
||
|
{ Mips::RA, 31U },
|
||
|
{ Mips::SP, 29U },
|
||
|
{ Mips::ZERO, 0U },
|
||
|
{ Mips::A0, 4U },
|
||
|
{ Mips::A1, 5U },
|
||
|
{ Mips::A2, 6U },
|
||
|
{ Mips::A3, 7U },
|
||
|
{ Mips::AT_64, 1U },
|
||
|
{ Mips::F0, 32U },
|
||
|
{ Mips::F1, 33U },
|
||
|
{ Mips::F2, 34U },
|
||
|
{ Mips::F3, 35U },
|
||
|
{ Mips::F4, 36U },
|
||
|
{ Mips::F5, 37U },
|
||
|
{ Mips::F6, 38U },
|
||
|
{ Mips::F7, 39U },
|
||
|
{ Mips::F8, 40U },
|
||
|
{ Mips::F9, 41U },
|
||
|
{ Mips::F10, 42U },
|
||
|
{ Mips::F11, 43U },
|
||
|
{ Mips::F12, 44U },
|
||
|
{ Mips::F13, 45U },
|
||
|
{ Mips::F14, 46U },
|
||
|
{ Mips::F15, 47U },
|
||
|
{ Mips::F16, 48U },
|
||
|
{ Mips::F17, 49U },
|
||
|
{ Mips::F18, 50U },
|
||
|
{ Mips::F19, 51U },
|
||
|
{ Mips::F20, 52U },
|
||
|
{ Mips::F21, 53U },
|
||
|
{ Mips::F22, 54U },
|
||
|
{ Mips::F23, 55U },
|
||
|
{ Mips::F24, 56U },
|
||
|
{ Mips::F25, 57U },
|
||
|
{ Mips::F26, 58U },
|
||
|
{ Mips::F27, 59U },
|
||
|
{ Mips::F28, 60U },
|
||
|
{ Mips::F29, 61U },
|
||
|
{ Mips::F30, 62U },
|
||
|
{ Mips::F31, 63U },
|
||
|
{ Mips::FP_64, 30U },
|
||
|
{ Mips::F_HI0, 32U },
|
||
|
{ Mips::F_HI1, 33U },
|
||
|
{ Mips::F_HI2, 34U },
|
||
|
{ Mips::F_HI3, 35U },
|
||
|
{ Mips::F_HI4, 36U },
|
||
|
{ Mips::F_HI5, 37U },
|
||
|
{ Mips::F_HI6, 38U },
|
||
|
{ Mips::F_HI7, 39U },
|
||
|
{ Mips::F_HI8, 40U },
|
||
|
{ Mips::F_HI9, 41U },
|
||
|
{ Mips::F_HI10, 42U },
|
||
|
{ Mips::F_HI11, 43U },
|
||
|
{ Mips::F_HI12, 44U },
|
||
|
{ Mips::F_HI13, 45U },
|
||
|
{ Mips::F_HI14, 46U },
|
||
|
{ Mips::F_HI15, 47U },
|
||
|
{ Mips::F_HI16, 48U },
|
||
|
{ Mips::F_HI17, 49U },
|
||
|
{ Mips::F_HI18, 50U },
|
||
|
{ Mips::F_HI19, 51U },
|
||
|
{ Mips::F_HI20, 52U },
|
||
|
{ Mips::F_HI21, 53U },
|
||
|
{ Mips::F_HI22, 54U },
|
||
|
{ Mips::F_HI23, 55U },
|
||
|
{ Mips::F_HI24, 56U },
|
||
|
{ Mips::F_HI25, 57U },
|
||
|
{ Mips::F_HI26, 58U },
|
||
|
{ Mips::F_HI27, 59U },
|
||
|
{ Mips::F_HI28, 60U },
|
||
|
{ Mips::F_HI29, 61U },
|
||
|
{ Mips::F_HI30, 62U },
|
||
|
{ Mips::F_HI31, 63U },
|
||
|
{ Mips::GP_64, 28U },
|
||
|
{ Mips::HI0, 64U },
|
||
|
{ Mips::HI1, 176U },
|
||
|
{ Mips::HI2, 178U },
|
||
|
{ Mips::HI3, 180U },
|
||
|
{ Mips::K0, 26U },
|
||
|
{ Mips::K1, 27U },
|
||
|
{ Mips::LO0, 65U },
|
||
|
{ Mips::LO1, 177U },
|
||
|
{ Mips::LO2, 179U },
|
||
|
{ Mips::LO3, 181U },
|
||
|
{ Mips::RA_64, 31U },
|
||
|
{ Mips::S0, 16U },
|
||
|
{ Mips::S1, 17U },
|
||
|
{ Mips::S2, 18U },
|
||
|
{ Mips::S3, 19U },
|
||
|
{ Mips::S4, 20U },
|
||
|
{ Mips::S5, 21U },
|
||
|
{ Mips::S6, 22U },
|
||
|
{ Mips::S7, 23U },
|
||
|
{ Mips::SP_64, 29U },
|
||
|
{ Mips::T0, 8U },
|
||
|
{ Mips::T1, 9U },
|
||
|
{ Mips::T2, 10U },
|
||
|
{ Mips::T3, 11U },
|
||
|
{ Mips::T4, 12U },
|
||
|
{ Mips::T5, 13U },
|
||
|
{ Mips::T6, 14U },
|
||
|
{ Mips::T7, 15U },
|
||
|
{ Mips::T8, 24U },
|
||
|
{ Mips::T9, 25U },
|
||
|
{ Mips::V0, 2U },
|
||
|
{ Mips::V1, 3U },
|
||
|
{ Mips::W0, 32U },
|
||
|
{ Mips::W1, 33U },
|
||
|
{ Mips::W2, 34U },
|
||
|
{ Mips::W3, 35U },
|
||
|
{ Mips::W4, 36U },
|
||
|
{ Mips::W5, 37U },
|
||
|
{ Mips::W6, 38U },
|
||
|
{ Mips::W7, 39U },
|
||
|
{ Mips::W8, 40U },
|
||
|
{ Mips::W9, 41U },
|
||
|
{ Mips::W10, 42U },
|
||
|
{ Mips::W11, 43U },
|
||
|
{ Mips::W12, 44U },
|
||
|
{ Mips::W13, 45U },
|
||
|
{ Mips::W14, 46U },
|
||
|
{ Mips::W15, 47U },
|
||
|
{ Mips::W16, 48U },
|
||
|
{ Mips::W17, 49U },
|
||
|
{ Mips::W18, 50U },
|
||
|
{ Mips::W19, 51U },
|
||
|
{ Mips::W20, 52U },
|
||
|
{ Mips::W21, 53U },
|
||
|
{ Mips::W22, 54U },
|
||
|
{ Mips::W23, 55U },
|
||
|
{ Mips::W24, 56U },
|
||
|
{ Mips::W25, 57U },
|
||
|
{ Mips::W26, 58U },
|
||
|
{ Mips::W27, 59U },
|
||
|
{ Mips::W28, 60U },
|
||
|
{ Mips::W29, 61U },
|
||
|
{ Mips::W30, 62U },
|
||
|
{ Mips::W31, 63U },
|
||
|
{ Mips::ZERO_64, 0U },
|
||
|
{ Mips::A0_64, 4U },
|
||
|
{ Mips::A1_64, 5U },
|
||
|
{ Mips::A2_64, 6U },
|
||
|
{ Mips::A3_64, 7U },
|
||
|
{ Mips::D0_64, 32U },
|
||
|
{ Mips::D1_64, 33U },
|
||
|
{ Mips::D2_64, 34U },
|
||
|
{ Mips::D3_64, 35U },
|
||
|
{ Mips::D4_64, 36U },
|
||
|
{ Mips::D5_64, 37U },
|
||
|
{ Mips::D6_64, 38U },
|
||
|
{ Mips::D7_64, 39U },
|
||
|
{ Mips::D8_64, 40U },
|
||
|
{ Mips::D9_64, 41U },
|
||
|
{ Mips::D10_64, 42U },
|
||
|
{ Mips::D11_64, 43U },
|
||
|
{ Mips::D12_64, 44U },
|
||
|
{ Mips::D13_64, 45U },
|
||
|
{ Mips::D14_64, 46U },
|
||
|
{ Mips::D15_64, 47U },
|
||
|
{ Mips::D16_64, 48U },
|
||
|
{ Mips::D17_64, 49U },
|
||
|
{ Mips::D18_64, 50U },
|
||
|
{ Mips::D19_64, 51U },
|
||
|
{ Mips::D20_64, 52U },
|
||
|
{ Mips::D21_64, 53U },
|
||
|
{ Mips::D22_64, 54U },
|
||
|
{ Mips::D23_64, 55U },
|
||
|
{ Mips::D24_64, 56U },
|
||
|
{ Mips::D25_64, 57U },
|
||
|
{ Mips::D26_64, 58U },
|
||
|
{ Mips::D27_64, 59U },
|
||
|
{ Mips::D28_64, 60U },
|
||
|
{ Mips::D29_64, 61U },
|
||
|
{ Mips::D30_64, 62U },
|
||
|
{ Mips::D31_64, 63U },
|
||
|
{ Mips::K0_64, 26U },
|
||
|
{ Mips::K1_64, 27U },
|
||
|
{ Mips::S0_64, 16U },
|
||
|
{ Mips::S1_64, 17U },
|
||
|
{ Mips::S2_64, 18U },
|
||
|
{ Mips::S3_64, 19U },
|
||
|
{ Mips::S4_64, 20U },
|
||
|
{ Mips::S5_64, 21U },
|
||
|
{ Mips::S6_64, 22U },
|
||
|
{ Mips::S7_64, 23U },
|
||
|
{ Mips::T0_64, 8U },
|
||
|
{ Mips::T1_64, 9U },
|
||
|
{ Mips::T2_64, 10U },
|
||
|
{ Mips::T3_64, 11U },
|
||
|
{ Mips::T4_64, 12U },
|
||
|
{ Mips::T5_64, 13U },
|
||
|
{ Mips::T6_64, 14U },
|
||
|
{ Mips::T7_64, 15U },
|
||
|
{ Mips::T8_64, 24U },
|
||
|
{ Mips::T9_64, 25U },
|
||
|
{ Mips::V0_64, 2U },
|
||
|
{ Mips::V1_64, 3U },
|
||
|
};
|
||
|
extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf);
|
||
|
|
||
|
extern const uint16_t MipsRegEncodingTable[] = {
|
||
|
0,
|
||
|
1,
|
||
|
0,
|
||
|
0,
|
||
|
0,
|
||
|
0,
|
||
|
0,
|
||
|
0,
|
||
|
30,
|
||
|
28,
|
||
|
2,
|
||
|
1,
|
||
|
0,
|
||
|
6,
|
||
|
4,
|
||
|
5,
|
||
|
3,
|
||
|
7,
|
||
|
0,
|
||
|
31,
|
||
|
29,
|
||
|
0,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
1,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
0,
|
||
|
2,
|
||
|
4,
|
||
|
6,
|
||
|
8,
|
||
|
10,
|
||
|
12,
|
||
|
14,
|
||
|
16,
|
||
|
18,
|
||
|
20,
|
||
|
22,
|
||
|
24,
|
||
|
26,
|
||
|
28,
|
||
|
30,
|
||
|
0,
|
||
|
0,
|
||
|
0,
|
||
|
0,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
30,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
28,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
26,
|
||
|
27,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
31,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
29,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
24,
|
||
|
25,
|
||
|
2,
|
||
|
3,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
0,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
0,
|
||
|
0,
|
||
|
1,
|
||
|
2,
|
||
|
3,
|
||
|
4,
|
||
|
5,
|
||
|
6,
|
||
|
7,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
24,
|
||
|
25,
|
||
|
26,
|
||
|
27,
|
||
|
28,
|
||
|
29,
|
||
|
30,
|
||
|
31,
|
||
|
0,
|
||
|
0,
|
||
|
26,
|
||
|
27,
|
||
|
0,
|
||
|
16,
|
||
|
17,
|
||
|
18,
|
||
|
19,
|
||
|
20,
|
||
|
21,
|
||
|
22,
|
||
|
23,
|
||
|
8,
|
||
|
9,
|
||
|
10,
|
||
|
11,
|
||
|
12,
|
||
|
13,
|
||
|
14,
|
||
|
15,
|
||
|
24,
|
||
|
25,
|
||
|
2,
|
||
|
3,
|
||
|
};
|
||
|
static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
|
||
|
RI->InitMCRegisterInfo(MipsRegDesc, 418, RA, PC, MipsMCRegisterClasses, 62, MipsRegUnitRoots, 297, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
|
||
|
MipsSubRegIdxRanges, MipsRegEncodingTable);
|
||
|
|
||
|
switch (DwarfFlavour) {
|
||
|
default:
|
||
|
llvm_unreachable("Unknown DWARF flavour");
|
||
|
case 0:
|
||
|
RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
|
||
|
break;
|
||
|
}
|
||
|
switch (EHFlavour) {
|
||
|
default:
|
||
|
llvm_unreachable("Unknown DWARF flavour");
|
||
|
case 0:
|
||
|
RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
|
||
|
break;
|
||
|
}
|
||
|
switch (DwarfFlavour) {
|
||
|
default:
|
||
|
llvm_unreachable("Unknown DWARF flavour");
|
||
|
case 0:
|
||
|
RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
|
||
|
break;
|
||
|
}
|
||
|
switch (EHFlavour) {
|
||
|
default:
|
||
|
llvm_unreachable("Unknown DWARF flavour");
|
||
|
case 0:
|
||
|
RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
} // End llvm namespace
|
||
|
#endif // GET_REGINFO_MC_DESC
|