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367 lines
13 KiB
367 lines
13 KiB
3 years ago
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//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides X86 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MCTargetDesc.h"
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#include "X86MCAsmInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/TargetRegistry.h"
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#if _MSC_VER
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#include <intrin.h>
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#endif
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using namespace llvm_ks;
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#define GET_REGINFO_MC_DESC
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#include "X86GenRegisterInfo.inc"
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#define GET_INSTRINFO_MC_DESC
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#include "X86GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "X86GenSubtargetInfo.inc"
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std::string X86_MC::ParseX86Triple(const Triple &TT) {
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std::string FS;
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if (TT.getArch() == Triple::x86_64)
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FS = "+64bit-mode,-32bit-mode,-16bit-mode";
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else if (TT.getEnvironment() != Triple::CODE16)
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FS = "-64bit-mode,+32bit-mode,-16bit-mode";
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else
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FS = "-64bit-mode,-32bit-mode,+16bit-mode";
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return FS;
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}
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unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
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if (TT.getArch() == Triple::x86_64)
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return DWARFFlavour::X86_64;
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if (TT.isOSDarwin())
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return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
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if (TT.isOSCygMing())
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// Unsupported by now, just quick fallback
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return DWARFFlavour::X86_32_Generic;
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return DWARFFlavour::X86_32_Generic;
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}
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void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
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// FIXME: TableGen these.
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for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
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unsigned SEH = MRI->getEncodingValue(Reg);
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MRI->mapLLVMRegToSEHReg(Reg, SEH);
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}
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}
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MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
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StringRef CPU, StringRef FS) {
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std::string ArchFS = X86_MC::ParseX86Triple(TT);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = (Twine(ArchFS) + "," + FS).str();
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else
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ArchFS = FS;
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}
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "generic";
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return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
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}
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static MCInstrInfo *createX86MCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitX86MCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
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unsigned RA = (TT.getArch() == Triple::x86_64)
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? X86::RIP // Should have dwarf #16.
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: X86::EIP; // Should have dwarf #8.
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MCRegisterInfo *X = new MCRegisterInfo();
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InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
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X86_MC::getDwarfRegFlavour(TT, true), RA);
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X86_MC::InitLLVM2SEHRegisterMapping(X);
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return X;
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}
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static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TheTriple) {
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bool is64Bit = TheTriple.getArch() == Triple::x86_64;
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MCAsmInfo *MAI;
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if (TheTriple.isOSBinFormatMachO()) {
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if (is64Bit)
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MAI = new X86_64MCAsmInfoDarwin(TheTriple);
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else
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MAI = new X86MCAsmInfoDarwin(TheTriple);
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} else if (TheTriple.isOSBinFormatELF()) {
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// Force the use of an ELF container.
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MAI = new X86ELFMCAsmInfo(TheTriple);
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} else if (TheTriple.isWindowsMSVCEnvironment() ||
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TheTriple.isWindowsCoreCLREnvironment()) {
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MAI = new X86MCAsmInfoMicrosoft(TheTriple);
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} else if (TheTriple.isOSCygMing() ||
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TheTriple.isWindowsItaniumEnvironment()) {
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MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
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} else {
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// The default is ELF.
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MAI = new X86ELFMCAsmInfo(TheTriple);
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}
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// Initialize initial frame state.
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// Calculate amount of bytes used for return address storing
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int stackGrowth = is64Bit ? -8 : -4;
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// Initial state of the frame pointer is esp+stackGrowth.
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unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
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nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
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MAI->addInitialFrameState(Inst);
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// Add return address to move list
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unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
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MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
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nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
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MAI->addInitialFrameState(Inst2);
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return MAI;
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}
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static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
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MCContext &Ctx) {
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// Default to the stock relocation info.
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return NULL;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeX86TargetMC() {
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for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(*T,
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X86_MC::createX86MCSubtargetInfo);
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// Register the code emitter.
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TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
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// Register the MC relocation info.
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TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
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}
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
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createX86_32AsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
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createX86_64AsmBackend);
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}
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unsigned llvm_ks::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
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bool High) {
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switch (Size) {
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default: return 0;
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case 8:
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if (High) {
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switch (Reg) {
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default: return getX86SubSuperRegisterOrZero(Reg, 64);
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case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
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return X86::SI;
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case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
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return X86::DI;
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case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
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return X86::BP;
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case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
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return X86::SP;
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case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
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return X86::AH;
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case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
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return X86::DH;
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case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
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return X86::CH;
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case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
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return X86::BH;
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}
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} else {
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switch (Reg) {
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default: return 0;
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case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
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return X86::AL;
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case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
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return X86::DL;
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case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
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return X86::CL;
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case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
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return X86::BL;
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case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
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return X86::SIL;
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case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
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return X86::DIL;
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case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
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return X86::BPL;
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case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
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return X86::SPL;
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case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
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return X86::R8B;
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case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
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return X86::R9B;
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case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
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return X86::R10B;
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case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
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return X86::R11B;
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case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
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return X86::R12B;
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case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
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return X86::R13B;
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case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
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return X86::R14B;
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case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
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return X86::R15B;
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}
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}
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case 16:
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switch (Reg) {
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default: return 0;
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case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
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return X86::AX;
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case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
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return X86::DX;
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case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
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return X86::CX;
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case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
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return X86::BX;
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case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
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return X86::SI;
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case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
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return X86::DI;
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case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
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return X86::BP;
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case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
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return X86::SP;
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case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
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return X86::R8W;
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case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
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return X86::R9W;
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case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
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return X86::R10W;
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case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
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return X86::R11W;
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case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
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return X86::R12W;
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case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
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return X86::R13W;
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case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
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return X86::R14W;
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case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
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return X86::R15W;
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}
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case 32:
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switch (Reg) {
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default: return 0;
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case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
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return X86::EAX;
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case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
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return X86::EDX;
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case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
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return X86::ECX;
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case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
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return X86::EBX;
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case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
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return X86::ESI;
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case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
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return X86::EDI;
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case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
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return X86::EBP;
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case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
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return X86::ESP;
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case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
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return X86::R8D;
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case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
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return X86::R9D;
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case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
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return X86::R10D;
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case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
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return X86::R11D;
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case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
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return X86::R12D;
|
||
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
||
|
|
return X86::R13D;
|
||
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
||
|
|
return X86::R14D;
|
||
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
||
|
|
return X86::R15D;
|
||
|
|
}
|
||
|
|
case 64:
|
||
|
|
switch (Reg) {
|
||
|
|
default: return 0;
|
||
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
||
|
|
return X86::RAX;
|
||
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
||
|
|
return X86::RDX;
|
||
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
||
|
|
return X86::RCX;
|
||
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
||
|
|
return X86::RBX;
|
||
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
||
|
|
return X86::RSI;
|
||
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
||
|
|
return X86::RDI;
|
||
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
||
|
|
return X86::RBP;
|
||
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
||
|
|
return X86::RSP;
|
||
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
||
|
|
return X86::R8;
|
||
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
||
|
|
return X86::R9;
|
||
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
||
|
|
return X86::R10;
|
||
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
||
|
|
return X86::R11;
|
||
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
||
|
|
return X86::R12;
|
||
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
||
|
|
return X86::R13;
|
||
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
||
|
|
return X86::R14;
|
||
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
||
|
|
return X86::R15;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned llvm_ks::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
|
||
|
|
unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
|
||
|
|
assert(Res != 0 && "Unexpected register or VT");
|
||
|
|
return Res;
|
||
|
|
}
|
||
|
|
|
||
|
|
|