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142 lines
4.6 KiB
142 lines
4.6 KiB
4 years ago
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//===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Hexagon specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonMCTargetDesc.h"
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#include "Hexagon.h"
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#include "HexagonMCAsmInfo.h"
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#include "HexagonMCELFStreamer.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectStreamer.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm_ks;
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#define GET_INSTRINFO_MC_DESC
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#include "HexagonGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "HexagonGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "HexagonGenRegisterInfo.inc"
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bool llvm_ks::HexagonDisableCompound;
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bool llvm_ks::HexagonDisableDuplex;
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StringRef HEXAGON_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) {
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if (CPU.empty())
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CPU = "hexagonv60";
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return CPU;
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}
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MCInstrInfo *llvm_ks::createHexagonMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitHexagonMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitHexagonMCRegisterInfo(X, Hexagon::R0);
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return X;
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}
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static MCSubtargetInfo *
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createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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CPU = HEXAGON_MC::selectHexagonCPU(TT, CPU);
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return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
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}
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namespace {
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class HexagonTargetELFStreamer : public HexagonTargetStreamer {
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public:
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MCELFStreamer &getStreamer() {
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return static_cast<MCELFStreamer &>(Streamer);
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}
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HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
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: HexagonTargetStreamer(S) {
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auto Bits = STI.getFeatureBits();
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unsigned Flags;
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if (Bits.to_ullong() & llvm_ks::Hexagon::ArchV5)
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Flags = ELF::EF_HEXAGON_MACH_V5;
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else
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Flags = ELF::EF_HEXAGON_MACH_V4;
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getStreamer().getAssembler().setELFHeaderEFlags(Flags);
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}
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void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment,
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unsigned AccessSize) override {
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HexagonMCELFStreamer &HexagonELFStreamer =
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static_cast<HexagonMCELFStreamer &>(getStreamer());
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HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
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AccessSize);
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}
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void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment,
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unsigned AccessSize) override {
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HexagonMCELFStreamer &HexagonELFStreamer =
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static_cast<HexagonMCELFStreamer &>(getStreamer());
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HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
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Symbol, Size, ByteAlignment, AccessSize);
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}
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};
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}
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static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT) {
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MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
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// VirtualFP = (R30 + #0).
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MCCFIInstruction Inst =
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MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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// Force static initialization.
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extern "C" void LLVMInitializeHexagonTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
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createHexagonMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
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createHexagonMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
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createHexagonMCSubtargetInfo);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
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createHexagonMCCodeEmitter);
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// Register the asm backend
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TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget,
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createHexagonAsmBackend);
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}
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