/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
namespace llvm_ks {

class MCRegisterClass;
extern const MCRegisterClass ARMMCRegisterClasses[];

namespace ARM {
enum {
  NoRegister,
  APSR = 1,
  APSR_NZCV = 2,
  CPSR = 3,
  FPEXC = 4,
  FPINST = 5,
  FPSCR = 6,
  FPSCR_NZCV = 7,
  FPSID = 8,
  ITSTATE = 9,
  LR = 10,
  PC = 11,
  SP = 12,
  SPSR = 13,
  D0 = 14,
  D1 = 15,
  D2 = 16,
  D3 = 17,
  D4 = 18,
  D5 = 19,
  D6 = 20,
  D7 = 21,
  D8 = 22,
  D9 = 23,
  D10 = 24,
  D11 = 25,
  D12 = 26,
  D13 = 27,
  D14 = 28,
  D15 = 29,
  D16 = 30,
  D17 = 31,
  D18 = 32,
  D19 = 33,
  D20 = 34,
  D21 = 35,
  D22 = 36,
  D23 = 37,
  D24 = 38,
  D25 = 39,
  D26 = 40,
  D27 = 41,
  D28 = 42,
  D29 = 43,
  D30 = 44,
  D31 = 45,
  FPINST2 = 46,
  MVFR0 = 47,
  MVFR1 = 48,
  MVFR2 = 49,
  Q0 = 50,
  Q1 = 51,
  Q2 = 52,
  Q3 = 53,
  Q4 = 54,
  Q5 = 55,
  Q6 = 56,
  Q7 = 57,
  Q8 = 58,
  Q9 = 59,
  Q10 = 60,
  Q11 = 61,
  Q12 = 62,
  Q13 = 63,
  Q14 = 64,
  Q15 = 65,
  R0 = 66,
  R1 = 67,
  R2 = 68,
  R3 = 69,
  R4 = 70,
  R5 = 71,
  R6 = 72,
  R7 = 73,
  R8 = 74,
  R9 = 75,
  R10 = 76,
  R11 = 77,
  R12 = 78,
  S0 = 79,
  S1 = 80,
  S2 = 81,
  S3 = 82,
  S4 = 83,
  S5 = 84,
  S6 = 85,
  S7 = 86,
  S8 = 87,
  S9 = 88,
  S10 = 89,
  S11 = 90,
  S12 = 91,
  S13 = 92,
  S14 = 93,
  S15 = 94,
  S16 = 95,
  S17 = 96,
  S18 = 97,
  S19 = 98,
  S20 = 99,
  S21 = 100,
  S22 = 101,
  S23 = 102,
  S24 = 103,
  S25 = 104,
  S26 = 105,
  S27 = 106,
  S28 = 107,
  S29 = 108,
  S30 = 109,
  S31 = 110,
  D0_D2 = 111,
  D1_D3 = 112,
  D2_D4 = 113,
  D3_D5 = 114,
  D4_D6 = 115,
  D5_D7 = 116,
  D6_D8 = 117,
  D7_D9 = 118,
  D8_D10 = 119,
  D9_D11 = 120,
  D10_D12 = 121,
  D11_D13 = 122,
  D12_D14 = 123,
  D13_D15 = 124,
  D14_D16 = 125,
  D15_D17 = 126,
  D16_D18 = 127,
  D17_D19 = 128,
  D18_D20 = 129,
  D19_D21 = 130,
  D20_D22 = 131,
  D21_D23 = 132,
  D22_D24 = 133,
  D23_D25 = 134,
  D24_D26 = 135,
  D25_D27 = 136,
  D26_D28 = 137,
  D27_D29 = 138,
  D28_D30 = 139,
  D29_D31 = 140,
  Q0_Q1 = 141,
  Q1_Q2 = 142,
  Q2_Q3 = 143,
  Q3_Q4 = 144,
  Q4_Q5 = 145,
  Q5_Q6 = 146,
  Q6_Q7 = 147,
  Q7_Q8 = 148,
  Q8_Q9 = 149,
  Q9_Q10 = 150,
  Q10_Q11 = 151,
  Q11_Q12 = 152,
  Q12_Q13 = 153,
  Q13_Q14 = 154,
  Q14_Q15 = 155,
  Q0_Q1_Q2_Q3 = 156,
  Q1_Q2_Q3_Q4 = 157,
  Q2_Q3_Q4_Q5 = 158,
  Q3_Q4_Q5_Q6 = 159,
  Q4_Q5_Q6_Q7 = 160,
  Q5_Q6_Q7_Q8 = 161,
  Q6_Q7_Q8_Q9 = 162,
  Q7_Q8_Q9_Q10 = 163,
  Q8_Q9_Q10_Q11 = 164,
  Q9_Q10_Q11_Q12 = 165,
  Q10_Q11_Q12_Q13 = 166,
  Q11_Q12_Q13_Q14 = 167,
  Q12_Q13_Q14_Q15 = 168,
  R12_SP = 169,
  R0_R1 = 170,
  R2_R3 = 171,
  R4_R5 = 172,
  R6_R7 = 173,
  R8_R9 = 174,
  R10_R11 = 175,
  D0_D1_D2 = 176,
  D1_D2_D3 = 177,
  D2_D3_D4 = 178,
  D3_D4_D5 = 179,
  D4_D5_D6 = 180,
  D5_D6_D7 = 181,
  D6_D7_D8 = 182,
  D7_D8_D9 = 183,
  D8_D9_D10 = 184,
  D9_D10_D11 = 185,
  D10_D11_D12 = 186,
  D11_D12_D13 = 187,
  D12_D13_D14 = 188,
  D13_D14_D15 = 189,
  D14_D15_D16 = 190,
  D15_D16_D17 = 191,
  D16_D17_D18 = 192,
  D17_D18_D19 = 193,
  D18_D19_D20 = 194,
  D19_D20_D21 = 195,
  D20_D21_D22 = 196,
  D21_D22_D23 = 197,
  D22_D23_D24 = 198,
  D23_D24_D25 = 199,
  D24_D25_D26 = 200,
  D25_D26_D27 = 201,
  D26_D27_D28 = 202,
  D27_D28_D29 = 203,
  D28_D29_D30 = 204,
  D29_D30_D31 = 205,
  D0_D2_D4 = 206,
  D1_D3_D5 = 207,
  D2_D4_D6 = 208,
  D3_D5_D7 = 209,
  D4_D6_D8 = 210,
  D5_D7_D9 = 211,
  D6_D8_D10 = 212,
  D7_D9_D11 = 213,
  D8_D10_D12 = 214,
  D9_D11_D13 = 215,
  D10_D12_D14 = 216,
  D11_D13_D15 = 217,
  D12_D14_D16 = 218,
  D13_D15_D17 = 219,
  D14_D16_D18 = 220,
  D15_D17_D19 = 221,
  D16_D18_D20 = 222,
  D17_D19_D21 = 223,
  D18_D20_D22 = 224,
  D19_D21_D23 = 225,
  D20_D22_D24 = 226,
  D21_D23_D25 = 227,
  D22_D24_D26 = 228,
  D23_D25_D27 = 229,
  D24_D26_D28 = 230,
  D25_D27_D29 = 231,
  D26_D28_D30 = 232,
  D27_D29_D31 = 233,
  D0_D2_D4_D6 = 234,
  D1_D3_D5_D7 = 235,
  D2_D4_D6_D8 = 236,
  D3_D5_D7_D9 = 237,
  D4_D6_D8_D10 = 238,
  D5_D7_D9_D11 = 239,
  D6_D8_D10_D12 = 240,
  D7_D9_D11_D13 = 241,
  D8_D10_D12_D14 = 242,
  D9_D11_D13_D15 = 243,
  D10_D12_D14_D16 = 244,
  D11_D13_D15_D17 = 245,
  D12_D14_D16_D18 = 246,
  D13_D15_D17_D19 = 247,
  D14_D16_D18_D20 = 248,
  D15_D17_D19_D21 = 249,
  D16_D18_D20_D22 = 250,
  D17_D19_D21_D23 = 251,
  D18_D20_D22_D24 = 252,
  D19_D21_D23_D25 = 253,
  D20_D22_D24_D26 = 254,
  D21_D23_D25_D27 = 255,
  D22_D24_D26_D28 = 256,
  D23_D25_D27_D29 = 257,
  D24_D26_D28_D30 = 258,
  D25_D27_D29_D31 = 259,
  D1_D2 = 260,
  D3_D4 = 261,
  D5_D6 = 262,
  D7_D8 = 263,
  D9_D10 = 264,
  D11_D12 = 265,
  D13_D14 = 266,
  D15_D16 = 267,
  D17_D18 = 268,
  D19_D20 = 269,
  D21_D22 = 270,
  D23_D24 = 271,
  D25_D26 = 272,
  D27_D28 = 273,
  D29_D30 = 274,
  D1_D2_D3_D4 = 275,
  D3_D4_D5_D6 = 276,
  D5_D6_D7_D8 = 277,
  D7_D8_D9_D10 = 278,
  D9_D10_D11_D12 = 279,
  D11_D12_D13_D14 = 280,
  D13_D14_D15_D16 = 281,
  D15_D16_D17_D18 = 282,
  D17_D18_D19_D20 = 283,
  D19_D20_D21_D22 = 284,
  D21_D22_D23_D24 = 285,
  D23_D24_D25_D26 = 286,
  D25_D26_D27_D28 = 287,
  D27_D28_D29_D30 = 288,
  NUM_TARGET_REGS 	// 289
};
}

// Register classes
namespace ARM {
enum {
  SPRRegClassID = 0,
  GPRRegClassID = 1,
  GPRwithAPSRRegClassID = 2,
  SPR_8RegClassID = 3,
  GPRnopcRegClassID = 4,
  rGPRRegClassID = 5,
  hGPRRegClassID = 6,
  tGPRRegClassID = 7,
  GPRnopc_and_hGPRRegClassID = 8,
  hGPR_and_rGPRRegClassID = 9,
  tcGPRRegClassID = 10,
  tGPR_and_tcGPRRegClassID = 11,
  CCRRegClassID = 12,
  GPRspRegClassID = 13,
  hGPR_and_tcGPRRegClassID = 14,
  DPRRegClassID = 15,
  DPR_VFP2RegClassID = 16,
  DPR_8RegClassID = 17,
  GPRPairRegClassID = 18,
  GPRPair_with_gsub_1_in_rGPRRegClassID = 19,
  GPRPair_with_gsub_0_in_tGPRRegClassID = 20,
  GPRPair_with_gsub_0_in_hGPRRegClassID = 21,
  GPRPair_with_gsub_0_in_tcGPRRegClassID = 22,
  GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 23,
  GPRPair_with_gsub_1_in_tcGPRRegClassID = 24,
  GPRPair_with_gsub_1_in_GPRspRegClassID = 25,
  DPairSpcRegClassID = 26,
  DPairSpc_with_ssub_0RegClassID = 27,
  DPairSpc_with_dsub_2_then_ssub_0RegClassID = 28,
  DPairSpc_with_dsub_0_in_DPR_8RegClassID = 29,
  DPairSpc_with_dsub_2_in_DPR_8RegClassID = 30,
  DPairRegClassID = 31,
  DPair_with_ssub_0RegClassID = 32,
  QPRRegClassID = 33,
  DPair_with_ssub_2RegClassID = 34,
  DPair_with_dsub_0_in_DPR_8RegClassID = 35,
  QPR_VFP2RegClassID = 36,
  DPair_with_dsub_1_in_DPR_8RegClassID = 37,
  QPR_8RegClassID = 38,
  DTripleRegClassID = 39,
  DTripleSpcRegClassID = 40,
  DTripleSpc_with_ssub_0RegClassID = 41,
  DTriple_with_ssub_0RegClassID = 42,
  DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 43,
  DTriple_with_qsub_0_in_QPRRegClassID = 44,
  DTriple_with_ssub_2RegClassID = 45,
  DTripleSpc_with_dsub_2_then_ssub_0RegClassID = 46,
  DTriple_with_dsub_2_then_ssub_0RegClassID = 47,
  DTripleSpc_with_dsub_4_then_ssub_0RegClassID = 48,
  DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 49,
  DTriple_with_dsub_0_in_DPR_8RegClassID = 50,
  DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 51,
  DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 52,
  DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 53,
  DTriple_with_dsub_1_in_DPR_8RegClassID = 54,
  DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID = 55,
  DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 56,
  DTriple_with_dsub_2_in_DPR_8RegClassID = 57,
  DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 58,
  DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID = 59,
  DTriple_with_qsub_0_in_QPR_8RegClassID = 60,
  DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID = 61,
  DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 62,
  DQuadSpcRegClassID = 63,
  DQuadSpc_with_ssub_0RegClassID = 64,
  DQuadSpc_with_dsub_2_then_ssub_0RegClassID = 65,
  DQuadSpc_with_dsub_4_then_ssub_0RegClassID = 66,
  DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 67,
  DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 68,
  DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 69,
  DQuadRegClassID = 70,
  DQuad_with_ssub_0RegClassID = 71,
  DQuad_with_ssub_2RegClassID = 72,
  QQPRRegClassID = 73,
  DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 74,
  DQuad_with_dsub_2_then_ssub_0RegClassID = 75,
  DQuad_with_dsub_3_then_ssub_0RegClassID = 76,
  DQuad_with_dsub_0_in_DPR_8RegClassID = 77,
  DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 78,
  DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 79,
  DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID = 80,
  DQuad_with_dsub_1_in_DPR_8RegClassID = 81,
  DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 82,
  DQuad_with_dsub_2_in_DPR_8RegClassID = 83,
  DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 84,
  DQuad_with_dsub_3_in_DPR_8RegClassID = 85,
  DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 86,
  DQuad_with_qsub_0_in_QPR_8RegClassID = 87,
  DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID = 88,
  DQuad_with_qsub_1_in_QPR_8RegClassID = 89,
  DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID = 90,
  QQQQPRRegClassID = 91,
  QQQQPR_with_ssub_0RegClassID = 92,
  QQQQPR_with_dsub_2_then_ssub_0RegClassID = 93,
  QQQQPR_with_dsub_5_then_ssub_0RegClassID = 94,
  QQQQPR_with_dsub_7_then_ssub_0RegClassID = 95,
  QQQQPR_with_dsub_0_in_DPR_8RegClassID = 96,
  QQQQPR_with_dsub_2_in_DPR_8RegClassID = 97,
  QQQQPR_with_dsub_4_in_DPR_8RegClassID = 98,
  QQQQPR_with_dsub_6_in_DPR_8RegClassID = 99,

  };
}

// Subregister indices
namespace ARM {
enum {
  NoSubRegister,
  dsub_0,	// 1
  dsub_1,	// 2
  dsub_2,	// 3
  dsub_3,	// 4
  dsub_4,	// 5
  dsub_5,	// 6
  dsub_6,	// 7
  dsub_7,	// 8
  gsub_0,	// 9
  gsub_1,	// 10
  qqsub_0,	// 11
  qqsub_1,	// 12
  qsub_0,	// 13
  qsub_1,	// 14
  qsub_2,	// 15
  qsub_3,	// 16
  ssub_0,	// 17
  ssub_1,	// 18
  ssub_2,	// 19
  ssub_3,	// 20
  dsub_2_then_ssub_0,	// 21
  dsub_2_then_ssub_1,	// 22
  dsub_3_then_ssub_0,	// 23
  dsub_3_then_ssub_1,	// 24
  dsub_7_then_ssub_0,	// 25
  dsub_7_then_ssub_1,	// 26
  dsub_6_then_ssub_0,	// 27
  dsub_6_then_ssub_1,	// 28
  dsub_5_then_ssub_0,	// 29
  dsub_5_then_ssub_1,	// 30
  dsub_4_then_ssub_0,	// 31
  dsub_4_then_ssub_1,	// 32
  dsub_0_dsub_2,	// 33
  dsub_0_dsub_1_dsub_2,	// 34
  dsub_1_dsub_3,	// 35
  dsub_1_dsub_2_dsub_3,	// 36
  dsub_1_dsub_2,	// 37
  dsub_0_dsub_2_dsub_4,	// 38
  dsub_0_dsub_2_dsub_4_dsub_6,	// 39
  dsub_1_dsub_3_dsub_5,	// 40
  dsub_1_dsub_3_dsub_5_dsub_7,	// 41
  dsub_1_dsub_2_dsub_3_dsub_4,	// 42
  dsub_2_dsub_4,	// 43
  dsub_2_dsub_3_dsub_4,	// 44
  dsub_2_dsub_4_dsub_6,	// 45
  dsub_3_dsub_5,	// 46
  dsub_3_dsub_4_dsub_5,	// 47
  dsub_3_dsub_5_dsub_7,	// 48
  dsub_3_dsub_4,	// 49
  dsub_3_dsub_4_dsub_5_dsub_6,	// 50
  dsub_4_dsub_6,	// 51
  dsub_4_dsub_5_dsub_6,	// 52
  dsub_5_dsub_7,	// 53
  dsub_5_dsub_6_dsub_7,	// 54
  dsub_5_dsub_6,	// 55
  qsub_1_qsub_2,	// 56
  NUM_TARGET_SUBREGS
};
}
} // End llvm namespace
#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
namespace llvm_ks {

extern const MCPhysReg ARMRegDiffLists[] = {
  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
  /* 105 */ 40, 1, 1, 1, 1, 0,
  /* 111 */ 42, 1, 1, 1, 1, 0,
  /* 117 */ 42, 1, 1, 1, 0,
  /* 122 */ 64510, 1, 1, 1, 0,
  /* 127 */ 65015, 1, 1, 1, 0,
  /* 132 */ 65282, 1, 1, 1, 0,
  /* 137 */ 65348, 1, 1, 1, 0,
  /* 142 */ 13, 1, 1, 0,
  /* 146 */ 42, 1, 1, 0,
  /* 150 */ 65388, 1, 1, 0,
  /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
  /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
  /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
  /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
  /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
  /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
  /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
  /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
  /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
  /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
  /* 254 */ 65489, 133, 65416, 1, 1, 0,
  /* 260 */ 65490, 133, 65416, 1, 1, 0,
  /* 266 */ 65491, 133, 65416, 1, 1, 0,
  /* 272 */ 65492, 133, 65416, 1, 1, 0,
  /* 278 */ 65493, 133, 65416, 1, 1, 0,
  /* 284 */ 65494, 133, 65416, 1, 1, 0,
  /* 290 */ 65495, 133, 65416, 1, 1, 0,
  /* 296 */ 65496, 133, 65416, 1, 1, 0,
  /* 302 */ 65497, 133, 65416, 1, 1, 0,
  /* 308 */ 65498, 133, 65416, 1, 1, 0,
  /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
  /* 339 */ 65326, 1, 3, 1, 0,
  /* 344 */ 13, 1, 0,
  /* 347 */ 14, 1, 0,
  /* 350 */ 65, 1, 0,
  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
  /* 556 */ 65045, 1, 0,
  /* 559 */ 65260, 1, 0,
  /* 562 */ 65299, 1, 0,
  /* 565 */ 65300, 1, 0,
  /* 568 */ 65301, 1, 0,
  /* 571 */ 65302, 1, 0,
  /* 574 */ 65303, 1, 0,
  /* 577 */ 65304, 1, 0,
  /* 580 */ 65305, 1, 0,
  /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
  /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
  /* 600 */ 65488, 13, 121, 65416, 1, 0,
  /* 606 */ 65489, 13, 121, 65416, 1, 0,
  /* 612 */ 65490, 13, 121, 65416, 1, 0,
  /* 618 */ 65491, 13, 121, 65416, 1, 0,
  /* 624 */ 65492, 13, 121, 65416, 1, 0,
  /* 630 */ 65493, 13, 121, 65416, 1, 0,
  /* 636 */ 65494, 13, 121, 65416, 1, 0,
  /* 642 */ 65495, 13, 121, 65416, 1, 0,
  /* 648 */ 65496, 13, 121, 65416, 1, 0,
  /* 654 */ 65497, 13, 121, 65416, 1, 0,
  /* 660 */ 65498, 13, 121, 65416, 1, 0,
  /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
  /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
  /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
  /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
  /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
  /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
  /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
  /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
  /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
  /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
  /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
  /* 765 */ 65488, 133, 65416, 1, 0,
  /* 770 */ 65499, 134, 65416, 1, 0,
  /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
  /* 783 */ 65432, 1, 0,
  /* 786 */ 65433, 1, 0,
  /* 789 */ 65434, 1, 0,
  /* 792 */ 65435, 1, 0,
  /* 795 */ 65436, 1, 0,
  /* 798 */ 65437, 1, 0,
  /* 801 */ 65464, 1, 0,
  /* 804 */ 65508, 1, 0,
  /* 807 */ 65509, 1, 0,
  /* 810 */ 65510, 1, 0,
  /* 813 */ 65511, 1, 0,
  /* 816 */ 65512, 1, 0,
  /* 819 */ 65513, 1, 0,
  /* 822 */ 65514, 1, 0,
  /* 825 */ 65515, 1, 0,
  /* 828 */ 65520, 1, 0,
  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
  /* 839 */ 65136, 1, 3, 1, 2, 0,
  /* 845 */ 65326, 1, 2, 0,
  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
  /* 856 */ 65136, 1, 2, 2, 0,
  /* 861 */ 65080, 1, 2, 2, 2, 0,
  /* 867 */ 65330, 2, 2, 2, 0,
  /* 872 */ 65080, 1, 3, 2, 2, 0,
  /* 878 */ 65358, 2, 2, 0,
  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
  /* 889 */ 65136, 1, 3, 2, 0,
  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
  /* 1038 */ 65344, 2, 2, 93, 2, 0,
  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
  /* 1080 */ 65439, 2, 0,
  /* 1083 */ 65453, 2, 0,
  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
  /* 1094 */ 65136, 1, 3, 1, 3, 0,
  /* 1100 */ 65326, 1, 3, 0,
  /* 1104 */ 5, 0,
  /* 1106 */ 140, 65486, 13, 0,
  /* 1110 */ 14, 0,
  /* 1112 */ 126, 65501, 15, 0,
  /* 1116 */ 10, 66, 0,
  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
  /* 1359 */ 91, 0,
  /* 1361 */ 98, 0,
  /* 1363 */ 99, 0,
  /* 1365 */ 100, 0,
  /* 1367 */ 101, 0,
  /* 1369 */ 102, 0,
  /* 1371 */ 103, 0,
  /* 1373 */ 104, 0,
  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
  /* 1526 */ 157, 0,
  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
  /* 2455 */ 65487, 13, 121, 65416, 0,
  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
  /* 2474 */ 65487, 133, 65416, 0,
  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
  /* 2832 */ 26, 65446, 92, 65445, 0,
  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
  /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
  /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
  /* 3839 */ 65298, 80, 1, 65456, 0,
  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
  /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
  /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
  /* 3948 */ 65439, 80, 1, 65457, 0,
  /* 3953 */ 28, 65457, 0,
  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
  /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
  /* 4002 */ 26, 65458, 80, 65457, 0,
  /* 4007 */ 65439, 79, 1, 65458, 0,
  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
  /* 4114 */ 65445, 65470, 0,
  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
  /* 4182 */ 65534, 0,
  /* 4184 */ 65535, 0,
};

extern const unsigned ARMLaneMaskLists[] = {
  /* 0 */ 0x00000000, ~0u,
  /* 2 */ 0x00000002, 0x00000001, ~0u,
  /* 5 */ 0x00000001, 0x00000002, ~0u,
  /* 8 */ 0x00000004, 0x00000008, ~0u,
  /* 11 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, ~0u,
  /* 16 */ 0x00000004, 0x00000008, 0x00000030, ~0u,
  /* 20 */ 0x0000000C, 0x00000030, ~0u,
  /* 23 */ 0x00000004, 0x00000008, 0x00000040, 0x00000080, ~0u,
  /* 28 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000080, ~0u,
  /* 35 */ 0x00000004, 0x00000008, 0x000000C0, ~0u,
  /* 39 */ 0x0000000C, 0x000000C0, ~0u,
  /* 42 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x000000C0, ~0u,
  /* 48 */ 0x00000004, 0x00000008, 0x00000030, 0x000000C0, ~0u,
  /* 53 */ 0x0000000C, 0x00000030, 0x000000C0, ~0u,
  /* 57 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000080, 0x00000100, 0x00000200, ~0u,
  /* 66 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000080, 0x00000300, ~0u,
  /* 74 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x000000C0, 0x00000300, ~0u,
  /* 81 */ 0x00000004, 0x00000008, 0x00000030, 0x000000C0, 0x00000300, ~0u,
  /* 87 */ 0x0000000C, 0x00000030, 0x000000C0, 0x00000300, ~0u,
  /* 92 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000080, 0x00000100, 0x00000200, 0x00010000, 0x00020000, 0x00004000, 0x00008000, 0x00001000, 0x00002000, 0x00000400, 0x00000800, ~0u,
  /* 109 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000080, 0x00000100, 0x00000200, 0x00010000, 0x00020000, 0x00004000, 0x00008000, 0x00003000, 0x00000C00, ~0u,
  /* 124 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x00000040, 0x00000080, 0x00000100, 0x00000200, 0x00030000, 0x0000C000, 0x00003000, 0x00000C00, ~0u,
  /* 137 */ 0x00000004, 0x00000008, 0x00000010, 0x00000020, 0x000000C0, 0x00000300, 0x00030000, 0x0000C000, 0x00003000, 0x00000C00, ~0u,
  /* 148 */ 0x0000000C, 0x00000030, 0x000000C0, 0x00000300, 0x00030000, 0x0000C000, 0x00003000, 0x00000C00, ~0u,
  /* 157 */ 0x00000004, 0x00000008, 0x00000040, 0x00000080, 0x00010000, 0x00020000, 0x00001000, 0x00002000, ~0u,
  /* 166 */ 0x00000004, 0x00000008, 0x00000040, 0x00000080, 0x00010000, 0x00020000, 0x00003000, ~0u,
  /* 174 */ 0x00000004, 0x00000008, 0x00000040, 0x00000080, 0x00030000, 0x00003000, ~0u,
  /* 181 */ 0x00000004, 0x00000008, 0x000000C0, 0x00030000, 0x00003000, ~0u,
  /* 187 */ 0x0000000C, 0x000000C0, 0x00030000, 0x00003000, ~0u,
  /* 192 */ 0x00000004, 0x00000008, 0x00000040, 0x00000080, 0x00010000, 0x00020000, ~0u,
  /* 199 */ 0x00000004, 0x00000008, 0x00000040, 0x00000080, 0x00030000, ~0u,
  /* 205 */ 0x00000004, 0x00000008, 0x000000C0, 0x00030000, ~0u,
  /* 210 */ 0x0000000C, 0x000000C0, 0x00030000, ~0u,
};

extern const uint16_t ARMSubRegIdxLists[] = {
  /* 0 */ 1, 2, 0,
  /* 3 */ 1, 17, 18, 2, 0,
  /* 8 */ 1, 3, 0,
  /* 11 */ 1, 17, 18, 3, 0,
  /* 16 */ 9, 10, 0,
  /* 19 */ 17, 18, 0,
  /* 22 */ 1, 17, 18, 2, 19, 20, 0,
  /* 29 */ 1, 17, 18, 3, 21, 22, 0,
  /* 36 */ 1, 2, 3, 13, 33, 37, 0,
  /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
  /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
  /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
  /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
  /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
  /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
  /* 188 */ 1, 3, 5, 33, 43, 0,
  /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
  /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
  /* 212 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 33, 43, 0,
  /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
  /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
  /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
  /* 260 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 33, 38, 43, 45, 51, 0,
  /* 276 */ 1, 17, 18, 3, 21, 22, 5, 31, 32, 7, 27, 28, 33, 38, 43, 45, 51, 0,
  /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 31, 32, 6, 29, 30, 16, 7, 27, 28, 8, 25, 26, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 64 },	// dsub_0
  { 64, 64 },	// dsub_1
  { 128, 64 },	// dsub_2
  { 192, 64 },	// dsub_3
  { 256, 64 },	// dsub_4
  { 320, 64 },	// dsub_5
  { 384, 64 },	// dsub_6
  { 448, 64 },	// dsub_7
  { 0, 32 },	// gsub_0
  { 32, 32 },	// gsub_1
  { 0, 256 },	// qqsub_0
  { 256, 256 },	// qqsub_1
  { 0, 128 },	// qsub_0
  { 128, 128 },	// qsub_1
  { 256, 128 },	// qsub_2
  { 384, 128 },	// qsub_3
  { 0, 32 },	// ssub_0
  { 32, 32 },	// ssub_1
  { 64, 32 },	// ssub_2
  { 96, 32 },	// ssub_3
  { 128, 32 },	// dsub_2_then_ssub_0
  { 160, 32 },	// dsub_2_then_ssub_1
  { 192, 32 },	// dsub_3_then_ssub_0
  { 224, 32 },	// dsub_3_then_ssub_1
  { 448, 32 },	// dsub_7_then_ssub_0
  { 480, 32 },	// dsub_7_then_ssub_1
  { 384, 32 },	// dsub_6_then_ssub_0
  { 416, 32 },	// dsub_6_then_ssub_1
  { 320, 32 },	// dsub_5_then_ssub_0
  { 352, 32 },	// dsub_5_then_ssub_1
  { 256, 32 },	// dsub_4_then_ssub_0
  { 288, 32 },	// dsub_4_then_ssub_1
  { 65535, 128 },	// dsub_0_dsub_2
  { 0, 192 },	// dsub_0_dsub_1_dsub_2
  { 65535, 128 },	// dsub_1_dsub_3
  { 64, 192 },	// dsub_1_dsub_2_dsub_3
  { 64, 128 },	// dsub_1_dsub_2
  { 65535, 192 },	// dsub_0_dsub_2_dsub_4
  { 65535, 256 },	// dsub_0_dsub_2_dsub_4_dsub_6
  { 65535, 192 },	// dsub_1_dsub_3_dsub_5
  { 65535, 256 },	// dsub_1_dsub_3_dsub_5_dsub_7
  { 64, 256 },	// dsub_1_dsub_2_dsub_3_dsub_4
  { 65535, 128 },	// dsub_2_dsub_4
  { 128, 192 },	// dsub_2_dsub_3_dsub_4
  { 65535, 192 },	// dsub_2_dsub_4_dsub_6
  { 65535, 128 },	// dsub_3_dsub_5
  { 192, 192 },	// dsub_3_dsub_4_dsub_5
  { 65535, 192 },	// dsub_3_dsub_5_dsub_7
  { 192, 128 },	// dsub_3_dsub_4
  { 192, 256 },	// dsub_3_dsub_4_dsub_5_dsub_6
  { 65535, 128 },	// dsub_4_dsub_6
  { 256, 192 },	// dsub_4_dsub_5_dsub_6
  { 65535, 128 },	// dsub_5_dsub_7
  { 320, 192 },	// dsub_5_dsub_6_dsub_7
  { 320, 128 },	// dsub_5_dsub_6
  { 128, 256 },	// qsub_1_qsub_2
};

extern const char ARMRegStrings[] = {
  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
  /* 39 */ 'R', '1', '0', 0,
  /* 43 */ 'S', '1', '0', 0,
  /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
  /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
  /* 79 */ 'S', '2', '0', 0,
  /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
  /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
  /* 115 */ 'S', '3', '0', 0,
  /* 119 */ 'D', '0', 0,
  /* 122 */ 'Q', '0', 0,
  /* 125 */ 'M', 'V', 'F', 'R', '0', 0,
  /* 131 */ 'S', '0', 0,
  /* 134 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
  /* 145 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
  /* 158 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
  /* 172 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
  /* 180 */ 'S', '1', '1', 0,
  /* 184 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
  /* 196 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
  /* 212 */ 'S', '2', '1', 0,
  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
  /* 228 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
  /* 244 */ 'S', '3', '1', 0,
  /* 248 */ 'D', '1', 0,
  /* 251 */ 'Q', '0', '_', 'Q', '1', 0,
  /* 257 */ 'M', 'V', 'F', 'R', '1', 0,
  /* 263 */ 'R', '0', '_', 'R', '1', 0,
  /* 269 */ 'S', '1', 0,
  /* 272 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
  /* 286 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
  /* 301 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
  /* 316 */ 'R', '1', '2', 0,
  /* 320 */ 'S', '1', '2', 0,
  /* 324 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
  /* 340 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
  /* 356 */ 'S', '2', '2', 0,
  /* 360 */ 'D', '0', '_', 'D', '2', 0,
  /* 366 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
  /* 375 */ 'Q', '1', '_', 'Q', '2', 0,
  /* 381 */ 'M', 'V', 'F', 'R', '2', 0,
  /* 387 */ 'S', '2', 0,
  /* 390 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0,
  /* 398 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
  /* 412 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
  /* 424 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
  /* 440 */ 'S', '1', '3', 0,
  /* 444 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
  /* 460 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
  /* 472 */ 'S', '2', '3', 0,
  /* 476 */ 'D', '1', '_', 'D', '3', 0,
  /* 482 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
  /* 491 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
  /* 503 */ 'R', '2', '_', 'R', '3', 0,
  /* 509 */ 'S', '3', 0,
  /* 512 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
  /* 527 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
  /* 543 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
  /* 559 */ 'S', '1', '4', 0,
  /* 563 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
  /* 579 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
  /* 595 */ 'S', '2', '4', 0,
  /* 599 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
  /* 608 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
  /* 620 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
  /* 632 */ 'R', '4', 0,
  /* 635 */ 'S', '4', 0,
  /* 638 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
  /* 653 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
  /* 665 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
  /* 681 */ 'S', '1', '5', 0,
  /* 685 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
  /* 701 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
  /* 713 */ 'S', '2', '5', 0,
  /* 717 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
  /* 726 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
  /* 735 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
  /* 747 */ 'R', '4', '_', 'R', '5', 0,
  /* 753 */ 'S', '5', 0,
  /* 756 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
  /* 772 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
  /* 788 */ 'S', '1', '6', 0,
  /* 792 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
  /* 808 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
  /* 824 */ 'S', '2', '6', 0,
  /* 828 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
  /* 840 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
  /* 852 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
  /* 864 */ 'R', '6', 0,
  /* 867 */ 'S', '6', 0,
  /* 870 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
  /* 886 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
  /* 898 */ 'S', '1', '7', 0,
  /* 902 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
  /* 918 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
  /* 930 */ 'S', '2', '7', 0,
  /* 934 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
  /* 946 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
  /* 955 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
  /* 967 */ 'R', '6', '_', 'R', '7', 0,
  /* 973 */ 'S', '7', 0,
  /* 976 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
  /* 992 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
  /* 1008 */ 'S', '1', '8', 0,
  /* 1012 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
  /* 1028 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
  /* 1044 */ 'S', '2', '8', 0,
  /* 1048 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
  /* 1060 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
  /* 1072 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
  /* 1084 */ 'R', '8', 0,
  /* 1087 */ 'S', '8', 0,
  /* 1090 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
  /* 1106 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
  /* 1118 */ 'S', '1', '9', 0,
  /* 1122 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
  /* 1138 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
  /* 1150 */ 'S', '2', '9', 0,
  /* 1154 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
  /* 1166 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
  /* 1175 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
  /* 1187 */ 'R', '8', '_', 'R', '9', 0,
  /* 1193 */ 'S', '9', 0,
  /* 1196 */ 'P', 'C', 0,
  /* 1199 */ 'F', 'P', 'E', 'X', 'C', 0,
  /* 1205 */ 'F', 'P', 'S', 'I', 'D', 0,
  /* 1211 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0,
  /* 1219 */ 'R', '1', '2', '_', 'S', 'P', 0,
  /* 1226 */ 'F', 'P', 'S', 'C', 'R', 0,
  /* 1232 */ 'L', 'R', 0,
  /* 1235 */ 'A', 'P', 'S', 'R', 0,
  /* 1240 */ 'C', 'P', 'S', 'R', 0,
  /* 1245 */ 'S', 'P', 'S', 'R', 0,
  /* 1250 */ 'F', 'P', 'I', 'N', 'S', 'T', 0,
  /* 1257 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0,
  /* 1268 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0,
};

extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
  { 12, 0, 0, 0, 0, 0 },
  { 1235, 16, 16, 2, 66945, 0 },
  { 1268, 16, 16, 2, 66945, 0 },
  { 1240, 16, 16, 2, 66945, 0 },
  { 1199, 16, 16, 2, 66945, 0 },
  { 1250, 16, 16, 2, 66945, 0 },
  { 1226, 16, 16, 2, 17664, 0 },
  { 1257, 16, 16, 2, 17664, 0 },
  { 1205, 16, 16, 2, 66913, 0 },
  { 1211, 16, 16, 2, 66913, 0 },
  { 1232, 16, 16, 2, 66913, 0 },
  { 1196, 16, 16, 2, 66913, 0 },
  { 1223, 16, 1526, 2, 66913, 0 },
  { 1245, 16, 16, 2, 66913, 0 },
  { 119, 350, 4013, 19, 13250, 8 },
  { 248, 357, 2479, 19, 13250, 8 },
  { 363, 364, 3957, 19, 13250, 8 },
  { 479, 378, 3845, 19, 13250, 8 },
  { 605, 392, 3893, 19, 13250, 8 },
  { 723, 406, 3724, 19, 13250, 8 },
  { 837, 420, 3780, 19, 13250, 8 },
  { 943, 434, 3604, 19, 13250, 8 },
  { 1057, 448, 3664, 19, 13250, 8 },
  { 1163, 462, 3484, 19, 13250, 8 },
  { 9, 476, 3544, 19, 13250, 8 },
  { 141, 490, 3364, 19, 13250, 8 },
  { 282, 504, 3424, 19, 13250, 8 },
  { 408, 518, 3244, 19, 13250, 8 },
  { 523, 532, 3304, 19, 13250, 8 },
  { 649, 546, 3149, 19, 13250, 8 },
  { 768, 16, 3208, 2, 17761, 0 },
  { 882, 16, 3078, 2, 17761, 0 },
  { 988, 16, 3113, 2, 17761, 0 },
  { 1102, 16, 3008, 2, 17761, 0 },
  { 59, 16, 3043, 2, 17761, 0 },
  { 192, 16, 2938, 2, 17761, 0 },
  { 336, 16, 2973, 2, 17761, 0 },
  { 456, 16, 2868, 2, 17761, 0 },
  { 575, 16, 2903, 2, 17761, 0 },
  { 697, 16, 2797, 2, 17761, 0 },
  { 804, 16, 2837, 2, 17761, 0 },
  { 914, 16, 2363, 2, 17761, 0 },
  { 1024, 16, 2411, 2, 17761, 0 },
  { 1134, 16, 2384, 2, 17761, 0 },
  { 95, 16, 2429, 2, 17761, 0 },
  { 224, 16, 2789, 2, 17761, 0 },
  { 390, 16, 16, 2, 17761, 0 },
  { 125, 16, 16, 2, 17761, 0 },
  { 257, 16, 16, 2, 17761, 0 },
  { 381, 16, 16, 2, 17761, 0 },
  { 122, 353, 1112, 22, 2196, 11 },
  { 254, 374, 775, 22, 2196, 11 },
  { 378, 402, 314, 22, 2196, 11 },
  { 500, 430, 244, 22, 2196, 11 },
  { 629, 458, 234, 22, 2196, 11 },
  { 744, 486, 224, 22, 2196, 11 },
  { 861, 514, 214, 22, 2196, 11 },
  { 964, 542, 204, 22, 2196, 11 },
  { 1081, 804, 194, 0, 12818, 20 },
  { 1184, 807, 184, 0, 12818, 20 },
  { 35, 810, 174, 0, 12818, 20 },
  { 168, 813, 164, 0, 12818, 20 },
  { 312, 816, 154, 0, 12818, 20 },
  { 436, 819, 591, 0, 12818, 20 },
  { 555, 822, 2447, 0, 12818, 20 },
  { 677, 825, 1106, 0, 12818, 20 },
  { 128, 16, 1373, 2, 66913, 0 },
  { 260, 16, 1371, 2, 66913, 0 },
  { 384, 16, 1371, 2, 66913, 0 },
  { 506, 16, 1369, 2, 66913, 0 },
  { 632, 16, 1369, 2, 66913, 0 },
  { 750, 16, 1367, 2, 66913, 0 },
  { 864, 16, 1367, 2, 66913, 0 },
  { 970, 16, 1365, 2, 66913, 0 },
  { 1084, 16, 1365, 2, 66913, 0 },
  { 1190, 16, 1363, 2, 66913, 0 },
  { 39, 16, 1363, 2, 66913, 0 },
  { 176, 16, 1361, 2, 66913, 0 },
  { 316, 16, 1359, 2, 66913, 0 },
  { 131, 16, 4021, 2, 65585, 0 },
  { 269, 16, 4012, 2, 65585, 0 },
  { 387, 16, 2490, 2, 65585, 0 },
  { 509, 16, 2478, 2, 65585, 0 },
  { 635, 16, 3974, 2, 65585, 0 },
  { 753, 16, 3956, 2, 65585, 0 },
  { 867, 16, 3863, 2, 65585, 0 },
  { 973, 16, 3844, 2, 65585, 0 },
  { 1087, 16, 3914, 2, 65585, 0 },
  { 1193, 16, 3892, 2, 65585, 0 },
  { 43, 16, 3745, 2, 65585, 0 },
  { 180, 16, 3723, 2, 65585, 0 },
  { 320, 16, 3803, 2, 65585, 0 },
  { 440, 16, 3779, 2, 65585, 0 },
  { 559, 16, 3627, 2, 65585, 0 },
  { 681, 16, 3603, 2, 65585, 0 },
  { 788, 16, 3687, 2, 65585, 0 },
  { 898, 16, 3663, 2, 65585, 0 },
  { 1008, 16, 3507, 2, 65585, 0 },
  { 1118, 16, 3483, 2, 65585, 0 },
  { 79, 16, 3567, 2, 65585, 0 },
  { 212, 16, 3543, 2, 65585, 0 },
  { 356, 16, 3387, 2, 65585, 0 },
  { 472, 16, 3363, 2, 65585, 0 },
  { 595, 16, 3447, 2, 65585, 0 },
  { 713, 16, 3423, 2, 65585, 0 },
  { 824, 16, 3267, 2, 65585, 0 },
  { 930, 16, 3243, 2, 65585, 0 },
  { 1044, 16, 3327, 2, 65585, 0 },
  { 1150, 16, 3303, 2, 65585, 0 },
  { 115, 16, 3172, 2, 65585, 0 },
  { 244, 16, 3148, 2, 65585, 0 },
  { 360, 367, 4015, 29, 5426, 23 },
  { 476, 381, 2502, 29, 5426, 23 },
  { 602, 395, 3992, 29, 5426, 23 },
  { 720, 409, 3882, 29, 5426, 23 },
  { 834, 423, 3936, 29, 5426, 23 },
  { 940, 437, 3767, 29, 5426, 23 },
  { 1054, 451, 3827, 29, 5426, 23 },
  { 1160, 465, 3651, 29, 5426, 23 },
  { 6, 479, 3711, 29, 5426, 23 },
  { 151, 493, 3531, 29, 5426, 23 },
  { 278, 507, 3591, 29, 5426, 23 },
  { 404, 521, 3411, 29, 5426, 23 },
  { 519, 535, 3471, 29, 5426, 23 },
  { 645, 549, 3291, 29, 5426, 23 },
  { 764, 4007, 3351, 11, 17602, 35 },
  { 878, 3948, 3196, 11, 13522, 35 },
  { 984, 1080, 3231, 8, 17329, 39 },
  { 1098, 1080, 3101, 8, 17329, 39 },
  { 55, 1080, 3136, 8, 17329, 39 },
  { 204, 1080, 3031, 8, 17329, 39 },
  { 332, 1080, 3066, 8, 17329, 39 },
  { 452, 1080, 2961, 8, 17329, 39 },
  { 571, 1080, 2996, 8, 17329, 39 },
  { 693, 1080, 2891, 8, 17329, 39 },
  { 800, 1080, 2926, 8, 17329, 39 },
  { 910, 1080, 2820, 8, 17329, 39 },
  { 1020, 1080, 2858, 8, 17329, 39 },
  { 1130, 1080, 2401, 8, 17329, 39 },
  { 91, 1080, 2440, 8, 17329, 39 },
  { 236, 1080, 2791, 8, 17329, 39 },
  { 251, 1339, 1114, 168, 1044, 57 },
  { 375, 1319, 347, 168, 1044, 57 },
  { 497, 1299, 142, 168, 1044, 57 },
  { 626, 1279, 142, 168, 1044, 57 },
  { 741, 1259, 142, 168, 1044, 57 },
  { 858, 1239, 142, 168, 1044, 57 },
  { 961, 1219, 142, 168, 1044, 57 },
  { 1078, 1203, 142, 88, 1456, 74 },
  { 1181, 1191, 142, 76, 2114, 87 },
  { 32, 1179, 142, 76, 2114, 87 },
  { 164, 1167, 142, 76, 2114, 87 },
  { 308, 1155, 142, 76, 2114, 87 },
  { 432, 1143, 142, 76, 2114, 87 },
  { 551, 1131, 344, 76, 2114, 87 },
  { 673, 1119, 1108, 76, 2114, 87 },
  { 491, 2156, 16, 474, 4, 92 },
  { 620, 2101, 16, 474, 4, 92 },
  { 735, 2046, 16, 474, 4, 92 },
  { 852, 1991, 16, 474, 4, 92 },
  { 955, 1936, 16, 474, 4, 92 },
  { 1072, 1885, 16, 423, 272, 109 },
  { 1175, 1838, 16, 376, 512, 124 },
  { 26, 1795, 16, 333, 720, 137 },
  { 158, 1756, 16, 294, 1186, 148 },
  { 301, 1717, 16, 294, 1186, 148 },
  { 424, 1678, 16, 294, 1186, 148 },
  { 543, 1639, 16, 294, 1186, 148 },
  { 665, 1600, 16, 294, 1186, 148 },
  { 1219, 4114, 16, 16, 17856, 2 },
  { 263, 783, 16, 16, 8946, 5 },
  { 503, 786, 16, 16, 8946, 5 },
  { 747, 789, 16, 16, 8946, 5 },
  { 967, 792, 16, 16, 8946, 5 },
  { 1187, 795, 16, 16, 8946, 5 },
  { 172, 798, 16, 16, 8946, 5 },
  { 366, 1513, 1113, 63, 1570, 28 },
  { 482, 4169, 2511, 63, 1570, 28 },
  { 611, 1500, 778, 63, 1570, 28 },
  { 726, 4156, 770, 63, 1570, 28 },
  { 843, 1487, 317, 63, 1570, 28 },
  { 946, 4143, 660, 63, 1570, 28 },
  { 1063, 1474, 308, 63, 1570, 28 },
  { 1166, 4130, 654, 63, 1570, 28 },
  { 16, 1461, 302, 63, 1570, 28 },
  { 134, 4117, 648, 63, 1570, 28 },
  { 289, 1448, 296, 63, 1570, 28 },
  { 412, 4101, 642, 63, 1570, 28 },
  { 531, 1435, 290, 63, 1570, 28 },
  { 653, 4088, 636, 63, 1570, 28 },
  { 776, 1424, 284, 52, 1680, 42 },
  { 886, 4079, 630, 43, 1872, 48 },
  { 996, 1417, 278, 36, 2401, 53 },
  { 1106, 4072, 624, 36, 2401, 53 },
  { 67, 1410, 272, 36, 2401, 53 },
  { 184, 4065, 618, 36, 2401, 53 },
  { 344, 1403, 266, 36, 2401, 53 },
  { 460, 4058, 612, 36, 2401, 53 },
  { 583, 1396, 260, 36, 2401, 53 },
  { 701, 4051, 606, 36, 2401, 53 },
  { 812, 1389, 254, 36, 2401, 53 },
  { 918, 4044, 600, 36, 2401, 53 },
  { 1032, 1382, 765, 36, 2401, 53 },
  { 1138, 4037, 2455, 36, 2401, 53 },
  { 103, 1375, 2474, 36, 2401, 53 },
  { 216, 4030, 1107, 36, 2401, 53 },
  { 599, 1026, 4018, 212, 5314, 192 },
  { 717, 1014, 3953, 212, 5314, 192 },
  { 831, 1002, 4002, 212, 5314, 192 },
  { 937, 990, 3909, 212, 5314, 192 },
  { 1051, 978, 3909, 212, 5314, 192 },
  { 1157, 966, 3798, 212, 5314, 192 },
  { 3, 954, 3798, 212, 5314, 192 },
  { 148, 942, 3682, 212, 5314, 192 },
  { 275, 930, 3682, 212, 5314, 192 },
  { 401, 918, 3562, 212, 5314, 192 },
  { 515, 906, 3562, 212, 5314, 192 },
  { 641, 894, 3442, 212, 5314, 192 },
  { 760, 1070, 3442, 202, 17506, 199 },
  { 874, 1060, 3322, 202, 13426, 199 },
  { 980, 1052, 3322, 194, 14226, 205 },
  { 1094, 1044, 3226, 194, 13698, 205 },
  { 51, 1038, 3226, 188, 14049, 210 },
  { 200, 1038, 3131, 188, 14049, 210 },
  { 328, 1038, 3131, 188, 14049, 210 },
  { 448, 1038, 3061, 188, 14049, 210 },
  { 567, 1038, 3061, 188, 14049, 210 },
  { 689, 1038, 2991, 188, 14049, 210 },
  { 796, 1038, 2991, 188, 14049, 210 },
  { 906, 1038, 2921, 188, 14049, 210 },
  { 1016, 1038, 2921, 188, 14049, 210 },
  { 1126, 1038, 2832, 188, 14049, 210 },
  { 87, 1038, 2855, 188, 14049, 210 },
  { 232, 1038, 2794, 188, 14049, 210 },
  { 828, 2677, 4010, 276, 5170, 157 },
  { 934, 2659, 3951, 276, 5170, 157 },
  { 1048, 2641, 3951, 276, 5170, 157 },
  { 1154, 2623, 3842, 276, 5170, 157 },
  { 0, 2605, 3842, 276, 5170, 157 },
  { 145, 2587, 3743, 276, 5170, 157 },
  { 272, 2569, 3743, 276, 5170, 157 },
  { 398, 2551, 3625, 276, 5170, 157 },
  { 512, 2533, 3625, 276, 5170, 157 },
  { 638, 2515, 3505, 276, 5170, 157 },
  { 756, 2773, 3505, 260, 17378, 166 },
  { 870, 2757, 3385, 260, 13298, 166 },
  { 976, 2743, 3385, 246, 14114, 174 },
  { 1090, 2729, 3265, 246, 13586, 174 },
  { 47, 2717, 3265, 234, 13954, 181 },
  { 196, 2705, 3170, 234, 13778, 181 },
  { 324, 2695, 3170, 224, 13873, 187 },
  { 444, 2695, 3099, 224, 13873, 187 },
  { 563, 2695, 3099, 224, 13873, 187 },
  { 685, 2695, 3029, 224, 13873, 187 },
  { 792, 2695, 3029, 224, 13873, 187 },
  { 902, 2695, 2959, 224, 13873, 187 },
  { 1012, 2695, 2959, 224, 13873, 187 },
  { 1122, 2695, 2856, 224, 13873, 187 },
  { 83, 2695, 2856, 224, 13873, 187 },
  { 228, 2695, 2795, 224, 13873, 187 },
  { 369, 360, 2509, 22, 1956, 11 },
  { 614, 388, 583, 22, 1956, 11 },
  { 846, 416, 756, 22, 1956, 11 },
  { 1066, 444, 747, 22, 1956, 11 },
  { 19, 472, 738, 22, 1956, 11 },
  { 293, 500, 729, 22, 1956, 11 },
  { 535, 528, 720, 22, 1956, 11 },
  { 780, 3839, 711, 3, 2336, 16 },
  { 1000, 562, 702, 0, 8898, 20 },
  { 71, 565, 693, 0, 8898, 20 },
  { 348, 568, 684, 0, 8898, 20 },
  { 587, 571, 675, 0, 8898, 20 },
  { 816, 574, 666, 0, 8898, 20 },
  { 1036, 577, 2460, 0, 8898, 20 },
  { 107, 580, 2468, 0, 8898, 20 },
  { 608, 2343, 2488, 148, 900, 57 },
  { 840, 2323, 588, 148, 900, 57 },
  { 1060, 2303, 588, 148, 900, 57 },
  { 13, 2283, 588, 148, 900, 57 },
  { 286, 2263, 588, 148, 900, 57 },
  { 527, 2243, 588, 148, 900, 57 },
  { 772, 2225, 588, 130, 1328, 66 },
  { 992, 2211, 588, 116, 1776, 81 },
  { 63, 1588, 588, 104, 2034, 87 },
  { 340, 1576, 588, 104, 2034, 87 },
  { 579, 1564, 588, 104, 2034, 87 },
  { 808, 1552, 588, 104, 2034, 87 },
  { 1028, 1540, 588, 104, 2034, 87 },
  { 99, 1528, 2382, 104, 2034, 87 },
};

extern const MCPhysReg ARMRegUnitRoots[][2] = {
  { ARM::APSR },
  { ARM::APSR_NZCV },
  { ARM::CPSR },
  { ARM::FPEXC },
  { ARM::FPINST },
  { ARM::FPSCR, ARM::FPSCR_NZCV },
  { ARM::FPSID },
  { ARM::ITSTATE },
  { ARM::LR },
  { ARM::PC },
  { ARM::SP },
  { ARM::SPSR },
  { ARM::S0 },
  { ARM::S1 },
  { ARM::S2 },
  { ARM::S3 },
  { ARM::S4 },
  { ARM::S5 },
  { ARM::S6 },
  { ARM::S7 },
  { ARM::S8 },
  { ARM::S9 },
  { ARM::S10 },
  { ARM::S11 },
  { ARM::S12 },
  { ARM::S13 },
  { ARM::S14 },
  { ARM::S15 },
  { ARM::S16 },
  { ARM::S17 },
  { ARM::S18 },
  { ARM::S19 },
  { ARM::S20 },
  { ARM::S21 },
  { ARM::S22 },
  { ARM::S23 },
  { ARM::S24 },
  { ARM::S25 },
  { ARM::S26 },
  { ARM::S27 },
  { ARM::S28 },
  { ARM::S29 },
  { ARM::S30 },
  { ARM::S31 },
  { ARM::D16 },
  { ARM::D17 },
  { ARM::D18 },
  { ARM::D19 },
  { ARM::D20 },
  { ARM::D21 },
  { ARM::D22 },
  { ARM::D23 },
  { ARM::D24 },
  { ARM::D25 },
  { ARM::D26 },
  { ARM::D27 },
  { ARM::D28 },
  { ARM::D29 },
  { ARM::D30 },
  { ARM::D31 },
  { ARM::FPINST2 },
  { ARM::MVFR0 },
  { ARM::MVFR1 },
  { ARM::MVFR2 },
  { ARM::R0 },
  { ARM::R1 },
  { ARM::R2 },
  { ARM::R3 },
  { ARM::R4 },
  { ARM::R5 },
  { ARM::R6 },
  { ARM::R7 },
  { ARM::R8 },
  { ARM::R9 },
  { ARM::R10 },
  { ARM::R11 },
  { ARM::R12 },
};

namespace {     // Register classes...
  // SPR Register Class...
  const MCPhysReg SPR[] = {
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
  };

  // SPR Bit set.
  const uint8_t SPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // GPR Register Class...
  const MCPhysReg GPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
  };

  // GPR Bit set.
  const uint8_t GPRBits[] = {
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // GPRwithAPSR Register Class...
  const MCPhysReg GPRwithAPSR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, 
  };

  // GPRwithAPSR Bit set.
  const uint8_t GPRwithAPSRBits[] = {
    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // SPR_8 Register Class...
  const MCPhysReg SPR_8[] = {
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, 
  };

  // SPR_8 Bit set.
  const uint8_t SPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // GPRnopc Register Class...
  const MCPhysReg GPRnopc[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
  };

  // GPRnopc Bit set.
  const uint8_t GPRnopcBits[] = {
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // rGPR Register Class...
  const MCPhysReg rGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
  };

  // rGPR Bit set.
  const uint8_t rGPRBits[] = {
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // hGPR Register Class...
  const MCPhysReg hGPR[] = {
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
  };

  // hGPR Bit set.
  const uint8_t hGPRBits[] = {
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
  };

  // tGPR Register Class...
  const MCPhysReg tGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, 
  };

  // tGPR Bit set.
  const uint8_t tGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // GPRnopc_and_hGPR Register Class...
  const MCPhysReg GPRnopc_and_hGPR[] = {
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
  };

  // GPRnopc_and_hGPR Bit set.
  const uint8_t GPRnopc_and_hGPRBits[] = {
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
  };

  // hGPR_and_rGPR Register Class...
  const MCPhysReg hGPR_and_rGPR[] = {
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
  };

  // hGPR_and_rGPR Bit set.
  const uint8_t hGPR_and_rGPRBits[] = {
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
  };

  // tcGPR Register Class...
  const MCPhysReg tcGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, 
  };

  // tcGPR Bit set.
  const uint8_t tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, 
  };

  // tGPR_and_tcGPR Register Class...
  const MCPhysReg tGPR_and_tcGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, 
  };

  // tGPR_and_tcGPR Bit set.
  const uint8_t tGPR_and_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // CCR Register Class...
  const MCPhysReg CCR[] = {
    ARM::CPSR, 
  };

  // CCR Bit set.
  const uint8_t CCRBits[] = {
    0x08, 
  };

  // GPRsp Register Class...
  const MCPhysReg GPRsp[] = {
    ARM::SP, 
  };

  // GPRsp Bit set.
  const uint8_t GPRspBits[] = {
    0x00, 0x10, 
  };

  // hGPR_and_tcGPR Register Class...
  const MCPhysReg hGPR_and_tcGPR[] = {
    ARM::R12, 
  };

  // hGPR_and_tcGPR Bit set.
  const uint8_t hGPR_and_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // DPR Register Class...
  const MCPhysReg DPR[] = {
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 
  };

  // DPR Bit set.
  const uint8_t DPRBits[] = {
    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // DPR_VFP2 Register Class...
  const MCPhysReg DPR_VFP2[] = {
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 
  };

  // DPR_VFP2 Bit set.
  const uint8_t DPR_VFP2Bits[] = {
    0x00, 0xc0, 0xff, 0x3f, 
  };

  // DPR_8 Register Class...
  const MCPhysReg DPR_8[] = {
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 
  };

  // DPR_8 Bit set.
  const uint8_t DPR_8Bits[] = {
    0x00, 0xc0, 0x3f, 
  };

  // GPRPair Register Class...
  const MCPhysReg GPRPair[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
  };

  // GPRPair Bit set.
  const uint8_t GPRPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 
  };

  // GPRPair_with_gsub_1_in_rGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, 
  };

  // GPRPair_with_gsub_1_in_rGPR Bit set.
  const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
  };

  // GPRPair_with_gsub_0_in_tGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 
  };

  // GPRPair_with_gsub_0_in_tGPR Bit set.
  const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // GPRPair_with_gsub_0_in_hGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
    ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
  };

  // GPRPair_with_gsub_0_in_hGPR Bit set.
  const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 
  };

  // GPRPair_with_gsub_0_in_tcGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, 
  };

  // GPRPair_with_gsub_0_in_tcGPR Bit set.
  const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 
  };

  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
    ARM::R8_R9, ARM::R10_R11, 
  };

  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
  const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 
  };

  // GPRPair_with_gsub_1_in_tcGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
    ARM::R0_R1, ARM::R2_R3, 
  };

  // GPRPair_with_gsub_1_in_tcGPR Bit set.
  const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
  };

  // GPRPair_with_gsub_1_in_GPRsp Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
    ARM::R12_SP, 
  };

  // GPRPair_with_gsub_1_in_GPRsp Bit set.
  const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
  };

  // DPairSpc Register Class...
  const MCPhysReg DPairSpc[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, 
  };

  // DPairSpc Bit set.
  const uint8_t DPairSpcBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
  };

  // DPairSpc_with_ssub_0 Register Class...
  const MCPhysReg DPairSpc_with_ssub_0[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 
  };

  // DPairSpc_with_ssub_0 Bit set.
  const uint8_t DPairSpc_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // DPairSpc_with_dsub_2_then_ssub_0 Register Class...
  const MCPhysReg DPairSpc_with_dsub_2_then_ssub_0[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, 
  };

  // DPairSpc_with_dsub_2_then_ssub_0 Bit set.
  const uint8_t DPairSpc_with_dsub_2_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 
  };

  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 
  };

  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, 
  };

  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 
  };

  // DPair Register Class...
  const MCPhysReg DPair[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, 
  };

  // DPair Bit set.
  const uint8_t DPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
  };

  // DPair_with_ssub_0 Register Class...
  const MCPhysReg DPair_with_ssub_0[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, 
  };

  // DPair_with_ssub_0 Bit set.
  const uint8_t DPair_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
  };

  // QPR Register Class...
  const MCPhysReg QPR[] = {
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 
  };

  // QPR Bit set.
  const uint8_t QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
  };

  // DPair_with_ssub_2 Register Class...
  const MCPhysReg DPair_with_ssub_2[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, 
  };

  // DPair_with_ssub_2 Bit set.
  const uint8_t DPair_with_ssub_2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
  };

  // DPair_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, 
  };

  // DPair_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
  };

  // QPR_VFP2 Register Class...
  const MCPhysReg QPR_VFP2[] = {
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 
  };

  // QPR_VFP2 Bit set.
  const uint8_t QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // DPair_with_dsub_1_in_DPR_8 Register Class...
  const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, 
  };

  // DPair_with_dsub_1_in_DPR_8 Bit set.
  const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
  };

  // QPR_8 Register Class...
  const MCPhysReg QPR_8[] = {
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 
  };

  // QPR_8 Bit set.
  const uint8_t QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // DTriple Register Class...
  const MCPhysReg DTriple[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, 
  };

  // DTriple Bit set.
  const uint8_t DTripleBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, 
  };

  // DTripleSpc Register Class...
  const MCPhysReg DTripleSpc[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
  };

  // DTripleSpc Bit set.
  const uint8_t DTripleSpcBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
  };

  // DTripleSpc_with_ssub_0 Register Class...
  const MCPhysReg DTripleSpc_with_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
  };

  // DTripleSpc_with_ssub_0 Bit set.
  const uint8_t DTripleSpc_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // DTriple_with_ssub_0 Register Class...
  const MCPhysReg DTriple_with_ssub_0[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, 
  };

  // DTriple_with_ssub_0 Bit set.
  const uint8_t DTriple_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
  };

  // DTriple_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DTriple_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, 
  };

  // DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, 
  };

  // DTriple_with_qsub_0_in_QPR Register Class...
  const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, 
  };

  // DTriple_with_qsub_0_in_QPR Bit set.
  const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 
  };

  // DTriple_with_ssub_2 Register Class...
  const MCPhysReg DTriple_with_ssub_2[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, 
  };

  // DTriple_with_ssub_2 Bit set.
  const uint8_t DTriple_with_ssub_2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 
  };

  // DTripleSpc_with_dsub_2_then_ssub_0 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_2_then_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
  };

  // DTripleSpc_with_dsub_2_then_ssub_0 Bit set.
  const uint8_t DTripleSpc_with_dsub_2_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
  };

  // DTriple_with_dsub_2_then_ssub_0 Register Class...
  const MCPhysReg DTriple_with_dsub_2_then_ssub_0[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, 
  };

  // DTriple_with_dsub_2_then_ssub_0 Bit set.
  const uint8_t DTriple_with_dsub_2_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
  };

  // DTripleSpc_with_dsub_4_then_ssub_0 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_4_then_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
  };

  // DTripleSpc_with_dsub_4_then_ssub_0 Bit set.
  const uint8_t DTripleSpc_with_dsub_4_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
  };

  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
  };

  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

  // DTriple_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, 
  };

  // DTriple_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
  };

  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
  const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, 
  };

  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
  const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
  };

  // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, 
  };

  // DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 
  };

  // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class...
  const MCPhysReg DTriple_with_dsub_1_dsub_2_in_QPR_VFP2[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, 
  };

  // DTriple_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set.
  const uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 
  };

  // DTriple_with_dsub_1_in_DPR_8 Register Class...
  const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, 
  };

  // DTriple_with_dsub_1_in_DPR_8 Bit set.
  const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Register Class...
  const MCPhysReg DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, 
  };

  // DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR Bit set.
  const uint8_t DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 
  };

  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
  };

  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // DTriple_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, 
  };

  // DTriple_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 
  };

  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
  };

  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
  const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
  };

  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, 
  };

  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
  };

  // DTriple_with_qsub_0_in_QPR_8 Register Class...
  const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, 
  };

  // DTriple_with_qsub_0_in_QPR_8 Bit set.
  const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 
  };

  // DTriple_with_dsub_1_dsub_2_in_QPR_8 Register Class...
  const MCPhysReg DTriple_with_dsub_1_dsub_2_in_QPR_8[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, 
  };

  // DTriple_with_dsub_1_dsub_2_in_QPR_8 Bit set.
  const uint8_t DTriple_with_dsub_1_dsub_2_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 
  };

  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, 
  };

  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
  const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 
  };

  // DQuadSpc Register Class...
  const MCPhysReg DQuadSpc[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
  };

  // DQuadSpc Bit set.
  const uint8_t DQuadSpcBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
  };

  // DQuadSpc_with_ssub_0 Register Class...
  const MCPhysReg DQuadSpc_with_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
  };

  // DQuadSpc_with_ssub_0 Bit set.
  const uint8_t DQuadSpc_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // DQuadSpc_with_dsub_2_then_ssub_0 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_2_then_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
  };

  // DQuadSpc_with_dsub_2_then_ssub_0 Bit set.
  const uint8_t DQuadSpc_with_dsub_2_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
  };

  // DQuadSpc_with_dsub_4_then_ssub_0 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_4_then_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
  };

  // DQuadSpc_with_dsub_4_then_ssub_0 Bit set.
  const uint8_t DQuadSpc_with_dsub_4_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
  };

  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
  };

  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
  };

  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
  };

  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
  const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
  };

  // DQuad Register Class...
  const MCPhysReg DQuad[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, 
  };

  // DQuad Bit set.
  const uint8_t DQuadBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
  };

  // DQuad_with_ssub_0 Register Class...
  const MCPhysReg DQuad_with_ssub_0[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, 
  };

  // DQuad_with_ssub_0 Bit set.
  const uint8_t DQuad_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // DQuad_with_ssub_2 Register Class...
  const MCPhysReg DQuad_with_ssub_2[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, 
  };

  // DQuad_with_ssub_2 Bit set.
  const uint8_t DQuad_with_ssub_2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
  };

  // QQPR Register Class...
  const MCPhysReg QQPR[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, 
  };

  // QQPR Bit set.
  const uint8_t QQPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
  };

  // DQuad_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DQuad_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, 
  };

  // DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
  };

  // DQuad_with_dsub_2_then_ssub_0 Register Class...
  const MCPhysReg DQuad_with_dsub_2_then_ssub_0[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, 
  };

  // DQuad_with_dsub_2_then_ssub_0 Bit set.
  const uint8_t DQuad_with_dsub_2_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
  };

  // DQuad_with_dsub_3_then_ssub_0 Register Class...
  const MCPhysReg DQuad_with_dsub_3_then_ssub_0[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, 
  };

  // DQuad_with_dsub_3_then_ssub_0 Bit set.
  const uint8_t DQuad_with_dsub_3_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
  };

  // DQuad_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, 
  };

  // DQuad_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
  };

  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
  const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, 
  };

  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
  const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
  };

  // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, 
  };

  // DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Register Class...
  const MCPhysReg DQuad_with_dsub_1_dsub_2_in_QPR_VFP2[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, 
  };

  // DQuad_with_dsub_1_dsub_2_in_QPR_VFP2 Bit set.
  const uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
  };

  // DQuad_with_dsub_1_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, 
  };

  // DQuad_with_dsub_1_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
  const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, 
  };

  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
  const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
  };

  // DQuad_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, 
  };

  // DQuad_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, 
  };

  // DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
  };

  // DQuad_with_dsub_3_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, 
  };

  // DQuad_with_dsub_3_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, 
  };

  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
  };

  // DQuad_with_qsub_0_in_QPR_8 Register Class...
  const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 
  };

  // DQuad_with_qsub_0_in_QPR_8 Bit set.
  const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
  };

  // DQuad_with_dsub_1_dsub_2_in_QPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_1_dsub_2_in_QPR_8[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, 
  };

  // DQuad_with_dsub_1_dsub_2_in_QPR_8 Bit set.
  const uint8_t DQuad_with_dsub_1_dsub_2_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DQuad_with_qsub_1_in_QPR_8 Register Class...
  const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, 
  };

  // DQuad_with_qsub_1_in_QPR_8 Bit set.
  const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
  };

  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Register Class...
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, 
  };

  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR Bit set.
  const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // QQQQPR Register Class...
  const MCPhysReg QQQQPR[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, 
  };

  // QQQQPR Bit set.
  const uint8_t QQQQPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
  };

  // QQQQPR_with_ssub_0 Register Class...
  const MCPhysReg QQQQPR_with_ssub_0[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, 
  };

  // QQQQPR_with_ssub_0 Bit set.
  const uint8_t QQQQPR_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
  };

  // QQQQPR_with_dsub_2_then_ssub_0 Register Class...
  const MCPhysReg QQQQPR_with_dsub_2_then_ssub_0[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, 
  };

  // QQQQPR_with_dsub_2_then_ssub_0 Bit set.
  const uint8_t QQQQPR_with_dsub_2_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
  };

  // QQQQPR_with_dsub_5_then_ssub_0 Register Class...
  const MCPhysReg QQQQPR_with_dsub_5_then_ssub_0[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, 
  };

  // QQQQPR_with_dsub_5_then_ssub_0 Bit set.
  const uint8_t QQQQPR_with_dsub_5_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
  };

  // QQQQPR_with_dsub_7_then_ssub_0 Register Class...
  const MCPhysReg QQQQPR_with_dsub_7_then_ssub_0[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, 
  };

  // QQQQPR_with_dsub_7_then_ssub_0 Bit set.
  const uint8_t QQQQPR_with_dsub_7_then_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 
  };

  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, 
  };

  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
  };

  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 
  };

  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
  };

  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, 
  };

  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
  };

  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, 
  };

  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

}

extern const char ARMRegClassStrings[] = {
  /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 19 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 40 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 63 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 84 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 102 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 122 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 171 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 204 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 239 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 272 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 302 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 334 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 364 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 397 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 432 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '5', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 463 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '7', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 494 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 503 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 533 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 565 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 595 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 632 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 671 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
  /* 689 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
  /* 709 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
  /* 727 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 755 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 785 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 817 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 847 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 874 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 903 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 930 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 957 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 986 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1013 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1041 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1071 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1103 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1133 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1160 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1189 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1216 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1244 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1274 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1306 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1334 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1361 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1390 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1417 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1451 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1487 */ 'S', 'P', 'R', '_', '8', 0,
  /* 1493 */ 'C', 'C', 'R', 0,
  /* 1497 */ 'D', 'P', 'R', 0,
  /* 1501 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1516 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1531 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1560 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1589 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0,
  /* 1606 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0,
  /* 1634 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 'r', 'G', 'P', 'R', 0,
  /* 1671 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'r', 'G', 'P', 'R', 0,
  /* 1699 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0,
  /* 1727 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0,
  /* 1734 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1797 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1857 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1911 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 't', 'h', 'e', 'n', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1977 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 2040 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 2103 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 2161 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 2228 */ 'S', 'P', 'R', 0,
  /* 2232 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0,
  /* 2244 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0,
  /* 2253 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0,
  /* 2264 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0,
  /* 2273 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0,
  /* 2281 */ 'D', 'Q', 'u', 'a', 'd', 0,
  /* 2287 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0,
  /* 2295 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0,
  /* 2324 */ 'D', 'P', 'a', 'i', 'r', 0,
  /* 2330 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0,
};

extern const MCRegisterClass ARMMCRegisterClasses[] = {
  { SPR, SPRBits, 2228, 32, sizeof(SPRBits), ARM::SPRRegClassID, 4, 4, 1, 1 },
  { GPR, GPRBits, 1512, 16, sizeof(GPRBits), ARM::GPRRegClassID, 4, 4, 1, 1 },
  { GPRwithAPSR, GPRwithAPSRBits, 2232, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 4, 4, 1, 1 },
  { SPR_8, SPR_8Bits, 1487, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 4, 4, 1, 1 },
  { GPRnopc, GPRnopcBits, 2273, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 4, 4, 1, 1 },
  { rGPR, rGPRBits, 1666, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 4, 4, 1, 1 },
  { hGPR, hGPRBits, 1601, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 4, 4, 1, 1 },
  { tGPR, tGPRBits, 1722, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 4, 4, 1, 1 },
  { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1589, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 4, 4, 1, 1 },
  { hGPR_and_rGPR, hGPR_and_rGPRBits, 1657, 6, sizeof(hGPR_and_rGPRBits), ARM::hGPR_and_rGPRRegClassID, 4, 4, 1, 1 },
  { tcGPR, tcGPRBits, 1510, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 4, 4, 1, 1 },
  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1516, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 4, 4, 1, 1 },
  { CCR, CCRBits, 1493, 1, sizeof(CCRBits), ARM::CCRRegClassID, 4, 4, -1, 0 },
  { GPRsp, GPRspBits, 2318, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 4, 4, 1, 1 },
  { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1501, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 4, 4, 1, 1 },
  { DPR, DPRBits, 1497, 32, sizeof(DPRBits), ARM::DPRRegClassID, 8, 8, 1, 1 },
  { DPR_VFP2, DPR_VFP2Bits, 494, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 8, 8, 1, 1 },
  { DPR_8, DPR_8Bits, 749, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 8, 8, 1, 1 },
  { GPRPair, GPRPairBits, 2330, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 8, 8, 1, 1 },
  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1671, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM::GPRPair_with_gsub_1_in_rGPRRegClassID, 8, 8, 1, 1 },
  { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1699, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 8, 8, 1, 1 },
  { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1606, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 8, 8, 1, 1 },
  { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 8, 8, 1, 1 },
  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1634, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 8, 8, 1, 1 },
  { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1560, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 8, 8, 1, 1 },
  { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2295, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 8, 8, 1, 1 },
  { DPairSpc, DPairSpcBits, 2264, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 16, 8, 1, 1 },
  { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 16, 8, 1, 1 },
  { DPairSpc_with_dsub_2_then_ssub_0, DPairSpc_with_dsub_2_then_ssub_0Bits, 239, 14, sizeof(DPairSpc_with_dsub_2_then_ssub_0Bits), ARM::DPairSpc_with_dsub_2_then_ssub_0RegClassID, 16, 8, 1, 1 },
  { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 817, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 16, 8, 1, 1 },
  { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 1103, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 16, 8, 1, 1 },
  { DPair, DPairBits, 2324, 31, sizeof(DPairBits), ARM::DPairRegClassID, 16, 16, 1, 1 },
  { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 16, 16, 1, 1 },
  { QPR, QPRBits, 1730, 16, sizeof(QPRBits), ARM::QPRRegClassID, 16, 16, 1, 1 },
  { DPair_with_ssub_2, DPair_with_ssub_2Bits, 709, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 16, 16, 1, 1 },
  { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 903, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 16, 16, 1, 1 },
  { QPR_VFP2, QPR_VFP2Bits, 524, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 16, 16, 1, 1 },
  { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 986, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 16, 16, 1, 1 },
  { QPR_8, QPR_8Bits, 1355, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 16, 16, 1, 1 },
  { DTriple, DTripleBits, 2287, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 24, 8, 1, 1 },
  { DTripleSpc, DTripleSpcBits, 2253, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 24, 8, 1, 1 },
  { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 24, 8, 1, 1 },
  { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_1_dsub_2_in_QPRBits, 2127, 15, sizeof(DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM::DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 },
  { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1770, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 },
  { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 689, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 24, 8, 1, 1 },
  { DTripleSpc_with_dsub_2_then_ssub_0, DTripleSpc_with_dsub_2_then_ssub_0Bits, 204, 14, sizeof(DTripleSpc_with_dsub_2_then_ssub_0Bits), ARM::DTripleSpc_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_2_then_ssub_0, DTriple_with_dsub_2_then_ssub_0Bits, 302, 14, sizeof(DTriple_with_dsub_2_then_ssub_0Bits), ARM::DTriple_with_dsub_2_then_ssub_0RegClassID, 24, 8, 1, 1 },
  { DTripleSpc_with_dsub_4_then_ssub_0, DTripleSpc_with_dsub_4_then_ssub_0Bits, 397, 12, sizeof(DTripleSpc_with_dsub_4_then_ssub_0Bits), ARM::DTripleSpc_with_dsub_4_then_ssub_0RegClassID, 24, 8, 1, 1 },
  { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 785, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 874, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 24, 8, 1, 1 },
  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 533, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 24, 8, 1, 1 },
  { DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 2103, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_1_dsub_2_in_QPR_VFP2, DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 632, 7, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM::DTriple_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 957, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits, 1734, 7, sizeof(DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_then_ssub_0_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 },
  { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 1071, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 1160, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 24, 8, 1, 1 },
  { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1274, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits, 2161, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_dsub_1_dsub_2_in_QPRRegClassID, 24, 8, 1, 1 },
  { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1361, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_1_dsub_2_in_QPR_8, DTriple_with_dsub_1_dsub_2_in_QPR_8Bits, 1451, 3, sizeof(DTriple_with_dsub_1_dsub_2_in_QPR_8Bits), ARM::DTriple_with_dsub_1_dsub_2_in_QPR_8RegClassID, 24, 8, 1, 1 },
  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1797, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 24, 8, 1, 1 },
  { DQuadSpc, DQuadSpcBits, 2244, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 32, 8, 1, 1 },
  { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 32, 8, 1, 1 },
  { DQuadSpc_with_dsub_2_then_ssub_0, DQuadSpc_with_dsub_2_then_ssub_0Bits, 171, 14, sizeof(DQuadSpc_with_dsub_2_then_ssub_0Bits), ARM::DQuadSpc_with_dsub_2_then_ssub_0RegClassID, 32, 8, 1, 1 },
  { DQuadSpc_with_dsub_4_then_ssub_0, DQuadSpc_with_dsub_4_then_ssub_0Bits, 364, 12, sizeof(DQuadSpc_with_dsub_4_then_ssub_0Bits), ARM::DQuadSpc_with_dsub_4_then_ssub_0RegClassID, 32, 8, 1, 1 },
  { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 755, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 32, 8, 1, 1 },
  { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 1041, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 32, 8, 1, 1 },
  { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1244, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 32, 8, 1, 1 },
  { DQuad, DQuadBits, 2281, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 32, 32, 1, 1 },
  { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 32, 32, 1, 1 },
  { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 671, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 32, 32, 1, 1 },
  { QQPR, QQPRBits, 1729, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_1_dsub_2_in_QPRBits, 1879, 14, sizeof(DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM::DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_2_then_ssub_0, DQuad_with_dsub_2_then_ssub_0Bits, 272, 14, sizeof(DQuad_with_dsub_2_then_ssub_0Bits), ARM::DQuad_with_dsub_2_then_ssub_0RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_3_then_ssub_0, DQuad_with_dsub_3_then_ssub_0Bits, 334, 13, sizeof(DQuad_with_dsub_3_then_ssub_0Bits), ARM::DQuad_with_dsub_3_then_ssub_0RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 847, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 32, 32, 1, 1 },
  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 503, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 32, 32, 1, 1 },
  { DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 1857, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_1_dsub_2_in_QPR_VFP2, DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits, 595, 7, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_VFP2Bits), ARM::DQuad_with_dsub_1_dsub_2_in_QPR_VFP2RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 930, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 32, 32, 1, 1 },
  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 565, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 1133, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 1911, 6, sizeof(DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM::DQuad_with_dsub_3_then_ssub_0_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1189, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 1977, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 },
  { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1334, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_1_dsub_2_in_QPR_8, DQuad_with_dsub_1_dsub_2_in_QPR_8Bits, 1417, 3, sizeof(DQuad_with_dsub_1_dsub_2_in_QPR_8Bits), ARM::DQuad_with_dsub_1_dsub_2_in_QPR_8RegClassID, 32, 32, 1, 1 },
  { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1390, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 32, 32, 1, 1 },
  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits, 2040, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_dsub_1_dsub_2_in_QPRRegClassID, 32, 32, 1, 1 },
  { QQQQPR, QQQQPRBits, 1727, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_dsub_2_then_ssub_0, QQQQPR_with_dsub_2_then_ssub_0Bits, 140, 7, sizeof(QQQQPR_with_dsub_2_then_ssub_0Bits), ARM::QQQQPR_with_dsub_2_then_ssub_0RegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_dsub_5_then_ssub_0, QQQQPR_with_dsub_5_then_ssub_0Bits, 432, 6, sizeof(QQQQPR_with_dsub_5_then_ssub_0Bits), ARM::QQQQPR_with_dsub_5_then_ssub_0RegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_dsub_7_then_ssub_0, QQQQPR_with_dsub_7_then_ssub_0Bits, 463, 5, sizeof(QQQQPR_with_dsub_7_then_ssub_0Bits), ARM::QQQQPR_with_dsub_7_then_ssub_0RegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 727, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 1013, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1216, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 64, 32, 1, 1 },
  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1306, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 64, 32, 1, 1 },
};

// ARM Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
  { 0U, ARM::R0 },
  { 1U, ARM::R1 },
  { 2U, ARM::R2 },
  { 3U, ARM::R3 },
  { 4U, ARM::R4 },
  { 5U, ARM::R5 },
  { 6U, ARM::R6 },
  { 7U, ARM::R7 },
  { 8U, ARM::R8 },
  { 9U, ARM::R9 },
  { 10U, ARM::R10 },
  { 11U, ARM::R11 },
  { 12U, ARM::R12 },
  { 13U, ARM::SP },
  { 14U, ARM::LR },
  { 15U, ARM::PC },
  { 256U, ARM::D0 },
  { 257U, ARM::D1 },
  { 258U, ARM::D2 },
  { 259U, ARM::D3 },
  { 260U, ARM::D4 },
  { 261U, ARM::D5 },
  { 262U, ARM::D6 },
  { 263U, ARM::D7 },
  { 264U, ARM::D8 },
  { 265U, ARM::D9 },
  { 266U, ARM::D10 },
  { 267U, ARM::D11 },
  { 268U, ARM::D12 },
  { 269U, ARM::D13 },
  { 270U, ARM::D14 },
  { 271U, ARM::D15 },
  { 272U, ARM::D16 },
  { 273U, ARM::D17 },
  { 274U, ARM::D18 },
  { 275U, ARM::D19 },
  { 276U, ARM::D20 },
  { 277U, ARM::D21 },
  { 278U, ARM::D22 },
  { 279U, ARM::D23 },
  { 280U, ARM::D24 },
  { 281U, ARM::D25 },
  { 282U, ARM::D26 },
  { 283U, ARM::D27 },
  { 284U, ARM::D28 },
  { 285U, ARM::D29 },
  { 286U, ARM::D30 },
  { 287U, ARM::D31 },
};
extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
  { 0U, ARM::R0 },
  { 1U, ARM::R1 },
  { 2U, ARM::R2 },
  { 3U, ARM::R3 },
  { 4U, ARM::R4 },
  { 5U, ARM::R5 },
  { 6U, ARM::R6 },
  { 7U, ARM::R7 },
  { 8U, ARM::R8 },
  { 9U, ARM::R9 },
  { 10U, ARM::R10 },
  { 11U, ARM::R11 },
  { 12U, ARM::R12 },
  { 13U, ARM::SP },
  { 14U, ARM::LR },
  { 15U, ARM::PC },
  { 256U, ARM::D0 },
  { 257U, ARM::D1 },
  { 258U, ARM::D2 },
  { 259U, ARM::D3 },
  { 260U, ARM::D4 },
  { 261U, ARM::D5 },
  { 262U, ARM::D6 },
  { 263U, ARM::D7 },
  { 264U, ARM::D8 },
  { 265U, ARM::D9 },
  { 266U, ARM::D10 },
  { 267U, ARM::D11 },
  { 268U, ARM::D12 },
  { 269U, ARM::D13 },
  { 270U, ARM::D14 },
  { 271U, ARM::D15 },
  { 272U, ARM::D16 },
  { 273U, ARM::D17 },
  { 274U, ARM::D18 },
  { 275U, ARM::D19 },
  { 276U, ARM::D20 },
  { 277U, ARM::D21 },
  { 278U, ARM::D22 },
  { 279U, ARM::D23 },
  { 280U, ARM::D24 },
  { 281U, ARM::D25 },
  { 282U, ARM::D26 },
  { 283U, ARM::D27 },
  { 284U, ARM::D28 },
  { 285U, ARM::D29 },
  { 286U, ARM::D30 },
  { 287U, ARM::D31 },
};
extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
  { ARM::LR, 14U },
  { ARM::PC, 15U },
  { ARM::SP, 13U },
  { ARM::D0, 256U },
  { ARM::D1, 257U },
  { ARM::D2, 258U },
  { ARM::D3, 259U },
  { ARM::D4, 260U },
  { ARM::D5, 261U },
  { ARM::D6, 262U },
  { ARM::D7, 263U },
  { ARM::D8, 264U },
  { ARM::D9, 265U },
  { ARM::D10, 266U },
  { ARM::D11, 267U },
  { ARM::D12, 268U },
  { ARM::D13, 269U },
  { ARM::D14, 270U },
  { ARM::D15, 271U },
  { ARM::D16, 272U },
  { ARM::D17, 273U },
  { ARM::D18, 274U },
  { ARM::D19, 275U },
  { ARM::D20, 276U },
  { ARM::D21, 277U },
  { ARM::D22, 278U },
  { ARM::D23, 279U },
  { ARM::D24, 280U },
  { ARM::D25, 281U },
  { ARM::D26, 282U },
  { ARM::D27, 283U },
  { ARM::D28, 284U },
  { ARM::D29, 285U },
  { ARM::D30, 286U },
  { ARM::D31, 287U },
  { ARM::R0, 0U },
  { ARM::R1, 1U },
  { ARM::R2, 2U },
  { ARM::R3, 3U },
  { ARM::R4, 4U },
  { ARM::R5, 5U },
  { ARM::R6, 6U },
  { ARM::R7, 7U },
  { ARM::R8, 8U },
  { ARM::R9, 9U },
  { ARM::R10, 10U },
  { ARM::R11, 11U },
  { ARM::R12, 12U },
};
extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
  { ARM::LR, 14U },
  { ARM::PC, 15U },
  { ARM::SP, 13U },
  { ARM::D0, 256U },
  { ARM::D1, 257U },
  { ARM::D2, 258U },
  { ARM::D3, 259U },
  { ARM::D4, 260U },
  { ARM::D5, 261U },
  { ARM::D6, 262U },
  { ARM::D7, 263U },
  { ARM::D8, 264U },
  { ARM::D9, 265U },
  { ARM::D10, 266U },
  { ARM::D11, 267U },
  { ARM::D12, 268U },
  { ARM::D13, 269U },
  { ARM::D14, 270U },
  { ARM::D15, 271U },
  { ARM::D16, 272U },
  { ARM::D17, 273U },
  { ARM::D18, 274U },
  { ARM::D19, 275U },
  { ARM::D20, 276U },
  { ARM::D21, 277U },
  { ARM::D22, 278U },
  { ARM::D23, 279U },
  { ARM::D24, 280U },
  { ARM::D25, 281U },
  { ARM::D26, 282U },
  { ARM::D27, 283U },
  { ARM::D28, 284U },
  { ARM::D29, 285U },
  { ARM::D30, 286U },
  { ARM::D31, 287U },
  { ARM::R0, 0U },
  { ARM::R1, 1U },
  { ARM::R2, 2U },
  { ARM::R3, 3U },
  { ARM::R4, 4U },
  { ARM::R5, 5U },
  { ARM::R6, 6U },
  { ARM::R7, 7U },
  { ARM::R8, 8U },
  { ARM::R9, 9U },
  { ARM::R10, 10U },
  { ARM::R11, 11U },
  { ARM::R12, 12U },
};
extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf);

extern const uint16_t ARMRegEncodingTable[] = {
  0,
  1,
  15,
  0,
  8,
  9,
  3,
  3,
  0,
  4,
  14,
  15,
  13,
  2,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  10,
  7,
  6,
  5,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  12,
  0,
  2,
  4,
  6,
  8,
  10,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  1,
  3,
  5,
  7,
  9,
  11,
  13,
  15,
  17,
  19,
  21,
  23,
  25,
  27,
  29,
  1,
  3,
  5,
  7,
  9,
  11,
  13,
  15,
  17,
  19,
  21,
  23,
  25,
  27,
};
static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 100, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57,
ARMSubRegIdxRanges, ARMRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // End llvm namespace
#endif // GET_REGINFO_MC_DESC