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7299 lines
732 KiB
7299 lines
732 KiB
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Target Instruction Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_INSTRINFO_ENUM
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#undef GET_INSTRINFO_ENUM
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namespace llvm_ks {
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namespace ARM {
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enum {
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PHI = 0,
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INLINEASM = 1,
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CFI_INSTRUCTION = 2,
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EH_LABEL = 3,
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GC_LABEL = 4,
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KILL = 5,
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EXTRACT_SUBREG = 6,
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INSERT_SUBREG = 7,
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IMPLICIT_DEF = 8,
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SUBREG_TO_REG = 9,
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COPY_TO_REGCLASS = 10,
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DBG_VALUE = 11,
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REG_SEQUENCE = 12,
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COPY = 13,
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BUNDLE = 14,
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LIFETIME_START = 15,
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LIFETIME_END = 16,
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STACKMAP = 17,
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PATCHPOINT = 18,
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LOAD_STACK_GUARD = 19,
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STATEPOINT = 20,
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LOCAL_ESCAPE = 21,
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FAULTING_LOAD_OP = 22,
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G_ADD = 23,
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ABS = 24,
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ADCri = 25,
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ADCrr = 26,
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ADCrsi = 27,
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ADCrsr = 28,
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ADDSri = 29,
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ADDSrr = 30,
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ADDSrsi = 31,
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ADDSrsr = 32,
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ADDri = 33,
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ADDrr = 34,
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ADDrsi = 35,
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ADDrsr = 36,
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ADJCALLSTACKDOWN = 37,
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ADJCALLSTACKUP = 38,
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ADR = 39,
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AESD = 40,
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AESE = 41,
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AESIMC = 42,
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AESMC = 43,
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ANDri = 44,
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ANDrr = 45,
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ANDrsi = 46,
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ANDrsr = 47,
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ASRi = 48,
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ASRr = 49,
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B = 50,
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BCCZi64 = 51,
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BCCi64 = 52,
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BFC = 53,
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BFI = 54,
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BICri = 55,
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BICrr = 56,
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BICrsi = 57,
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BICrsr = 58,
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BKPT = 59,
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BL = 60,
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BLX = 61,
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BLX_pred = 62,
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BLXi = 63,
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BL_pred = 64,
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BMOVPCB_CALL = 65,
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BMOVPCRX_CALL = 66,
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BR_JTadd = 67,
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BR_JTm = 68,
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BR_JTr = 69,
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BX = 70,
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BXJ = 71,
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BX_CALL = 72,
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BX_RET = 73,
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BX_pred = 74,
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Bcc = 75,
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CDP = 76,
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CDP2 = 77,
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CLREX = 78,
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CLZ = 79,
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CMNri = 80,
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CMNzrr = 81,
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CMNzrsi = 82,
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CMNzrsr = 83,
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CMPri = 84,
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CMPrr = 85,
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CMPrsi = 86,
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CMPrsr = 87,
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CONSTPOOL_ENTRY = 88,
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COPY_STRUCT_BYVAL_I32 = 89,
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CPS1p = 90,
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CPS2p = 91,
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CPS3p = 92,
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CRC32B = 93,
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CRC32CB = 94,
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CRC32CH = 95,
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CRC32CW = 96,
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CRC32H = 97,
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CRC32W = 98,
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DBG = 99,
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DMB = 100,
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DSB = 101,
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EORri = 102,
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EORrr = 103,
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EORrsi = 104,
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EORrsr = 105,
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ERET = 106,
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FCONSTD = 107,
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FCONSTH = 108,
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FCONSTS = 109,
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FLDMXDB_UPD = 110,
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FLDMXIA = 111,
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FLDMXIA_UPD = 112,
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FMSTAT = 113,
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FSTMXDB_UPD = 114,
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FSTMXIA = 115,
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FSTMXIA_UPD = 116,
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HINT = 117,
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HLT = 118,
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HVC = 119,
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ISB = 120,
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ITasm = 121,
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Int_eh_sjlj_dispatchsetup = 122,
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Int_eh_sjlj_longjmp = 123,
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Int_eh_sjlj_setjmp = 124,
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Int_eh_sjlj_setjmp_nofp = 125,
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Int_eh_sjlj_setup_dispatch = 126,
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JUMPTABLE_ADDRS = 127,
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JUMPTABLE_INSTS = 128,
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JUMPTABLE_TBB = 129,
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JUMPTABLE_TBH = 130,
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LDA = 131,
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LDAB = 132,
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LDAEX = 133,
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LDAEXB = 134,
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LDAEXD = 135,
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LDAEXH = 136,
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LDAH = 137,
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LDC2L_OFFSET = 138,
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LDC2L_OPTION = 139,
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LDC2L_POST = 140,
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LDC2L_PRE = 141,
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LDC2_OFFSET = 142,
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LDC2_OPTION = 143,
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LDC2_POST = 144,
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LDC2_PRE = 145,
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LDCL_OFFSET = 146,
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LDCL_OPTION = 147,
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LDCL_POST = 148,
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LDCL_PRE = 149,
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LDC_OFFSET = 150,
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LDC_OPTION = 151,
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LDC_POST = 152,
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LDC_PRE = 153,
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LDMDA = 154,
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LDMDA_UPD = 155,
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LDMDB = 156,
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LDMDB_UPD = 157,
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LDMIA = 158,
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LDMIA_RET = 159,
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LDMIA_UPD = 160,
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LDMIB = 161,
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LDMIB_UPD = 162,
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LDRBT_POST = 163,
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LDRBT_POST_IMM = 164,
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LDRBT_POST_REG = 165,
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LDRB_POST_IMM = 166,
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LDRB_POST_REG = 167,
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LDRB_PRE_IMM = 168,
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LDRB_PRE_REG = 169,
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LDRBi12 = 170,
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LDRBrs = 171,
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LDRD = 172,
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LDRD_POST = 173,
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LDRD_PRE = 174,
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LDREX = 175,
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LDREXB = 176,
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LDREXD = 177,
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LDREXH = 178,
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LDRH = 179,
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LDRHTi = 180,
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LDRHTr = 181,
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LDRH_POST = 182,
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LDRH_PRE = 183,
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LDRLIT_ga_abs = 184,
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LDRLIT_ga_pcrel = 185,
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LDRLIT_ga_pcrel_ldr = 186,
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LDRSB = 187,
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LDRSBTi = 188,
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LDRSBTr = 189,
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LDRSB_POST = 190,
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LDRSB_PRE = 191,
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LDRSH = 192,
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LDRSHTi = 193,
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LDRSHTr = 194,
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LDRSH_POST = 195,
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LDRSH_PRE = 196,
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LDRT_POST = 197,
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LDRT_POST_IMM = 198,
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LDRT_POST_REG = 199,
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LDR_POST_IMM = 200,
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LDR_POST_REG = 201,
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LDR_PRE_IMM = 202,
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LDR_PRE_REG = 203,
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LDRcp = 204,
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LDRi12 = 205,
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LDRrs = 206,
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LEApcrel = 207,
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LEApcrelJT = 208,
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LSLi = 209,
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LSLr = 210,
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LSRi = 211,
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LSRr = 212,
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MCR = 213,
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MCR2 = 214,
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MCRR = 215,
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MCRR2 = 216,
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MEMCPY = 217,
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MLA = 218,
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MLAv5 = 219,
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MLS = 220,
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MOVCCi = 221,
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MOVCCi16 = 222,
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MOVCCi32imm = 223,
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MOVCCr = 224,
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MOVCCsi = 225,
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MOVCCsr = 226,
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MOVPCLR = 227,
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MOVPCRX = 228,
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MOVTi16 = 229,
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MOVTi16_ga_pcrel = 230,
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MOV_ga_pcrel = 231,
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MOV_ga_pcrel_ldr = 232,
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MOVi = 233,
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MOVi16 = 234,
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MOVi16_ga_pcrel = 235,
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MOVi32imm = 236,
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MOVr = 237,
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MOVr_TC = 238,
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MOVsi = 239,
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MOVsr = 240,
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MOVsra_flag = 241,
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MOVsrl_flag = 242,
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MRC = 243,
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MRC2 = 244,
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MRRC = 245,
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MRRC2 = 246,
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MRS = 247,
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MRSbanked = 248,
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MRSsys = 249,
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MSR = 250,
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MSRbanked = 251,
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MSRi = 252,
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MUL = 253,
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MULv5 = 254,
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MVNCCi = 255,
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MVNi = 256,
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MVNr = 257,
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MVNsi = 258,
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MVNsr = 259,
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ORRri = 260,
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ORRrr = 261,
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ORRrsi = 262,
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ORRrsr = 263,
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PICADD = 264,
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PICLDR = 265,
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PICLDRB = 266,
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PICLDRH = 267,
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PICLDRSB = 268,
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PICLDRSH = 269,
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PICSTR = 270,
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PICSTRB = 271,
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PICSTRH = 272,
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PKHBT = 273,
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PKHTB = 274,
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PLDWi12 = 275,
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PLDWrs = 276,
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PLDi12 = 277,
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PLDrs = 278,
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PLIi12 = 279,
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PLIrs = 280,
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QADD = 281,
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QADD16 = 282,
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QADD8 = 283,
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QASX = 284,
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QDADD = 285,
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QDSUB = 286,
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QSAX = 287,
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QSUB = 288,
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QSUB16 = 289,
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QSUB8 = 290,
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RBIT = 291,
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REV = 292,
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REV16 = 293,
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REVSH = 294,
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RFEDA = 295,
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RFEDA_UPD = 296,
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RFEDB = 297,
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RFEDB_UPD = 298,
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RFEIA = 299,
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RFEIA_UPD = 300,
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RFEIB = 301,
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RFEIB_UPD = 302,
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RORi = 303,
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RORr = 304,
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RRX = 305,
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RRXi = 306,
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RSBSri = 307,
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RSBSrsi = 308,
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RSBSrsr = 309,
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RSBri = 310,
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RSBrr = 311,
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RSBrsi = 312,
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RSBrsr = 313,
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RSCri = 314,
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RSCrr = 315,
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RSCrsi = 316,
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RSCrsr = 317,
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SADD16 = 318,
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SADD8 = 319,
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SASX = 320,
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SBCri = 321,
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SBCrr = 322,
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SBCrsi = 323,
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SBCrsr = 324,
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SBFX = 325,
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SDIV = 326,
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SEL = 327,
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SETEND = 328,
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SETPAN = 329,
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SHA1C = 330,
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SHA1H = 331,
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SHA1M = 332,
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SHA1P = 333,
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SHA1SU0 = 334,
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SHA1SU1 = 335,
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SHA256H = 336,
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SHA256H2 = 337,
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SHA256SU0 = 338,
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SHA256SU1 = 339,
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SHADD16 = 340,
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SHADD8 = 341,
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SHASX = 342,
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SHSAX = 343,
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SHSUB16 = 344,
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SHSUB8 = 345,
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SMC = 346,
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SMLABB = 347,
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SMLABT = 348,
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SMLAD = 349,
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SMLADX = 350,
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SMLAL = 351,
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SMLALBB = 352,
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SMLALBT = 353,
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SMLALD = 354,
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SMLALDX = 355,
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SMLALTB = 356,
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SMLALTT = 357,
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SMLALv5 = 358,
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SMLATB = 359,
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SMLATT = 360,
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SMLAWB = 361,
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SMLAWT = 362,
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SMLSD = 363,
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SMLSDX = 364,
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SMLSLD = 365,
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SMLSLDX = 366,
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SMMLA = 367,
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SMMLAR = 368,
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SMMLS = 369,
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SMMLSR = 370,
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SMMUL = 371,
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SMMULR = 372,
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SMUAD = 373,
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SMUADX = 374,
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SMULBB = 375,
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SMULBT = 376,
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SMULL = 377,
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SMULLv5 = 378,
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SMULTB = 379,
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SMULTT = 380,
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SMULWB = 381,
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SMULWT = 382,
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SMUSD = 383,
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SMUSDX = 384,
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SPACE = 385,
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SRSDA = 386,
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SRSDA_UPD = 387,
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SRSDB = 388,
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SRSDB_UPD = 389,
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SRSIA = 390,
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SRSIA_UPD = 391,
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SRSIB = 392,
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SRSIB_UPD = 393,
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SSAT = 394,
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SSAT16 = 395,
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SSAX = 396,
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SSUB16 = 397,
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SSUB8 = 398,
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STC2L_OFFSET = 399,
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STC2L_OPTION = 400,
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STC2L_POST = 401,
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STC2L_PRE = 402,
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STC2_OFFSET = 403,
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STC2_OPTION = 404,
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STC2_POST = 405,
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STC2_PRE = 406,
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STCL_OFFSET = 407,
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STCL_OPTION = 408,
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STCL_POST = 409,
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STCL_PRE = 410,
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STC_OFFSET = 411,
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STC_OPTION = 412,
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STC_POST = 413,
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STC_PRE = 414,
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STL = 415,
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STLB = 416,
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STLEX = 417,
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STLEXB = 418,
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STLEXD = 419,
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STLEXH = 420,
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STLH = 421,
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STMDA = 422,
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STMDA_UPD = 423,
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STMDB = 424,
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STMDB_UPD = 425,
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STMIA = 426,
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STMIA_UPD = 427,
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STMIB = 428,
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STMIB_UPD = 429,
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STRBT_POST = 430,
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STRBT_POST_IMM = 431,
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STRBT_POST_REG = 432,
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STRB_POST_IMM = 433,
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STRB_POST_REG = 434,
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STRB_PRE_IMM = 435,
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STRB_PRE_REG = 436,
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STRBi12 = 437,
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STRBi_preidx = 438,
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STRBr_preidx = 439,
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STRBrs = 440,
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STRD = 441,
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STRD_POST = 442,
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STRD_PRE = 443,
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STREX = 444,
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STREXB = 445,
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STREXD = 446,
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STREXH = 447,
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STRH = 448,
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STRHTi = 449,
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STRHTr = 450,
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STRH_POST = 451,
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STRH_PRE = 452,
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STRH_preidx = 453,
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STRT_POST = 454,
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STRT_POST_IMM = 455,
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STRT_POST_REG = 456,
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STR_POST_IMM = 457,
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STR_POST_REG = 458,
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STR_PRE_IMM = 459,
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STR_PRE_REG = 460,
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STRi12 = 461,
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STRi_preidx = 462,
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STRr_preidx = 463,
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STRrs = 464,
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SUBS_PC_LR = 465,
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SUBSri = 466,
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SUBSrr = 467,
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SUBSrsi = 468,
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SUBSrsr = 469,
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SUBri = 470,
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SUBrr = 471,
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SUBrsi = 472,
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SUBrsr = 473,
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SVC = 474,
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SWP = 475,
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SWPB = 476,
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SXTAB = 477,
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SXTAB16 = 478,
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SXTAH = 479,
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SXTB = 480,
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SXTB16 = 481,
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SXTH = 482,
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TAILJMPd = 483,
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TAILJMPr = 484,
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TCRETURNdi = 485,
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TCRETURNri = 486,
|
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TEQri = 487,
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TEQrr = 488,
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TEQrsi = 489,
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TEQrsr = 490,
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TPsoft = 491,
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TRAP = 492,
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|
TRAPNaCl = 493,
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TSTri = 494,
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TSTrr = 495,
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|
TSTrsi = 496,
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TSTrsr = 497,
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UADD16 = 498,
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UADD8 = 499,
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UASX = 500,
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UBFX = 501,
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UDF = 502,
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UDIV = 503,
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UHADD16 = 504,
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UHADD8 = 505,
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UHASX = 506,
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UHSAX = 507,
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UHSUB16 = 508,
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UHSUB8 = 509,
|
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UMAAL = 510,
|
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UMLAL = 511,
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UMLALv5 = 512,
|
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UMULL = 513,
|
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UMULLv5 = 514,
|
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UQADD16 = 515,
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UQADD8 = 516,
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UQASX = 517,
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UQSAX = 518,
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UQSUB16 = 519,
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UQSUB8 = 520,
|
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USAD8 = 521,
|
|
USADA8 = 522,
|
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USAT = 523,
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USAT16 = 524,
|
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USAX = 525,
|
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USUB16 = 526,
|
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USUB8 = 527,
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UXTAB = 528,
|
|
UXTAB16 = 529,
|
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UXTAH = 530,
|
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UXTB = 531,
|
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UXTB16 = 532,
|
|
UXTH = 533,
|
|
VABALsv2i64 = 534,
|
|
VABALsv4i32 = 535,
|
|
VABALsv8i16 = 536,
|
|
VABALuv2i64 = 537,
|
|
VABALuv4i32 = 538,
|
|
VABALuv8i16 = 539,
|
|
VABAsv16i8 = 540,
|
|
VABAsv2i32 = 541,
|
|
VABAsv4i16 = 542,
|
|
VABAsv4i32 = 543,
|
|
VABAsv8i16 = 544,
|
|
VABAsv8i8 = 545,
|
|
VABAuv16i8 = 546,
|
|
VABAuv2i32 = 547,
|
|
VABAuv4i16 = 548,
|
|
VABAuv4i32 = 549,
|
|
VABAuv8i16 = 550,
|
|
VABAuv8i8 = 551,
|
|
VABDLsv2i64 = 552,
|
|
VABDLsv4i32 = 553,
|
|
VABDLsv8i16 = 554,
|
|
VABDLuv2i64 = 555,
|
|
VABDLuv4i32 = 556,
|
|
VABDLuv8i16 = 557,
|
|
VABDfd = 558,
|
|
VABDfq = 559,
|
|
VABDhd = 560,
|
|
VABDhq = 561,
|
|
VABDsv16i8 = 562,
|
|
VABDsv2i32 = 563,
|
|
VABDsv4i16 = 564,
|
|
VABDsv4i32 = 565,
|
|
VABDsv8i16 = 566,
|
|
VABDsv8i8 = 567,
|
|
VABDuv16i8 = 568,
|
|
VABDuv2i32 = 569,
|
|
VABDuv4i16 = 570,
|
|
VABDuv4i32 = 571,
|
|
VABDuv8i16 = 572,
|
|
VABDuv8i8 = 573,
|
|
VABSD = 574,
|
|
VABSH = 575,
|
|
VABSS = 576,
|
|
VABSfd = 577,
|
|
VABSfq = 578,
|
|
VABShd = 579,
|
|
VABShq = 580,
|
|
VABSv16i8 = 581,
|
|
VABSv2i32 = 582,
|
|
VABSv4i16 = 583,
|
|
VABSv4i32 = 584,
|
|
VABSv8i16 = 585,
|
|
VABSv8i8 = 586,
|
|
VACGEfd = 587,
|
|
VACGEfq = 588,
|
|
VACGEhd = 589,
|
|
VACGEhq = 590,
|
|
VACGTfd = 591,
|
|
VACGTfq = 592,
|
|
VACGThd = 593,
|
|
VACGThq = 594,
|
|
VADDD = 595,
|
|
VADDH = 596,
|
|
VADDHNv2i32 = 597,
|
|
VADDHNv4i16 = 598,
|
|
VADDHNv8i8 = 599,
|
|
VADDLsv2i64 = 600,
|
|
VADDLsv4i32 = 601,
|
|
VADDLsv8i16 = 602,
|
|
VADDLuv2i64 = 603,
|
|
VADDLuv4i32 = 604,
|
|
VADDLuv8i16 = 605,
|
|
VADDS = 606,
|
|
VADDWsv2i64 = 607,
|
|
VADDWsv4i32 = 608,
|
|
VADDWsv8i16 = 609,
|
|
VADDWuv2i64 = 610,
|
|
VADDWuv4i32 = 611,
|
|
VADDWuv8i16 = 612,
|
|
VADDfd = 613,
|
|
VADDfq = 614,
|
|
VADDhd = 615,
|
|
VADDhq = 616,
|
|
VADDv16i8 = 617,
|
|
VADDv1i64 = 618,
|
|
VADDv2i32 = 619,
|
|
VADDv2i64 = 620,
|
|
VADDv4i16 = 621,
|
|
VADDv4i32 = 622,
|
|
VADDv8i16 = 623,
|
|
VADDv8i8 = 624,
|
|
VANDd = 625,
|
|
VANDq = 626,
|
|
VBICd = 627,
|
|
VBICiv2i32 = 628,
|
|
VBICiv4i16 = 629,
|
|
VBICiv4i32 = 630,
|
|
VBICiv8i16 = 631,
|
|
VBICq = 632,
|
|
VBIFd = 633,
|
|
VBIFq = 634,
|
|
VBITd = 635,
|
|
VBITq = 636,
|
|
VBSLd = 637,
|
|
VBSLq = 638,
|
|
VCEQfd = 639,
|
|
VCEQfq = 640,
|
|
VCEQhd = 641,
|
|
VCEQhq = 642,
|
|
VCEQv16i8 = 643,
|
|
VCEQv2i32 = 644,
|
|
VCEQv4i16 = 645,
|
|
VCEQv4i32 = 646,
|
|
VCEQv8i16 = 647,
|
|
VCEQv8i8 = 648,
|
|
VCEQzv16i8 = 649,
|
|
VCEQzv2f32 = 650,
|
|
VCEQzv2i32 = 651,
|
|
VCEQzv4f16 = 652,
|
|
VCEQzv4f32 = 653,
|
|
VCEQzv4i16 = 654,
|
|
VCEQzv4i32 = 655,
|
|
VCEQzv8f16 = 656,
|
|
VCEQzv8i16 = 657,
|
|
VCEQzv8i8 = 658,
|
|
VCGEfd = 659,
|
|
VCGEfq = 660,
|
|
VCGEhd = 661,
|
|
VCGEhq = 662,
|
|
VCGEsv16i8 = 663,
|
|
VCGEsv2i32 = 664,
|
|
VCGEsv4i16 = 665,
|
|
VCGEsv4i32 = 666,
|
|
VCGEsv8i16 = 667,
|
|
VCGEsv8i8 = 668,
|
|
VCGEuv16i8 = 669,
|
|
VCGEuv2i32 = 670,
|
|
VCGEuv4i16 = 671,
|
|
VCGEuv4i32 = 672,
|
|
VCGEuv8i16 = 673,
|
|
VCGEuv8i8 = 674,
|
|
VCGEzv16i8 = 675,
|
|
VCGEzv2f32 = 676,
|
|
VCGEzv2i32 = 677,
|
|
VCGEzv4f16 = 678,
|
|
VCGEzv4f32 = 679,
|
|
VCGEzv4i16 = 680,
|
|
VCGEzv4i32 = 681,
|
|
VCGEzv8f16 = 682,
|
|
VCGEzv8i16 = 683,
|
|
VCGEzv8i8 = 684,
|
|
VCGTfd = 685,
|
|
VCGTfq = 686,
|
|
VCGThd = 687,
|
|
VCGThq = 688,
|
|
VCGTsv16i8 = 689,
|
|
VCGTsv2i32 = 690,
|
|
VCGTsv4i16 = 691,
|
|
VCGTsv4i32 = 692,
|
|
VCGTsv8i16 = 693,
|
|
VCGTsv8i8 = 694,
|
|
VCGTuv16i8 = 695,
|
|
VCGTuv2i32 = 696,
|
|
VCGTuv4i16 = 697,
|
|
VCGTuv4i32 = 698,
|
|
VCGTuv8i16 = 699,
|
|
VCGTuv8i8 = 700,
|
|
VCGTzv16i8 = 701,
|
|
VCGTzv2f32 = 702,
|
|
VCGTzv2i32 = 703,
|
|
VCGTzv4f16 = 704,
|
|
VCGTzv4f32 = 705,
|
|
VCGTzv4i16 = 706,
|
|
VCGTzv4i32 = 707,
|
|
VCGTzv8f16 = 708,
|
|
VCGTzv8i16 = 709,
|
|
VCGTzv8i8 = 710,
|
|
VCLEzv16i8 = 711,
|
|
VCLEzv2f32 = 712,
|
|
VCLEzv2i32 = 713,
|
|
VCLEzv4f16 = 714,
|
|
VCLEzv4f32 = 715,
|
|
VCLEzv4i16 = 716,
|
|
VCLEzv4i32 = 717,
|
|
VCLEzv8f16 = 718,
|
|
VCLEzv8i16 = 719,
|
|
VCLEzv8i8 = 720,
|
|
VCLSv16i8 = 721,
|
|
VCLSv2i32 = 722,
|
|
VCLSv4i16 = 723,
|
|
VCLSv4i32 = 724,
|
|
VCLSv8i16 = 725,
|
|
VCLSv8i8 = 726,
|
|
VCLTzv16i8 = 727,
|
|
VCLTzv2f32 = 728,
|
|
VCLTzv2i32 = 729,
|
|
VCLTzv4f16 = 730,
|
|
VCLTzv4f32 = 731,
|
|
VCLTzv4i16 = 732,
|
|
VCLTzv4i32 = 733,
|
|
VCLTzv8f16 = 734,
|
|
VCLTzv8i16 = 735,
|
|
VCLTzv8i8 = 736,
|
|
VCLZv16i8 = 737,
|
|
VCLZv2i32 = 738,
|
|
VCLZv4i16 = 739,
|
|
VCLZv4i32 = 740,
|
|
VCLZv8i16 = 741,
|
|
VCLZv8i8 = 742,
|
|
VCMPD = 743,
|
|
VCMPED = 744,
|
|
VCMPEH = 745,
|
|
VCMPES = 746,
|
|
VCMPEZD = 747,
|
|
VCMPEZH = 748,
|
|
VCMPEZS = 749,
|
|
VCMPH = 750,
|
|
VCMPS = 751,
|
|
VCMPZD = 752,
|
|
VCMPZH = 753,
|
|
VCMPZS = 754,
|
|
VCNTd = 755,
|
|
VCNTq = 756,
|
|
VCVTANSDf = 757,
|
|
VCVTANSDh = 758,
|
|
VCVTANSQf = 759,
|
|
VCVTANSQh = 760,
|
|
VCVTANUDf = 761,
|
|
VCVTANUDh = 762,
|
|
VCVTANUQf = 763,
|
|
VCVTANUQh = 764,
|
|
VCVTASD = 765,
|
|
VCVTASH = 766,
|
|
VCVTASS = 767,
|
|
VCVTAUD = 768,
|
|
VCVTAUH = 769,
|
|
VCVTAUS = 770,
|
|
VCVTBDH = 771,
|
|
VCVTBHD = 772,
|
|
VCVTBHS = 773,
|
|
VCVTBSH = 774,
|
|
VCVTDS = 775,
|
|
VCVTMNSDf = 776,
|
|
VCVTMNSDh = 777,
|
|
VCVTMNSQf = 778,
|
|
VCVTMNSQh = 779,
|
|
VCVTMNUDf = 780,
|
|
VCVTMNUDh = 781,
|
|
VCVTMNUQf = 782,
|
|
VCVTMNUQh = 783,
|
|
VCVTMSD = 784,
|
|
VCVTMSH = 785,
|
|
VCVTMSS = 786,
|
|
VCVTMUD = 787,
|
|
VCVTMUH = 788,
|
|
VCVTMUS = 789,
|
|
VCVTNNSDf = 790,
|
|
VCVTNNSDh = 791,
|
|
VCVTNNSQf = 792,
|
|
VCVTNNSQh = 793,
|
|
VCVTNNUDf = 794,
|
|
VCVTNNUDh = 795,
|
|
VCVTNNUQf = 796,
|
|
VCVTNNUQh = 797,
|
|
VCVTNSD = 798,
|
|
VCVTNSH = 799,
|
|
VCVTNSS = 800,
|
|
VCVTNUD = 801,
|
|
VCVTNUH = 802,
|
|
VCVTNUS = 803,
|
|
VCVTPNSDf = 804,
|
|
VCVTPNSDh = 805,
|
|
VCVTPNSQf = 806,
|
|
VCVTPNSQh = 807,
|
|
VCVTPNUDf = 808,
|
|
VCVTPNUDh = 809,
|
|
VCVTPNUQf = 810,
|
|
VCVTPNUQh = 811,
|
|
VCVTPSD = 812,
|
|
VCVTPSH = 813,
|
|
VCVTPSS = 814,
|
|
VCVTPUD = 815,
|
|
VCVTPUH = 816,
|
|
VCVTPUS = 817,
|
|
VCVTSD = 818,
|
|
VCVTTDH = 819,
|
|
VCVTTHD = 820,
|
|
VCVTTHS = 821,
|
|
VCVTTSH = 822,
|
|
VCVTf2h = 823,
|
|
VCVTf2sd = 824,
|
|
VCVTf2sq = 825,
|
|
VCVTf2ud = 826,
|
|
VCVTf2uq = 827,
|
|
VCVTf2xsd = 828,
|
|
VCVTf2xsq = 829,
|
|
VCVTf2xud = 830,
|
|
VCVTf2xuq = 831,
|
|
VCVTh2f = 832,
|
|
VCVTh2sd = 833,
|
|
VCVTh2sq = 834,
|
|
VCVTh2ud = 835,
|
|
VCVTh2uq = 836,
|
|
VCVTh2xsd = 837,
|
|
VCVTh2xsq = 838,
|
|
VCVTh2xud = 839,
|
|
VCVTh2xuq = 840,
|
|
VCVTs2fd = 841,
|
|
VCVTs2fq = 842,
|
|
VCVTs2hd = 843,
|
|
VCVTs2hq = 844,
|
|
VCVTu2fd = 845,
|
|
VCVTu2fq = 846,
|
|
VCVTu2hd = 847,
|
|
VCVTu2hq = 848,
|
|
VCVTxs2fd = 849,
|
|
VCVTxs2fq = 850,
|
|
VCVTxs2hd = 851,
|
|
VCVTxs2hq = 852,
|
|
VCVTxu2fd = 853,
|
|
VCVTxu2fq = 854,
|
|
VCVTxu2hd = 855,
|
|
VCVTxu2hq = 856,
|
|
VDIVD = 857,
|
|
VDIVH = 858,
|
|
VDIVS = 859,
|
|
VDUP16d = 860,
|
|
VDUP16q = 861,
|
|
VDUP32d = 862,
|
|
VDUP32q = 863,
|
|
VDUP8d = 864,
|
|
VDUP8q = 865,
|
|
VDUPLN16d = 866,
|
|
VDUPLN16q = 867,
|
|
VDUPLN32d = 868,
|
|
VDUPLN32q = 869,
|
|
VDUPLN8d = 870,
|
|
VDUPLN8q = 871,
|
|
VEORd = 872,
|
|
VEORq = 873,
|
|
VEXTd16 = 874,
|
|
VEXTd32 = 875,
|
|
VEXTd8 = 876,
|
|
VEXTq16 = 877,
|
|
VEXTq32 = 878,
|
|
VEXTq64 = 879,
|
|
VEXTq8 = 880,
|
|
VFMAD = 881,
|
|
VFMAH = 882,
|
|
VFMAS = 883,
|
|
VFMAfd = 884,
|
|
VFMAfq = 885,
|
|
VFMAhd = 886,
|
|
VFMAhq = 887,
|
|
VFMSD = 888,
|
|
VFMSH = 889,
|
|
VFMSS = 890,
|
|
VFMSfd = 891,
|
|
VFMSfq = 892,
|
|
VFMShd = 893,
|
|
VFMShq = 894,
|
|
VFNMAD = 895,
|
|
VFNMAH = 896,
|
|
VFNMAS = 897,
|
|
VFNMSD = 898,
|
|
VFNMSH = 899,
|
|
VFNMSS = 900,
|
|
VGETLNi32 = 901,
|
|
VGETLNs16 = 902,
|
|
VGETLNs8 = 903,
|
|
VGETLNu16 = 904,
|
|
VGETLNu8 = 905,
|
|
VHADDsv16i8 = 906,
|
|
VHADDsv2i32 = 907,
|
|
VHADDsv4i16 = 908,
|
|
VHADDsv4i32 = 909,
|
|
VHADDsv8i16 = 910,
|
|
VHADDsv8i8 = 911,
|
|
VHADDuv16i8 = 912,
|
|
VHADDuv2i32 = 913,
|
|
VHADDuv4i16 = 914,
|
|
VHADDuv4i32 = 915,
|
|
VHADDuv8i16 = 916,
|
|
VHADDuv8i8 = 917,
|
|
VHSUBsv16i8 = 918,
|
|
VHSUBsv2i32 = 919,
|
|
VHSUBsv4i16 = 920,
|
|
VHSUBsv4i32 = 921,
|
|
VHSUBsv8i16 = 922,
|
|
VHSUBsv8i8 = 923,
|
|
VHSUBuv16i8 = 924,
|
|
VHSUBuv2i32 = 925,
|
|
VHSUBuv4i16 = 926,
|
|
VHSUBuv4i32 = 927,
|
|
VHSUBuv8i16 = 928,
|
|
VHSUBuv8i8 = 929,
|
|
VINSH = 930,
|
|
VLD1DUPd16 = 931,
|
|
VLD1DUPd16wb_fixed = 932,
|
|
VLD1DUPd16wb_register = 933,
|
|
VLD1DUPd32 = 934,
|
|
VLD1DUPd32wb_fixed = 935,
|
|
VLD1DUPd32wb_register = 936,
|
|
VLD1DUPd8 = 937,
|
|
VLD1DUPd8wb_fixed = 938,
|
|
VLD1DUPd8wb_register = 939,
|
|
VLD1DUPq16 = 940,
|
|
VLD1DUPq16wb_fixed = 941,
|
|
VLD1DUPq16wb_register = 942,
|
|
VLD1DUPq32 = 943,
|
|
VLD1DUPq32wb_fixed = 944,
|
|
VLD1DUPq32wb_register = 945,
|
|
VLD1DUPq8 = 946,
|
|
VLD1DUPq8wb_fixed = 947,
|
|
VLD1DUPq8wb_register = 948,
|
|
VLD1LNd16 = 949,
|
|
VLD1LNd16_UPD = 950,
|
|
VLD1LNd32 = 951,
|
|
VLD1LNd32_UPD = 952,
|
|
VLD1LNd8 = 953,
|
|
VLD1LNd8_UPD = 954,
|
|
VLD1LNdAsm_16 = 955,
|
|
VLD1LNdAsm_32 = 956,
|
|
VLD1LNdAsm_8 = 957,
|
|
VLD1LNdWB_fixed_Asm_16 = 958,
|
|
VLD1LNdWB_fixed_Asm_32 = 959,
|
|
VLD1LNdWB_fixed_Asm_8 = 960,
|
|
VLD1LNdWB_register_Asm_16 = 961,
|
|
VLD1LNdWB_register_Asm_32 = 962,
|
|
VLD1LNdWB_register_Asm_8 = 963,
|
|
VLD1LNq16Pseudo = 964,
|
|
VLD1LNq16Pseudo_UPD = 965,
|
|
VLD1LNq32Pseudo = 966,
|
|
VLD1LNq32Pseudo_UPD = 967,
|
|
VLD1LNq8Pseudo = 968,
|
|
VLD1LNq8Pseudo_UPD = 969,
|
|
VLD1d16 = 970,
|
|
VLD1d16Q = 971,
|
|
VLD1d16Qwb_fixed = 972,
|
|
VLD1d16Qwb_register = 973,
|
|
VLD1d16T = 974,
|
|
VLD1d16Twb_fixed = 975,
|
|
VLD1d16Twb_register = 976,
|
|
VLD1d16wb_fixed = 977,
|
|
VLD1d16wb_register = 978,
|
|
VLD1d32 = 979,
|
|
VLD1d32Q = 980,
|
|
VLD1d32Qwb_fixed = 981,
|
|
VLD1d32Qwb_register = 982,
|
|
VLD1d32T = 983,
|
|
VLD1d32Twb_fixed = 984,
|
|
VLD1d32Twb_register = 985,
|
|
VLD1d32wb_fixed = 986,
|
|
VLD1d32wb_register = 987,
|
|
VLD1d64 = 988,
|
|
VLD1d64Q = 989,
|
|
VLD1d64QPseudo = 990,
|
|
VLD1d64QPseudoWB_fixed = 991,
|
|
VLD1d64QPseudoWB_register = 992,
|
|
VLD1d64Qwb_fixed = 993,
|
|
VLD1d64Qwb_register = 994,
|
|
VLD1d64T = 995,
|
|
VLD1d64TPseudo = 996,
|
|
VLD1d64TPseudoWB_fixed = 997,
|
|
VLD1d64TPseudoWB_register = 998,
|
|
VLD1d64Twb_fixed = 999,
|
|
VLD1d64Twb_register = 1000,
|
|
VLD1d64wb_fixed = 1001,
|
|
VLD1d64wb_register = 1002,
|
|
VLD1d8 = 1003,
|
|
VLD1d8Q = 1004,
|
|
VLD1d8Qwb_fixed = 1005,
|
|
VLD1d8Qwb_register = 1006,
|
|
VLD1d8T = 1007,
|
|
VLD1d8Twb_fixed = 1008,
|
|
VLD1d8Twb_register = 1009,
|
|
VLD1d8wb_fixed = 1010,
|
|
VLD1d8wb_register = 1011,
|
|
VLD1q16 = 1012,
|
|
VLD1q16wb_fixed = 1013,
|
|
VLD1q16wb_register = 1014,
|
|
VLD1q32 = 1015,
|
|
VLD1q32wb_fixed = 1016,
|
|
VLD1q32wb_register = 1017,
|
|
VLD1q64 = 1018,
|
|
VLD1q64wb_fixed = 1019,
|
|
VLD1q64wb_register = 1020,
|
|
VLD1q8 = 1021,
|
|
VLD1q8wb_fixed = 1022,
|
|
VLD1q8wb_register = 1023,
|
|
VLD2DUPd16 = 1024,
|
|
VLD2DUPd16wb_fixed = 1025,
|
|
VLD2DUPd16wb_register = 1026,
|
|
VLD2DUPd16x2 = 1027,
|
|
VLD2DUPd16x2wb_fixed = 1028,
|
|
VLD2DUPd16x2wb_register = 1029,
|
|
VLD2DUPd32 = 1030,
|
|
VLD2DUPd32wb_fixed = 1031,
|
|
VLD2DUPd32wb_register = 1032,
|
|
VLD2DUPd32x2 = 1033,
|
|
VLD2DUPd32x2wb_fixed = 1034,
|
|
VLD2DUPd32x2wb_register = 1035,
|
|
VLD2DUPd8 = 1036,
|
|
VLD2DUPd8wb_fixed = 1037,
|
|
VLD2DUPd8wb_register = 1038,
|
|
VLD2DUPd8x2 = 1039,
|
|
VLD2DUPd8x2wb_fixed = 1040,
|
|
VLD2DUPd8x2wb_register = 1041,
|
|
VLD2LNd16 = 1042,
|
|
VLD2LNd16Pseudo = 1043,
|
|
VLD2LNd16Pseudo_UPD = 1044,
|
|
VLD2LNd16_UPD = 1045,
|
|
VLD2LNd32 = 1046,
|
|
VLD2LNd32Pseudo = 1047,
|
|
VLD2LNd32Pseudo_UPD = 1048,
|
|
VLD2LNd32_UPD = 1049,
|
|
VLD2LNd8 = 1050,
|
|
VLD2LNd8Pseudo = 1051,
|
|
VLD2LNd8Pseudo_UPD = 1052,
|
|
VLD2LNd8_UPD = 1053,
|
|
VLD2LNdAsm_16 = 1054,
|
|
VLD2LNdAsm_32 = 1055,
|
|
VLD2LNdAsm_8 = 1056,
|
|
VLD2LNdWB_fixed_Asm_16 = 1057,
|
|
VLD2LNdWB_fixed_Asm_32 = 1058,
|
|
VLD2LNdWB_fixed_Asm_8 = 1059,
|
|
VLD2LNdWB_register_Asm_16 = 1060,
|
|
VLD2LNdWB_register_Asm_32 = 1061,
|
|
VLD2LNdWB_register_Asm_8 = 1062,
|
|
VLD2LNq16 = 1063,
|
|
VLD2LNq16Pseudo = 1064,
|
|
VLD2LNq16Pseudo_UPD = 1065,
|
|
VLD2LNq16_UPD = 1066,
|
|
VLD2LNq32 = 1067,
|
|
VLD2LNq32Pseudo = 1068,
|
|
VLD2LNq32Pseudo_UPD = 1069,
|
|
VLD2LNq32_UPD = 1070,
|
|
VLD2LNqAsm_16 = 1071,
|
|
VLD2LNqAsm_32 = 1072,
|
|
VLD2LNqWB_fixed_Asm_16 = 1073,
|
|
VLD2LNqWB_fixed_Asm_32 = 1074,
|
|
VLD2LNqWB_register_Asm_16 = 1075,
|
|
VLD2LNqWB_register_Asm_32 = 1076,
|
|
VLD2b16 = 1077,
|
|
VLD2b16wb_fixed = 1078,
|
|
VLD2b16wb_register = 1079,
|
|
VLD2b32 = 1080,
|
|
VLD2b32wb_fixed = 1081,
|
|
VLD2b32wb_register = 1082,
|
|
VLD2b8 = 1083,
|
|
VLD2b8wb_fixed = 1084,
|
|
VLD2b8wb_register = 1085,
|
|
VLD2d16 = 1086,
|
|
VLD2d16wb_fixed = 1087,
|
|
VLD2d16wb_register = 1088,
|
|
VLD2d32 = 1089,
|
|
VLD2d32wb_fixed = 1090,
|
|
VLD2d32wb_register = 1091,
|
|
VLD2d8 = 1092,
|
|
VLD2d8wb_fixed = 1093,
|
|
VLD2d8wb_register = 1094,
|
|
VLD2q16 = 1095,
|
|
VLD2q16Pseudo = 1096,
|
|
VLD2q16PseudoWB_fixed = 1097,
|
|
VLD2q16PseudoWB_register = 1098,
|
|
VLD2q16wb_fixed = 1099,
|
|
VLD2q16wb_register = 1100,
|
|
VLD2q32 = 1101,
|
|
VLD2q32Pseudo = 1102,
|
|
VLD2q32PseudoWB_fixed = 1103,
|
|
VLD2q32PseudoWB_register = 1104,
|
|
VLD2q32wb_fixed = 1105,
|
|
VLD2q32wb_register = 1106,
|
|
VLD2q8 = 1107,
|
|
VLD2q8Pseudo = 1108,
|
|
VLD2q8PseudoWB_fixed = 1109,
|
|
VLD2q8PseudoWB_register = 1110,
|
|
VLD2q8wb_fixed = 1111,
|
|
VLD2q8wb_register = 1112,
|
|
VLD3DUPd16 = 1113,
|
|
VLD3DUPd16Pseudo = 1114,
|
|
VLD3DUPd16Pseudo_UPD = 1115,
|
|
VLD3DUPd16_UPD = 1116,
|
|
VLD3DUPd32 = 1117,
|
|
VLD3DUPd32Pseudo = 1118,
|
|
VLD3DUPd32Pseudo_UPD = 1119,
|
|
VLD3DUPd32_UPD = 1120,
|
|
VLD3DUPd8 = 1121,
|
|
VLD3DUPd8Pseudo = 1122,
|
|
VLD3DUPd8Pseudo_UPD = 1123,
|
|
VLD3DUPd8_UPD = 1124,
|
|
VLD3DUPdAsm_16 = 1125,
|
|
VLD3DUPdAsm_32 = 1126,
|
|
VLD3DUPdAsm_8 = 1127,
|
|
VLD3DUPdWB_fixed_Asm_16 = 1128,
|
|
VLD3DUPdWB_fixed_Asm_32 = 1129,
|
|
VLD3DUPdWB_fixed_Asm_8 = 1130,
|
|
VLD3DUPdWB_register_Asm_16 = 1131,
|
|
VLD3DUPdWB_register_Asm_32 = 1132,
|
|
VLD3DUPdWB_register_Asm_8 = 1133,
|
|
VLD3DUPq16 = 1134,
|
|
VLD3DUPq16_UPD = 1135,
|
|
VLD3DUPq32 = 1136,
|
|
VLD3DUPq32_UPD = 1137,
|
|
VLD3DUPq8 = 1138,
|
|
VLD3DUPq8_UPD = 1139,
|
|
VLD3DUPqAsm_16 = 1140,
|
|
VLD3DUPqAsm_32 = 1141,
|
|
VLD3DUPqAsm_8 = 1142,
|
|
VLD3DUPqWB_fixed_Asm_16 = 1143,
|
|
VLD3DUPqWB_fixed_Asm_32 = 1144,
|
|
VLD3DUPqWB_fixed_Asm_8 = 1145,
|
|
VLD3DUPqWB_register_Asm_16 = 1146,
|
|
VLD3DUPqWB_register_Asm_32 = 1147,
|
|
VLD3DUPqWB_register_Asm_8 = 1148,
|
|
VLD3LNd16 = 1149,
|
|
VLD3LNd16Pseudo = 1150,
|
|
VLD3LNd16Pseudo_UPD = 1151,
|
|
VLD3LNd16_UPD = 1152,
|
|
VLD3LNd32 = 1153,
|
|
VLD3LNd32Pseudo = 1154,
|
|
VLD3LNd32Pseudo_UPD = 1155,
|
|
VLD3LNd32_UPD = 1156,
|
|
VLD3LNd8 = 1157,
|
|
VLD3LNd8Pseudo = 1158,
|
|
VLD3LNd8Pseudo_UPD = 1159,
|
|
VLD3LNd8_UPD = 1160,
|
|
VLD3LNdAsm_16 = 1161,
|
|
VLD3LNdAsm_32 = 1162,
|
|
VLD3LNdAsm_8 = 1163,
|
|
VLD3LNdWB_fixed_Asm_16 = 1164,
|
|
VLD3LNdWB_fixed_Asm_32 = 1165,
|
|
VLD3LNdWB_fixed_Asm_8 = 1166,
|
|
VLD3LNdWB_register_Asm_16 = 1167,
|
|
VLD3LNdWB_register_Asm_32 = 1168,
|
|
VLD3LNdWB_register_Asm_8 = 1169,
|
|
VLD3LNq16 = 1170,
|
|
VLD3LNq16Pseudo = 1171,
|
|
VLD3LNq16Pseudo_UPD = 1172,
|
|
VLD3LNq16_UPD = 1173,
|
|
VLD3LNq32 = 1174,
|
|
VLD3LNq32Pseudo = 1175,
|
|
VLD3LNq32Pseudo_UPD = 1176,
|
|
VLD3LNq32_UPD = 1177,
|
|
VLD3LNqAsm_16 = 1178,
|
|
VLD3LNqAsm_32 = 1179,
|
|
VLD3LNqWB_fixed_Asm_16 = 1180,
|
|
VLD3LNqWB_fixed_Asm_32 = 1181,
|
|
VLD3LNqWB_register_Asm_16 = 1182,
|
|
VLD3LNqWB_register_Asm_32 = 1183,
|
|
VLD3d16 = 1184,
|
|
VLD3d16Pseudo = 1185,
|
|
VLD3d16Pseudo_UPD = 1186,
|
|
VLD3d16_UPD = 1187,
|
|
VLD3d32 = 1188,
|
|
VLD3d32Pseudo = 1189,
|
|
VLD3d32Pseudo_UPD = 1190,
|
|
VLD3d32_UPD = 1191,
|
|
VLD3d8 = 1192,
|
|
VLD3d8Pseudo = 1193,
|
|
VLD3d8Pseudo_UPD = 1194,
|
|
VLD3d8_UPD = 1195,
|
|
VLD3dAsm_16 = 1196,
|
|
VLD3dAsm_32 = 1197,
|
|
VLD3dAsm_8 = 1198,
|
|
VLD3dWB_fixed_Asm_16 = 1199,
|
|
VLD3dWB_fixed_Asm_32 = 1200,
|
|
VLD3dWB_fixed_Asm_8 = 1201,
|
|
VLD3dWB_register_Asm_16 = 1202,
|
|
VLD3dWB_register_Asm_32 = 1203,
|
|
VLD3dWB_register_Asm_8 = 1204,
|
|
VLD3q16 = 1205,
|
|
VLD3q16Pseudo_UPD = 1206,
|
|
VLD3q16_UPD = 1207,
|
|
VLD3q16oddPseudo = 1208,
|
|
VLD3q16oddPseudo_UPD = 1209,
|
|
VLD3q32 = 1210,
|
|
VLD3q32Pseudo_UPD = 1211,
|
|
VLD3q32_UPD = 1212,
|
|
VLD3q32oddPseudo = 1213,
|
|
VLD3q32oddPseudo_UPD = 1214,
|
|
VLD3q8 = 1215,
|
|
VLD3q8Pseudo_UPD = 1216,
|
|
VLD3q8_UPD = 1217,
|
|
VLD3q8oddPseudo = 1218,
|
|
VLD3q8oddPseudo_UPD = 1219,
|
|
VLD3qAsm_16 = 1220,
|
|
VLD3qAsm_32 = 1221,
|
|
VLD3qAsm_8 = 1222,
|
|
VLD3qWB_fixed_Asm_16 = 1223,
|
|
VLD3qWB_fixed_Asm_32 = 1224,
|
|
VLD3qWB_fixed_Asm_8 = 1225,
|
|
VLD3qWB_register_Asm_16 = 1226,
|
|
VLD3qWB_register_Asm_32 = 1227,
|
|
VLD3qWB_register_Asm_8 = 1228,
|
|
VLD4DUPd16 = 1229,
|
|
VLD4DUPd16Pseudo = 1230,
|
|
VLD4DUPd16Pseudo_UPD = 1231,
|
|
VLD4DUPd16_UPD = 1232,
|
|
VLD4DUPd32 = 1233,
|
|
VLD4DUPd32Pseudo = 1234,
|
|
VLD4DUPd32Pseudo_UPD = 1235,
|
|
VLD4DUPd32_UPD = 1236,
|
|
VLD4DUPd8 = 1237,
|
|
VLD4DUPd8Pseudo = 1238,
|
|
VLD4DUPd8Pseudo_UPD = 1239,
|
|
VLD4DUPd8_UPD = 1240,
|
|
VLD4DUPdAsm_16 = 1241,
|
|
VLD4DUPdAsm_32 = 1242,
|
|
VLD4DUPdAsm_8 = 1243,
|
|
VLD4DUPdWB_fixed_Asm_16 = 1244,
|
|
VLD4DUPdWB_fixed_Asm_32 = 1245,
|
|
VLD4DUPdWB_fixed_Asm_8 = 1246,
|
|
VLD4DUPdWB_register_Asm_16 = 1247,
|
|
VLD4DUPdWB_register_Asm_32 = 1248,
|
|
VLD4DUPdWB_register_Asm_8 = 1249,
|
|
VLD4DUPq16 = 1250,
|
|
VLD4DUPq16_UPD = 1251,
|
|
VLD4DUPq32 = 1252,
|
|
VLD4DUPq32_UPD = 1253,
|
|
VLD4DUPq8 = 1254,
|
|
VLD4DUPq8_UPD = 1255,
|
|
VLD4DUPqAsm_16 = 1256,
|
|
VLD4DUPqAsm_32 = 1257,
|
|
VLD4DUPqAsm_8 = 1258,
|
|
VLD4DUPqWB_fixed_Asm_16 = 1259,
|
|
VLD4DUPqWB_fixed_Asm_32 = 1260,
|
|
VLD4DUPqWB_fixed_Asm_8 = 1261,
|
|
VLD4DUPqWB_register_Asm_16 = 1262,
|
|
VLD4DUPqWB_register_Asm_32 = 1263,
|
|
VLD4DUPqWB_register_Asm_8 = 1264,
|
|
VLD4LNd16 = 1265,
|
|
VLD4LNd16Pseudo = 1266,
|
|
VLD4LNd16Pseudo_UPD = 1267,
|
|
VLD4LNd16_UPD = 1268,
|
|
VLD4LNd32 = 1269,
|
|
VLD4LNd32Pseudo = 1270,
|
|
VLD4LNd32Pseudo_UPD = 1271,
|
|
VLD4LNd32_UPD = 1272,
|
|
VLD4LNd8 = 1273,
|
|
VLD4LNd8Pseudo = 1274,
|
|
VLD4LNd8Pseudo_UPD = 1275,
|
|
VLD4LNd8_UPD = 1276,
|
|
VLD4LNdAsm_16 = 1277,
|
|
VLD4LNdAsm_32 = 1278,
|
|
VLD4LNdAsm_8 = 1279,
|
|
VLD4LNdWB_fixed_Asm_16 = 1280,
|
|
VLD4LNdWB_fixed_Asm_32 = 1281,
|
|
VLD4LNdWB_fixed_Asm_8 = 1282,
|
|
VLD4LNdWB_register_Asm_16 = 1283,
|
|
VLD4LNdWB_register_Asm_32 = 1284,
|
|
VLD4LNdWB_register_Asm_8 = 1285,
|
|
VLD4LNq16 = 1286,
|
|
VLD4LNq16Pseudo = 1287,
|
|
VLD4LNq16Pseudo_UPD = 1288,
|
|
VLD4LNq16_UPD = 1289,
|
|
VLD4LNq32 = 1290,
|
|
VLD4LNq32Pseudo = 1291,
|
|
VLD4LNq32Pseudo_UPD = 1292,
|
|
VLD4LNq32_UPD = 1293,
|
|
VLD4LNqAsm_16 = 1294,
|
|
VLD4LNqAsm_32 = 1295,
|
|
VLD4LNqWB_fixed_Asm_16 = 1296,
|
|
VLD4LNqWB_fixed_Asm_32 = 1297,
|
|
VLD4LNqWB_register_Asm_16 = 1298,
|
|
VLD4LNqWB_register_Asm_32 = 1299,
|
|
VLD4d16 = 1300,
|
|
VLD4d16Pseudo = 1301,
|
|
VLD4d16Pseudo_UPD = 1302,
|
|
VLD4d16_UPD = 1303,
|
|
VLD4d32 = 1304,
|
|
VLD4d32Pseudo = 1305,
|
|
VLD4d32Pseudo_UPD = 1306,
|
|
VLD4d32_UPD = 1307,
|
|
VLD4d8 = 1308,
|
|
VLD4d8Pseudo = 1309,
|
|
VLD4d8Pseudo_UPD = 1310,
|
|
VLD4d8_UPD = 1311,
|
|
VLD4dAsm_16 = 1312,
|
|
VLD4dAsm_32 = 1313,
|
|
VLD4dAsm_8 = 1314,
|
|
VLD4dWB_fixed_Asm_16 = 1315,
|
|
VLD4dWB_fixed_Asm_32 = 1316,
|
|
VLD4dWB_fixed_Asm_8 = 1317,
|
|
VLD4dWB_register_Asm_16 = 1318,
|
|
VLD4dWB_register_Asm_32 = 1319,
|
|
VLD4dWB_register_Asm_8 = 1320,
|
|
VLD4q16 = 1321,
|
|
VLD4q16Pseudo_UPD = 1322,
|
|
VLD4q16_UPD = 1323,
|
|
VLD4q16oddPseudo = 1324,
|
|
VLD4q16oddPseudo_UPD = 1325,
|
|
VLD4q32 = 1326,
|
|
VLD4q32Pseudo_UPD = 1327,
|
|
VLD4q32_UPD = 1328,
|
|
VLD4q32oddPseudo = 1329,
|
|
VLD4q32oddPseudo_UPD = 1330,
|
|
VLD4q8 = 1331,
|
|
VLD4q8Pseudo_UPD = 1332,
|
|
VLD4q8_UPD = 1333,
|
|
VLD4q8oddPseudo = 1334,
|
|
VLD4q8oddPseudo_UPD = 1335,
|
|
VLD4qAsm_16 = 1336,
|
|
VLD4qAsm_32 = 1337,
|
|
VLD4qAsm_8 = 1338,
|
|
VLD4qWB_fixed_Asm_16 = 1339,
|
|
VLD4qWB_fixed_Asm_32 = 1340,
|
|
VLD4qWB_fixed_Asm_8 = 1341,
|
|
VLD4qWB_register_Asm_16 = 1342,
|
|
VLD4qWB_register_Asm_32 = 1343,
|
|
VLD4qWB_register_Asm_8 = 1344,
|
|
VLDMDDB_UPD = 1345,
|
|
VLDMDIA = 1346,
|
|
VLDMDIA_UPD = 1347,
|
|
VLDMQIA = 1348,
|
|
VLDMSDB_UPD = 1349,
|
|
VLDMSIA = 1350,
|
|
VLDMSIA_UPD = 1351,
|
|
VLDRD = 1352,
|
|
VLDRH = 1353,
|
|
VLDRS = 1354,
|
|
VLLDM = 1355,
|
|
VLSTM = 1356,
|
|
VMAXNMD = 1357,
|
|
VMAXNMH = 1358,
|
|
VMAXNMNDf = 1359,
|
|
VMAXNMNDh = 1360,
|
|
VMAXNMNQf = 1361,
|
|
VMAXNMNQh = 1362,
|
|
VMAXNMS = 1363,
|
|
VMAXfd = 1364,
|
|
VMAXfq = 1365,
|
|
VMAXhd = 1366,
|
|
VMAXhq = 1367,
|
|
VMAXsv16i8 = 1368,
|
|
VMAXsv2i32 = 1369,
|
|
VMAXsv4i16 = 1370,
|
|
VMAXsv4i32 = 1371,
|
|
VMAXsv8i16 = 1372,
|
|
VMAXsv8i8 = 1373,
|
|
VMAXuv16i8 = 1374,
|
|
VMAXuv2i32 = 1375,
|
|
VMAXuv4i16 = 1376,
|
|
VMAXuv4i32 = 1377,
|
|
VMAXuv8i16 = 1378,
|
|
VMAXuv8i8 = 1379,
|
|
VMINNMD = 1380,
|
|
VMINNMH = 1381,
|
|
VMINNMNDf = 1382,
|
|
VMINNMNDh = 1383,
|
|
VMINNMNQf = 1384,
|
|
VMINNMNQh = 1385,
|
|
VMINNMS = 1386,
|
|
VMINfd = 1387,
|
|
VMINfq = 1388,
|
|
VMINhd = 1389,
|
|
VMINhq = 1390,
|
|
VMINsv16i8 = 1391,
|
|
VMINsv2i32 = 1392,
|
|
VMINsv4i16 = 1393,
|
|
VMINsv4i32 = 1394,
|
|
VMINsv8i16 = 1395,
|
|
VMINsv8i8 = 1396,
|
|
VMINuv16i8 = 1397,
|
|
VMINuv2i32 = 1398,
|
|
VMINuv4i16 = 1399,
|
|
VMINuv4i32 = 1400,
|
|
VMINuv8i16 = 1401,
|
|
VMINuv8i8 = 1402,
|
|
VMLAD = 1403,
|
|
VMLAH = 1404,
|
|
VMLALslsv2i32 = 1405,
|
|
VMLALslsv4i16 = 1406,
|
|
VMLALsluv2i32 = 1407,
|
|
VMLALsluv4i16 = 1408,
|
|
VMLALsv2i64 = 1409,
|
|
VMLALsv4i32 = 1410,
|
|
VMLALsv8i16 = 1411,
|
|
VMLALuv2i64 = 1412,
|
|
VMLALuv4i32 = 1413,
|
|
VMLALuv8i16 = 1414,
|
|
VMLAS = 1415,
|
|
VMLAfd = 1416,
|
|
VMLAfq = 1417,
|
|
VMLAhd = 1418,
|
|
VMLAhq = 1419,
|
|
VMLAslfd = 1420,
|
|
VMLAslfq = 1421,
|
|
VMLAslhd = 1422,
|
|
VMLAslhq = 1423,
|
|
VMLAslv2i32 = 1424,
|
|
VMLAslv4i16 = 1425,
|
|
VMLAslv4i32 = 1426,
|
|
VMLAslv8i16 = 1427,
|
|
VMLAv16i8 = 1428,
|
|
VMLAv2i32 = 1429,
|
|
VMLAv4i16 = 1430,
|
|
VMLAv4i32 = 1431,
|
|
VMLAv8i16 = 1432,
|
|
VMLAv8i8 = 1433,
|
|
VMLSD = 1434,
|
|
VMLSH = 1435,
|
|
VMLSLslsv2i32 = 1436,
|
|
VMLSLslsv4i16 = 1437,
|
|
VMLSLsluv2i32 = 1438,
|
|
VMLSLsluv4i16 = 1439,
|
|
VMLSLsv2i64 = 1440,
|
|
VMLSLsv4i32 = 1441,
|
|
VMLSLsv8i16 = 1442,
|
|
VMLSLuv2i64 = 1443,
|
|
VMLSLuv4i32 = 1444,
|
|
VMLSLuv8i16 = 1445,
|
|
VMLSS = 1446,
|
|
VMLSfd = 1447,
|
|
VMLSfq = 1448,
|
|
VMLShd = 1449,
|
|
VMLShq = 1450,
|
|
VMLSslfd = 1451,
|
|
VMLSslfq = 1452,
|
|
VMLSslhd = 1453,
|
|
VMLSslhq = 1454,
|
|
VMLSslv2i32 = 1455,
|
|
VMLSslv4i16 = 1456,
|
|
VMLSslv4i32 = 1457,
|
|
VMLSslv8i16 = 1458,
|
|
VMLSv16i8 = 1459,
|
|
VMLSv2i32 = 1460,
|
|
VMLSv4i16 = 1461,
|
|
VMLSv4i32 = 1462,
|
|
VMLSv8i16 = 1463,
|
|
VMLSv8i8 = 1464,
|
|
VMOVD = 1465,
|
|
VMOVD0 = 1466,
|
|
VMOVDRR = 1467,
|
|
VMOVDcc = 1468,
|
|
VMOVH = 1469,
|
|
VMOVHR = 1470,
|
|
VMOVLsv2i64 = 1471,
|
|
VMOVLsv4i32 = 1472,
|
|
VMOVLsv8i16 = 1473,
|
|
VMOVLuv2i64 = 1474,
|
|
VMOVLuv4i32 = 1475,
|
|
VMOVLuv8i16 = 1476,
|
|
VMOVNv2i32 = 1477,
|
|
VMOVNv4i16 = 1478,
|
|
VMOVNv8i8 = 1479,
|
|
VMOVQ0 = 1480,
|
|
VMOVRH = 1481,
|
|
VMOVRRD = 1482,
|
|
VMOVRRS = 1483,
|
|
VMOVRS = 1484,
|
|
VMOVS = 1485,
|
|
VMOVSR = 1486,
|
|
VMOVSRR = 1487,
|
|
VMOVScc = 1488,
|
|
VMOVv16i8 = 1489,
|
|
VMOVv1i64 = 1490,
|
|
VMOVv2f32 = 1491,
|
|
VMOVv2i32 = 1492,
|
|
VMOVv2i64 = 1493,
|
|
VMOVv4f32 = 1494,
|
|
VMOVv4i16 = 1495,
|
|
VMOVv4i32 = 1496,
|
|
VMOVv8i16 = 1497,
|
|
VMOVv8i8 = 1498,
|
|
VMRS = 1499,
|
|
VMRS_FPEXC = 1500,
|
|
VMRS_FPINST = 1501,
|
|
VMRS_FPINST2 = 1502,
|
|
VMRS_FPSID = 1503,
|
|
VMRS_MVFR0 = 1504,
|
|
VMRS_MVFR1 = 1505,
|
|
VMRS_MVFR2 = 1506,
|
|
VMSR = 1507,
|
|
VMSR_FPEXC = 1508,
|
|
VMSR_FPINST = 1509,
|
|
VMSR_FPINST2 = 1510,
|
|
VMSR_FPSID = 1511,
|
|
VMULD = 1512,
|
|
VMULH = 1513,
|
|
VMULLp64 = 1514,
|
|
VMULLp8 = 1515,
|
|
VMULLslsv2i32 = 1516,
|
|
VMULLslsv4i16 = 1517,
|
|
VMULLsluv2i32 = 1518,
|
|
VMULLsluv4i16 = 1519,
|
|
VMULLsv2i64 = 1520,
|
|
VMULLsv4i32 = 1521,
|
|
VMULLsv8i16 = 1522,
|
|
VMULLuv2i64 = 1523,
|
|
VMULLuv4i32 = 1524,
|
|
VMULLuv8i16 = 1525,
|
|
VMULS = 1526,
|
|
VMULfd = 1527,
|
|
VMULfq = 1528,
|
|
VMULhd = 1529,
|
|
VMULhq = 1530,
|
|
VMULpd = 1531,
|
|
VMULpq = 1532,
|
|
VMULslfd = 1533,
|
|
VMULslfq = 1534,
|
|
VMULslhd = 1535,
|
|
VMULslhq = 1536,
|
|
VMULslv2i32 = 1537,
|
|
VMULslv4i16 = 1538,
|
|
VMULslv4i32 = 1539,
|
|
VMULslv8i16 = 1540,
|
|
VMULv16i8 = 1541,
|
|
VMULv2i32 = 1542,
|
|
VMULv4i16 = 1543,
|
|
VMULv4i32 = 1544,
|
|
VMULv8i16 = 1545,
|
|
VMULv8i8 = 1546,
|
|
VMVNd = 1547,
|
|
VMVNq = 1548,
|
|
VMVNv2i32 = 1549,
|
|
VMVNv4i16 = 1550,
|
|
VMVNv4i32 = 1551,
|
|
VMVNv8i16 = 1552,
|
|
VNEGD = 1553,
|
|
VNEGH = 1554,
|
|
VNEGS = 1555,
|
|
VNEGf32q = 1556,
|
|
VNEGfd = 1557,
|
|
VNEGhd = 1558,
|
|
VNEGhq = 1559,
|
|
VNEGs16d = 1560,
|
|
VNEGs16q = 1561,
|
|
VNEGs32d = 1562,
|
|
VNEGs32q = 1563,
|
|
VNEGs8d = 1564,
|
|
VNEGs8q = 1565,
|
|
VNMLAD = 1566,
|
|
VNMLAH = 1567,
|
|
VNMLAS = 1568,
|
|
VNMLSD = 1569,
|
|
VNMLSH = 1570,
|
|
VNMLSS = 1571,
|
|
VNMULD = 1572,
|
|
VNMULH = 1573,
|
|
VNMULS = 1574,
|
|
VORNd = 1575,
|
|
VORNq = 1576,
|
|
VORRd = 1577,
|
|
VORRiv2i32 = 1578,
|
|
VORRiv4i16 = 1579,
|
|
VORRiv4i32 = 1580,
|
|
VORRiv8i16 = 1581,
|
|
VORRq = 1582,
|
|
VPADALsv16i8 = 1583,
|
|
VPADALsv2i32 = 1584,
|
|
VPADALsv4i16 = 1585,
|
|
VPADALsv4i32 = 1586,
|
|
VPADALsv8i16 = 1587,
|
|
VPADALsv8i8 = 1588,
|
|
VPADALuv16i8 = 1589,
|
|
VPADALuv2i32 = 1590,
|
|
VPADALuv4i16 = 1591,
|
|
VPADALuv4i32 = 1592,
|
|
VPADALuv8i16 = 1593,
|
|
VPADALuv8i8 = 1594,
|
|
VPADDLsv16i8 = 1595,
|
|
VPADDLsv2i32 = 1596,
|
|
VPADDLsv4i16 = 1597,
|
|
VPADDLsv4i32 = 1598,
|
|
VPADDLsv8i16 = 1599,
|
|
VPADDLsv8i8 = 1600,
|
|
VPADDLuv16i8 = 1601,
|
|
VPADDLuv2i32 = 1602,
|
|
VPADDLuv4i16 = 1603,
|
|
VPADDLuv4i32 = 1604,
|
|
VPADDLuv8i16 = 1605,
|
|
VPADDLuv8i8 = 1606,
|
|
VPADDf = 1607,
|
|
VPADDh = 1608,
|
|
VPADDi16 = 1609,
|
|
VPADDi32 = 1610,
|
|
VPADDi8 = 1611,
|
|
VPMAXf = 1612,
|
|
VPMAXh = 1613,
|
|
VPMAXs16 = 1614,
|
|
VPMAXs32 = 1615,
|
|
VPMAXs8 = 1616,
|
|
VPMAXu16 = 1617,
|
|
VPMAXu32 = 1618,
|
|
VPMAXu8 = 1619,
|
|
VPMINf = 1620,
|
|
VPMINh = 1621,
|
|
VPMINs16 = 1622,
|
|
VPMINs32 = 1623,
|
|
VPMINs8 = 1624,
|
|
VPMINu16 = 1625,
|
|
VPMINu32 = 1626,
|
|
VPMINu8 = 1627,
|
|
VQABSv16i8 = 1628,
|
|
VQABSv2i32 = 1629,
|
|
VQABSv4i16 = 1630,
|
|
VQABSv4i32 = 1631,
|
|
VQABSv8i16 = 1632,
|
|
VQABSv8i8 = 1633,
|
|
VQADDsv16i8 = 1634,
|
|
VQADDsv1i64 = 1635,
|
|
VQADDsv2i32 = 1636,
|
|
VQADDsv2i64 = 1637,
|
|
VQADDsv4i16 = 1638,
|
|
VQADDsv4i32 = 1639,
|
|
VQADDsv8i16 = 1640,
|
|
VQADDsv8i8 = 1641,
|
|
VQADDuv16i8 = 1642,
|
|
VQADDuv1i64 = 1643,
|
|
VQADDuv2i32 = 1644,
|
|
VQADDuv2i64 = 1645,
|
|
VQADDuv4i16 = 1646,
|
|
VQADDuv4i32 = 1647,
|
|
VQADDuv8i16 = 1648,
|
|
VQADDuv8i8 = 1649,
|
|
VQDMLALslv2i32 = 1650,
|
|
VQDMLALslv4i16 = 1651,
|
|
VQDMLALv2i64 = 1652,
|
|
VQDMLALv4i32 = 1653,
|
|
VQDMLSLslv2i32 = 1654,
|
|
VQDMLSLslv4i16 = 1655,
|
|
VQDMLSLv2i64 = 1656,
|
|
VQDMLSLv4i32 = 1657,
|
|
VQDMULHslv2i32 = 1658,
|
|
VQDMULHslv4i16 = 1659,
|
|
VQDMULHslv4i32 = 1660,
|
|
VQDMULHslv8i16 = 1661,
|
|
VQDMULHv2i32 = 1662,
|
|
VQDMULHv4i16 = 1663,
|
|
VQDMULHv4i32 = 1664,
|
|
VQDMULHv8i16 = 1665,
|
|
VQDMULLslv2i32 = 1666,
|
|
VQDMULLslv4i16 = 1667,
|
|
VQDMULLv2i64 = 1668,
|
|
VQDMULLv4i32 = 1669,
|
|
VQMOVNsuv2i32 = 1670,
|
|
VQMOVNsuv4i16 = 1671,
|
|
VQMOVNsuv8i8 = 1672,
|
|
VQMOVNsv2i32 = 1673,
|
|
VQMOVNsv4i16 = 1674,
|
|
VQMOVNsv8i8 = 1675,
|
|
VQMOVNuv2i32 = 1676,
|
|
VQMOVNuv4i16 = 1677,
|
|
VQMOVNuv8i8 = 1678,
|
|
VQNEGv16i8 = 1679,
|
|
VQNEGv2i32 = 1680,
|
|
VQNEGv4i16 = 1681,
|
|
VQNEGv4i32 = 1682,
|
|
VQNEGv8i16 = 1683,
|
|
VQNEGv8i8 = 1684,
|
|
VQRDMLAHslv2i32 = 1685,
|
|
VQRDMLAHslv4i16 = 1686,
|
|
VQRDMLAHslv4i32 = 1687,
|
|
VQRDMLAHslv8i16 = 1688,
|
|
VQRDMLAHv2i32 = 1689,
|
|
VQRDMLAHv4i16 = 1690,
|
|
VQRDMLAHv4i32 = 1691,
|
|
VQRDMLAHv8i16 = 1692,
|
|
VQRDMLSHslv2i32 = 1693,
|
|
VQRDMLSHslv4i16 = 1694,
|
|
VQRDMLSHslv4i32 = 1695,
|
|
VQRDMLSHslv8i16 = 1696,
|
|
VQRDMLSHv2i32 = 1697,
|
|
VQRDMLSHv4i16 = 1698,
|
|
VQRDMLSHv4i32 = 1699,
|
|
VQRDMLSHv8i16 = 1700,
|
|
VQRDMULHslv2i32 = 1701,
|
|
VQRDMULHslv4i16 = 1702,
|
|
VQRDMULHslv4i32 = 1703,
|
|
VQRDMULHslv8i16 = 1704,
|
|
VQRDMULHv2i32 = 1705,
|
|
VQRDMULHv4i16 = 1706,
|
|
VQRDMULHv4i32 = 1707,
|
|
VQRDMULHv8i16 = 1708,
|
|
VQRSHLsv16i8 = 1709,
|
|
VQRSHLsv1i64 = 1710,
|
|
VQRSHLsv2i32 = 1711,
|
|
VQRSHLsv2i64 = 1712,
|
|
VQRSHLsv4i16 = 1713,
|
|
VQRSHLsv4i32 = 1714,
|
|
VQRSHLsv8i16 = 1715,
|
|
VQRSHLsv8i8 = 1716,
|
|
VQRSHLuv16i8 = 1717,
|
|
VQRSHLuv1i64 = 1718,
|
|
VQRSHLuv2i32 = 1719,
|
|
VQRSHLuv2i64 = 1720,
|
|
VQRSHLuv4i16 = 1721,
|
|
VQRSHLuv4i32 = 1722,
|
|
VQRSHLuv8i16 = 1723,
|
|
VQRSHLuv8i8 = 1724,
|
|
VQRSHRNsv2i32 = 1725,
|
|
VQRSHRNsv4i16 = 1726,
|
|
VQRSHRNsv8i8 = 1727,
|
|
VQRSHRNuv2i32 = 1728,
|
|
VQRSHRNuv4i16 = 1729,
|
|
VQRSHRNuv8i8 = 1730,
|
|
VQRSHRUNv2i32 = 1731,
|
|
VQRSHRUNv4i16 = 1732,
|
|
VQRSHRUNv8i8 = 1733,
|
|
VQSHLsiv16i8 = 1734,
|
|
VQSHLsiv1i64 = 1735,
|
|
VQSHLsiv2i32 = 1736,
|
|
VQSHLsiv2i64 = 1737,
|
|
VQSHLsiv4i16 = 1738,
|
|
VQSHLsiv4i32 = 1739,
|
|
VQSHLsiv8i16 = 1740,
|
|
VQSHLsiv8i8 = 1741,
|
|
VQSHLsuv16i8 = 1742,
|
|
VQSHLsuv1i64 = 1743,
|
|
VQSHLsuv2i32 = 1744,
|
|
VQSHLsuv2i64 = 1745,
|
|
VQSHLsuv4i16 = 1746,
|
|
VQSHLsuv4i32 = 1747,
|
|
VQSHLsuv8i16 = 1748,
|
|
VQSHLsuv8i8 = 1749,
|
|
VQSHLsv16i8 = 1750,
|
|
VQSHLsv1i64 = 1751,
|
|
VQSHLsv2i32 = 1752,
|
|
VQSHLsv2i64 = 1753,
|
|
VQSHLsv4i16 = 1754,
|
|
VQSHLsv4i32 = 1755,
|
|
VQSHLsv8i16 = 1756,
|
|
VQSHLsv8i8 = 1757,
|
|
VQSHLuiv16i8 = 1758,
|
|
VQSHLuiv1i64 = 1759,
|
|
VQSHLuiv2i32 = 1760,
|
|
VQSHLuiv2i64 = 1761,
|
|
VQSHLuiv4i16 = 1762,
|
|
VQSHLuiv4i32 = 1763,
|
|
VQSHLuiv8i16 = 1764,
|
|
VQSHLuiv8i8 = 1765,
|
|
VQSHLuv16i8 = 1766,
|
|
VQSHLuv1i64 = 1767,
|
|
VQSHLuv2i32 = 1768,
|
|
VQSHLuv2i64 = 1769,
|
|
VQSHLuv4i16 = 1770,
|
|
VQSHLuv4i32 = 1771,
|
|
VQSHLuv8i16 = 1772,
|
|
VQSHLuv8i8 = 1773,
|
|
VQSHRNsv2i32 = 1774,
|
|
VQSHRNsv4i16 = 1775,
|
|
VQSHRNsv8i8 = 1776,
|
|
VQSHRNuv2i32 = 1777,
|
|
VQSHRNuv4i16 = 1778,
|
|
VQSHRNuv8i8 = 1779,
|
|
VQSHRUNv2i32 = 1780,
|
|
VQSHRUNv4i16 = 1781,
|
|
VQSHRUNv8i8 = 1782,
|
|
VQSUBsv16i8 = 1783,
|
|
VQSUBsv1i64 = 1784,
|
|
VQSUBsv2i32 = 1785,
|
|
VQSUBsv2i64 = 1786,
|
|
VQSUBsv4i16 = 1787,
|
|
VQSUBsv4i32 = 1788,
|
|
VQSUBsv8i16 = 1789,
|
|
VQSUBsv8i8 = 1790,
|
|
VQSUBuv16i8 = 1791,
|
|
VQSUBuv1i64 = 1792,
|
|
VQSUBuv2i32 = 1793,
|
|
VQSUBuv2i64 = 1794,
|
|
VQSUBuv4i16 = 1795,
|
|
VQSUBuv4i32 = 1796,
|
|
VQSUBuv8i16 = 1797,
|
|
VQSUBuv8i8 = 1798,
|
|
VRADDHNv2i32 = 1799,
|
|
VRADDHNv4i16 = 1800,
|
|
VRADDHNv8i8 = 1801,
|
|
VRECPEd = 1802,
|
|
VRECPEfd = 1803,
|
|
VRECPEfq = 1804,
|
|
VRECPEhd = 1805,
|
|
VRECPEhq = 1806,
|
|
VRECPEq = 1807,
|
|
VRECPSfd = 1808,
|
|
VRECPSfq = 1809,
|
|
VRECPShd = 1810,
|
|
VRECPShq = 1811,
|
|
VREV16d8 = 1812,
|
|
VREV16q8 = 1813,
|
|
VREV32d16 = 1814,
|
|
VREV32d8 = 1815,
|
|
VREV32q16 = 1816,
|
|
VREV32q8 = 1817,
|
|
VREV64d16 = 1818,
|
|
VREV64d32 = 1819,
|
|
VREV64d8 = 1820,
|
|
VREV64q16 = 1821,
|
|
VREV64q32 = 1822,
|
|
VREV64q8 = 1823,
|
|
VRHADDsv16i8 = 1824,
|
|
VRHADDsv2i32 = 1825,
|
|
VRHADDsv4i16 = 1826,
|
|
VRHADDsv4i32 = 1827,
|
|
VRHADDsv8i16 = 1828,
|
|
VRHADDsv8i8 = 1829,
|
|
VRHADDuv16i8 = 1830,
|
|
VRHADDuv2i32 = 1831,
|
|
VRHADDuv4i16 = 1832,
|
|
VRHADDuv4i32 = 1833,
|
|
VRHADDuv8i16 = 1834,
|
|
VRHADDuv8i8 = 1835,
|
|
VRINTAD = 1836,
|
|
VRINTAH = 1837,
|
|
VRINTANDf = 1838,
|
|
VRINTANDh = 1839,
|
|
VRINTANQf = 1840,
|
|
VRINTANQh = 1841,
|
|
VRINTAS = 1842,
|
|
VRINTMD = 1843,
|
|
VRINTMH = 1844,
|
|
VRINTMNDf = 1845,
|
|
VRINTMNDh = 1846,
|
|
VRINTMNQf = 1847,
|
|
VRINTMNQh = 1848,
|
|
VRINTMS = 1849,
|
|
VRINTND = 1850,
|
|
VRINTNH = 1851,
|
|
VRINTNNDf = 1852,
|
|
VRINTNNDh = 1853,
|
|
VRINTNNQf = 1854,
|
|
VRINTNNQh = 1855,
|
|
VRINTNS = 1856,
|
|
VRINTPD = 1857,
|
|
VRINTPH = 1858,
|
|
VRINTPNDf = 1859,
|
|
VRINTPNDh = 1860,
|
|
VRINTPNQf = 1861,
|
|
VRINTPNQh = 1862,
|
|
VRINTPS = 1863,
|
|
VRINTRD = 1864,
|
|
VRINTRH = 1865,
|
|
VRINTRS = 1866,
|
|
VRINTXD = 1867,
|
|
VRINTXH = 1868,
|
|
VRINTXNDf = 1869,
|
|
VRINTXNDh = 1870,
|
|
VRINTXNQf = 1871,
|
|
VRINTXNQh = 1872,
|
|
VRINTXS = 1873,
|
|
VRINTZD = 1874,
|
|
VRINTZH = 1875,
|
|
VRINTZNDf = 1876,
|
|
VRINTZNDh = 1877,
|
|
VRINTZNQf = 1878,
|
|
VRINTZNQh = 1879,
|
|
VRINTZS = 1880,
|
|
VRSHLsv16i8 = 1881,
|
|
VRSHLsv1i64 = 1882,
|
|
VRSHLsv2i32 = 1883,
|
|
VRSHLsv2i64 = 1884,
|
|
VRSHLsv4i16 = 1885,
|
|
VRSHLsv4i32 = 1886,
|
|
VRSHLsv8i16 = 1887,
|
|
VRSHLsv8i8 = 1888,
|
|
VRSHLuv16i8 = 1889,
|
|
VRSHLuv1i64 = 1890,
|
|
VRSHLuv2i32 = 1891,
|
|
VRSHLuv2i64 = 1892,
|
|
VRSHLuv4i16 = 1893,
|
|
VRSHLuv4i32 = 1894,
|
|
VRSHLuv8i16 = 1895,
|
|
VRSHLuv8i8 = 1896,
|
|
VRSHRNv2i32 = 1897,
|
|
VRSHRNv4i16 = 1898,
|
|
VRSHRNv8i8 = 1899,
|
|
VRSHRsv16i8 = 1900,
|
|
VRSHRsv1i64 = 1901,
|
|
VRSHRsv2i32 = 1902,
|
|
VRSHRsv2i64 = 1903,
|
|
VRSHRsv4i16 = 1904,
|
|
VRSHRsv4i32 = 1905,
|
|
VRSHRsv8i16 = 1906,
|
|
VRSHRsv8i8 = 1907,
|
|
VRSHRuv16i8 = 1908,
|
|
VRSHRuv1i64 = 1909,
|
|
VRSHRuv2i32 = 1910,
|
|
VRSHRuv2i64 = 1911,
|
|
VRSHRuv4i16 = 1912,
|
|
VRSHRuv4i32 = 1913,
|
|
VRSHRuv8i16 = 1914,
|
|
VRSHRuv8i8 = 1915,
|
|
VRSQRTEd = 1916,
|
|
VRSQRTEfd = 1917,
|
|
VRSQRTEfq = 1918,
|
|
VRSQRTEhd = 1919,
|
|
VRSQRTEhq = 1920,
|
|
VRSQRTEq = 1921,
|
|
VRSQRTSfd = 1922,
|
|
VRSQRTSfq = 1923,
|
|
VRSQRTShd = 1924,
|
|
VRSQRTShq = 1925,
|
|
VRSRAsv16i8 = 1926,
|
|
VRSRAsv1i64 = 1927,
|
|
VRSRAsv2i32 = 1928,
|
|
VRSRAsv2i64 = 1929,
|
|
VRSRAsv4i16 = 1930,
|
|
VRSRAsv4i32 = 1931,
|
|
VRSRAsv8i16 = 1932,
|
|
VRSRAsv8i8 = 1933,
|
|
VRSRAuv16i8 = 1934,
|
|
VRSRAuv1i64 = 1935,
|
|
VRSRAuv2i32 = 1936,
|
|
VRSRAuv2i64 = 1937,
|
|
VRSRAuv4i16 = 1938,
|
|
VRSRAuv4i32 = 1939,
|
|
VRSRAuv8i16 = 1940,
|
|
VRSRAuv8i8 = 1941,
|
|
VRSUBHNv2i32 = 1942,
|
|
VRSUBHNv4i16 = 1943,
|
|
VRSUBHNv8i8 = 1944,
|
|
VSELEQD = 1945,
|
|
VSELEQH = 1946,
|
|
VSELEQS = 1947,
|
|
VSELGED = 1948,
|
|
VSELGEH = 1949,
|
|
VSELGES = 1950,
|
|
VSELGTD = 1951,
|
|
VSELGTH = 1952,
|
|
VSELGTS = 1953,
|
|
VSELVSD = 1954,
|
|
VSELVSH = 1955,
|
|
VSELVSS = 1956,
|
|
VSETLNi16 = 1957,
|
|
VSETLNi32 = 1958,
|
|
VSETLNi8 = 1959,
|
|
VSHLLi16 = 1960,
|
|
VSHLLi32 = 1961,
|
|
VSHLLi8 = 1962,
|
|
VSHLLsv2i64 = 1963,
|
|
VSHLLsv4i32 = 1964,
|
|
VSHLLsv8i16 = 1965,
|
|
VSHLLuv2i64 = 1966,
|
|
VSHLLuv4i32 = 1967,
|
|
VSHLLuv8i16 = 1968,
|
|
VSHLiv16i8 = 1969,
|
|
VSHLiv1i64 = 1970,
|
|
VSHLiv2i32 = 1971,
|
|
VSHLiv2i64 = 1972,
|
|
VSHLiv4i16 = 1973,
|
|
VSHLiv4i32 = 1974,
|
|
VSHLiv8i16 = 1975,
|
|
VSHLiv8i8 = 1976,
|
|
VSHLsv16i8 = 1977,
|
|
VSHLsv1i64 = 1978,
|
|
VSHLsv2i32 = 1979,
|
|
VSHLsv2i64 = 1980,
|
|
VSHLsv4i16 = 1981,
|
|
VSHLsv4i32 = 1982,
|
|
VSHLsv8i16 = 1983,
|
|
VSHLsv8i8 = 1984,
|
|
VSHLuv16i8 = 1985,
|
|
VSHLuv1i64 = 1986,
|
|
VSHLuv2i32 = 1987,
|
|
VSHLuv2i64 = 1988,
|
|
VSHLuv4i16 = 1989,
|
|
VSHLuv4i32 = 1990,
|
|
VSHLuv8i16 = 1991,
|
|
VSHLuv8i8 = 1992,
|
|
VSHRNv2i32 = 1993,
|
|
VSHRNv4i16 = 1994,
|
|
VSHRNv8i8 = 1995,
|
|
VSHRsv16i8 = 1996,
|
|
VSHRsv1i64 = 1997,
|
|
VSHRsv2i32 = 1998,
|
|
VSHRsv2i64 = 1999,
|
|
VSHRsv4i16 = 2000,
|
|
VSHRsv4i32 = 2001,
|
|
VSHRsv8i16 = 2002,
|
|
VSHRsv8i8 = 2003,
|
|
VSHRuv16i8 = 2004,
|
|
VSHRuv1i64 = 2005,
|
|
VSHRuv2i32 = 2006,
|
|
VSHRuv2i64 = 2007,
|
|
VSHRuv4i16 = 2008,
|
|
VSHRuv4i32 = 2009,
|
|
VSHRuv8i16 = 2010,
|
|
VSHRuv8i8 = 2011,
|
|
VSHTOD = 2012,
|
|
VSHTOH = 2013,
|
|
VSHTOS = 2014,
|
|
VSITOD = 2015,
|
|
VSITOH = 2016,
|
|
VSITOS = 2017,
|
|
VSLIv16i8 = 2018,
|
|
VSLIv1i64 = 2019,
|
|
VSLIv2i32 = 2020,
|
|
VSLIv2i64 = 2021,
|
|
VSLIv4i16 = 2022,
|
|
VSLIv4i32 = 2023,
|
|
VSLIv8i16 = 2024,
|
|
VSLIv8i8 = 2025,
|
|
VSLTOD = 2026,
|
|
VSLTOH = 2027,
|
|
VSLTOS = 2028,
|
|
VSQRTD = 2029,
|
|
VSQRTH = 2030,
|
|
VSQRTS = 2031,
|
|
VSRAsv16i8 = 2032,
|
|
VSRAsv1i64 = 2033,
|
|
VSRAsv2i32 = 2034,
|
|
VSRAsv2i64 = 2035,
|
|
VSRAsv4i16 = 2036,
|
|
VSRAsv4i32 = 2037,
|
|
VSRAsv8i16 = 2038,
|
|
VSRAsv8i8 = 2039,
|
|
VSRAuv16i8 = 2040,
|
|
VSRAuv1i64 = 2041,
|
|
VSRAuv2i32 = 2042,
|
|
VSRAuv2i64 = 2043,
|
|
VSRAuv4i16 = 2044,
|
|
VSRAuv4i32 = 2045,
|
|
VSRAuv8i16 = 2046,
|
|
VSRAuv8i8 = 2047,
|
|
VSRIv16i8 = 2048,
|
|
VSRIv1i64 = 2049,
|
|
VSRIv2i32 = 2050,
|
|
VSRIv2i64 = 2051,
|
|
VSRIv4i16 = 2052,
|
|
VSRIv4i32 = 2053,
|
|
VSRIv8i16 = 2054,
|
|
VSRIv8i8 = 2055,
|
|
VST1LNd16 = 2056,
|
|
VST1LNd16_UPD = 2057,
|
|
VST1LNd32 = 2058,
|
|
VST1LNd32_UPD = 2059,
|
|
VST1LNd8 = 2060,
|
|
VST1LNd8_UPD = 2061,
|
|
VST1LNdAsm_16 = 2062,
|
|
VST1LNdAsm_32 = 2063,
|
|
VST1LNdAsm_8 = 2064,
|
|
VST1LNdWB_fixed_Asm_16 = 2065,
|
|
VST1LNdWB_fixed_Asm_32 = 2066,
|
|
VST1LNdWB_fixed_Asm_8 = 2067,
|
|
VST1LNdWB_register_Asm_16 = 2068,
|
|
VST1LNdWB_register_Asm_32 = 2069,
|
|
VST1LNdWB_register_Asm_8 = 2070,
|
|
VST1LNq16Pseudo = 2071,
|
|
VST1LNq16Pseudo_UPD = 2072,
|
|
VST1LNq32Pseudo = 2073,
|
|
VST1LNq32Pseudo_UPD = 2074,
|
|
VST1LNq8Pseudo = 2075,
|
|
VST1LNq8Pseudo_UPD = 2076,
|
|
VST1d16 = 2077,
|
|
VST1d16Q = 2078,
|
|
VST1d16Qwb_fixed = 2079,
|
|
VST1d16Qwb_register = 2080,
|
|
VST1d16T = 2081,
|
|
VST1d16Twb_fixed = 2082,
|
|
VST1d16Twb_register = 2083,
|
|
VST1d16wb_fixed = 2084,
|
|
VST1d16wb_register = 2085,
|
|
VST1d32 = 2086,
|
|
VST1d32Q = 2087,
|
|
VST1d32Qwb_fixed = 2088,
|
|
VST1d32Qwb_register = 2089,
|
|
VST1d32T = 2090,
|
|
VST1d32Twb_fixed = 2091,
|
|
VST1d32Twb_register = 2092,
|
|
VST1d32wb_fixed = 2093,
|
|
VST1d32wb_register = 2094,
|
|
VST1d64 = 2095,
|
|
VST1d64Q = 2096,
|
|
VST1d64QPseudo = 2097,
|
|
VST1d64QPseudoWB_fixed = 2098,
|
|
VST1d64QPseudoWB_register = 2099,
|
|
VST1d64Qwb_fixed = 2100,
|
|
VST1d64Qwb_register = 2101,
|
|
VST1d64T = 2102,
|
|
VST1d64TPseudo = 2103,
|
|
VST1d64TPseudoWB_fixed = 2104,
|
|
VST1d64TPseudoWB_register = 2105,
|
|
VST1d64Twb_fixed = 2106,
|
|
VST1d64Twb_register = 2107,
|
|
VST1d64wb_fixed = 2108,
|
|
VST1d64wb_register = 2109,
|
|
VST1d8 = 2110,
|
|
VST1d8Q = 2111,
|
|
VST1d8Qwb_fixed = 2112,
|
|
VST1d8Qwb_register = 2113,
|
|
VST1d8T = 2114,
|
|
VST1d8Twb_fixed = 2115,
|
|
VST1d8Twb_register = 2116,
|
|
VST1d8wb_fixed = 2117,
|
|
VST1d8wb_register = 2118,
|
|
VST1q16 = 2119,
|
|
VST1q16wb_fixed = 2120,
|
|
VST1q16wb_register = 2121,
|
|
VST1q32 = 2122,
|
|
VST1q32wb_fixed = 2123,
|
|
VST1q32wb_register = 2124,
|
|
VST1q64 = 2125,
|
|
VST1q64wb_fixed = 2126,
|
|
VST1q64wb_register = 2127,
|
|
VST1q8 = 2128,
|
|
VST1q8wb_fixed = 2129,
|
|
VST1q8wb_register = 2130,
|
|
VST2LNd16 = 2131,
|
|
VST2LNd16Pseudo = 2132,
|
|
VST2LNd16Pseudo_UPD = 2133,
|
|
VST2LNd16_UPD = 2134,
|
|
VST2LNd32 = 2135,
|
|
VST2LNd32Pseudo = 2136,
|
|
VST2LNd32Pseudo_UPD = 2137,
|
|
VST2LNd32_UPD = 2138,
|
|
VST2LNd8 = 2139,
|
|
VST2LNd8Pseudo = 2140,
|
|
VST2LNd8Pseudo_UPD = 2141,
|
|
VST2LNd8_UPD = 2142,
|
|
VST2LNdAsm_16 = 2143,
|
|
VST2LNdAsm_32 = 2144,
|
|
VST2LNdAsm_8 = 2145,
|
|
VST2LNdWB_fixed_Asm_16 = 2146,
|
|
VST2LNdWB_fixed_Asm_32 = 2147,
|
|
VST2LNdWB_fixed_Asm_8 = 2148,
|
|
VST2LNdWB_register_Asm_16 = 2149,
|
|
VST2LNdWB_register_Asm_32 = 2150,
|
|
VST2LNdWB_register_Asm_8 = 2151,
|
|
VST2LNq16 = 2152,
|
|
VST2LNq16Pseudo = 2153,
|
|
VST2LNq16Pseudo_UPD = 2154,
|
|
VST2LNq16_UPD = 2155,
|
|
VST2LNq32 = 2156,
|
|
VST2LNq32Pseudo = 2157,
|
|
VST2LNq32Pseudo_UPD = 2158,
|
|
VST2LNq32_UPD = 2159,
|
|
VST2LNqAsm_16 = 2160,
|
|
VST2LNqAsm_32 = 2161,
|
|
VST2LNqWB_fixed_Asm_16 = 2162,
|
|
VST2LNqWB_fixed_Asm_32 = 2163,
|
|
VST2LNqWB_register_Asm_16 = 2164,
|
|
VST2LNqWB_register_Asm_32 = 2165,
|
|
VST2b16 = 2166,
|
|
VST2b16wb_fixed = 2167,
|
|
VST2b16wb_register = 2168,
|
|
VST2b32 = 2169,
|
|
VST2b32wb_fixed = 2170,
|
|
VST2b32wb_register = 2171,
|
|
VST2b8 = 2172,
|
|
VST2b8wb_fixed = 2173,
|
|
VST2b8wb_register = 2174,
|
|
VST2d16 = 2175,
|
|
VST2d16wb_fixed = 2176,
|
|
VST2d16wb_register = 2177,
|
|
VST2d32 = 2178,
|
|
VST2d32wb_fixed = 2179,
|
|
VST2d32wb_register = 2180,
|
|
VST2d8 = 2181,
|
|
VST2d8wb_fixed = 2182,
|
|
VST2d8wb_register = 2183,
|
|
VST2q16 = 2184,
|
|
VST2q16Pseudo = 2185,
|
|
VST2q16PseudoWB_fixed = 2186,
|
|
VST2q16PseudoWB_register = 2187,
|
|
VST2q16wb_fixed = 2188,
|
|
VST2q16wb_register = 2189,
|
|
VST2q32 = 2190,
|
|
VST2q32Pseudo = 2191,
|
|
VST2q32PseudoWB_fixed = 2192,
|
|
VST2q32PseudoWB_register = 2193,
|
|
VST2q32wb_fixed = 2194,
|
|
VST2q32wb_register = 2195,
|
|
VST2q8 = 2196,
|
|
VST2q8Pseudo = 2197,
|
|
VST2q8PseudoWB_fixed = 2198,
|
|
VST2q8PseudoWB_register = 2199,
|
|
VST2q8wb_fixed = 2200,
|
|
VST2q8wb_register = 2201,
|
|
VST3LNd16 = 2202,
|
|
VST3LNd16Pseudo = 2203,
|
|
VST3LNd16Pseudo_UPD = 2204,
|
|
VST3LNd16_UPD = 2205,
|
|
VST3LNd32 = 2206,
|
|
VST3LNd32Pseudo = 2207,
|
|
VST3LNd32Pseudo_UPD = 2208,
|
|
VST3LNd32_UPD = 2209,
|
|
VST3LNd8 = 2210,
|
|
VST3LNd8Pseudo = 2211,
|
|
VST3LNd8Pseudo_UPD = 2212,
|
|
VST3LNd8_UPD = 2213,
|
|
VST3LNdAsm_16 = 2214,
|
|
VST3LNdAsm_32 = 2215,
|
|
VST3LNdAsm_8 = 2216,
|
|
VST3LNdWB_fixed_Asm_16 = 2217,
|
|
VST3LNdWB_fixed_Asm_32 = 2218,
|
|
VST3LNdWB_fixed_Asm_8 = 2219,
|
|
VST3LNdWB_register_Asm_16 = 2220,
|
|
VST3LNdWB_register_Asm_32 = 2221,
|
|
VST3LNdWB_register_Asm_8 = 2222,
|
|
VST3LNq16 = 2223,
|
|
VST3LNq16Pseudo = 2224,
|
|
VST3LNq16Pseudo_UPD = 2225,
|
|
VST3LNq16_UPD = 2226,
|
|
VST3LNq32 = 2227,
|
|
VST3LNq32Pseudo = 2228,
|
|
VST3LNq32Pseudo_UPD = 2229,
|
|
VST3LNq32_UPD = 2230,
|
|
VST3LNqAsm_16 = 2231,
|
|
VST3LNqAsm_32 = 2232,
|
|
VST3LNqWB_fixed_Asm_16 = 2233,
|
|
VST3LNqWB_fixed_Asm_32 = 2234,
|
|
VST3LNqWB_register_Asm_16 = 2235,
|
|
VST3LNqWB_register_Asm_32 = 2236,
|
|
VST3d16 = 2237,
|
|
VST3d16Pseudo = 2238,
|
|
VST3d16Pseudo_UPD = 2239,
|
|
VST3d16_UPD = 2240,
|
|
VST3d32 = 2241,
|
|
VST3d32Pseudo = 2242,
|
|
VST3d32Pseudo_UPD = 2243,
|
|
VST3d32_UPD = 2244,
|
|
VST3d8 = 2245,
|
|
VST3d8Pseudo = 2246,
|
|
VST3d8Pseudo_UPD = 2247,
|
|
VST3d8_UPD = 2248,
|
|
VST3dAsm_16 = 2249,
|
|
VST3dAsm_32 = 2250,
|
|
VST3dAsm_8 = 2251,
|
|
VST3dWB_fixed_Asm_16 = 2252,
|
|
VST3dWB_fixed_Asm_32 = 2253,
|
|
VST3dWB_fixed_Asm_8 = 2254,
|
|
VST3dWB_register_Asm_16 = 2255,
|
|
VST3dWB_register_Asm_32 = 2256,
|
|
VST3dWB_register_Asm_8 = 2257,
|
|
VST3q16 = 2258,
|
|
VST3q16Pseudo_UPD = 2259,
|
|
VST3q16_UPD = 2260,
|
|
VST3q16oddPseudo = 2261,
|
|
VST3q16oddPseudo_UPD = 2262,
|
|
VST3q32 = 2263,
|
|
VST3q32Pseudo_UPD = 2264,
|
|
VST3q32_UPD = 2265,
|
|
VST3q32oddPseudo = 2266,
|
|
VST3q32oddPseudo_UPD = 2267,
|
|
VST3q8 = 2268,
|
|
VST3q8Pseudo_UPD = 2269,
|
|
VST3q8_UPD = 2270,
|
|
VST3q8oddPseudo = 2271,
|
|
VST3q8oddPseudo_UPD = 2272,
|
|
VST3qAsm_16 = 2273,
|
|
VST3qAsm_32 = 2274,
|
|
VST3qAsm_8 = 2275,
|
|
VST3qWB_fixed_Asm_16 = 2276,
|
|
VST3qWB_fixed_Asm_32 = 2277,
|
|
VST3qWB_fixed_Asm_8 = 2278,
|
|
VST3qWB_register_Asm_16 = 2279,
|
|
VST3qWB_register_Asm_32 = 2280,
|
|
VST3qWB_register_Asm_8 = 2281,
|
|
VST4LNd16 = 2282,
|
|
VST4LNd16Pseudo = 2283,
|
|
VST4LNd16Pseudo_UPD = 2284,
|
|
VST4LNd16_UPD = 2285,
|
|
VST4LNd32 = 2286,
|
|
VST4LNd32Pseudo = 2287,
|
|
VST4LNd32Pseudo_UPD = 2288,
|
|
VST4LNd32_UPD = 2289,
|
|
VST4LNd8 = 2290,
|
|
VST4LNd8Pseudo = 2291,
|
|
VST4LNd8Pseudo_UPD = 2292,
|
|
VST4LNd8_UPD = 2293,
|
|
VST4LNdAsm_16 = 2294,
|
|
VST4LNdAsm_32 = 2295,
|
|
VST4LNdAsm_8 = 2296,
|
|
VST4LNdWB_fixed_Asm_16 = 2297,
|
|
VST4LNdWB_fixed_Asm_32 = 2298,
|
|
VST4LNdWB_fixed_Asm_8 = 2299,
|
|
VST4LNdWB_register_Asm_16 = 2300,
|
|
VST4LNdWB_register_Asm_32 = 2301,
|
|
VST4LNdWB_register_Asm_8 = 2302,
|
|
VST4LNq16 = 2303,
|
|
VST4LNq16Pseudo = 2304,
|
|
VST4LNq16Pseudo_UPD = 2305,
|
|
VST4LNq16_UPD = 2306,
|
|
VST4LNq32 = 2307,
|
|
VST4LNq32Pseudo = 2308,
|
|
VST4LNq32Pseudo_UPD = 2309,
|
|
VST4LNq32_UPD = 2310,
|
|
VST4LNqAsm_16 = 2311,
|
|
VST4LNqAsm_32 = 2312,
|
|
VST4LNqWB_fixed_Asm_16 = 2313,
|
|
VST4LNqWB_fixed_Asm_32 = 2314,
|
|
VST4LNqWB_register_Asm_16 = 2315,
|
|
VST4LNqWB_register_Asm_32 = 2316,
|
|
VST4d16 = 2317,
|
|
VST4d16Pseudo = 2318,
|
|
VST4d16Pseudo_UPD = 2319,
|
|
VST4d16_UPD = 2320,
|
|
VST4d32 = 2321,
|
|
VST4d32Pseudo = 2322,
|
|
VST4d32Pseudo_UPD = 2323,
|
|
VST4d32_UPD = 2324,
|
|
VST4d8 = 2325,
|
|
VST4d8Pseudo = 2326,
|
|
VST4d8Pseudo_UPD = 2327,
|
|
VST4d8_UPD = 2328,
|
|
VST4dAsm_16 = 2329,
|
|
VST4dAsm_32 = 2330,
|
|
VST4dAsm_8 = 2331,
|
|
VST4dWB_fixed_Asm_16 = 2332,
|
|
VST4dWB_fixed_Asm_32 = 2333,
|
|
VST4dWB_fixed_Asm_8 = 2334,
|
|
VST4dWB_register_Asm_16 = 2335,
|
|
VST4dWB_register_Asm_32 = 2336,
|
|
VST4dWB_register_Asm_8 = 2337,
|
|
VST4q16 = 2338,
|
|
VST4q16Pseudo_UPD = 2339,
|
|
VST4q16_UPD = 2340,
|
|
VST4q16oddPseudo = 2341,
|
|
VST4q16oddPseudo_UPD = 2342,
|
|
VST4q32 = 2343,
|
|
VST4q32Pseudo_UPD = 2344,
|
|
VST4q32_UPD = 2345,
|
|
VST4q32oddPseudo = 2346,
|
|
VST4q32oddPseudo_UPD = 2347,
|
|
VST4q8 = 2348,
|
|
VST4q8Pseudo_UPD = 2349,
|
|
VST4q8_UPD = 2350,
|
|
VST4q8oddPseudo = 2351,
|
|
VST4q8oddPseudo_UPD = 2352,
|
|
VST4qAsm_16 = 2353,
|
|
VST4qAsm_32 = 2354,
|
|
VST4qAsm_8 = 2355,
|
|
VST4qWB_fixed_Asm_16 = 2356,
|
|
VST4qWB_fixed_Asm_32 = 2357,
|
|
VST4qWB_fixed_Asm_8 = 2358,
|
|
VST4qWB_register_Asm_16 = 2359,
|
|
VST4qWB_register_Asm_32 = 2360,
|
|
VST4qWB_register_Asm_8 = 2361,
|
|
VSTMDDB_UPD = 2362,
|
|
VSTMDIA = 2363,
|
|
VSTMDIA_UPD = 2364,
|
|
VSTMQIA = 2365,
|
|
VSTMSDB_UPD = 2366,
|
|
VSTMSIA = 2367,
|
|
VSTMSIA_UPD = 2368,
|
|
VSTRD = 2369,
|
|
VSTRH = 2370,
|
|
VSTRS = 2371,
|
|
VSUBD = 2372,
|
|
VSUBH = 2373,
|
|
VSUBHNv2i32 = 2374,
|
|
VSUBHNv4i16 = 2375,
|
|
VSUBHNv8i8 = 2376,
|
|
VSUBLsv2i64 = 2377,
|
|
VSUBLsv4i32 = 2378,
|
|
VSUBLsv8i16 = 2379,
|
|
VSUBLuv2i64 = 2380,
|
|
VSUBLuv4i32 = 2381,
|
|
VSUBLuv8i16 = 2382,
|
|
VSUBS = 2383,
|
|
VSUBWsv2i64 = 2384,
|
|
VSUBWsv4i32 = 2385,
|
|
VSUBWsv8i16 = 2386,
|
|
VSUBWuv2i64 = 2387,
|
|
VSUBWuv4i32 = 2388,
|
|
VSUBWuv8i16 = 2389,
|
|
VSUBfd = 2390,
|
|
VSUBfq = 2391,
|
|
VSUBhd = 2392,
|
|
VSUBhq = 2393,
|
|
VSUBv16i8 = 2394,
|
|
VSUBv1i64 = 2395,
|
|
VSUBv2i32 = 2396,
|
|
VSUBv2i64 = 2397,
|
|
VSUBv4i16 = 2398,
|
|
VSUBv4i32 = 2399,
|
|
VSUBv8i16 = 2400,
|
|
VSUBv8i8 = 2401,
|
|
VSWPd = 2402,
|
|
VSWPq = 2403,
|
|
VTBL1 = 2404,
|
|
VTBL2 = 2405,
|
|
VTBL3 = 2406,
|
|
VTBL3Pseudo = 2407,
|
|
VTBL4 = 2408,
|
|
VTBL4Pseudo = 2409,
|
|
VTBX1 = 2410,
|
|
VTBX2 = 2411,
|
|
VTBX3 = 2412,
|
|
VTBX3Pseudo = 2413,
|
|
VTBX4 = 2414,
|
|
VTBX4Pseudo = 2415,
|
|
VTOSHD = 2416,
|
|
VTOSHH = 2417,
|
|
VTOSHS = 2418,
|
|
VTOSIRD = 2419,
|
|
VTOSIRH = 2420,
|
|
VTOSIRS = 2421,
|
|
VTOSIZD = 2422,
|
|
VTOSIZH = 2423,
|
|
VTOSIZS = 2424,
|
|
VTOSLD = 2425,
|
|
VTOSLH = 2426,
|
|
VTOSLS = 2427,
|
|
VTOUHD = 2428,
|
|
VTOUHH = 2429,
|
|
VTOUHS = 2430,
|
|
VTOUIRD = 2431,
|
|
VTOUIRH = 2432,
|
|
VTOUIRS = 2433,
|
|
VTOUIZD = 2434,
|
|
VTOUIZH = 2435,
|
|
VTOUIZS = 2436,
|
|
VTOULD = 2437,
|
|
VTOULH = 2438,
|
|
VTOULS = 2439,
|
|
VTRNd16 = 2440,
|
|
VTRNd32 = 2441,
|
|
VTRNd8 = 2442,
|
|
VTRNq16 = 2443,
|
|
VTRNq32 = 2444,
|
|
VTRNq8 = 2445,
|
|
VTSTv16i8 = 2446,
|
|
VTSTv2i32 = 2447,
|
|
VTSTv4i16 = 2448,
|
|
VTSTv4i32 = 2449,
|
|
VTSTv8i16 = 2450,
|
|
VTSTv8i8 = 2451,
|
|
VUHTOD = 2452,
|
|
VUHTOH = 2453,
|
|
VUHTOS = 2454,
|
|
VUITOD = 2455,
|
|
VUITOH = 2456,
|
|
VUITOS = 2457,
|
|
VULTOD = 2458,
|
|
VULTOH = 2459,
|
|
VULTOS = 2460,
|
|
VUZPd16 = 2461,
|
|
VUZPd8 = 2462,
|
|
VUZPq16 = 2463,
|
|
VUZPq32 = 2464,
|
|
VUZPq8 = 2465,
|
|
VZIPd16 = 2466,
|
|
VZIPd8 = 2467,
|
|
VZIPq16 = 2468,
|
|
VZIPq32 = 2469,
|
|
VZIPq8 = 2470,
|
|
WIN__CHKSTK = 2471,
|
|
WIN__DBZCHK = 2472,
|
|
sysLDMDA = 2473,
|
|
sysLDMDA_UPD = 2474,
|
|
sysLDMDB = 2475,
|
|
sysLDMDB_UPD = 2476,
|
|
sysLDMIA = 2477,
|
|
sysLDMIA_UPD = 2478,
|
|
sysLDMIB = 2479,
|
|
sysLDMIB_UPD = 2480,
|
|
sysSTMDA = 2481,
|
|
sysSTMDA_UPD = 2482,
|
|
sysSTMDB = 2483,
|
|
sysSTMDB_UPD = 2484,
|
|
sysSTMIA = 2485,
|
|
sysSTMIA_UPD = 2486,
|
|
sysSTMIB = 2487,
|
|
sysSTMIB_UPD = 2488,
|
|
t2ABS = 2489,
|
|
t2ADCri = 2490,
|
|
t2ADCrr = 2491,
|
|
t2ADCrs = 2492,
|
|
t2ADDSri = 2493,
|
|
t2ADDSrr = 2494,
|
|
t2ADDSrs = 2495,
|
|
t2ADDri = 2496,
|
|
t2ADDri12 = 2497,
|
|
t2ADDrr = 2498,
|
|
t2ADDrs = 2499,
|
|
t2ADR = 2500,
|
|
t2ANDri = 2501,
|
|
t2ANDrr = 2502,
|
|
t2ANDrs = 2503,
|
|
t2ASRri = 2504,
|
|
t2ASRrr = 2505,
|
|
t2B = 2506,
|
|
t2BFC = 2507,
|
|
t2BFI = 2508,
|
|
t2BICri = 2509,
|
|
t2BICrr = 2510,
|
|
t2BICrs = 2511,
|
|
t2BR_JT = 2512,
|
|
t2BXJ = 2513,
|
|
t2Bcc = 2514,
|
|
t2CDP = 2515,
|
|
t2CDP2 = 2516,
|
|
t2CLREX = 2517,
|
|
t2CLZ = 2518,
|
|
t2CMNri = 2519,
|
|
t2CMNzrr = 2520,
|
|
t2CMNzrs = 2521,
|
|
t2CMPri = 2522,
|
|
t2CMPrr = 2523,
|
|
t2CMPrs = 2524,
|
|
t2CPS1p = 2525,
|
|
t2CPS2p = 2526,
|
|
t2CPS3p = 2527,
|
|
t2CRC32B = 2528,
|
|
t2CRC32CB = 2529,
|
|
t2CRC32CH = 2530,
|
|
t2CRC32CW = 2531,
|
|
t2CRC32H = 2532,
|
|
t2CRC32W = 2533,
|
|
t2DBG = 2534,
|
|
t2DCPS1 = 2535,
|
|
t2DCPS2 = 2536,
|
|
t2DCPS3 = 2537,
|
|
t2DMB = 2538,
|
|
t2DSB = 2539,
|
|
t2EORri = 2540,
|
|
t2EORrr = 2541,
|
|
t2EORrs = 2542,
|
|
t2HINT = 2543,
|
|
t2HVC = 2544,
|
|
t2ISB = 2545,
|
|
t2IT = 2546,
|
|
t2Int_eh_sjlj_setjmp = 2547,
|
|
t2Int_eh_sjlj_setjmp_nofp = 2548,
|
|
t2LDA = 2549,
|
|
t2LDAB = 2550,
|
|
t2LDAEX = 2551,
|
|
t2LDAEXB = 2552,
|
|
t2LDAEXD = 2553,
|
|
t2LDAEXH = 2554,
|
|
t2LDAH = 2555,
|
|
t2LDC2L_OFFSET = 2556,
|
|
t2LDC2L_OPTION = 2557,
|
|
t2LDC2L_POST = 2558,
|
|
t2LDC2L_PRE = 2559,
|
|
t2LDC2_OFFSET = 2560,
|
|
t2LDC2_OPTION = 2561,
|
|
t2LDC2_POST = 2562,
|
|
t2LDC2_PRE = 2563,
|
|
t2LDCL_OFFSET = 2564,
|
|
t2LDCL_OPTION = 2565,
|
|
t2LDCL_POST = 2566,
|
|
t2LDCL_PRE = 2567,
|
|
t2LDC_OFFSET = 2568,
|
|
t2LDC_OPTION = 2569,
|
|
t2LDC_POST = 2570,
|
|
t2LDC_PRE = 2571,
|
|
t2LDMDB = 2572,
|
|
t2LDMDB_UPD = 2573,
|
|
t2LDMIA = 2574,
|
|
t2LDMIA_RET = 2575,
|
|
t2LDMIA_UPD = 2576,
|
|
t2LDRBT = 2577,
|
|
t2LDRB_POST = 2578,
|
|
t2LDRB_PRE = 2579,
|
|
t2LDRBi12 = 2580,
|
|
t2LDRBi8 = 2581,
|
|
t2LDRBpci = 2582,
|
|
t2LDRBpcrel = 2583,
|
|
t2LDRBs = 2584,
|
|
t2LDRD_POST = 2585,
|
|
t2LDRD_PRE = 2586,
|
|
t2LDRDi8 = 2587,
|
|
t2LDREX = 2588,
|
|
t2LDREXB = 2589,
|
|
t2LDREXD = 2590,
|
|
t2LDREXH = 2591,
|
|
t2LDRHT = 2592,
|
|
t2LDRH_POST = 2593,
|
|
t2LDRH_PRE = 2594,
|
|
t2LDRHi12 = 2595,
|
|
t2LDRHi8 = 2596,
|
|
t2LDRHpci = 2597,
|
|
t2LDRHpcrel = 2598,
|
|
t2LDRHs = 2599,
|
|
t2LDRSBT = 2600,
|
|
t2LDRSB_POST = 2601,
|
|
t2LDRSB_PRE = 2602,
|
|
t2LDRSBi12 = 2603,
|
|
t2LDRSBi8 = 2604,
|
|
t2LDRSBpci = 2605,
|
|
t2LDRSBpcrel = 2606,
|
|
t2LDRSBs = 2607,
|
|
t2LDRSHT = 2608,
|
|
t2LDRSH_POST = 2609,
|
|
t2LDRSH_PRE = 2610,
|
|
t2LDRSHi12 = 2611,
|
|
t2LDRSHi8 = 2612,
|
|
t2LDRSHpci = 2613,
|
|
t2LDRSHpcrel = 2614,
|
|
t2LDRSHs = 2615,
|
|
t2LDRT = 2616,
|
|
t2LDR_POST = 2617,
|
|
t2LDR_PRE = 2618,
|
|
t2LDRi12 = 2619,
|
|
t2LDRi8 = 2620,
|
|
t2LDRpci = 2621,
|
|
t2LDRpci_pic = 2622,
|
|
t2LDRpcrel = 2623,
|
|
t2LDRs = 2624,
|
|
t2LEApcrel = 2625,
|
|
t2LEApcrelJT = 2626,
|
|
t2LSLri = 2627,
|
|
t2LSLrr = 2628,
|
|
t2LSRri = 2629,
|
|
t2LSRrr = 2630,
|
|
t2MCR = 2631,
|
|
t2MCR2 = 2632,
|
|
t2MCRR = 2633,
|
|
t2MCRR2 = 2634,
|
|
t2MLA = 2635,
|
|
t2MLS = 2636,
|
|
t2MOVCCasr = 2637,
|
|
t2MOVCCi = 2638,
|
|
t2MOVCCi16 = 2639,
|
|
t2MOVCCi32imm = 2640,
|
|
t2MOVCClsl = 2641,
|
|
t2MOVCClsr = 2642,
|
|
t2MOVCCr = 2643,
|
|
t2MOVCCror = 2644,
|
|
t2MOVSsi = 2645,
|
|
t2MOVSsr = 2646,
|
|
t2MOVTi16 = 2647,
|
|
t2MOVTi16_ga_pcrel = 2648,
|
|
t2MOV_ga_pcrel = 2649,
|
|
t2MOVi = 2650,
|
|
t2MOVi16 = 2651,
|
|
t2MOVi16_ga_pcrel = 2652,
|
|
t2MOVi32imm = 2653,
|
|
t2MOVr = 2654,
|
|
t2MOVsi = 2655,
|
|
t2MOVsr = 2656,
|
|
t2MOVsra_flag = 2657,
|
|
t2MOVsrl_flag = 2658,
|
|
t2MRC = 2659,
|
|
t2MRC2 = 2660,
|
|
t2MRRC = 2661,
|
|
t2MRRC2 = 2662,
|
|
t2MRS_AR = 2663,
|
|
t2MRS_M = 2664,
|
|
t2MRSbanked = 2665,
|
|
t2MRSsys_AR = 2666,
|
|
t2MSR_AR = 2667,
|
|
t2MSR_M = 2668,
|
|
t2MSRbanked = 2669,
|
|
t2MUL = 2670,
|
|
t2MVNCCi = 2671,
|
|
t2MVNi = 2672,
|
|
t2MVNr = 2673,
|
|
t2MVNs = 2674,
|
|
t2ORNri = 2675,
|
|
t2ORNrr = 2676,
|
|
t2ORNrs = 2677,
|
|
t2ORRri = 2678,
|
|
t2ORRrr = 2679,
|
|
t2ORRrs = 2680,
|
|
t2PKHBT = 2681,
|
|
t2PKHTB = 2682,
|
|
t2PLDWi12 = 2683,
|
|
t2PLDWi8 = 2684,
|
|
t2PLDWs = 2685,
|
|
t2PLDi12 = 2686,
|
|
t2PLDi8 = 2687,
|
|
t2PLDpci = 2688,
|
|
t2PLDs = 2689,
|
|
t2PLIi12 = 2690,
|
|
t2PLIi8 = 2691,
|
|
t2PLIpci = 2692,
|
|
t2PLIs = 2693,
|
|
t2QADD = 2694,
|
|
t2QADD16 = 2695,
|
|
t2QADD8 = 2696,
|
|
t2QASX = 2697,
|
|
t2QDADD = 2698,
|
|
t2QDSUB = 2699,
|
|
t2QSAX = 2700,
|
|
t2QSUB = 2701,
|
|
t2QSUB16 = 2702,
|
|
t2QSUB8 = 2703,
|
|
t2RBIT = 2704,
|
|
t2REV = 2705,
|
|
t2REV16 = 2706,
|
|
t2REVSH = 2707,
|
|
t2RFEDB = 2708,
|
|
t2RFEDBW = 2709,
|
|
t2RFEIA = 2710,
|
|
t2RFEIAW = 2711,
|
|
t2RORri = 2712,
|
|
t2RORrr = 2713,
|
|
t2RRX = 2714,
|
|
t2RSBSri = 2715,
|
|
t2RSBSrs = 2716,
|
|
t2RSBri = 2717,
|
|
t2RSBrr = 2718,
|
|
t2RSBrs = 2719,
|
|
t2SADD16 = 2720,
|
|
t2SADD8 = 2721,
|
|
t2SASX = 2722,
|
|
t2SBCri = 2723,
|
|
t2SBCrr = 2724,
|
|
t2SBCrs = 2725,
|
|
t2SBFX = 2726,
|
|
t2SDIV = 2727,
|
|
t2SEL = 2728,
|
|
t2SETPAN = 2729,
|
|
t2SG = 2730,
|
|
t2SHADD16 = 2731,
|
|
t2SHADD8 = 2732,
|
|
t2SHASX = 2733,
|
|
t2SHSAX = 2734,
|
|
t2SHSUB16 = 2735,
|
|
t2SHSUB8 = 2736,
|
|
t2SMC = 2737,
|
|
t2SMLABB = 2738,
|
|
t2SMLABT = 2739,
|
|
t2SMLAD = 2740,
|
|
t2SMLADX = 2741,
|
|
t2SMLAL = 2742,
|
|
t2SMLALBB = 2743,
|
|
t2SMLALBT = 2744,
|
|
t2SMLALD = 2745,
|
|
t2SMLALDX = 2746,
|
|
t2SMLALTB = 2747,
|
|
t2SMLALTT = 2748,
|
|
t2SMLATB = 2749,
|
|
t2SMLATT = 2750,
|
|
t2SMLAWB = 2751,
|
|
t2SMLAWT = 2752,
|
|
t2SMLSD = 2753,
|
|
t2SMLSDX = 2754,
|
|
t2SMLSLD = 2755,
|
|
t2SMLSLDX = 2756,
|
|
t2SMMLA = 2757,
|
|
t2SMMLAR = 2758,
|
|
t2SMMLS = 2759,
|
|
t2SMMLSR = 2760,
|
|
t2SMMUL = 2761,
|
|
t2SMMULR = 2762,
|
|
t2SMUAD = 2763,
|
|
t2SMUADX = 2764,
|
|
t2SMULBB = 2765,
|
|
t2SMULBT = 2766,
|
|
t2SMULL = 2767,
|
|
t2SMULTB = 2768,
|
|
t2SMULTT = 2769,
|
|
t2SMULWB = 2770,
|
|
t2SMULWT = 2771,
|
|
t2SMUSD = 2772,
|
|
t2SMUSDX = 2773,
|
|
t2SRSDB = 2774,
|
|
t2SRSDB_UPD = 2775,
|
|
t2SRSIA = 2776,
|
|
t2SRSIA_UPD = 2777,
|
|
t2SSAT = 2778,
|
|
t2SSAT16 = 2779,
|
|
t2SSAX = 2780,
|
|
t2SSUB16 = 2781,
|
|
t2SSUB8 = 2782,
|
|
t2STC2L_OFFSET = 2783,
|
|
t2STC2L_OPTION = 2784,
|
|
t2STC2L_POST = 2785,
|
|
t2STC2L_PRE = 2786,
|
|
t2STC2_OFFSET = 2787,
|
|
t2STC2_OPTION = 2788,
|
|
t2STC2_POST = 2789,
|
|
t2STC2_PRE = 2790,
|
|
t2STCL_OFFSET = 2791,
|
|
t2STCL_OPTION = 2792,
|
|
t2STCL_POST = 2793,
|
|
t2STCL_PRE = 2794,
|
|
t2STC_OFFSET = 2795,
|
|
t2STC_OPTION = 2796,
|
|
t2STC_POST = 2797,
|
|
t2STC_PRE = 2798,
|
|
t2STL = 2799,
|
|
t2STLB = 2800,
|
|
t2STLEX = 2801,
|
|
t2STLEXB = 2802,
|
|
t2STLEXD = 2803,
|
|
t2STLEXH = 2804,
|
|
t2STLH = 2805,
|
|
t2STMDB = 2806,
|
|
t2STMDB_UPD = 2807,
|
|
t2STMIA = 2808,
|
|
t2STMIA_UPD = 2809,
|
|
t2STRBT = 2810,
|
|
t2STRB_POST = 2811,
|
|
t2STRB_PRE = 2812,
|
|
t2STRB_preidx = 2813,
|
|
t2STRBi12 = 2814,
|
|
t2STRBi8 = 2815,
|
|
t2STRBs = 2816,
|
|
t2STRD_POST = 2817,
|
|
t2STRD_PRE = 2818,
|
|
t2STRDi8 = 2819,
|
|
t2STREX = 2820,
|
|
t2STREXB = 2821,
|
|
t2STREXD = 2822,
|
|
t2STREXH = 2823,
|
|
t2STRHT = 2824,
|
|
t2STRH_POST = 2825,
|
|
t2STRH_PRE = 2826,
|
|
t2STRH_preidx = 2827,
|
|
t2STRHi12 = 2828,
|
|
t2STRHi8 = 2829,
|
|
t2STRHs = 2830,
|
|
t2STRT = 2831,
|
|
t2STR_POST = 2832,
|
|
t2STR_PRE = 2833,
|
|
t2STR_preidx = 2834,
|
|
t2STRi12 = 2835,
|
|
t2STRi8 = 2836,
|
|
t2STRs = 2837,
|
|
t2SUBS_PC_LR = 2838,
|
|
t2SUBSri = 2839,
|
|
t2SUBSrr = 2840,
|
|
t2SUBSrs = 2841,
|
|
t2SUBri = 2842,
|
|
t2SUBri12 = 2843,
|
|
t2SUBrr = 2844,
|
|
t2SUBrs = 2845,
|
|
t2SXTAB = 2846,
|
|
t2SXTAB16 = 2847,
|
|
t2SXTAH = 2848,
|
|
t2SXTB = 2849,
|
|
t2SXTB16 = 2850,
|
|
t2SXTH = 2851,
|
|
t2TBB = 2852,
|
|
t2TBB_JT = 2853,
|
|
t2TBH = 2854,
|
|
t2TBH_JT = 2855,
|
|
t2TEQri = 2856,
|
|
t2TEQrr = 2857,
|
|
t2TEQrs = 2858,
|
|
t2TSTri = 2859,
|
|
t2TSTrr = 2860,
|
|
t2TSTrs = 2861,
|
|
t2TT = 2862,
|
|
t2TTA = 2863,
|
|
t2TTAT = 2864,
|
|
t2TTT = 2865,
|
|
t2UADD16 = 2866,
|
|
t2UADD8 = 2867,
|
|
t2UASX = 2868,
|
|
t2UBFX = 2869,
|
|
t2UDF = 2870,
|
|
t2UDIV = 2871,
|
|
t2UHADD16 = 2872,
|
|
t2UHADD8 = 2873,
|
|
t2UHASX = 2874,
|
|
t2UHSAX = 2875,
|
|
t2UHSUB16 = 2876,
|
|
t2UHSUB8 = 2877,
|
|
t2UMAAL = 2878,
|
|
t2UMLAL = 2879,
|
|
t2UMULL = 2880,
|
|
t2UQADD16 = 2881,
|
|
t2UQADD8 = 2882,
|
|
t2UQASX = 2883,
|
|
t2UQSAX = 2884,
|
|
t2UQSUB16 = 2885,
|
|
t2UQSUB8 = 2886,
|
|
t2USAD8 = 2887,
|
|
t2USADA8 = 2888,
|
|
t2USAT = 2889,
|
|
t2USAT16 = 2890,
|
|
t2USAX = 2891,
|
|
t2USUB16 = 2892,
|
|
t2USUB8 = 2893,
|
|
t2UXTAB = 2894,
|
|
t2UXTAB16 = 2895,
|
|
t2UXTAH = 2896,
|
|
t2UXTB = 2897,
|
|
t2UXTB16 = 2898,
|
|
t2UXTH = 2899,
|
|
tADC = 2900,
|
|
tADDframe = 2901,
|
|
tADDhirr = 2902,
|
|
tADDi3 = 2903,
|
|
tADDi8 = 2904,
|
|
tADDrSP = 2905,
|
|
tADDrSPi = 2906,
|
|
tADDrr = 2907,
|
|
tADDspi = 2908,
|
|
tADDspr = 2909,
|
|
tADJCALLSTACKDOWN = 2910,
|
|
tADJCALLSTACKUP = 2911,
|
|
tADR = 2912,
|
|
tAND = 2913,
|
|
tASRri = 2914,
|
|
tASRrr = 2915,
|
|
tB = 2916,
|
|
tBIC = 2917,
|
|
tBKPT = 2918,
|
|
tBL = 2919,
|
|
tBLXNSr = 2920,
|
|
tBLXi = 2921,
|
|
tBLXr = 2922,
|
|
tBRIND = 2923,
|
|
tBR_JTr = 2924,
|
|
tBX = 2925,
|
|
tBXNS = 2926,
|
|
tBX_CALL = 2927,
|
|
tBX_RET = 2928,
|
|
tBX_RET_vararg = 2929,
|
|
tBcc = 2930,
|
|
tBfar = 2931,
|
|
tCBNZ = 2932,
|
|
tCBZ = 2933,
|
|
tCMNz = 2934,
|
|
tCMPhir = 2935,
|
|
tCMPi8 = 2936,
|
|
tCMPr = 2937,
|
|
tCPS = 2938,
|
|
tEOR = 2939,
|
|
tHINT = 2940,
|
|
tHLT = 2941,
|
|
tInt_eh_sjlj_longjmp = 2942,
|
|
tInt_eh_sjlj_setjmp = 2943,
|
|
tLDMIA = 2944,
|
|
tLDMIA_UPD = 2945,
|
|
tLDRBi = 2946,
|
|
tLDRBr = 2947,
|
|
tLDRHi = 2948,
|
|
tLDRHr = 2949,
|
|
tLDRLIT_ga_abs = 2950,
|
|
tLDRLIT_ga_pcrel = 2951,
|
|
tLDRSB = 2952,
|
|
tLDRSH = 2953,
|
|
tLDRi = 2954,
|
|
tLDRpci = 2955,
|
|
tLDRpci_pic = 2956,
|
|
tLDRr = 2957,
|
|
tLDRspi = 2958,
|
|
tLEApcrel = 2959,
|
|
tLEApcrelJT = 2960,
|
|
tLSLri = 2961,
|
|
tLSLrr = 2962,
|
|
tLSRri = 2963,
|
|
tLSRrr = 2964,
|
|
tMOVCCr_pseudo = 2965,
|
|
tMOVSr = 2966,
|
|
tMOVi8 = 2967,
|
|
tMOVr = 2968,
|
|
tMUL = 2969,
|
|
tMVN = 2970,
|
|
tORR = 2971,
|
|
tPICADD = 2972,
|
|
tPOP = 2973,
|
|
tPOP_RET = 2974,
|
|
tPUSH = 2975,
|
|
tREV = 2976,
|
|
tREV16 = 2977,
|
|
tREVSH = 2978,
|
|
tROR = 2979,
|
|
tRSB = 2980,
|
|
tSBC = 2981,
|
|
tSETEND = 2982,
|
|
tSTMIA_UPD = 2983,
|
|
tSTRBi = 2984,
|
|
tSTRBr = 2985,
|
|
tSTRHi = 2986,
|
|
tSTRHr = 2987,
|
|
tSTRi = 2988,
|
|
tSTRr = 2989,
|
|
tSTRspi = 2990,
|
|
tSUBi3 = 2991,
|
|
tSUBi8 = 2992,
|
|
tSUBrr = 2993,
|
|
tSUBspi = 2994,
|
|
tSVC = 2995,
|
|
tSXTB = 2996,
|
|
tSXTH = 2997,
|
|
tTAILJMPd = 2998,
|
|
tTAILJMPdND = 2999,
|
|
tTAILJMPr = 3000,
|
|
tTPsoft = 3001,
|
|
tTRAP = 3002,
|
|
tTST = 3003,
|
|
tUDF = 3004,
|
|
tUXTB = 3005,
|
|
tUXTH = 3006,
|
|
INSTRUCTION_LIST_END = 3007
|
|
};
|
|
|
|
namespace Sched {
|
|
enum {
|
|
NoInstrModel = 0,
|
|
IIC_iALUi_WriteALU_ReadALU = 1,
|
|
IIC_iALUr_WriteALU_ReadALU_ReadALU = 2,
|
|
IIC_iALUsr_WriteALUsi_ReadALU = 3,
|
|
IIC_iALUsr_WriteALUsr_ReadALUsr = 4,
|
|
IIC_iALUsr_WriteALUSsr_ReadALUsr = 5,
|
|
IIC_iBITi_WriteALU_ReadALU = 6,
|
|
IIC_iBITr_WriteALU_ReadALU_ReadALU = 7,
|
|
IIC_iBITsr_WriteALUsi_ReadALU = 8,
|
|
IIC_iBITsr_WriteALUsr_ReadALUsr = 9,
|
|
IIC_Br_WriteBr = 10,
|
|
IIC_iUNAsi = 11,
|
|
IIC_Br_WriteBrL = 12,
|
|
WriteBrL = 13,
|
|
IIC_Br_WriteBrTbl = 14,
|
|
WriteBr = 15,
|
|
IIC_iUNAr_WriteALU = 16,
|
|
IIC_iCMPi_WriteCMP_ReadALU = 17,
|
|
IIC_iCMPr_WriteCMP_ReadALU_ReadALU = 18,
|
|
IIC_iCMPsr_WriteCMPsi_ReadALU = 19,
|
|
IIC_iCMPsr_WriteCMPsr_ReadALU = 20,
|
|
IIC_fpUNA64 = 21,
|
|
IIC_fpUNA16 = 22,
|
|
IIC_fpUNA32 = 23,
|
|
IIC_fpSTAT = 24,
|
|
IIC_iLoad_m = 25,
|
|
IIC_iLoad_mu = 26,
|
|
IIC_iLoad_mBr = 27,
|
|
IIC_iLoad_bh_ru = 28,
|
|
IIC_iLoad_bh_iu = 29,
|
|
IIC_iLoad_bh_r = 30,
|
|
IIC_iLoad_bh_si = 31,
|
|
IIC_iLoad_d_r = 32,
|
|
IIC_iLoad_d_ru = 33,
|
|
IIC_iLoad_i = 34,
|
|
IIC_iLoadiALU = 35,
|
|
IIC_iLoad_ru = 36,
|
|
IIC_iLoad_iu = 37,
|
|
IIC_iLoad_r = 38,
|
|
IIC_iLoad_si = 39,
|
|
IIC_iMAC32 = 40,
|
|
IIC_iCMOVi_WriteALU = 41,
|
|
IIC_iMOVi_WriteALU = 42,
|
|
IIC_iCMOVix2 = 43,
|
|
IIC_iCMOVr_WriteALU = 44,
|
|
IIC_iCMOVsr_WriteALU = 45,
|
|
IIC_iMOVix2addpc = 46,
|
|
IIC_iMOVix2ld = 47,
|
|
IIC_iMOVix2 = 48,
|
|
IIC_iMOVr_WriteALU = 49,
|
|
IIC_iMOVsr_WriteALU = 50,
|
|
IIC_iMOVsi_WriteALU = 51,
|
|
IIC_iMUL32 = 52,
|
|
IIC_iMVNi_WriteALU = 53,
|
|
IIC_iMVNr_WriteALU = 54,
|
|
IIC_iMVNsr_WriteALU = 55,
|
|
IIC_iALUr_WriteALU_ReadALU = 56,
|
|
IIC_iStore_r = 57,
|
|
IIC_iStore_bh_r = 58,
|
|
IIC_iALUsi_WriteALUsi_ReadALU = 59,
|
|
IIC_iBITsi_WriteALUsi_ReadALU = 60,
|
|
IIC_Preload_WritePreLd = 61,
|
|
IIC_iDIV = 62,
|
|
IIC_iMAC16 = 63,
|
|
IIC_iMAC64 = 64,
|
|
IIC_iMUL16 = 65,
|
|
IIC_iMUL64 = 66,
|
|
IIC_iStore_m = 67,
|
|
IIC_iStore_mu = 68,
|
|
IIC_iStore_bh_ru = 69,
|
|
IIC_iStore_bh_iu = 70,
|
|
IIC_iStore_ru = 71,
|
|
IIC_iStore_bh_si = 72,
|
|
IIC_iStore_d_r = 73,
|
|
IIC_iStore_d_ru = 74,
|
|
IIC_iStore_iu = 75,
|
|
IIC_iStore_si = 76,
|
|
IIC_Br = 77,
|
|
IIC_iEXTAr_WriteALUsr = 78,
|
|
IIC_iEXTr_WriteALUsi = 79,
|
|
IIC_iTSTi_WriteCMP_ReadALU = 80,
|
|
IIC_iTSTr_WriteCMP_ReadALU_ReadALU = 81,
|
|
IIC_iTSTsr_WriteCMPsi_ReadALU = 82,
|
|
IIC_iTSTsr_WriteCMPsr_ReadALU = 83,
|
|
WriteALU_ReadALU_ReadALU = 84,
|
|
IIC_VABAD = 85,
|
|
IIC_VABAQ = 86,
|
|
IIC_VSUBi4Q = 87,
|
|
IIC_VBIND = 88,
|
|
IIC_VBINQ = 89,
|
|
IIC_VSUBi4D = 90,
|
|
IIC_VUNAD = 91,
|
|
IIC_VUNAQ = 92,
|
|
IIC_VUNAiQ = 93,
|
|
IIC_VUNAiD = 94,
|
|
IIC_fpALU64 = 95,
|
|
IIC_fpALU16 = 96,
|
|
IIC_VBINi4D = 97,
|
|
IIC_VSHLiD = 98,
|
|
IIC_fpALU32 = 99,
|
|
IIC_VSUBiD = 100,
|
|
IIC_VBINiQ = 101,
|
|
IIC_VBINiD = 102,
|
|
IIC_VMOVImm = 103,
|
|
IIC_VCNTiD = 104,
|
|
IIC_VCNTiQ = 105,
|
|
IIC_fpCMP64 = 106,
|
|
IIC_fpCMP16 = 107,
|
|
IIC_fpCMP32 = 108,
|
|
IIC_fpCVTSH = 109,
|
|
IIC_fpCVTHS = 110,
|
|
IIC_fpCVTDS = 111,
|
|
IIC_fpCVTSD = 112,
|
|
IIC_fpDIV64 = 113,
|
|
IIC_fpDIV16 = 114,
|
|
IIC_fpDIV32 = 115,
|
|
IIC_VMOVIS = 116,
|
|
IIC_VMOVD = 117,
|
|
IIC_VMOVQ = 118,
|
|
IIC_VEXTD = 119,
|
|
IIC_VEXTQ = 120,
|
|
IIC_fpFMAC64 = 121,
|
|
IIC_fpFMAC16 = 122,
|
|
IIC_fpFMAC32 = 123,
|
|
IIC_VFMACD = 124,
|
|
IIC_VFMACQ = 125,
|
|
IIC_VMOVSI = 126,
|
|
IIC_VBINi4Q = 127,
|
|
IIC_VLD1dup = 128,
|
|
IIC_VLD1dupu = 129,
|
|
IIC_VLD1ln = 130,
|
|
IIC_VLD1lnu = 131,
|
|
IIC_VLD1 = 132,
|
|
IIC_VLD1x4 = 133,
|
|
IIC_VLD1x2u = 134,
|
|
IIC_VLD1x3 = 135,
|
|
IIC_VLD1u = 136,
|
|
IIC_VLD1x2 = 137,
|
|
IIC_VLD2dup = 138,
|
|
IIC_VLD2dupu = 139,
|
|
IIC_VLD2ln = 140,
|
|
IIC_VLD2lnu = 141,
|
|
IIC_VLD2 = 142,
|
|
IIC_VLD2u = 143,
|
|
IIC_VLD2x2 = 144,
|
|
IIC_VLD2x2u = 145,
|
|
IIC_VLD3dup = 146,
|
|
IIC_VLD3dupu = 147,
|
|
IIC_VLD3ln = 148,
|
|
IIC_VLD3lnu = 149,
|
|
IIC_VLD3 = 150,
|
|
IIC_VLD3u = 151,
|
|
IIC_VLD4dup = 152,
|
|
IIC_VLD4dupu = 153,
|
|
IIC_VLD4ln = 154,
|
|
IIC_VLD4lnu = 155,
|
|
IIC_VLD4 = 156,
|
|
IIC_VLD4u = 157,
|
|
IIC_fpLoad_mu = 158,
|
|
IIC_fpLoad_m = 159,
|
|
IIC_fpLoad64 = 160,
|
|
IIC_fpLoad16 = 161,
|
|
IIC_fpLoad32 = 162,
|
|
IIC_fpStore_m = 163,
|
|
IIC_fpMAC64 = 164,
|
|
IIC_fpMAC16 = 165,
|
|
IIC_VMACi32D = 166,
|
|
IIC_VMACi16D = 167,
|
|
IIC_fpMAC32 = 168,
|
|
IIC_VMACD = 169,
|
|
IIC_VMACQ = 170,
|
|
IIC_VMACi32Q = 171,
|
|
IIC_VMACi16Q = 172,
|
|
IIC_fpMOVID = 173,
|
|
IIC_fpMOVIS = 174,
|
|
IIC_VQUNAiD = 175,
|
|
IIC_VMOVN = 176,
|
|
IIC_fpMOVSI = 177,
|
|
IIC_fpMOVDI = 178,
|
|
IIC_fpMUL64 = 179,
|
|
IIC_fpMUL16 = 180,
|
|
IIC_VMULi16D = 181,
|
|
IIC_VMULi32D = 182,
|
|
IIC_fpMUL32 = 183,
|
|
IIC_VFMULD = 184,
|
|
IIC_VFMULQ = 185,
|
|
IIC_VMULi16Q = 186,
|
|
IIC_VMULi32Q = 187,
|
|
IIC_VSHLiQ = 188,
|
|
IIC_VPALiQ = 189,
|
|
IIC_VPALiD = 190,
|
|
IIC_VPBIND = 191,
|
|
IIC_VQUNAiQ = 192,
|
|
IIC_VSHLi4Q = 193,
|
|
IIC_VSHLi4D = 194,
|
|
IIC_VRECSD = 195,
|
|
IIC_VRECSQ = 196,
|
|
IIC_VMOVISL = 197,
|
|
IIC_fpCVTID_WriteCvtFP = 198,
|
|
IIC_fpCVTIH_WriteCvtFP = 199,
|
|
IIC_fpCVTIS_WriteCvtFP = 200,
|
|
IIC_fpCVTID = 201,
|
|
IIC_fpCVTIH = 202,
|
|
IIC_fpCVTIS = 203,
|
|
IIC_fpSQRT64 = 204,
|
|
IIC_fpSQRT16 = 205,
|
|
IIC_fpSQRT32 = 206,
|
|
IIC_VST1ln = 207,
|
|
IIC_VST1lnu = 208,
|
|
IIC_VST1 = 209,
|
|
IIC_VST1x4 = 210,
|
|
IIC_VLD1x4u = 211,
|
|
IIC_VST1x3 = 212,
|
|
IIC_VLD1x3u = 213,
|
|
IIC_VST1x4u = 214,
|
|
IIC_VST1x3u = 215,
|
|
IIC_VST1x2 = 216,
|
|
IIC_VST2ln = 217,
|
|
IIC_VST2lnu = 218,
|
|
IIC_VST2 = 219,
|
|
IIC_VST2x2 = 220,
|
|
IIC_VST2x2u = 221,
|
|
IIC_VST3ln = 222,
|
|
IIC_VST3lnu = 223,
|
|
IIC_VST3 = 224,
|
|
IIC_VST3u = 225,
|
|
IIC_VST4ln = 226,
|
|
IIC_VST4lnu = 227,
|
|
IIC_VST4 = 228,
|
|
IIC_VST4u = 229,
|
|
IIC_fpStore_mu = 230,
|
|
IIC_fpStore64 = 231,
|
|
IIC_fpStore16 = 232,
|
|
IIC_fpStore32 = 233,
|
|
IIC_VSUBiQ = 234,
|
|
IIC_VTB1 = 235,
|
|
IIC_VTB2 = 236,
|
|
IIC_VTB3 = 237,
|
|
IIC_VTB4 = 238,
|
|
IIC_VTBX1 = 239,
|
|
IIC_VTBX2 = 240,
|
|
IIC_VTBX3 = 241,
|
|
IIC_VTBX4 = 242,
|
|
IIC_fpCVTDI_WriteCvtFP = 243,
|
|
IIC_fpCVTHI_WriteCvtFP = 244,
|
|
IIC_fpCVTSI_WriteCvtFP = 245,
|
|
IIC_fpCVTDI = 246,
|
|
IIC_fpCVTHI = 247,
|
|
IIC_fpCVTSI = 248,
|
|
IIC_VPERMD = 249,
|
|
IIC_VPERMQ = 250,
|
|
IIC_VPERMQ3 = 251,
|
|
IIC_iALUsi_WriteALUsi_ReadALUsr = 252,
|
|
IIC_iBITi = 253,
|
|
IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 254,
|
|
IIC_iCMPi_WriteCMP = 255,
|
|
IIC_iCMPr_WriteCMP = 256,
|
|
IIC_iCMPsi_WriteCMPsi = 257,
|
|
IIC_iALUx = 258,
|
|
IIC_iLoad_bh_i = 259,
|
|
IIC_iLoad_d_i = 260,
|
|
IIC_iCMOVsi_WriteALU = 261,
|
|
IIC_iMOVi = 262,
|
|
IIC_iMVNsi_WriteALU = 263,
|
|
IIC_iALUsir_WriteALUsi_ReadALU = 264,
|
|
IIC_iStore_bh_i = 265,
|
|
IIC_iStore_i = 266,
|
|
IIC_iEXTAsr = 267,
|
|
IIC_iEXTr = 268,
|
|
IIC_iTSTi_WriteCMP = 269,
|
|
IIC_iTSTr_WriteCMP = 270,
|
|
IIC_iTSTsi_WriteCMPsi = 271,
|
|
IIC_iALUr_WriteALU = 272,
|
|
IIC_iALUi_WriteALU = 273,
|
|
IIC_iBITr_WriteALU = 274,
|
|
IIC_iPop = 275,
|
|
IIC_iPop_Br_WriteBrL = 276,
|
|
IIC_iTSTr_WriteALU = 277,
|
|
ANDri_BICri_EORri_ORRri = 278,
|
|
ANDrr_BICrr_EORrr_ORRrr = 279,
|
|
ANDrsi_BICrsi_EORrsi_ORRrsi = 280,
|
|
ANDrsr_BICrsr_EORrsr_ORRrsr = 281,
|
|
MOVCCsi_MOVCCsr = 282,
|
|
MOVsi_MOVsr = 283,
|
|
MOVsra_flag_MOVsrl_flag = 284,
|
|
MVNsr = 285,
|
|
MVNr = 286,
|
|
MOVCCi32imm = 287,
|
|
MOVi32imm = 288,
|
|
MOV_ga_pcrel = 289,
|
|
MOV_ga_pcrel_ldr = 290,
|
|
SEL = 291,
|
|
BFC_BFI_SBFX_UBFX = 292,
|
|
MLA_MLAv5_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 293,
|
|
MUL_MULv5_SMMUL_SMMULR = 294,
|
|
SMLAL_SMLALBB_SMLALBT_SMLALTB_SMLALTT_SMLALv5_UMAAL_UMLAL_UMLALv5 = 295,
|
|
SMULL_SMULLv5_UMULL_UMULLv5 = 296,
|
|
SMLAD_SMLADX_SMLALD_SMLALDX_SMLSD_SMLSDX_SMLSLD_SMLSLDX_SMUAD_SMUADX_SMUSD_SMUSDX = 297,
|
|
SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 298,
|
|
SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 299,
|
|
LDRi12_PICLDR = 300,
|
|
LDRrs = 301,
|
|
LDRBi12_LDRH_LDRSB_LDRSH_PICLDRB_PICLDRH_PICLDRSB_PICLDRSH = 302,
|
|
LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE = 303,
|
|
SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 304,
|
|
t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 305,
|
|
t2MOVCCi32imm = 306,
|
|
t2MOVi32imm = 307,
|
|
t2MOV_ga_pcrel = 308,
|
|
t2MOVi16_ga_pcrel = 309,
|
|
t2SEL = 310,
|
|
t2BFC_t2SBFX_t2UBFX = 311,
|
|
t2BFI = 312,
|
|
QADD_QADD16_QADD8_QASX_QDADD_QDSUB_QSAX_QSUB_QSUB16_QSUB8_UQADD16_UQADD8_UQASX_UQSAX_UQSUB16_UQSUB8 = 313,
|
|
SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QASX_t2QDADD_t2QDSUB_t2QSAX_t2QSUB_t2QSUB16_t2QSUB8_t2SSAT_t2SSAT16_t2UQADD16_t2UQADD8_t2UQASX_t2UQSAX_t2UQSUB16_t2UQSUB8_t2USAT_t2USAT16 = 314,
|
|
SADD16_SADD8_SASX_SSAX_SSUB16_SSUB8_UADD16_UADD8_UASX_USAX_USUB16_USUB8 = 315,
|
|
t2SADD16_t2SADD8_t2SASX_t2SSAX_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2UASX_t2USAX_t2USUB16_t2USUB8 = 316,
|
|
SHADD16_SHADD8_SHASX_SHSAX_SHSUB16_SHSUB8_UHADD16_UHADD8_UHASX_UHSAX_UHSUB16_UHSUB8 = 317,
|
|
SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 318,
|
|
t2SHADD16_t2SHADD8_t2SHASX_t2SHSAX_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHASX_t2UHSAX_t2UHSUB16_t2UHSUB8 = 319,
|
|
t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 320,
|
|
USAD8 = 321,
|
|
USADA8 = 322,
|
|
SMUSD_SMUSDX = 323,
|
|
t2MUL_t2SMMUL_t2SMMULR = 324,
|
|
t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 325,
|
|
t2SMUSD_t2SMUSDX = 326,
|
|
t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 327,
|
|
SMUAD_SMUADX = 328,
|
|
t2SMUAD_t2SMUADX = 329,
|
|
SMLSD_SMLSDX = 330,
|
|
t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 331,
|
|
t2SMLSD_t2SMLSDX = 332,
|
|
SMLAD_SMLADX = 333,
|
|
t2SMLAD_t2SMLADX = 334,
|
|
SMULL_UMULL = 335,
|
|
t2SMULL_t2UMULL = 336,
|
|
t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2SMLSLD_t2SMLSLDX_t2UMAAL_t2UMLAL = 337,
|
|
SDIV_UDIV_t2SDIV_t2UDIV = 338,
|
|
LDRBi12 = 339,
|
|
LDRBrs_t2LDRBs_t2LDRHs = 340,
|
|
LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic = 341,
|
|
LDRi12 = 342,
|
|
t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci_tLDRBi_tLDRHi = 343,
|
|
t2LDRi12_t2LDRi8_t2LDRpci_tLDRi_tLDRpci_tLDRspi = 344,
|
|
t2LDRpci_pic = 345,
|
|
t2LDRs = 346,
|
|
tLDRBr_tLDRHr = 347,
|
|
tLDRr = 348,
|
|
LDRH_PICLDRB_PICLDRH = 349,
|
|
LDRcp = 350,
|
|
t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 351,
|
|
t2LDRSBpcrel_t2LDRSHpcrel = 352,
|
|
t2LDRSBs_t2LDRSHs = 353,
|
|
tLDRSB_tLDRSH = 354,
|
|
LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG = 355,
|
|
LDRB_POST_IMM_LDRB_PRE_IMM_t2LDRB_POST_t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 356,
|
|
LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE = 357,
|
|
LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG = 358,
|
|
LDR_POST_IMM_LDR_PRE_IMM_t2LDR_POST_t2LDR_PRE = 359,
|
|
t2LDRBT_t2LDRHT = 360,
|
|
t2LDRT = 361,
|
|
t2LDRSBT_t2LDRSHT = 362,
|
|
t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 363,
|
|
LDRD = 364,
|
|
t2LDRDi8 = 365,
|
|
LDRD_POST_LDRD_PRE_t2LDRD_POST_t2LDRD_PRE = 366,
|
|
LDMDA_LDMDB_LDMIA_LDMIB_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_t2LDMDB_t2LDMIA_tLDMIA = 367,
|
|
LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD_tLDMIA_UPD = 368,
|
|
LDMIA_RET_t2LDMIA_RET = 369,
|
|
tPOP = 370,
|
|
tPOP_RET = 371,
|
|
PICSTR_STRi12_tSTRr = 372,
|
|
PICSTRB_PICSTRH_STRBi12_STRH_tSTRBr_tSTRHr = 373,
|
|
STRBrs_t2STRBs_t2STRHs = 374,
|
|
STREX_STREXB_STREXD_STREXH = 375,
|
|
STRrs_t2STRs = 376,
|
|
t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8_tSTRBi_tSTRHi = 377,
|
|
t2STRi12_t2STRi8_tSTRi_tSTRspi = 378,
|
|
STRBT_POST_STRT_POST = 379,
|
|
STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRHTi_STRHTr_STRH_POST_STRH_PRE = 380,
|
|
STRB_POST_IMM_STRB_PRE_IMM_t2STRB_POST_t2STRB_PRE_t2STRH_POST = 381,
|
|
STRBi_preidx_STRBr_preidx_STRH_preidx_STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_t2STRB_preidx_t2STRH_preidx_t2STR_preidx = 382,
|
|
STR_POST_IMM_STR_PRE_IMM_t2STRH_PRE_t2STR_POST_t2STR_PRE = 383,
|
|
t2STRBT_t2STRHT = 384,
|
|
t2STRT = 385,
|
|
STRD_t2STRDi8 = 386,
|
|
STRD_POST_STRD_PRE_t2STRD_POST_t2STRD_PRE = 387,
|
|
STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 388,
|
|
STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 389,
|
|
tPUSH = 390,
|
|
LDRLIT_ga_abs_tLDRLIT_ga_abs = 391,
|
|
LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel = 392,
|
|
LDRLIT_ga_pcrel_ldr = 393,
|
|
ITasm = 394,
|
|
t2IT = 395,
|
|
VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VNEGs16d_VNEGs32d_VNEGs8d_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VPADDi16_VPADDi32_VPADDi8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 396,
|
|
VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16_VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8 = 397,
|
|
VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VBIFq_VBITq_VEORq_VORNq_VORRq = 398,
|
|
VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VBIFd_VBITd_VEORd_VORNd_VORRd = 399,
|
|
VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 400,
|
|
VBSLd_VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 401,
|
|
VBSLq_VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 402,
|
|
VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 403,
|
|
VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8 = 404,
|
|
VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 405,
|
|
VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 406,
|
|
VNEGf32q = 407,
|
|
VNEGfd = 408,
|
|
VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 409,
|
|
VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8 = 410,
|
|
VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 411,
|
|
VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 412,
|
|
VEXTd16_VEXTd32_VEXTd8 = 413,
|
|
VEXTq16_VEXTq32_VEXTq64_VEXTq8 = 414,
|
|
VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8 = 415,
|
|
VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8 = 416,
|
|
VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 417,
|
|
VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 418,
|
|
VABSfd = 419,
|
|
VABSfq = 420,
|
|
VABSv16i8_VABSv4i32_VABSv8i16 = 421,
|
|
VABSv2i32_VABSv4i16_VABSv8i8 = 422,
|
|
VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 423,
|
|
VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 424,
|
|
VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 425,
|
|
VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8 = 426,
|
|
VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8 = 427,
|
|
VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 428,
|
|
VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 429,
|
|
VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 430,
|
|
VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 431,
|
|
VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 432,
|
|
VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 433,
|
|
VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16_VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 434,
|
|
VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 435,
|
|
VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd = 436,
|
|
VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq = 437,
|
|
VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 438,
|
|
VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 439,
|
|
VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8 = 440,
|
|
VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 441,
|
|
VTBL1 = 442,
|
|
VTBX1 = 443,
|
|
VTBL2 = 444,
|
|
VTBX2 = 445,
|
|
VTBL3_VTBL3Pseudo = 446,
|
|
VTBX3_VTBX3Pseudo = 447,
|
|
VTBL4_VTBL4Pseudo = 448,
|
|
VTBX4_VTBX4Pseudo = 449,
|
|
VSWPd_VSWPq = 450,
|
|
VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8 = 451,
|
|
VTRNq16_VTRNq32_VTRNq8 = 452,
|
|
VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 453,
|
|
VABSD_VNEGD = 454,
|
|
VABSS_VNEGS = 455,
|
|
VCMPD_VCMPED_VCMPEZD_VCMPZD = 456,
|
|
VCMPES_VCMPEZS_VCMPS_VCMPZS = 457,
|
|
VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 458,
|
|
VABDfd_VABDhd_VADDfd_VMAXfd_VMAXhd_VMINfd_VMINhd_VSUBfd = 459,
|
|
VABDfq_VABDhq_VADDfq_VMAXfq_VMAXhq_VMINfq_VMINhq_VSUBfq = 460,
|
|
VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 461,
|
|
VADDS_VSUBS = 462,
|
|
VMAXNMD_VMAXNMH_VMAXNMNDf_VMAXNMNDh_VMAXNMNQf_VMAXNMNQh_VMAXNMS_VMINNMD_VMINNMH_VMINNMNDf_VMINNMNDh_VMINNMNQf_VMINNMNQh_VMINNMS = 463,
|
|
VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh = 464,
|
|
VADDD_VSUBD = 465,
|
|
VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 466,
|
|
VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 467,
|
|
VMULLp64 = 468,
|
|
VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16 = 469,
|
|
VMULLsv2i64_VMULLuv2i64_VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32 = 470,
|
|
VMULS_VNMULS = 471,
|
|
VMULfd = 472,
|
|
VMULfq = 473,
|
|
VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 474,
|
|
VMULslfd = 475,
|
|
VMULslfq = 476,
|
|
VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 477,
|
|
VMULD_VNMULD = 478,
|
|
VFMAD_VFMSD_VFNMAD_VFNMSD = 479,
|
|
VFMAS_VFMSS_VFNMAS_VFNMSS = 480,
|
|
VFNMAH_VFNMSH = 481,
|
|
VMLAD_VMLSD_VNMLAD_VNMLSD = 482,
|
|
VMLAH_VMLSH_VNMLAH_VNMLSH = 483,
|
|
VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 484,
|
|
VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 485,
|
|
VMLAS_VMLSS_VNMLAS_VNMLSS = 486,
|
|
VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 487,
|
|
VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 488,
|
|
VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 489,
|
|
VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 490,
|
|
VFMAfd_VFMSfd = 491,
|
|
VFMAfq_VFMSfq = 492,
|
|
VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTBHD_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 493,
|
|
VCVTBHS_VCVTTHS = 494,
|
|
VCVTBSH_VCVTTSH = 495,
|
|
VCVTDS = 496,
|
|
VCVTSD = 497,
|
|
VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 498,
|
|
VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 499,
|
|
VSITOD_VUITOD = 500,
|
|
VSITOH_VUITOH = 501,
|
|
VSITOS_VUITOS = 502,
|
|
VTOSHD_VTOSLD_VTOUHD_VTOULD = 503,
|
|
VTOSHH_VTOSLH_VTOUHH_VTOULH = 504,
|
|
VTOSHS_VTOSLS_VTOUHS_VTOULS = 505,
|
|
VTOSIRD_VTOSIZD_VTOUIRD_VTOUIZD = 506,
|
|
VTOSIRH_VTOSIZH_VTOUIRH_VTOUIZH = 507,
|
|
VTOSIRS_VTOSIZS_VTOUIRS_VTOUIZS = 508,
|
|
FCONSTD_VMOVD_VMOVDcc = 509,
|
|
FCONSTS_VMOVS_VMOVScc = 510,
|
|
VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 511,
|
|
VMVNd_VMVNq = 512,
|
|
VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 513,
|
|
VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 514,
|
|
VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8 = 515,
|
|
VDUPLN16d_VDUPLN32d_VDUPLN8d = 516,
|
|
VDUPLN16q_VDUPLN32q_VDUPLN8q = 517,
|
|
VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 518,
|
|
VMOVRS = 519,
|
|
VMOVSR = 520,
|
|
VSETLNi16_VSETLNi32_VSETLNi8 = 521,
|
|
VMOVRRD_VMOVRRS = 522,
|
|
VMOVDRR = 523,
|
|
VMOVSRR = 524,
|
|
VGETLNi32_VGETLNu16_VGETLNu8 = 525,
|
|
VGETLNs16_VGETLNs8 = 526,
|
|
VMRS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2 = 527,
|
|
VMSR_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSID = 528,
|
|
FMSTAT = 529,
|
|
VLDRD = 530,
|
|
VLDRS = 531,
|
|
VSTRD = 532,
|
|
VSTRS = 533,
|
|
VLDMQIA = 534,
|
|
VSTMQIA = 535,
|
|
VLDMDIA_VLDMSIA = 536,
|
|
VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 537,
|
|
VSTMDIA_VSTMSIA = 538,
|
|
VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 539,
|
|
VLD1d16_VLD1d32_VLD1d64_VLD1d8 = 540,
|
|
VLD1q16_VLD1q32_VLD1q64_VLD1q8 = 541,
|
|
VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 542,
|
|
VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 543,
|
|
VLD1d16T_VLD1d32T_VLD1d64T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register_VLD1d8T = 544,
|
|
VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 545,
|
|
VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register_VLD1d8Q = 546,
|
|
VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 547,
|
|
VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 548,
|
|
VLD2q16_VLD2q16Pseudo_VLD2q32_VLD2q32Pseudo_VLD2q8_VLD2q8Pseudo = 549,
|
|
VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 550,
|
|
VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register_VLD2q8wb_fixed_VLD2q8wb_register = 551,
|
|
VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 552,
|
|
VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo = 553,
|
|
VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 554,
|
|
VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 555,
|
|
VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 556,
|
|
VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo = 557,
|
|
VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 558,
|
|
VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 559,
|
|
VLD1DUPd16_VLD1DUPd32_VLD1DUPd8_VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 560,
|
|
VLD1LNd16_VLD1LNd32_VLD1LNd8_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo = 561,
|
|
VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_fixed_VLD1DUPq16wb_register_VLD1DUPq32wb_fixed_VLD1DUPq32wb_register_VLD1DUPq8wb_fixed_VLD1DUPq8wb_register = 562,
|
|
VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 563,
|
|
VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 564,
|
|
VLD2LNd16_VLD2LNd16Pseudo_VLD2LNd32_VLD2LNd32Pseudo_VLD2LNd8_VLD2LNd8Pseudo_VLD2LNq16_VLD2LNq16Pseudo_VLD2LNq32_VLD2LNq32Pseudo = 565,
|
|
VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD = 566,
|
|
VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 567,
|
|
VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD = 568,
|
|
VLD3DUPd16_VLD3DUPd16Pseudo_VLD3DUPd32_VLD3DUPd32Pseudo_VLD3DUPd8_VLD3DUPd8Pseudo_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8 = 569,
|
|
VLD3LNd16_VLD3LNd16Pseudo_VLD3LNd32_VLD3LNd32Pseudo_VLD3LNd8_VLD3LNd8Pseudo_VLD3LNq16_VLD3LNq16Pseudo_VLD3LNq32_VLD3LNq32Pseudo = 570,
|
|
VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 571,
|
|
VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD = 572,
|
|
VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 573,
|
|
VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD = 574,
|
|
VLD4DUPd16_VLD4DUPd16Pseudo_VLD4DUPd32_VLD4DUPd32Pseudo_VLD4DUPd8_VLD4DUPd8Pseudo_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 575,
|
|
VLD4LNd16_VLD4LNd16Pseudo_VLD4LNd32_VLD4LNd32Pseudo_VLD4LNd8_VLD4LNd8Pseudo_VLD4LNq16_VLD4LNq16Pseudo_VLD4LNq32_VLD4LNq32Pseudo = 576,
|
|
VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 577,
|
|
VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD = 578,
|
|
VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 579,
|
|
VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD = 580,
|
|
VST1d16_VST1d32_VST1d64_VST1d8 = 581,
|
|
VST1q16_VST1q32_VST1q64_VST1q8 = 582,
|
|
VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 583,
|
|
VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 584,
|
|
VST1d16T_VST1d32T_VST1d64T_VST1d64TPseudo_VST1d8T = 585,
|
|
VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 586,
|
|
VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register = 587,
|
|
VST1d16Q_VST1d32Q_VST1d64Q_VST1d64QPseudo_VST1d8Q = 588,
|
|
VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 589,
|
|
VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register = 590,
|
|
VST2b16_VST2b32_VST2b8_VST2d16_VST2d32_VST2d8 = 591,
|
|
VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 592,
|
|
VST2q16_VST2q16Pseudo_VST2q32_VST2q32Pseudo_VST2q8_VST2q8Pseudo = 593,
|
|
VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register = 594,
|
|
VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register = 595,
|
|
VST3d16_VST3d16Pseudo_VST3d32_VST3d32Pseudo_VST3d8_VST3d8Pseudo_VST3q16_VST3q16oddPseudo_VST3q32_VST3q32oddPseudo_VST3q8_VST3q8oddPseudo = 596,
|
|
VST3d16Pseudo_UPD_VST3d16_UPD_VST3d32Pseudo_UPD_VST3d32_UPD_VST3d8Pseudo_UPD_VST3d8_UPD_VST3q16Pseudo_UPD_VST3q16_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8_UPD_VST3q8oddPseudo_UPD = 597,
|
|
VST4d16_VST4d16Pseudo_VST4d32_VST4d32Pseudo_VST4d8_VST4d8Pseudo_VST4q16_VST4q16oddPseudo_VST4q32_VST4q32oddPseudo_VST4q8_VST4q8oddPseudo = 598,
|
|
VST4d16Pseudo_UPD_VST4d16_UPD_VST4d32Pseudo_UPD_VST4d32_UPD_VST4d8Pseudo_UPD_VST4d8_UPD_VST4q16Pseudo_UPD_VST4q16_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8_UPD_VST4q8oddPseudo_UPD = 599,
|
|
VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 600,
|
|
VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 601,
|
|
VST2LNd16_VST2LNd16Pseudo_VST2LNd32_VST2LNd32Pseudo_VST2LNd8_VST2LNd8Pseudo_VST2LNq16_VST2LNq16Pseudo_VST2LNq32_VST2LNq32Pseudo = 602,
|
|
VST2LNd16Pseudo_UPD_VST2LNd16_UPD_VST2LNd32Pseudo_UPD_VST2LNd32_UPD_VST2LNd8Pseudo_UPD_VST2LNd8_UPD_VST2LNq16Pseudo_UPD_VST2LNq16_UPD_VST2LNq32Pseudo_UPD_VST2LNq32_UPD = 603,
|
|
VST3LNd16_VST3LNd16Pseudo_VST3LNd32_VST3LNd32Pseudo_VST3LNd8_VST3LNd8Pseudo_VST3LNq16_VST3LNq16Pseudo_VST3LNq32_VST3LNq32Pseudo = 604,
|
|
VST3LNd16Pseudo_UPD_VST3LNd16_UPD_VST3LNd32Pseudo_UPD_VST3LNd32_UPD_VST3LNd8Pseudo_UPD_VST3LNd8_UPD_VST3LNq16Pseudo_UPD_VST3LNq16_UPD_VST3LNq32Pseudo_UPD_VST3LNq32_UPD = 605,
|
|
VST4LNd16_VST4LNd16Pseudo_VST4LNd32_VST4LNd32Pseudo_VST4LNd8_VST4LNd8Pseudo_VST4LNq16_VST4LNq16Pseudo_VST4LNq32_VST4LNq32Pseudo = 606,
|
|
VST4LNd16Pseudo_UPD_VST4LNd16_UPD_VST4LNd32Pseudo_UPD_VST4LNd32_UPD_VST4LNd8Pseudo_UPD_VST4LNd8_UPD_VST4LNq16Pseudo_UPD_VST4LNq16_UPD_VST4LNq32Pseudo_UPD_VST4LNq32_UPD = 607,
|
|
VDIVS = 608,
|
|
VSQRTS = 609,
|
|
VDIVD = 610,
|
|
VSQRTD = 611,
|
|
ABS = 612,
|
|
SCHED_LIST_END = 613
|
|
};
|
|
} // end Sched namespace
|
|
} // end ARM namespace
|
|
} // end llvm namespace
|
|
#endif // GET_INSTRINFO_ENUM
|
|
|
|
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|
|
|* *|
|
|
|* Target Instruction Descriptors *|
|
|
|* *|
|
|
|* Automatically generated file, do not edit! *|
|
|
|* *|
|
|
\*===----------------------------------------------------------------------===*/
|
|
|
|
|
|
#ifdef GET_INSTRINFO_MC_DESC
|
|
#undef GET_INSTRINFO_MC_DESC
|
|
namespace llvm_ks {
|
|
|
|
static const MCPhysReg ImplicitList1[] = { ARM::CPSR, 0 };
|
|
static const MCPhysReg ImplicitList2[] = { ARM::SP, 0 };
|
|
static const MCPhysReg ImplicitList3[] = { ARM::LR, 0 };
|
|
static const MCPhysReg ImplicitList4[] = { ARM::PC, 0 };
|
|
static const MCPhysReg ImplicitList5[] = { ARM::FPSCR_NZCV, 0 };
|
|
static const MCPhysReg ImplicitList6[] = { ARM::R7, ARM::LR, ARM::SP, 0 };
|
|
static const MCPhysReg ImplicitList7[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
|
|
static const MCPhysReg ImplicitList8[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
|
|
static const MCPhysReg ImplicitList9[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
|
|
static const MCPhysReg ImplicitList10[] = { ARM::FPSCR, 0 };
|
|
static const MCPhysReg ImplicitList11[] = { ARM::R4, 0 };
|
|
static const MCPhysReg ImplicitList12[] = { ARM::R4, ARM::SP, 0 };
|
|
static const MCPhysReg ImplicitList13[] = { ARM::ITSTATE, 0 };
|
|
static const MCPhysReg ImplicitList14[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
|
|
static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 };
|
|
|
|
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo13[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo14[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo15[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo16[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo17[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo20[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo21[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo22[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo25[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo26[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo27[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo28[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo33[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo34[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo35[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo37[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo38[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo39[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo41[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo44[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo46[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo48[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo49[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo50[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo51[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo52[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo53[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo54[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo55[] = { { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo56[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
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static const MCOperandInfo OperandInfo57[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo58[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo59[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo60[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo61[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo62[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo63[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo64[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo65[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo66[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo67[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo68[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo69[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo70[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo71[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo73[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo74[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo75[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo76[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo77[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo78[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo79[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo80[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo81[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo82[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo83[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo84[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo85[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo86[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo87[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo88[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo89[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo90[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo91[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo92[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo93[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo94[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo95[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo96[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo97[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo98[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo99[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo100[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo101[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo102[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo103[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
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static const MCOperandInfo OperandInfo104[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
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static const MCOperandInfo OperandInfo105[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo106[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo107[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo108[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo109[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo110[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo113[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo114[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo115[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo116[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo117[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo118[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo119[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo120[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo121[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo122[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo123[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo124[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo125[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo126[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo127[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo128[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo129[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo130[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo131[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo132[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo133[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo134[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo135[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo136[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo137[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo138[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo139[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo140[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo141[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo142[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo143[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo144[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo145[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo146[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo147[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo148[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo149[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo150[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo151[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo152[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo153[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo154[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo155[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo156[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo157[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo158[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo159[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo160[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo161[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo162[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo163[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo164[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo165[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo166[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo167[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo168[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo169[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo170[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo171[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo172[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo173[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo174[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo175[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo176[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo177[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo178[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo179[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo180[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo181[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo182[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo183[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo184[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo185[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo186[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo187[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo188[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo189[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo190[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo191[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo192[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo193[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((4 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo194[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo195[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((4 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo196[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo197[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo198[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo199[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo200[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo201[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo202[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo203[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo204[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo205[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo206[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo207[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo208[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo209[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo210[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo211[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo212[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo213[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo214[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo215[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo216[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo217[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo218[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo219[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo220[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo221[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo222[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo223[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo224[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo225[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo226[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo227[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo228[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo229[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo230[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo231[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo232[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo233[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo234[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo235[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo236[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo237[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo238[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo239[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo240[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo241[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo242[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo243[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo244[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo245[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo246[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo247[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo248[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo249[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo250[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo251[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo252[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo253[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo254[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo255[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo256[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo257[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo258[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo259[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo260[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo261[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo262[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo263[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo264[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo265[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo266[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo267[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo268[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo269[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo270[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo271[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo272[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo273[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo274[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo275[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo276[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo277[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo278[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo279[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo280[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo281[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo282[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo283[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo284[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo285[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo286[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo287[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo288[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo289[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo290[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo291[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo292[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo293[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo294[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo295[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo296[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo297[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo298[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo299[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo300[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo301[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo302[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo303[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo304[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo305[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo306[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo307[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo308[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo309[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo310[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo311[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo312[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo313[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo314[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo315[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo316[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo317[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo318[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo319[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo320[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo321[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo322[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo323[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo324[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo325[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo326[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo327[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo328[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo329[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo330[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo331[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo332[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo333[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo334[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo335[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo336[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo337[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo338[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo339[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo340[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo341[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo342[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo343[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo344[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo345[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo346[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo347[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo348[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo349[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
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static const MCOperandInfo OperandInfo350[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
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static const MCOperandInfo OperandInfo351[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo352[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
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static const MCOperandInfo OperandInfo353[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo354[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo355[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo356[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo357[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo358[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo359[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo360[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo361[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo362[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo363[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo364[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo365[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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static const MCOperandInfo OperandInfo366[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
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extern const MCInstrDesc ARMInsts[] = {
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{ 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #0 = PHI
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{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
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{ 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2 = CFI_INSTRUCTION
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{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #3 = EH_LABEL
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{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #4 = GC_LABEL
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{ 5, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #5 = KILL
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{ 6, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = EXTRACT_SUBREG
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{ 7, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #7 = INSERT_SUBREG
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{ 8, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #8 = IMPLICIT_DEF
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{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #9 = SUBREG_TO_REG
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{ 10, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #10 = COPY_TO_REGCLASS
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{ 11, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11 = DBG_VALUE
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{ 12, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #12 = REG_SEQUENCE
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{ 13, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #13 = COPY
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{ 14, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #14 = BUNDLE
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{ 15, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #15 = LIFETIME_START
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{ 16, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #16 = LIFETIME_END
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{ 17, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #17 = STACKMAP
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{ 18, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #18 = PATCHPOINT
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{ 19, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #19 = LOAD_STACK_GUARD
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{ 20, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #20 = STATEPOINT
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{ 21, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #21 = LOCAL_ESCAPE
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{ 22, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #22 = FAULTING_LOAD_OP
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{ 23, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #23 = G_ADD
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{ 24, 2, 1, 8, 612, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #24 = ABS
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{ 25, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #25 = ADCri
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{ 26, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr }, // Inst #26 = ADCrr
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{ 27, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo16, -1 ,nullptr }, // Inst #27 = ADCrsi
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{ 28, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #28 = ADCrsr
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{ 29, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #29 = ADDSri
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{ 30, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19, -1 ,nullptr }, // Inst #30 = ADDSrr
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{ 31, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr }, // Inst #31 = ADDSrsi
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{ 32, 7, 1, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr }, // Inst #32 = ADDSrsr
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|
{ 33, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #33 = ADDri
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{ 34, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #34 = ADDrr
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{ 35, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #35 = ADDrsi
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{ 36, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #36 = ADDrsr
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{ 37, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo23, -1 ,nullptr }, // Inst #37 = ADJCALLSTACKDOWN
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{ 38, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo24, -1 ,nullptr }, // Inst #38 = ADJCALLSTACKUP
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{ 39, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xd01ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #39 = ADR
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|
{ 40, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #40 = AESD
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{ 41, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #41 = AESE
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|
{ 42, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #42 = AESIMC
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{ 43, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #43 = AESMC
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{ 44, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = ANDri
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{ 45, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #45 = ANDrr
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{ 46, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #46 = ANDrsi
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{ 47, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #47 = ANDrsr
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{ 48, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #48 = ASRi
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{ 49, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #49 = ASRr
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{ 50, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #50 = B
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{ 51, 4, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr }, // Inst #51 = BCCZi64
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{ 52, 6, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #52 = BCCi64
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{ 53, 5, 1, 4, 292, 0|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #53 = BFC
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{ 54, 6, 1, 4, 292, 0|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #54 = BFI
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{ 55, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #55 = BICri
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{ 56, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #56 = BICrr
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{ 57, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #57 = BICrsi
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{ 58, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #58 = BICrsr
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{ 59, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #59 = BKPT
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{ 60, 1, 0, 4, 12, 0|(1ULL<<MCID::Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo29, -1 ,nullptr }, // Inst #60 = BL
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{ 61, 1, 0, 4, 12, 0|(1ULL<<MCID::Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #61 = BLX
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{ 62, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo35, -1 ,nullptr }, // Inst #62 = BLX_pred
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{ 63, 1, 0, 4, 13, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #63 = BLXi
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{ 64, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #64 = BL_pred
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{ 65, 1, 0, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo29, -1 ,nullptr }, // Inst #65 = BMOVPCB_CALL
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{ 66, 1, 0, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #66 = BMOVPCRX_CALL
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{ 67, 3, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #67 = BR_JTadd
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{ 68, 4, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #68 = BR_JTm
|
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{ 69, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #69 = BR_JTr
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{ 70, 1, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #70 = BX
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{ 71, 3, 0, 4, 15, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #71 = BXJ
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{ 72, 1, 0, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #72 = BX_CALL
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{ 73, 2, 0, 4, 10, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #73 = BX_RET
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{ 74, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #74 = BX_pred
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{ 75, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #75 = Bcc
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{ 76, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #76 = CDP
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{ 77, 6, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #77 = CDP2
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{ 78, 0, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #78 = CLREX
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{ 79, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #79 = CLZ
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{ 80, 4, 0, 4, 17, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #80 = CMNri
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{ 81, 4, 0, 4, 18, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #81 = CMNzrr
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{ 82, 5, 0, 4, 19, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #82 = CMNzrsi
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{ 83, 6, 0, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #83 = CMNzrsr
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{ 84, 4, 0, 4, 17, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #84 = CMPri
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{ 85, 4, 0, 4, 18, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #85 = CMPrr
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{ 86, 5, 0, 4, 19, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #86 = CMPrsi
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{ 87, 6, 0, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #87 = CMPrsr
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{ 88, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #88 = CONSTPOOL_ENTRY
|
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{ 89, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #89 = COPY_STRUCT_BYVAL_I32
|
|
{ 90, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #90 = CPS1p
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|
{ 91, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #91 = CPS2p
|
|
{ 92, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #92 = CPS3p
|
|
{ 93, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #93 = CRC32B
|
|
{ 94, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #94 = CRC32CB
|
|
{ 95, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #95 = CRC32CH
|
|
{ 96, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #96 = CRC32CW
|
|
{ 97, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #97 = CRC32H
|
|
{ 98, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #98 = CRC32W
|
|
{ 99, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #99 = DBG
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|
{ 100, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #100 = DMB
|
|
{ 101, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #101 = DSB
|
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{ 102, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #102 = EORri
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{ 103, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #103 = EORrr
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{ 104, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #104 = EORrsi
|
|
{ 105, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #105 = EORrsr
|
|
{ 106, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList4, OperandInfo41, -1 ,nullptr }, // Inst #106 = ERET
|
|
{ 107, 4, 1, 4, 509, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #107 = FCONSTD
|
|
{ 108, 4, 1, 4, 22, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #108 = FCONSTH
|
|
{ 109, 4, 1, 4, 510, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #109 = FCONSTS
|
|
{ 110, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #110 = FLDMXDB_UPD
|
|
{ 111, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #111 = FLDMXIA
|
|
{ 112, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #112 = FLDMXIA_UPD
|
|
{ 113, 2, 0, 4, 529, 0|(1ULL<<MCID::Predicable), 0x8c00ULL, ImplicitList5, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #113 = FMSTAT
|
|
{ 114, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #114 = FSTMXDB_UPD
|
|
{ 115, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #115 = FSTMXIA
|
|
{ 116, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #116 = FSTMXIA_UPD
|
|
{ 117, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #117 = HINT
|
|
{ 118, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #118 = HLT
|
|
{ 119, 1, 0, 4, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #119 = HVC
|
|
{ 120, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #120 = ISB
|
|
{ 121, 2, 0, 0, 394, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,&getITDeprecationInfo }, // Inst #121 = ITasm
|
|
{ 122, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #122 = Int_eh_sjlj_dispatchsetup
|
|
{ 123, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #123 = Int_eh_sjlj_longjmp
|
|
{ 124, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo13, -1 ,nullptr }, // Inst #124 = Int_eh_sjlj_setjmp
|
|
{ 125, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo13, -1 ,nullptr }, // Inst #125 = Int_eh_sjlj_setjmp_nofp
|
|
{ 126, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #126 = Int_eh_sjlj_setup_dispatch
|
|
{ 127, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #127 = JUMPTABLE_ADDRS
|
|
{ 128, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #128 = JUMPTABLE_INSTS
|
|
{ 129, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #129 = JUMPTABLE_TBB
|
|
{ 130, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #130 = JUMPTABLE_TBH
|
|
{ 131, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #131 = LDA
|
|
{ 132, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #132 = LDAB
|
|
{ 133, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #133 = LDAEX
|
|
{ 134, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #134 = LDAEXB
|
|
{ 135, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #135 = LDAEXD
|
|
{ 136, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #136 = LDAEXH
|
|
{ 137, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #137 = LDAH
|
|
{ 138, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #138 = LDC2L_OFFSET
|
|
{ 139, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #139 = LDC2L_OPTION
|
|
{ 140, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #140 = LDC2L_POST
|
|
{ 141, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #141 = LDC2L_PRE
|
|
{ 142, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #142 = LDC2_OFFSET
|
|
{ 143, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #143 = LDC2_OPTION
|
|
{ 144, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #144 = LDC2_POST
|
|
{ 145, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #145 = LDC2_PRE
|
|
{ 146, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #146 = LDCL_OFFSET
|
|
{ 147, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #147 = LDCL_OPTION
|
|
{ 148, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #148 = LDCL_POST
|
|
{ 149, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #149 = LDCL_PRE
|
|
{ 150, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #150 = LDC_OFFSET
|
|
{ 151, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #151 = LDC_OPTION
|
|
{ 152, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #152 = LDC_POST
|
|
{ 153, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #153 = LDC_PRE
|
|
{ 154, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #154 = LDMDA
|
|
{ 155, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #155 = LDMDA_UPD
|
|
{ 156, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #156 = LDMDB
|
|
{ 157, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #157 = LDMDB_UPD
|
|
{ 158, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #158 = LDMIA
|
|
{ 159, 5, 1, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #159 = LDMIA_RET
|
|
{ 160, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #160 = LDMIA_UPD
|
|
{ 161, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #161 = LDMIB
|
|
{ 162, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #162 = LDMIB_UPD
|
|
{ 163, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #163 = LDRBT_POST
|
|
{ 164, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #164 = LDRBT_POST_IMM
|
|
{ 165, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #165 = LDRBT_POST_REG
|
|
{ 166, 7, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #166 = LDRB_POST_IMM
|
|
{ 167, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #167 = LDRB_POST_REG
|
|
{ 168, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #168 = LDRB_PRE_IMM
|
|
{ 169, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #169 = LDRB_PRE_REG
|
|
{ 170, 5, 1, 4, 339, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #170 = LDRBi12
|
|
{ 171, 6, 1, 4, 340, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #171 = LDRBrs
|
|
{ 172, 7, 2, 4, 364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x403ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #172 = LDRD
|
|
{ 173, 8, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x443ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #173 = LDRD_POST
|
|
{ 174, 8, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x423ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #174 = LDRD_PRE
|
|
{ 175, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #175 = LDREX
|
|
{ 176, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #176 = LDREXB
|
|
{ 177, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #177 = LDREXD
|
|
{ 178, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #178 = LDREXH
|
|
{ 179, 6, 1, 4, 349, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #179 = LDRH
|
|
{ 180, 6, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #180 = LDRHTi
|
|
{ 181, 7, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #181 = LDRHTr
|
|
{ 182, 7, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #182 = LDRH_POST
|
|
{ 183, 7, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #183 = LDRH_PRE
|
|
{ 184, 2, 1, 0, 391, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #184 = LDRLIT_ga_abs
|
|
{ 185, 2, 1, 0, 392, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #185 = LDRLIT_ga_pcrel
|
|
{ 186, 2, 1, 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #186 = LDRLIT_ga_pcrel_ldr
|
|
{ 187, 6, 1, 4, 302, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #187 = LDRSB
|
|
{ 188, 6, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #188 = LDRSBTi
|
|
{ 189, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #189 = LDRSBTr
|
|
{ 190, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #190 = LDRSB_POST
|
|
{ 191, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #191 = LDRSB_PRE
|
|
{ 192, 6, 1, 4, 302, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #192 = LDRSH
|
|
{ 193, 6, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #193 = LDRSHTi
|
|
{ 194, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #194 = LDRSHTr
|
|
{ 195, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #195 = LDRSH_POST
|
|
{ 196, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #196 = LDRSH_PRE
|
|
{ 197, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #197 = LDRT_POST
|
|
{ 198, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #198 = LDRT_POST_IMM
|
|
{ 199, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #199 = LDRT_POST_REG
|
|
{ 200, 7, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #200 = LDR_POST_IMM
|
|
{ 201, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #201 = LDR_POST_REG
|
|
{ 202, 6, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #202 = LDR_PRE_IMM
|
|
{ 203, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #203 = LDR_PRE_REG
|
|
{ 204, 5, 1, 4, 350, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #204 = LDRcp
|
|
{ 205, 5, 1, 4, 342, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #205 = LDRi12
|
|
{ 206, 6, 1, 4, 301, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #206 = LDRrs
|
|
{ 207, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #207 = LEApcrel
|
|
{ 208, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #208 = LEApcrelJT
|
|
{ 209, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #209 = LSLi
|
|
{ 210, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #210 = LSLr
|
|
{ 211, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #211 = LSRi
|
|
{ 212, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #212 = LSRr
|
|
{ 213, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72, -1 ,&getMCRDeprecationInfo }, // Inst #213 = MCR
|
|
{ 214, 6, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #214 = MCR2
|
|
{ 215, 7, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #215 = MCRR
|
|
{ 216, 5, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #216 = MCRR2
|
|
{ 217, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #217 = MEMCPY
|
|
{ 218, 7, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #218 = MLA
|
|
{ 219, 7, 1, 4, 293, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #219 = MLAv5
|
|
{ 220, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #220 = MLS
|
|
{ 221, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #221 = MOVCCi
|
|
{ 222, 5, 1, 4, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #222 = MOVCCi16
|
|
{ 223, 5, 1, 8, 287, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #223 = MOVCCi32imm
|
|
{ 224, 5, 1, 4, 44, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #224 = MOVCCr
|
|
{ 225, 6, 1, 4, 282, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #225 = MOVCCsi
|
|
{ 226, 7, 1, 4, 282, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #226 = MOVCCsr
|
|
{ 227, 2, 0, 4, 10, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #227 = MOVPCLR
|
|
{ 228, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #228 = MOVPCRX
|
|
{ 229, 5, 1, 4, 42, 0|(1ULL<<MCID::Predicable), 0x2201ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #229 = MOVTi16
|
|
{ 230, 4, 1, 0, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #230 = MOVTi16_ga_pcrel
|
|
{ 231, 2, 1, 0, 289, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #231 = MOV_ga_pcrel
|
|
{ 232, 2, 1, 0, 290, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #232 = MOV_ga_pcrel_ldr
|
|
{ 233, 5, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #233 = MOVi
|
|
{ 234, 4, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #234 = MOVi16
|
|
{ 235, 3, 1, 0, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #235 = MOVi16_ga_pcrel
|
|
{ 236, 2, 1, 0, 288, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #236 = MOVi32imm
|
|
{ 237, 5, 1, 4, 49, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #237 = MOVr
|
|
{ 238, 5, 1, 4, 49, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #238 = MOVr_TC
|
|
{ 239, 6, 1, 4, 283, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #239 = MOVsi
|
|
{ 240, 7, 1, 4, 283, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #240 = MOVsr
|
|
{ 241, 2, 1, 0, 284, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #241 = MOVsra_flag
|
|
{ 242, 2, 1, 0, 284, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #242 = MOVsrl_flag
|
|
{ 243, 8, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #243 = MRC
|
|
{ 244, 6, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #244 = MRC2
|
|
{ 245, 7, 2, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #245 = MRRC
|
|
{ 246, 5, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #246 = MRRC2
|
|
{ 247, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #247 = MRS
|
|
{ 248, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #248 = MRSbanked
|
|
{ 249, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #249 = MRSsys
|
|
{ 250, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #250 = MSR
|
|
{ 251, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #251 = MSRbanked
|
|
{ 252, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #252 = MSRi
|
|
{ 253, 6, 1, 4, 294, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #253 = MUL
|
|
{ 254, 6, 1, 4, 294, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #254 = MULv5
|
|
{ 255, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #255 = MVNCCi
|
|
{ 256, 5, 1, 4, 53, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #256 = MVNi
|
|
{ 257, 5, 1, 4, 286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #257 = MVNr
|
|
{ 258, 6, 1, 4, 55, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #258 = MVNsi
|
|
{ 259, 7, 1, 4, 285, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #259 = MVNsr
|
|
{ 260, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #260 = ORRri
|
|
{ 261, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #261 = ORRrr
|
|
{ 262, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #262 = ORRrsi
|
|
{ 263, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #263 = ORRrsr
|
|
{ 264, 5, 1, 4, 56, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #264 = PICADD
|
|
{ 265, 5, 1, 4, 300, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #265 = PICLDR
|
|
{ 266, 5, 1, 4, 349, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #266 = PICLDRB
|
|
{ 267, 5, 1, 4, 349, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #267 = PICLDRH
|
|
{ 268, 5, 1, 4, 302, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #268 = PICLDRSB
|
|
{ 269, 5, 1, 4, 302, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #269 = PICLDRSH
|
|
{ 270, 5, 0, 4, 372, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #270 = PICSTR
|
|
{ 271, 5, 0, 4, 373, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #271 = PICSTRB
|
|
{ 272, 5, 0, 4, 373, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #272 = PICSTRH
|
|
{ 273, 6, 1, 4, 59, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #273 = PKHBT
|
|
{ 274, 6, 1, 4, 60, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #274 = PKHTB
|
|
{ 275, 2, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #275 = PLDWi12
|
|
{ 276, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #276 = PLDWrs
|
|
{ 277, 2, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #277 = PLDi12
|
|
{ 278, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #278 = PLDrs
|
|
{ 279, 2, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #279 = PLIi12
|
|
{ 280, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #280 = PLIrs
|
|
{ 281, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #281 = QADD
|
|
{ 282, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #282 = QADD16
|
|
{ 283, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #283 = QADD8
|
|
{ 284, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #284 = QASX
|
|
{ 285, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #285 = QDADD
|
|
{ 286, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #286 = QDSUB
|
|
{ 287, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #287 = QSAX
|
|
{ 288, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #288 = QSUB
|
|
{ 289, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #289 = QSUB16
|
|
{ 290, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #290 = QSUB8
|
|
{ 291, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #291 = RBIT
|
|
{ 292, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #292 = REV
|
|
{ 293, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #293 = REV16
|
|
{ 294, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #294 = REVSH
|
|
{ 295, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #295 = RFEDA
|
|
{ 296, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #296 = RFEDA_UPD
|
|
{ 297, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #297 = RFEDB
|
|
{ 298, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #298 = RFEDB_UPD
|
|
{ 299, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #299 = RFEIA
|
|
{ 300, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #300 = RFEIA_UPD
|
|
{ 301, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #301 = RFEIB
|
|
{ 302, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #302 = RFEIB_UPD
|
|
{ 303, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #303 = RORi
|
|
{ 304, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #304 = RORr
|
|
{ 305, 2, 1, 0, 51, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #305 = RRX
|
|
{ 306, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #306 = RRXi
|
|
{ 307, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #307 = RSBSri
|
|
{ 308, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr }, // Inst #308 = RSBSrsi
|
|
{ 309, 7, 1, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr }, // Inst #309 = RSBSrsr
|
|
{ 310, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #310 = RSBri
|
|
{ 311, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #311 = RSBrr
|
|
{ 312, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #312 = RSBrsi
|
|
{ 313, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #313 = RSBrsr
|
|
{ 314, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #314 = RSCri
|
|
{ 315, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr }, // Inst #315 = RSCrr
|
|
{ 316, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo16, -1 ,nullptr }, // Inst #316 = RSCrsi
|
|
{ 317, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo22, -1 ,nullptr }, // Inst #317 = RSCrsr
|
|
{ 318, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #318 = SADD16
|
|
{ 319, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #319 = SADD8
|
|
{ 320, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #320 = SASX
|
|
{ 321, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #321 = SBCri
|
|
{ 322, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr }, // Inst #322 = SBCrr
|
|
{ 323, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo16, -1 ,nullptr }, // Inst #323 = SBCrsi
|
|
{ 324, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #324 = SBCrsr
|
|
{ 325, 6, 1, 4, 292, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #325 = SBFX
|
|
{ 326, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #326 = SDIV
|
|
{ 327, 5, 1, 4, 291, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #327 = SEL
|
|
{ 328, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, ARM::HasV8Ops ,nullptr }, // Inst #328 = SETEND
|
|
{ 329, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #329 = SETPAN
|
|
{ 330, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #330 = SHA1C
|
|
{ 331, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #331 = SHA1H
|
|
{ 332, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #332 = SHA1M
|
|
{ 333, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #333 = SHA1P
|
|
{ 334, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #334 = SHA1SU0
|
|
{ 335, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #335 = SHA1SU1
|
|
{ 336, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #336 = SHA256H
|
|
{ 337, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #337 = SHA256H2
|
|
{ 338, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #338 = SHA256SU0
|
|
{ 339, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #339 = SHA256SU1
|
|
{ 340, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #340 = SHADD16
|
|
{ 341, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #341 = SHADD8
|
|
{ 342, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #342 = SHASX
|
|
{ 343, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #343 = SHSAX
|
|
{ 344, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #344 = SHSUB16
|
|
{ 345, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #345 = SHSUB8
|
|
{ 346, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #346 = SMC
|
|
{ 347, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #347 = SMLABB
|
|
{ 348, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #348 = SMLABT
|
|
{ 349, 6, 1, 4, 333, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #349 = SMLAD
|
|
{ 350, 6, 1, 4, 333, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #350 = SMLADX
|
|
{ 351, 9, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #351 = SMLAL
|
|
{ 352, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #352 = SMLALBB
|
|
{ 353, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #353 = SMLALBT
|
|
{ 354, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #354 = SMLALD
|
|
{ 355, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #355 = SMLALDX
|
|
{ 356, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #356 = SMLALTB
|
|
{ 357, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #357 = SMLALTT
|
|
{ 358, 9, 2, 4, 295, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #358 = SMLALv5
|
|
{ 359, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #359 = SMLATB
|
|
{ 360, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #360 = SMLATT
|
|
{ 361, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #361 = SMLAWB
|
|
{ 362, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #362 = SMLAWT
|
|
{ 363, 6, 1, 4, 330, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #363 = SMLSD
|
|
{ 364, 6, 1, 4, 330, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #364 = SMLSDX
|
|
{ 365, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #365 = SMLSLD
|
|
{ 366, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #366 = SMLSLDX
|
|
{ 367, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #367 = SMMLA
|
|
{ 368, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #368 = SMMLAR
|
|
{ 369, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #369 = SMMLS
|
|
{ 370, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #370 = SMMLSR
|
|
{ 371, 5, 1, 4, 294, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #371 = SMMUL
|
|
{ 372, 5, 1, 4, 294, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #372 = SMMULR
|
|
{ 373, 5, 1, 4, 328, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #373 = SMUAD
|
|
{ 374, 5, 1, 4, 328, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #374 = SMUADX
|
|
{ 375, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #375 = SMULBB
|
|
{ 376, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #376 = SMULBT
|
|
{ 377, 7, 2, 4, 335, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #377 = SMULL
|
|
{ 378, 7, 2, 4, 296, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #378 = SMULLv5
|
|
{ 379, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #379 = SMULTB
|
|
{ 380, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #380 = SMULTT
|
|
{ 381, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #381 = SMULWB
|
|
{ 382, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #382 = SMULWT
|
|
{ 383, 5, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #383 = SMUSD
|
|
{ 384, 5, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #384 = SMUSDX
|
|
{ 385, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #385 = SPACE
|
|
{ 386, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #386 = SRSDA
|
|
{ 387, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #387 = SRSDA_UPD
|
|
{ 388, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #388 = SRSDB
|
|
{ 389, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #389 = SRSDB_UPD
|
|
{ 390, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #390 = SRSIA
|
|
{ 391, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #391 = SRSIA_UPD
|
|
{ 392, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #392 = SRSIB
|
|
{ 393, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #393 = SRSIB_UPD
|
|
{ 394, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0x680ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #394 = SSAT
|
|
{ 395, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #395 = SSAT16
|
|
{ 396, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #396 = SSAX
|
|
{ 397, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #397 = SSUB16
|
|
{ 398, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #398 = SSUB8
|
|
{ 399, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #399 = STC2L_OFFSET
|
|
{ 400, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #400 = STC2L_OPTION
|
|
{ 401, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #401 = STC2L_POST
|
|
{ 402, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #402 = STC2L_PRE
|
|
{ 403, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #403 = STC2_OFFSET
|
|
{ 404, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #404 = STC2_OPTION
|
|
{ 405, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #405 = STC2_POST
|
|
{ 406, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #406 = STC2_PRE
|
|
{ 407, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #407 = STCL_OFFSET
|
|
{ 408, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #408 = STCL_OPTION
|
|
{ 409, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #409 = STCL_POST
|
|
{ 410, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #410 = STCL_PRE
|
|
{ 411, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #411 = STC_OFFSET
|
|
{ 412, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #412 = STC_OPTION
|
|
{ 413, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #413 = STC_POST
|
|
{ 414, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #414 = STC_PRE
|
|
{ 415, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #415 = STL
|
|
{ 416, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #416 = STLB
|
|
{ 417, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #417 = STLEX
|
|
{ 418, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #418 = STLEXB
|
|
{ 419, 5, 1, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #419 = STLEXD
|
|
{ 420, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #420 = STLEXH
|
|
{ 421, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #421 = STLH
|
|
{ 422, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #422 = STMDA
|
|
{ 423, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #423 = STMDA_UPD
|
|
{ 424, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #424 = STMDB
|
|
{ 425, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #425 = STMDB_UPD
|
|
{ 426, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #426 = STMIA
|
|
{ 427, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #427 = STMIA_UPD
|
|
{ 428, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #428 = STMIB
|
|
{ 429, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #429 = STMIB_UPD
|
|
{ 430, 4, 0, 0, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #430 = STRBT_POST
|
|
{ 431, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #431 = STRBT_POST_IMM
|
|
{ 432, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #432 = STRBT_POST_REG
|
|
{ 433, 7, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #433 = STRB_POST_IMM
|
|
{ 434, 7, 1, 4, 380, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #434 = STRB_POST_REG
|
|
{ 435, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #435 = STRB_PRE_IMM
|
|
{ 436, 7, 1, 4, 380, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #436 = STRB_PRE_REG
|
|
{ 437, 5, 0, 4, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x390ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #437 = STRBi12
|
|
{ 438, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #438 = STRBi_preidx
|
|
{ 439, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #439 = STRBr_preidx
|
|
{ 440, 6, 0, 4, 374, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #440 = STRBrs
|
|
{ 441, 7, 0, 4, 386, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x483ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #441 = STRD
|
|
{ 442, 8, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4c3ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #442 = STRD_POST
|
|
{ 443, 8, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4a3ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #443 = STRD_PRE
|
|
{ 444, 5, 1, 4, 375, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #444 = STREX
|
|
{ 445, 5, 1, 4, 375, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #445 = STREXB
|
|
{ 446, 5, 1, 4, 375, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #446 = STREXD
|
|
{ 447, 5, 1, 4, 375, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #447 = STREXH
|
|
{ 448, 6, 0, 4, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x483ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #448 = STRH
|
|
{ 449, 6, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #449 = STRHTi
|
|
{ 450, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #450 = STRHTr
|
|
{ 451, 7, 1, 4, 380, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #451 = STRH_POST
|
|
{ 452, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a3ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #452 = STRH_PRE
|
|
{ 453, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #453 = STRH_preidx
|
|
{ 454, 4, 0, 0, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #454 = STRT_POST
|
|
{ 455, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #455 = STRT_POST_IMM
|
|
{ 456, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #456 = STRT_POST_REG
|
|
{ 457, 7, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #457 = STR_POST_IMM
|
|
{ 458, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #458 = STR_POST_REG
|
|
{ 459, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #459 = STR_PRE_IMM
|
|
{ 460, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #460 = STR_PRE_REG
|
|
{ 461, 5, 0, 4, 372, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x390ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #461 = STRi12
|
|
{ 462, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #462 = STRi_preidx
|
|
{ 463, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #463 = STRr_preidx
|
|
{ 464, 6, 0, 4, 376, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #464 = STRrs
|
|
{ 465, 3, 0, 4, 77, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #465 = SUBS_PC_LR
|
|
{ 466, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #466 = SUBSri
|
|
{ 467, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19, -1 ,nullptr }, // Inst #467 = SUBSrr
|
|
{ 468, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr }, // Inst #468 = SUBSrsi
|
|
{ 469, 7, 1, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr }, // Inst #469 = SUBSrsr
|
|
{ 470, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #470 = SUBri
|
|
{ 471, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #471 = SUBrr
|
|
{ 472, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #472 = SUBrsi
|
|
{ 473, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #473 = SUBrsr
|
|
{ 474, 3, 0, 4, 10, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #474 = SVC
|
|
{ 475, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #475 = SWP
|
|
{ 476, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #476 = SWPB
|
|
{ 477, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #477 = SXTAB
|
|
{ 478, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #478 = SXTAB16
|
|
{ 479, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #479 = SXTAH
|
|
{ 480, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #480 = SXTB
|
|
{ 481, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #481 = SXTB16
|
|
{ 482, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #482 = SXTH
|
|
{ 483, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #483 = TAILJMPd
|
|
{ 484, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #484 = TAILJMPr
|
|
{ 485, 1, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #485 = TCRETURNdi
|
|
{ 486, 1, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #486 = TCRETURNri
|
|
{ 487, 4, 0, 4, 80, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #487 = TEQri
|
|
{ 488, 4, 0, 4, 81, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #488 = TEQrr
|
|
{ 489, 5, 0, 4, 82, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #489 = TEQrsi
|
|
{ 490, 6, 0, 4, 83, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #490 = TEQrsr
|
|
{ 491, 0, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #491 = TPsoft
|
|
{ 492, 0, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #492 = TRAP
|
|
{ 493, 0, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #493 = TRAPNaCl
|
|
{ 494, 4, 0, 4, 80, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #494 = TSTri
|
|
{ 495, 4, 0, 4, 81, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #495 = TSTrr
|
|
{ 496, 5, 0, 4, 82, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #496 = TSTrsi
|
|
{ 497, 6, 0, 4, 83, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #497 = TSTrsr
|
|
{ 498, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #498 = UADD16
|
|
{ 499, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #499 = UADD8
|
|
{ 500, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #500 = UASX
|
|
{ 501, 6, 1, 4, 292, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #501 = UBFX
|
|
{ 502, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #502 = UDF
|
|
{ 503, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #503 = UDIV
|
|
{ 504, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #504 = UHADD16
|
|
{ 505, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #505 = UHADD8
|
|
{ 506, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #506 = UHASX
|
|
{ 507, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #507 = UHSAX
|
|
{ 508, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #508 = UHSUB16
|
|
{ 509, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #509 = UHSUB8
|
|
{ 510, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #510 = UMAAL
|
|
{ 511, 9, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #511 = UMLAL
|
|
{ 512, 9, 2, 4, 295, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #512 = UMLALv5
|
|
{ 513, 7, 2, 4, 335, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #513 = UMULL
|
|
{ 514, 7, 2, 4, 296, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #514 = UMULLv5
|
|
{ 515, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #515 = UQADD16
|
|
{ 516, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #516 = UQADD8
|
|
{ 517, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #517 = UQASX
|
|
{ 518, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #518 = UQSAX
|
|
{ 519, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #519 = UQSUB16
|
|
{ 520, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #520 = UQSUB8
|
|
{ 521, 5, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #521 = USAD8
|
|
{ 522, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #522 = USADA8
|
|
{ 523, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0x680ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #523 = USAT
|
|
{ 524, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #524 = USAT16
|
|
{ 525, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #525 = USAX
|
|
{ 526, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #526 = USUB16
|
|
{ 527, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #527 = USUB8
|
|
{ 528, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #528 = UXTAB
|
|
{ 529, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #529 = UXTAB16
|
|
{ 530, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #530 = UXTAH
|
|
{ 531, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #531 = UXTB
|
|
{ 532, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #532 = UXTB16
|
|
{ 533, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #533 = UXTH
|
|
{ 534, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #534 = VABALsv2i64
|
|
{ 535, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #535 = VABALsv4i32
|
|
{ 536, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #536 = VABALsv8i16
|
|
{ 537, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #537 = VABALuv2i64
|
|
{ 538, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #538 = VABALuv4i32
|
|
{ 539, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #539 = VABALuv8i16
|
|
{ 540, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #540 = VABAsv16i8
|
|
{ 541, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #541 = VABAsv2i32
|
|
{ 542, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #542 = VABAsv4i16
|
|
{ 543, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #543 = VABAsv4i32
|
|
{ 544, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #544 = VABAsv8i16
|
|
{ 545, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #545 = VABAsv8i8
|
|
{ 546, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #546 = VABAuv16i8
|
|
{ 547, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #547 = VABAuv2i32
|
|
{ 548, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #548 = VABAuv4i16
|
|
{ 549, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #549 = VABAuv4i32
|
|
{ 550, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #550 = VABAuv8i16
|
|
{ 551, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #551 = VABAuv8i8
|
|
{ 552, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #552 = VABDLsv2i64
|
|
{ 553, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #553 = VABDLsv4i32
|
|
{ 554, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #554 = VABDLsv8i16
|
|
{ 555, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #555 = VABDLuv2i64
|
|
{ 556, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #556 = VABDLuv4i32
|
|
{ 557, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #557 = VABDLuv8i16
|
|
{ 558, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #558 = VABDfd
|
|
{ 559, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #559 = VABDfq
|
|
{ 560, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #560 = VABDhd
|
|
{ 561, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #561 = VABDhq
|
|
{ 562, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #562 = VABDsv16i8
|
|
{ 563, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #563 = VABDsv2i32
|
|
{ 564, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #564 = VABDsv4i16
|
|
{ 565, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #565 = VABDsv4i32
|
|
{ 566, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #566 = VABDsv8i16
|
|
{ 567, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #567 = VABDsv8i8
|
|
{ 568, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #568 = VABDuv16i8
|
|
{ 569, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #569 = VABDuv2i32
|
|
{ 570, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #570 = VABDuv4i16
|
|
{ 571, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #571 = VABDuv4i32
|
|
{ 572, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #572 = VABDuv8i16
|
|
{ 573, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #573 = VABDuv8i8
|
|
{ 574, 4, 1, 4, 454, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #574 = VABSD
|
|
{ 575, 4, 1, 4, 22, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #575 = VABSH
|
|
{ 576, 4, 1, 4, 455, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #576 = VABSS
|
|
{ 577, 4, 1, 4, 419, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #577 = VABSfd
|
|
{ 578, 4, 1, 4, 420, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #578 = VABSfq
|
|
{ 579, 4, 1, 4, 91, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #579 = VABShd
|
|
{ 580, 4, 1, 4, 92, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #580 = VABShq
|
|
{ 581, 4, 1, 4, 421, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #581 = VABSv16i8
|
|
{ 582, 4, 1, 4, 422, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #582 = VABSv2i32
|
|
{ 583, 4, 1, 4, 422, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #583 = VABSv4i16
|
|
{ 584, 4, 1, 4, 421, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #584 = VABSv4i32
|
|
{ 585, 4, 1, 4, 421, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #585 = VABSv8i16
|
|
{ 586, 4, 1, 4, 422, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #586 = VABSv8i8
|
|
{ 587, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #587 = VACGEfd
|
|
{ 588, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #588 = VACGEfq
|
|
{ 589, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #589 = VACGEhd
|
|
{ 590, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #590 = VACGEhq
|
|
{ 591, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #591 = VACGTfd
|
|
{ 592, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #592 = VACGTfq
|
|
{ 593, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #593 = VACGThd
|
|
{ 594, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #594 = VACGThq
|
|
{ 595, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #595 = VADDD
|
|
{ 596, 5, 1, 4, 96, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #596 = VADDH
|
|
{ 597, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #597 = VADDHNv2i32
|
|
{ 598, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #598 = VADDHNv4i16
|
|
{ 599, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #599 = VADDHNv8i8
|
|
{ 600, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #600 = VADDLsv2i64
|
|
{ 601, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #601 = VADDLsv4i32
|
|
{ 602, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #602 = VADDLsv8i16
|
|
{ 603, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #603 = VADDLuv2i64
|
|
{ 604, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #604 = VADDLuv4i32
|
|
{ 605, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #605 = VADDLuv8i16
|
|
{ 606, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #606 = VADDS
|
|
{ 607, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #607 = VADDWsv2i64
|
|
{ 608, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #608 = VADDWsv4i32
|
|
{ 609, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #609 = VADDWsv8i16
|
|
{ 610, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #610 = VADDWuv2i64
|
|
{ 611, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #611 = VADDWuv4i32
|
|
{ 612, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #612 = VADDWuv8i16
|
|
{ 613, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #613 = VADDfd
|
|
{ 614, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #614 = VADDfq
|
|
{ 615, 5, 1, 4, 88, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #615 = VADDhd
|
|
{ 616, 5, 1, 4, 89, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #616 = VADDhq
|
|
{ 617, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #617 = VADDv16i8
|
|
{ 618, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #618 = VADDv1i64
|
|
{ 619, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #619 = VADDv2i32
|
|
{ 620, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #620 = VADDv2i64
|
|
{ 621, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #621 = VADDv4i16
|
|
{ 622, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #622 = VADDv4i32
|
|
{ 623, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #623 = VADDv8i16
|
|
{ 624, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #624 = VADDv8i8
|
|
{ 625, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #625 = VANDd
|
|
{ 626, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #626 = VANDq
|
|
{ 627, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #627 = VBICd
|
|
{ 628, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #628 = VBICiv2i32
|
|
{ 629, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #629 = VBICiv4i16
|
|
{ 630, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #630 = VBICiv4i32
|
|
{ 631, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #631 = VBICiv8i16
|
|
{ 632, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #632 = VBICq
|
|
{ 633, 6, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #633 = VBIFd
|
|
{ 634, 6, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #634 = VBIFq
|
|
{ 635, 6, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #635 = VBITd
|
|
{ 636, 6, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #636 = VBITq
|
|
{ 637, 6, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #637 = VBSLd
|
|
{ 638, 6, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #638 = VBSLq
|
|
{ 639, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #639 = VCEQfd
|
|
{ 640, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #640 = VCEQfq
|
|
{ 641, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #641 = VCEQhd
|
|
{ 642, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #642 = VCEQhq
|
|
{ 643, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #643 = VCEQv16i8
|
|
{ 644, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #644 = VCEQv2i32
|
|
{ 645, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #645 = VCEQv4i16
|
|
{ 646, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #646 = VCEQv4i32
|
|
{ 647, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #647 = VCEQv8i16
|
|
{ 648, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #648 = VCEQv8i8
|
|
{ 649, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #649 = VCEQzv16i8
|
|
{ 650, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #650 = VCEQzv2f32
|
|
{ 651, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #651 = VCEQzv2i32
|
|
{ 652, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #652 = VCEQzv4f16
|
|
{ 653, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #653 = VCEQzv4f32
|
|
{ 654, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #654 = VCEQzv4i16
|
|
{ 655, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #655 = VCEQzv4i32
|
|
{ 656, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #656 = VCEQzv8f16
|
|
{ 657, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #657 = VCEQzv8i16
|
|
{ 658, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #658 = VCEQzv8i8
|
|
{ 659, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #659 = VCGEfd
|
|
{ 660, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #660 = VCGEfq
|
|
{ 661, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #661 = VCGEhd
|
|
{ 662, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #662 = VCGEhq
|
|
{ 663, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #663 = VCGEsv16i8
|
|
{ 664, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #664 = VCGEsv2i32
|
|
{ 665, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #665 = VCGEsv4i16
|
|
{ 666, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #666 = VCGEsv4i32
|
|
{ 667, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #667 = VCGEsv8i16
|
|
{ 668, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #668 = VCGEsv8i8
|
|
{ 669, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #669 = VCGEuv16i8
|
|
{ 670, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #670 = VCGEuv2i32
|
|
{ 671, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #671 = VCGEuv4i16
|
|
{ 672, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #672 = VCGEuv4i32
|
|
{ 673, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #673 = VCGEuv8i16
|
|
{ 674, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #674 = VCGEuv8i8
|
|
{ 675, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #675 = VCGEzv16i8
|
|
{ 676, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #676 = VCGEzv2f32
|
|
{ 677, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #677 = VCGEzv2i32
|
|
{ 678, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #678 = VCGEzv4f16
|
|
{ 679, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #679 = VCGEzv4f32
|
|
{ 680, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #680 = VCGEzv4i16
|
|
{ 681, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #681 = VCGEzv4i32
|
|
{ 682, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #682 = VCGEzv8f16
|
|
{ 683, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #683 = VCGEzv8i16
|
|
{ 684, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #684 = VCGEzv8i8
|
|
{ 685, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #685 = VCGTfd
|
|
{ 686, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #686 = VCGTfq
|
|
{ 687, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #687 = VCGThd
|
|
{ 688, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #688 = VCGThq
|
|
{ 689, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #689 = VCGTsv16i8
|
|
{ 690, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #690 = VCGTsv2i32
|
|
{ 691, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #691 = VCGTsv4i16
|
|
{ 692, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #692 = VCGTsv4i32
|
|
{ 693, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #693 = VCGTsv8i16
|
|
{ 694, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #694 = VCGTsv8i8
|
|
{ 695, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #695 = VCGTuv16i8
|
|
{ 696, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #696 = VCGTuv2i32
|
|
{ 697, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #697 = VCGTuv4i16
|
|
{ 698, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #698 = VCGTuv4i32
|
|
{ 699, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #699 = VCGTuv8i16
|
|
{ 700, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #700 = VCGTuv8i8
|
|
{ 701, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #701 = VCGTzv16i8
|
|
{ 702, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #702 = VCGTzv2f32
|
|
{ 703, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #703 = VCGTzv2i32
|
|
{ 704, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #704 = VCGTzv4f16
|
|
{ 705, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #705 = VCGTzv4f32
|
|
{ 706, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #706 = VCGTzv4i16
|
|
{ 707, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #707 = VCGTzv4i32
|
|
{ 708, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #708 = VCGTzv8f16
|
|
{ 709, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #709 = VCGTzv8i16
|
|
{ 710, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #710 = VCGTzv8i8
|
|
{ 711, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #711 = VCLEzv16i8
|
|
{ 712, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #712 = VCLEzv2f32
|
|
{ 713, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #713 = VCLEzv2i32
|
|
{ 714, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #714 = VCLEzv4f16
|
|
{ 715, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #715 = VCLEzv4f32
|
|
{ 716, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #716 = VCLEzv4i16
|
|
{ 717, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #717 = VCLEzv4i32
|
|
{ 718, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #718 = VCLEzv8f16
|
|
{ 719, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #719 = VCLEzv8i16
|
|
{ 720, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #720 = VCLEzv8i8
|
|
{ 721, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #721 = VCLSv16i8
|
|
{ 722, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #722 = VCLSv2i32
|
|
{ 723, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #723 = VCLSv4i16
|
|
{ 724, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #724 = VCLSv4i32
|
|
{ 725, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #725 = VCLSv8i16
|
|
{ 726, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #726 = VCLSv8i8
|
|
{ 727, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #727 = VCLTzv16i8
|
|
{ 728, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #728 = VCLTzv2f32
|
|
{ 729, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #729 = VCLTzv2i32
|
|
{ 730, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #730 = VCLTzv4f16
|
|
{ 731, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #731 = VCLTzv4f32
|
|
{ 732, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #732 = VCLTzv4i16
|
|
{ 733, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #733 = VCLTzv4i32
|
|
{ 734, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #734 = VCLTzv8f16
|
|
{ 735, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #735 = VCLTzv8i16
|
|
{ 736, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #736 = VCLTzv8i8
|
|
{ 737, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #737 = VCLZv16i8
|
|
{ 738, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #738 = VCLZv2i32
|
|
{ 739, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #739 = VCLZv4i16
|
|
{ 740, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #740 = VCLZv4i32
|
|
{ 741, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #741 = VCLZv8i16
|
|
{ 742, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #742 = VCLZv8i8
|
|
{ 743, 4, 0, 4, 456, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo137, -1 ,nullptr }, // Inst #743 = VCMPD
|
|
{ 744, 4, 0, 4, 456, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo137, -1 ,nullptr }, // Inst #744 = VCMPED
|
|
{ 745, 4, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #745 = VCMPEH
|
|
{ 746, 4, 0, 4, 457, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #746 = VCMPES
|
|
{ 747, 3, 0, 4, 456, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo145, -1 ,nullptr }, // Inst #747 = VCMPEZD
|
|
{ 748, 3, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #748 = VCMPEZH
|
|
{ 749, 3, 0, 4, 457, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #749 = VCMPEZS
|
|
{ 750, 4, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #750 = VCMPH
|
|
{ 751, 4, 0, 4, 457, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #751 = VCMPS
|
|
{ 752, 3, 0, 4, 456, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo145, -1 ,nullptr }, // Inst #752 = VCMPZD
|
|
{ 753, 3, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #753 = VCMPZH
|
|
{ 754, 3, 0, 4, 457, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #754 = VCMPZS
|
|
{ 755, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #755 = VCNTd
|
|
{ 756, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #756 = VCNTq
|
|
{ 757, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #757 = VCVTANSDf
|
|
{ 758, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #758 = VCVTANSDh
|
|
{ 759, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #759 = VCVTANSQf
|
|
{ 760, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #760 = VCVTANSQh
|
|
{ 761, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #761 = VCVTANUDf
|
|
{ 762, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #762 = VCVTANUDh
|
|
{ 763, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #763 = VCVTANUQf
|
|
{ 764, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #764 = VCVTANUQh
|
|
{ 765, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #765 = VCVTASD
|
|
{ 766, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #766 = VCVTASH
|
|
{ 767, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #767 = VCVTASS
|
|
{ 768, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #768 = VCVTAUD
|
|
{ 769, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #769 = VCVTAUH
|
|
{ 770, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #770 = VCVTAUS
|
|
{ 771, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #771 = VCVTBDH
|
|
{ 772, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #772 = VCVTBHD
|
|
{ 773, 4, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #773 = VCVTBHS
|
|
{ 774, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #774 = VCVTBSH
|
|
{ 775, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #775 = VCVTDS
|
|
{ 776, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #776 = VCVTMNSDf
|
|
{ 777, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #777 = VCVTMNSDh
|
|
{ 778, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #778 = VCVTMNSQf
|
|
{ 779, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #779 = VCVTMNSQh
|
|
{ 780, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #780 = VCVTMNUDf
|
|
{ 781, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #781 = VCVTMNUDh
|
|
{ 782, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #782 = VCVTMNUQf
|
|
{ 783, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #783 = VCVTMNUQh
|
|
{ 784, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #784 = VCVTMSD
|
|
{ 785, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #785 = VCVTMSH
|
|
{ 786, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #786 = VCVTMSS
|
|
{ 787, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #787 = VCVTMUD
|
|
{ 788, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #788 = VCVTMUH
|
|
{ 789, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #789 = VCVTMUS
|
|
{ 790, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #790 = VCVTNNSDf
|
|
{ 791, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #791 = VCVTNNSDh
|
|
{ 792, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #792 = VCVTNNSQf
|
|
{ 793, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #793 = VCVTNNSQh
|
|
{ 794, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #794 = VCVTNNUDf
|
|
{ 795, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #795 = VCVTNNUDh
|
|
{ 796, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #796 = VCVTNNUQf
|
|
{ 797, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #797 = VCVTNNUQh
|
|
{ 798, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #798 = VCVTNSD
|
|
{ 799, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #799 = VCVTNSH
|
|
{ 800, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #800 = VCVTNSS
|
|
{ 801, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #801 = VCVTNUD
|
|
{ 802, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #802 = VCVTNUH
|
|
{ 803, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #803 = VCVTNUS
|
|
{ 804, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #804 = VCVTPNSDf
|
|
{ 805, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #805 = VCVTPNSDh
|
|
{ 806, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #806 = VCVTPNSQf
|
|
{ 807, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #807 = VCVTPNSQh
|
|
{ 808, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #808 = VCVTPNUDf
|
|
{ 809, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #809 = VCVTPNUDh
|
|
{ 810, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #810 = VCVTPNUQf
|
|
{ 811, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #811 = VCVTPNUQh
|
|
{ 812, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #812 = VCVTPSD
|
|
{ 813, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #813 = VCVTPSH
|
|
{ 814, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #814 = VCVTPSS
|
|
{ 815, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #815 = VCVTPUD
|
|
{ 816, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #816 = VCVTPUH
|
|
{ 817, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #817 = VCVTPUS
|
|
{ 818, 4, 1, 4, 497, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #818 = VCVTSD
|
|
{ 819, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #819 = VCVTTDH
|
|
{ 820, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #820 = VCVTTHD
|
|
{ 821, 4, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #821 = VCVTTHS
|
|
{ 822, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #822 = VCVTTSH
|
|
{ 823, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #823 = VCVTf2h
|
|
{ 824, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #824 = VCVTf2sd
|
|
{ 825, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #825 = VCVTf2sq
|
|
{ 826, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #826 = VCVTf2ud
|
|
{ 827, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #827 = VCVTf2uq
|
|
{ 828, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #828 = VCVTf2xsd
|
|
{ 829, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #829 = VCVTf2xsq
|
|
{ 830, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #830 = VCVTf2xud
|
|
{ 831, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #831 = VCVTf2xuq
|
|
{ 832, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #832 = VCVTh2f
|
|
{ 833, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #833 = VCVTh2sd
|
|
{ 834, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #834 = VCVTh2sq
|
|
{ 835, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #835 = VCVTh2ud
|
|
{ 836, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #836 = VCVTh2uq
|
|
{ 837, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #837 = VCVTh2xsd
|
|
{ 838, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #838 = VCVTh2xsq
|
|
{ 839, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #839 = VCVTh2xud
|
|
{ 840, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #840 = VCVTh2xuq
|
|
{ 841, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #841 = VCVTs2fd
|
|
{ 842, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #842 = VCVTs2fq
|
|
{ 843, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #843 = VCVTs2hd
|
|
{ 844, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #844 = VCVTs2hq
|
|
{ 845, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #845 = VCVTu2fd
|
|
{ 846, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #846 = VCVTu2fq
|
|
{ 847, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #847 = VCVTu2hd
|
|
{ 848, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #848 = VCVTu2hq
|
|
{ 849, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #849 = VCVTxs2fd
|
|
{ 850, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #850 = VCVTxs2fq
|
|
{ 851, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #851 = VCVTxs2hd
|
|
{ 852, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #852 = VCVTxs2hq
|
|
{ 853, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #853 = VCVTxu2fd
|
|
{ 854, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #854 = VCVTxu2fq
|
|
{ 855, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #855 = VCVTxu2hd
|
|
{ 856, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #856 = VCVTxu2hq
|
|
{ 857, 5, 1, 4, 610, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #857 = VDIVD
|
|
{ 858, 5, 1, 4, 114, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #858 = VDIVH
|
|
{ 859, 5, 1, 4, 608, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #859 = VDIVS
|
|
{ 860, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #860 = VDUP16d
|
|
{ 861, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #861 = VDUP16q
|
|
{ 862, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #862 = VDUP32d
|
|
{ 863, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #863 = VDUP32q
|
|
{ 864, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #864 = VDUP8d
|
|
{ 865, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #865 = VDUP8q
|
|
{ 866, 5, 1, 4, 516, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #866 = VDUPLN16d
|
|
{ 867, 5, 1, 4, 517, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #867 = VDUPLN16q
|
|
{ 868, 5, 1, 4, 516, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #868 = VDUPLN32d
|
|
{ 869, 5, 1, 4, 517, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #869 = VDUPLN32q
|
|
{ 870, 5, 1, 4, 516, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #870 = VDUPLN8d
|
|
{ 871, 5, 1, 4, 517, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #871 = VDUPLN8q
|
|
{ 872, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #872 = VEORd
|
|
{ 873, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #873 = VEORq
|
|
{ 874, 6, 1, 4, 413, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #874 = VEXTd16
|
|
{ 875, 6, 1, 4, 413, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #875 = VEXTd32
|
|
{ 876, 6, 1, 4, 413, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #876 = VEXTd8
|
|
{ 877, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #877 = VEXTq16
|
|
{ 878, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #878 = VEXTq32
|
|
{ 879, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #879 = VEXTq64
|
|
{ 880, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #880 = VEXTq8
|
|
{ 881, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #881 = VFMAD
|
|
{ 882, 6, 1, 4, 122, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #882 = VFMAH
|
|
{ 883, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #883 = VFMAS
|
|
{ 884, 6, 1, 4, 491, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #884 = VFMAfd
|
|
{ 885, 6, 1, 4, 492, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #885 = VFMAfq
|
|
{ 886, 6, 1, 4, 124, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #886 = VFMAhd
|
|
{ 887, 6, 1, 4, 125, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #887 = VFMAhq
|
|
{ 888, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #888 = VFMSD
|
|
{ 889, 6, 1, 4, 122, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #889 = VFMSH
|
|
{ 890, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #890 = VFMSS
|
|
{ 891, 6, 1, 4, 491, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #891 = VFMSfd
|
|
{ 892, 6, 1, 4, 492, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #892 = VFMSfq
|
|
{ 893, 6, 1, 4, 124, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #893 = VFMShd
|
|
{ 894, 6, 1, 4, 125, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #894 = VFMShq
|
|
{ 895, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #895 = VFNMAD
|
|
{ 896, 6, 1, 4, 481, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #896 = VFNMAH
|
|
{ 897, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #897 = VFNMAS
|
|
{ 898, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #898 = VFNMSD
|
|
{ 899, 6, 1, 4, 481, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #899 = VFNMSH
|
|
{ 900, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #900 = VFNMSS
|
|
{ 901, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #901 = VGETLNi32
|
|
{ 902, 5, 1, 4, 526, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #902 = VGETLNs16
|
|
{ 903, 5, 1, 4, 526, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #903 = VGETLNs8
|
|
{ 904, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #904 = VGETLNu16
|
|
{ 905, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #905 = VGETLNu8
|
|
{ 906, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #906 = VHADDsv16i8
|
|
{ 907, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #907 = VHADDsv2i32
|
|
{ 908, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #908 = VHADDsv4i16
|
|
{ 909, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #909 = VHADDsv4i32
|
|
{ 910, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #910 = VHADDsv8i16
|
|
{ 911, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #911 = VHADDsv8i8
|
|
{ 912, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #912 = VHADDuv16i8
|
|
{ 913, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #913 = VHADDuv2i32
|
|
{ 914, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #914 = VHADDuv4i16
|
|
{ 915, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #915 = VHADDuv4i32
|
|
{ 916, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #916 = VHADDuv8i16
|
|
{ 917, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #917 = VHADDuv8i8
|
|
{ 918, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #918 = VHSUBsv16i8
|
|
{ 919, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #919 = VHSUBsv2i32
|
|
{ 920, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #920 = VHSUBsv4i16
|
|
{ 921, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #921 = VHSUBsv4i32
|
|
{ 922, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #922 = VHSUBsv8i16
|
|
{ 923, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #923 = VHSUBsv8i8
|
|
{ 924, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #924 = VHSUBuv16i8
|
|
{ 925, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #925 = VHSUBuv2i32
|
|
{ 926, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #926 = VHSUBuv4i16
|
|
{ 927, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #927 = VHSUBuv4i32
|
|
{ 928, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #928 = VHSUBuv8i16
|
|
{ 929, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #929 = VHSUBuv8i8
|
|
{ 930, 2, 1, 4, 22, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #930 = VINSH
|
|
{ 931, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #931 = VLD1DUPd16
|
|
{ 932, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #932 = VLD1DUPd16wb_fixed
|
|
{ 933, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #933 = VLD1DUPd16wb_register
|
|
{ 934, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #934 = VLD1DUPd32
|
|
{ 935, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #935 = VLD1DUPd32wb_fixed
|
|
{ 936, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #936 = VLD1DUPd32wb_register
|
|
{ 937, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #937 = VLD1DUPd8
|
|
{ 938, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #938 = VLD1DUPd8wb_fixed
|
|
{ 939, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #939 = VLD1DUPd8wb_register
|
|
{ 940, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #940 = VLD1DUPq16
|
|
{ 941, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #941 = VLD1DUPq16wb_fixed
|
|
{ 942, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #942 = VLD1DUPq16wb_register
|
|
{ 943, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #943 = VLD1DUPq32
|
|
{ 944, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #944 = VLD1DUPq32wb_fixed
|
|
{ 945, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #945 = VLD1DUPq32wb_register
|
|
{ 946, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #946 = VLD1DUPq8
|
|
{ 947, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #947 = VLD1DUPq8wb_fixed
|
|
{ 948, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #948 = VLD1DUPq8wb_register
|
|
{ 949, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #949 = VLD1LNd16
|
|
{ 950, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #950 = VLD1LNd16_UPD
|
|
{ 951, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #951 = VLD1LNd32
|
|
{ 952, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #952 = VLD1LNd32_UPD
|
|
{ 953, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #953 = VLD1LNd8
|
|
{ 954, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #954 = VLD1LNd8_UPD
|
|
{ 955, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #955 = VLD1LNdAsm_16
|
|
{ 956, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #956 = VLD1LNdAsm_32
|
|
{ 957, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #957 = VLD1LNdAsm_8
|
|
{ 958, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #958 = VLD1LNdWB_fixed_Asm_16
|
|
{ 959, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #959 = VLD1LNdWB_fixed_Asm_32
|
|
{ 960, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #960 = VLD1LNdWB_fixed_Asm_8
|
|
{ 961, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #961 = VLD1LNdWB_register_Asm_16
|
|
{ 962, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #962 = VLD1LNdWB_register_Asm_32
|
|
{ 963, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #963 = VLD1LNdWB_register_Asm_8
|
|
{ 964, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #964 = VLD1LNq16Pseudo
|
|
{ 965, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #965 = VLD1LNq16Pseudo_UPD
|
|
{ 966, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #966 = VLD1LNq32Pseudo
|
|
{ 967, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #967 = VLD1LNq32Pseudo_UPD
|
|
{ 968, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #968 = VLD1LNq8Pseudo
|
|
{ 969, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #969 = VLD1LNq8Pseudo_UPD
|
|
{ 970, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #970 = VLD1d16
|
|
{ 971, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #971 = VLD1d16Q
|
|
{ 972, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #972 = VLD1d16Qwb_fixed
|
|
{ 973, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #973 = VLD1d16Qwb_register
|
|
{ 974, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #974 = VLD1d16T
|
|
{ 975, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #975 = VLD1d16Twb_fixed
|
|
{ 976, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #976 = VLD1d16Twb_register
|
|
{ 977, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #977 = VLD1d16wb_fixed
|
|
{ 978, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #978 = VLD1d16wb_register
|
|
{ 979, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #979 = VLD1d32
|
|
{ 980, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #980 = VLD1d32Q
|
|
{ 981, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #981 = VLD1d32Qwb_fixed
|
|
{ 982, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #982 = VLD1d32Qwb_register
|
|
{ 983, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #983 = VLD1d32T
|
|
{ 984, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #984 = VLD1d32Twb_fixed
|
|
{ 985, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #985 = VLD1d32Twb_register
|
|
{ 986, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #986 = VLD1d32wb_fixed
|
|
{ 987, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #987 = VLD1d32wb_register
|
|
{ 988, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #988 = VLD1d64
|
|
{ 989, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #989 = VLD1d64Q
|
|
{ 990, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #990 = VLD1d64QPseudo
|
|
{ 991, 6, 2, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #991 = VLD1d64QPseudoWB_fixed
|
|
{ 992, 7, 2, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #992 = VLD1d64QPseudoWB_register
|
|
{ 993, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #993 = VLD1d64Qwb_fixed
|
|
{ 994, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #994 = VLD1d64Qwb_register
|
|
{ 995, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #995 = VLD1d64T
|
|
{ 996, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #996 = VLD1d64TPseudo
|
|
{ 997, 6, 2, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #997 = VLD1d64TPseudoWB_fixed
|
|
{ 998, 7, 2, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #998 = VLD1d64TPseudoWB_register
|
|
{ 999, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #999 = VLD1d64Twb_fixed
|
|
{ 1000, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1000 = VLD1d64Twb_register
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|
{ 1001, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1001 = VLD1d64wb_fixed
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|
{ 1002, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1002 = VLD1d64wb_register
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|
{ 1003, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1003 = VLD1d8
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|
{ 1004, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1004 = VLD1d8Q
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|
{ 1005, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1005 = VLD1d8Qwb_fixed
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|
{ 1006, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1006 = VLD1d8Qwb_register
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|
{ 1007, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1007 = VLD1d8T
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|
{ 1008, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1008 = VLD1d8Twb_fixed
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|
{ 1009, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1009 = VLD1d8Twb_register
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|
{ 1010, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1010 = VLD1d8wb_fixed
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|
{ 1011, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1011 = VLD1d8wb_register
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|
{ 1012, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1012 = VLD1q16
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|
{ 1013, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1013 = VLD1q16wb_fixed
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|
{ 1014, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1014 = VLD1q16wb_register
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|
{ 1015, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1015 = VLD1q32
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|
{ 1016, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1016 = VLD1q32wb_fixed
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|
{ 1017, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1017 = VLD1q32wb_register
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|
{ 1018, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1018 = VLD1q64
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|
{ 1019, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1019 = VLD1q64wb_fixed
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|
{ 1020, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1020 = VLD1q64wb_register
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|
{ 1021, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1021 = VLD1q8
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|
{ 1022, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1022 = VLD1q8wb_fixed
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|
{ 1023, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1023 = VLD1q8wb_register
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|
{ 1024, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1024 = VLD2DUPd16
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|
{ 1025, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1025 = VLD2DUPd16wb_fixed
|
|
{ 1026, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1026 = VLD2DUPd16wb_register
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|
{ 1027, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1027 = VLD2DUPd16x2
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|
{ 1028, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1028 = VLD2DUPd16x2wb_fixed
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|
{ 1029, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1029 = VLD2DUPd16x2wb_register
|
|
{ 1030, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1030 = VLD2DUPd32
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|
{ 1031, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1031 = VLD2DUPd32wb_fixed
|
|
{ 1032, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1032 = VLD2DUPd32wb_register
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|
{ 1033, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1033 = VLD2DUPd32x2
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|
{ 1034, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1034 = VLD2DUPd32x2wb_fixed
|
|
{ 1035, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1035 = VLD2DUPd32x2wb_register
|
|
{ 1036, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1036 = VLD2DUPd8
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|
{ 1037, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1037 = VLD2DUPd8wb_fixed
|
|
{ 1038, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1038 = VLD2DUPd8wb_register
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|
{ 1039, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1039 = VLD2DUPd8x2
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|
{ 1040, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1040 = VLD2DUPd8x2wb_fixed
|
|
{ 1041, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1041 = VLD2DUPd8x2wb_register
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|
{ 1042, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1042 = VLD2LNd16
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|
{ 1043, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1043 = VLD2LNd16Pseudo
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|
{ 1044, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1044 = VLD2LNd16Pseudo_UPD
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|
{ 1045, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1045 = VLD2LNd16_UPD
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|
{ 1046, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1046 = VLD2LNd32
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|
{ 1047, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1047 = VLD2LNd32Pseudo
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|
{ 1048, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1048 = VLD2LNd32Pseudo_UPD
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|
{ 1049, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1049 = VLD2LNd32_UPD
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|
{ 1050, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1050 = VLD2LNd8
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|
{ 1051, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1051 = VLD2LNd8Pseudo
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|
{ 1052, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1052 = VLD2LNd8Pseudo_UPD
|
|
{ 1053, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1053 = VLD2LNd8_UPD
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|
{ 1054, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1054 = VLD2LNdAsm_16
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|
{ 1055, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1055 = VLD2LNdAsm_32
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|
{ 1056, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1056 = VLD2LNdAsm_8
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|
{ 1057, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1057 = VLD2LNdWB_fixed_Asm_16
|
|
{ 1058, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1058 = VLD2LNdWB_fixed_Asm_32
|
|
{ 1059, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1059 = VLD2LNdWB_fixed_Asm_8
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|
{ 1060, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1060 = VLD2LNdWB_register_Asm_16
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|
{ 1061, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1061 = VLD2LNdWB_register_Asm_32
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|
{ 1062, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1062 = VLD2LNdWB_register_Asm_8
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|
{ 1063, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1063 = VLD2LNq16
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|
{ 1064, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1064 = VLD2LNq16Pseudo
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|
{ 1065, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1065 = VLD2LNq16Pseudo_UPD
|
|
{ 1066, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1066 = VLD2LNq16_UPD
|
|
{ 1067, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1067 = VLD2LNq32
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|
{ 1068, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1068 = VLD2LNq32Pseudo
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|
{ 1069, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1069 = VLD2LNq32Pseudo_UPD
|
|
{ 1070, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1070 = VLD2LNq32_UPD
|
|
{ 1071, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1071 = VLD2LNqAsm_16
|
|
{ 1072, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1072 = VLD2LNqAsm_32
|
|
{ 1073, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1073 = VLD2LNqWB_fixed_Asm_16
|
|
{ 1074, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1074 = VLD2LNqWB_fixed_Asm_32
|
|
{ 1075, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1075 = VLD2LNqWB_register_Asm_16
|
|
{ 1076, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1076 = VLD2LNqWB_register_Asm_32
|
|
{ 1077, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1077 = VLD2b16
|
|
{ 1078, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1078 = VLD2b16wb_fixed
|
|
{ 1079, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1079 = VLD2b16wb_register
|
|
{ 1080, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1080 = VLD2b32
|
|
{ 1081, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1081 = VLD2b32wb_fixed
|
|
{ 1082, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1082 = VLD2b32wb_register
|
|
{ 1083, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1083 = VLD2b8
|
|
{ 1084, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1084 = VLD2b8wb_fixed
|
|
{ 1085, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1085 = VLD2b8wb_register
|
|
{ 1086, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1086 = VLD2d16
|
|
{ 1087, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1087 = VLD2d16wb_fixed
|
|
{ 1088, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1088 = VLD2d16wb_register
|
|
{ 1089, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1089 = VLD2d32
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{ 1090, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1090 = VLD2d32wb_fixed
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|
{ 1091, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1091 = VLD2d32wb_register
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|
{ 1092, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1092 = VLD2d8
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|
{ 1093, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1093 = VLD2d8wb_fixed
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|
{ 1094, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1094 = VLD2d8wb_register
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|
{ 1095, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1095 = VLD2q16
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|
{ 1096, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1096 = VLD2q16Pseudo
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{ 1097, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1097 = VLD2q16PseudoWB_fixed
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|
{ 1098, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1098 = VLD2q16PseudoWB_register
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{ 1099, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1099 = VLD2q16wb_fixed
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|
{ 1100, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1100 = VLD2q16wb_register
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|
{ 1101, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1101 = VLD2q32
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{ 1102, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1102 = VLD2q32Pseudo
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{ 1103, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1103 = VLD2q32PseudoWB_fixed
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|
{ 1104, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1104 = VLD2q32PseudoWB_register
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|
{ 1105, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1105 = VLD2q32wb_fixed
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|
{ 1106, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1106 = VLD2q32wb_register
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|
{ 1107, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1107 = VLD2q8
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{ 1108, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1108 = VLD2q8Pseudo
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{ 1109, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1109 = VLD2q8PseudoWB_fixed
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|
{ 1110, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1110 = VLD2q8PseudoWB_register
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|
{ 1111, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1111 = VLD2q8wb_fixed
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{ 1112, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1112 = VLD2q8wb_register
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|
{ 1113, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1113 = VLD3DUPd16
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|
{ 1114, 5, 1, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1114 = VLD3DUPd16Pseudo
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|
{ 1115, 7, 2, 4, 573, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1115 = VLD3DUPd16Pseudo_UPD
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|
{ 1116, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1116 = VLD3DUPd16_UPD
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|
{ 1117, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1117 = VLD3DUPd32
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|
{ 1118, 5, 1, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1118 = VLD3DUPd32Pseudo
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|
{ 1119, 7, 2, 4, 573, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1119 = VLD3DUPd32Pseudo_UPD
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|
{ 1120, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1120 = VLD3DUPd32_UPD
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|
{ 1121, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1121 = VLD3DUPd8
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|
{ 1122, 5, 1, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1122 = VLD3DUPd8Pseudo
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|
{ 1123, 7, 2, 4, 573, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1123 = VLD3DUPd8Pseudo_UPD
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|
{ 1124, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1124 = VLD3DUPd8_UPD
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|
{ 1125, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1125 = VLD3DUPdAsm_16
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|
{ 1126, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1126 = VLD3DUPdAsm_32
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|
{ 1127, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1127 = VLD3DUPdAsm_8
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|
{ 1128, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1128 = VLD3DUPdWB_fixed_Asm_16
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|
{ 1129, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1129 = VLD3DUPdWB_fixed_Asm_32
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|
{ 1130, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1130 = VLD3DUPdWB_fixed_Asm_8
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|
{ 1131, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1131 = VLD3DUPdWB_register_Asm_16
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|
{ 1132, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1132 = VLD3DUPdWB_register_Asm_32
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|
{ 1133, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1133 = VLD3DUPdWB_register_Asm_8
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|
{ 1134, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1134 = VLD3DUPq16
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{ 1135, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1135 = VLD3DUPq16_UPD
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|
{ 1136, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1136 = VLD3DUPq32
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{ 1137, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1137 = VLD3DUPq32_UPD
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|
{ 1138, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1138 = VLD3DUPq8
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|
{ 1139, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1139 = VLD3DUPq8_UPD
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|
{ 1140, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1140 = VLD3DUPqAsm_16
|
|
{ 1141, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1141 = VLD3DUPqAsm_32
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|
{ 1142, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1142 = VLD3DUPqAsm_8
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|
{ 1143, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1143 = VLD3DUPqWB_fixed_Asm_16
|
|
{ 1144, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1144 = VLD3DUPqWB_fixed_Asm_32
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|
{ 1145, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1145 = VLD3DUPqWB_fixed_Asm_8
|
|
{ 1146, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1146 = VLD3DUPqWB_register_Asm_16
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|
{ 1147, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1147 = VLD3DUPqWB_register_Asm_32
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|
{ 1148, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1148 = VLD3DUPqWB_register_Asm_8
|
|
{ 1149, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1149 = VLD3LNd16
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|
{ 1150, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1150 = VLD3LNd16Pseudo
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|
{ 1151, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1151 = VLD3LNd16Pseudo_UPD
|
|
{ 1152, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1152 = VLD3LNd16_UPD
|
|
{ 1153, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1153 = VLD3LNd32
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|
{ 1154, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1154 = VLD3LNd32Pseudo
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|
{ 1155, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1155 = VLD3LNd32Pseudo_UPD
|
|
{ 1156, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1156 = VLD3LNd32_UPD
|
|
{ 1157, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1157 = VLD3LNd8
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|
{ 1158, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1158 = VLD3LNd8Pseudo
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|
{ 1159, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1159 = VLD3LNd8Pseudo_UPD
|
|
{ 1160, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1160 = VLD3LNd8_UPD
|
|
{ 1161, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1161 = VLD3LNdAsm_16
|
|
{ 1162, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1162 = VLD3LNdAsm_32
|
|
{ 1163, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1163 = VLD3LNdAsm_8
|
|
{ 1164, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1164 = VLD3LNdWB_fixed_Asm_16
|
|
{ 1165, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1165 = VLD3LNdWB_fixed_Asm_32
|
|
{ 1166, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1166 = VLD3LNdWB_fixed_Asm_8
|
|
{ 1167, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1167 = VLD3LNdWB_register_Asm_16
|
|
{ 1168, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1168 = VLD3LNdWB_register_Asm_32
|
|
{ 1169, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1169 = VLD3LNdWB_register_Asm_8
|
|
{ 1170, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1170 = VLD3LNq16
|
|
{ 1171, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1171 = VLD3LNq16Pseudo
|
|
{ 1172, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1172 = VLD3LNq16Pseudo_UPD
|
|
{ 1173, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1173 = VLD3LNq16_UPD
|
|
{ 1174, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1174 = VLD3LNq32
|
|
{ 1175, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1175 = VLD3LNq32Pseudo
|
|
{ 1176, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1176 = VLD3LNq32Pseudo_UPD
|
|
{ 1177, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1177 = VLD3LNq32_UPD
|
|
{ 1178, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1178 = VLD3LNqAsm_16
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|
{ 1179, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1179 = VLD3LNqAsm_32
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|
{ 1180, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1180 = VLD3LNqWB_fixed_Asm_16
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|
{ 1181, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1181 = VLD3LNqWB_fixed_Asm_32
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|
{ 1182, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1182 = VLD3LNqWB_register_Asm_16
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|
{ 1183, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1183 = VLD3LNqWB_register_Asm_32
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|
{ 1184, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1184 = VLD3d16
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|
{ 1185, 5, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1185 = VLD3d16Pseudo
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|
{ 1186, 7, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1186 = VLD3d16Pseudo_UPD
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|
{ 1187, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1187 = VLD3d16_UPD
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|
{ 1188, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1188 = VLD3d32
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|
{ 1189, 5, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1189 = VLD3d32Pseudo
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|
{ 1190, 7, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1190 = VLD3d32Pseudo_UPD
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|
{ 1191, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1191 = VLD3d32_UPD
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|
{ 1192, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1192 = VLD3d8
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|
{ 1193, 5, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1193 = VLD3d8Pseudo
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|
{ 1194, 7, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1194 = VLD3d8Pseudo_UPD
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|
{ 1195, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1195 = VLD3d8_UPD
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|
{ 1196, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1196 = VLD3dAsm_16
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|
{ 1197, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1197 = VLD3dAsm_32
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|
{ 1198, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1198 = VLD3dAsm_8
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|
{ 1199, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1199 = VLD3dWB_fixed_Asm_16
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|
{ 1200, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1200 = VLD3dWB_fixed_Asm_32
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|
{ 1201, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1201 = VLD3dWB_fixed_Asm_8
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|
{ 1202, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1202 = VLD3dWB_register_Asm_16
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|
{ 1203, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1203 = VLD3dWB_register_Asm_32
|
|
{ 1204, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1204 = VLD3dWB_register_Asm_8
|
|
{ 1205, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1205 = VLD3q16
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|
{ 1206, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1206 = VLD3q16Pseudo_UPD
|
|
{ 1207, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1207 = VLD3q16_UPD
|
|
{ 1208, 6, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1208 = VLD3q16oddPseudo
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|
{ 1209, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1209 = VLD3q16oddPseudo_UPD
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|
{ 1210, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1210 = VLD3q32
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|
{ 1211, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1211 = VLD3q32Pseudo_UPD
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|
{ 1212, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1212 = VLD3q32_UPD
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|
{ 1213, 6, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1213 = VLD3q32oddPseudo
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|
{ 1214, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1214 = VLD3q32oddPseudo_UPD
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|
{ 1215, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1215 = VLD3q8
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|
{ 1216, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1216 = VLD3q8Pseudo_UPD
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|
{ 1217, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1217 = VLD3q8_UPD
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|
{ 1218, 6, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1218 = VLD3q8oddPseudo
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|
{ 1219, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1219 = VLD3q8oddPseudo_UPD
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|
{ 1220, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1220 = VLD3qAsm_16
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|
{ 1221, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1221 = VLD3qAsm_32
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|
{ 1222, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1222 = VLD3qAsm_8
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|
{ 1223, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1223 = VLD3qWB_fixed_Asm_16
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|
{ 1224, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1224 = VLD3qWB_fixed_Asm_32
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|
{ 1225, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1225 = VLD3qWB_fixed_Asm_8
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|
{ 1226, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1226 = VLD3qWB_register_Asm_16
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|
{ 1227, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1227 = VLD3qWB_register_Asm_32
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|
{ 1228, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1228 = VLD3qWB_register_Asm_8
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|
{ 1229, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1229 = VLD4DUPd16
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{ 1230, 5, 1, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1230 = VLD4DUPd16Pseudo
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|
{ 1231, 7, 2, 4, 579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1231 = VLD4DUPd16Pseudo_UPD
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|
{ 1232, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1232 = VLD4DUPd16_UPD
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|
{ 1233, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1233 = VLD4DUPd32
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|
{ 1234, 5, 1, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1234 = VLD4DUPd32Pseudo
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|
{ 1235, 7, 2, 4, 579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1235 = VLD4DUPd32Pseudo_UPD
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|
{ 1236, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1236 = VLD4DUPd32_UPD
|
|
{ 1237, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1237 = VLD4DUPd8
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|
{ 1238, 5, 1, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1238 = VLD4DUPd8Pseudo
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|
{ 1239, 7, 2, 4, 579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1239 = VLD4DUPd8Pseudo_UPD
|
|
{ 1240, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1240 = VLD4DUPd8_UPD
|
|
{ 1241, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1241 = VLD4DUPdAsm_16
|
|
{ 1242, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1242 = VLD4DUPdAsm_32
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|
{ 1243, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1243 = VLD4DUPdAsm_8
|
|
{ 1244, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1244 = VLD4DUPdWB_fixed_Asm_16
|
|
{ 1245, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1245 = VLD4DUPdWB_fixed_Asm_32
|
|
{ 1246, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1246 = VLD4DUPdWB_fixed_Asm_8
|
|
{ 1247, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1247 = VLD4DUPdWB_register_Asm_16
|
|
{ 1248, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1248 = VLD4DUPdWB_register_Asm_32
|
|
{ 1249, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1249 = VLD4DUPdWB_register_Asm_8
|
|
{ 1250, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1250 = VLD4DUPq16
|
|
{ 1251, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1251 = VLD4DUPq16_UPD
|
|
{ 1252, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1252 = VLD4DUPq32
|
|
{ 1253, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1253 = VLD4DUPq32_UPD
|
|
{ 1254, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1254 = VLD4DUPq8
|
|
{ 1255, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1255 = VLD4DUPq8_UPD
|
|
{ 1256, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1256 = VLD4DUPqAsm_16
|
|
{ 1257, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1257 = VLD4DUPqAsm_32
|
|
{ 1258, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1258 = VLD4DUPqAsm_8
|
|
{ 1259, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1259 = VLD4DUPqWB_fixed_Asm_16
|
|
{ 1260, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1260 = VLD4DUPqWB_fixed_Asm_32
|
|
{ 1261, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1261 = VLD4DUPqWB_fixed_Asm_8
|
|
{ 1262, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1262 = VLD4DUPqWB_register_Asm_16
|
|
{ 1263, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1263 = VLD4DUPqWB_register_Asm_32
|
|
{ 1264, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1264 = VLD4DUPqWB_register_Asm_8
|
|
{ 1265, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1265 = VLD4LNd16
|
|
{ 1266, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1266 = VLD4LNd16Pseudo
|
|
{ 1267, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1267 = VLD4LNd16Pseudo_UPD
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|
{ 1268, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1268 = VLD4LNd16_UPD
|
|
{ 1269, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1269 = VLD4LNd32
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|
{ 1270, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1270 = VLD4LNd32Pseudo
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|
{ 1271, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1271 = VLD4LNd32Pseudo_UPD
|
|
{ 1272, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1272 = VLD4LNd32_UPD
|
|
{ 1273, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1273 = VLD4LNd8
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|
{ 1274, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1274 = VLD4LNd8Pseudo
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|
{ 1275, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1275 = VLD4LNd8Pseudo_UPD
|
|
{ 1276, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1276 = VLD4LNd8_UPD
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|
{ 1277, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1277 = VLD4LNdAsm_16
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|
{ 1278, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1278 = VLD4LNdAsm_32
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|
{ 1279, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1279 = VLD4LNdAsm_8
|
|
{ 1280, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1280 = VLD4LNdWB_fixed_Asm_16
|
|
{ 1281, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1281 = VLD4LNdWB_fixed_Asm_32
|
|
{ 1282, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1282 = VLD4LNdWB_fixed_Asm_8
|
|
{ 1283, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1283 = VLD4LNdWB_register_Asm_16
|
|
{ 1284, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1284 = VLD4LNdWB_register_Asm_32
|
|
{ 1285, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1285 = VLD4LNdWB_register_Asm_8
|
|
{ 1286, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1286 = VLD4LNq16
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|
{ 1287, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1287 = VLD4LNq16Pseudo
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|
{ 1288, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1288 = VLD4LNq16Pseudo_UPD
|
|
{ 1289, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1289 = VLD4LNq16_UPD
|
|
{ 1290, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1290 = VLD4LNq32
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|
{ 1291, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1291 = VLD4LNq32Pseudo
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|
{ 1292, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1292 = VLD4LNq32Pseudo_UPD
|
|
{ 1293, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1293 = VLD4LNq32_UPD
|
|
{ 1294, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1294 = VLD4LNqAsm_16
|
|
{ 1295, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1295 = VLD4LNqAsm_32
|
|
{ 1296, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1296 = VLD4LNqWB_fixed_Asm_16
|
|
{ 1297, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1297 = VLD4LNqWB_fixed_Asm_32
|
|
{ 1298, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1298 = VLD4LNqWB_register_Asm_16
|
|
{ 1299, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1299 = VLD4LNqWB_register_Asm_32
|
|
{ 1300, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1300 = VLD4d16
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|
{ 1301, 5, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1301 = VLD4d16Pseudo
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|
{ 1302, 7, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1302 = VLD4d16Pseudo_UPD
|
|
{ 1303, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1303 = VLD4d16_UPD
|
|
{ 1304, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1304 = VLD4d32
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|
{ 1305, 5, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1305 = VLD4d32Pseudo
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|
{ 1306, 7, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1306 = VLD4d32Pseudo_UPD
|
|
{ 1307, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1307 = VLD4d32_UPD
|
|
{ 1308, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1308 = VLD4d8
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|
{ 1309, 5, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1309 = VLD4d8Pseudo
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|
{ 1310, 7, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1310 = VLD4d8Pseudo_UPD
|
|
{ 1311, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1311 = VLD4d8_UPD
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|
{ 1312, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1312 = VLD4dAsm_16
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|
{ 1313, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1313 = VLD4dAsm_32
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|
{ 1314, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1314 = VLD4dAsm_8
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|
{ 1315, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1315 = VLD4dWB_fixed_Asm_16
|
|
{ 1316, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1316 = VLD4dWB_fixed_Asm_32
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|
{ 1317, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1317 = VLD4dWB_fixed_Asm_8
|
|
{ 1318, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1318 = VLD4dWB_register_Asm_16
|
|
{ 1319, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1319 = VLD4dWB_register_Asm_32
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|
{ 1320, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1320 = VLD4dWB_register_Asm_8
|
|
{ 1321, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1321 = VLD4q16
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{ 1322, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1322 = VLD4q16Pseudo_UPD
|
|
{ 1323, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1323 = VLD4q16_UPD
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|
{ 1324, 6, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1324 = VLD4q16oddPseudo
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{ 1325, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1325 = VLD4q16oddPseudo_UPD
|
|
{ 1326, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1326 = VLD4q32
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|
{ 1327, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1327 = VLD4q32Pseudo_UPD
|
|
{ 1328, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1328 = VLD4q32_UPD
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|
{ 1329, 6, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1329 = VLD4q32oddPseudo
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|
{ 1330, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1330 = VLD4q32oddPseudo_UPD
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|
{ 1331, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1331 = VLD4q8
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{ 1332, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1332 = VLD4q8Pseudo_UPD
|
|
{ 1333, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1333 = VLD4q8_UPD
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|
{ 1334, 6, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1334 = VLD4q8oddPseudo
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|
{ 1335, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1335 = VLD4q8oddPseudo_UPD
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{ 1336, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1336 = VLD4qAsm_16
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|
{ 1337, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1337 = VLD4qAsm_32
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|
{ 1338, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1338 = VLD4qAsm_8
|
|
{ 1339, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1339 = VLD4qWB_fixed_Asm_16
|
|
{ 1340, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1340 = VLD4qWB_fixed_Asm_32
|
|
{ 1341, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1341 = VLD4qWB_fixed_Asm_8
|
|
{ 1342, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1342 = VLD4qWB_register_Asm_16
|
|
{ 1343, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1343 = VLD4qWB_register_Asm_32
|
|
{ 1344, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1344 = VLD4qWB_register_Asm_8
|
|
{ 1345, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1345 = VLDMDDB_UPD
|
|
{ 1346, 4, 0, 4, 536, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1346 = VLDMDIA
|
|
{ 1347, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1347 = VLDMDIA_UPD
|
|
{ 1348, 4, 1, 4, 534, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1348 = VLDMQIA
|
|
{ 1349, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1349 = VLDMSDB_UPD
|
|
{ 1350, 4, 0, 4, 536, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1350 = VLDMSIA
|
|
{ 1351, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1351 = VLDMSIA_UPD
|
|
{ 1352, 5, 1, 4, 530, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1352 = VLDRD
|
|
{ 1353, 5, 1, 4, 161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x18b05ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1353 = VLDRH
|
|
{ 1354, 5, 1, 4, 531, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1354 = VLDRS
|
|
{ 1355, 3, 0, 4, 159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1355 = VLLDM
|
|
{ 1356, 3, 0, 4, 163, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1356 = VLSTM
|
|
{ 1357, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1357 = VMAXNMD
|
|
{ 1358, 3, 1, 4, 463, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1358 = VMAXNMH
|
|
{ 1359, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1359 = VMAXNMNDf
|
|
{ 1360, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1360 = VMAXNMNDh
|
|
{ 1361, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1361 = VMAXNMNQf
|
|
{ 1362, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1362 = VMAXNMNQh
|
|
{ 1363, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1363 = VMAXNMS
|
|
{ 1364, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1364 = VMAXfd
|
|
{ 1365, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1365 = VMAXfq
|
|
{ 1366, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1366 = VMAXhd
|
|
{ 1367, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1367 = VMAXhq
|
|
{ 1368, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1368 = VMAXsv16i8
|
|
{ 1369, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1369 = VMAXsv2i32
|
|
{ 1370, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1370 = VMAXsv4i16
|
|
{ 1371, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1371 = VMAXsv4i32
|
|
{ 1372, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1372 = VMAXsv8i16
|
|
{ 1373, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1373 = VMAXsv8i8
|
|
{ 1374, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1374 = VMAXuv16i8
|
|
{ 1375, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1375 = VMAXuv2i32
|
|
{ 1376, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1376 = VMAXuv4i16
|
|
{ 1377, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1377 = VMAXuv4i32
|
|
{ 1378, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1378 = VMAXuv8i16
|
|
{ 1379, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1379 = VMAXuv8i8
|
|
{ 1380, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1380 = VMINNMD
|
|
{ 1381, 3, 1, 4, 463, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1381 = VMINNMH
|
|
{ 1382, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1382 = VMINNMNDf
|
|
{ 1383, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1383 = VMINNMNDh
|
|
{ 1384, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1384 = VMINNMNQf
|
|
{ 1385, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1385 = VMINNMNQh
|
|
{ 1386, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1386 = VMINNMS
|
|
{ 1387, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1387 = VMINfd
|
|
{ 1388, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1388 = VMINfq
|
|
{ 1389, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1389 = VMINhd
|
|
{ 1390, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1390 = VMINhq
|
|
{ 1391, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1391 = VMINsv16i8
|
|
{ 1392, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1392 = VMINsv2i32
|
|
{ 1393, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1393 = VMINsv4i16
|
|
{ 1394, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1394 = VMINsv4i32
|
|
{ 1395, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1395 = VMINsv8i16
|
|
{ 1396, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1396 = VMINsv8i8
|
|
{ 1397, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1397 = VMINuv16i8
|
|
{ 1398, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1398 = VMINuv2i32
|
|
{ 1399, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1399 = VMINuv4i16
|
|
{ 1400, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1400 = VMINuv4i32
|
|
{ 1401, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1401 = VMINuv8i16
|
|
{ 1402, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1402 = VMINuv8i8
|
|
{ 1403, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1403 = VMLAD
|
|
{ 1404, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1404 = VMLAH
|
|
{ 1405, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1405 = VMLALslsv2i32
|
|
{ 1406, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1406 = VMLALslsv4i16
|
|
{ 1407, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1407 = VMLALsluv2i32
|
|
{ 1408, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1408 = VMLALsluv4i16
|
|
{ 1409, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1409 = VMLALsv2i64
|
|
{ 1410, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1410 = VMLALsv4i32
|
|
{ 1411, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1411 = VMLALsv8i16
|
|
{ 1412, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1412 = VMLALuv2i64
|
|
{ 1413, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1413 = VMLALuv4i32
|
|
{ 1414, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1414 = VMLALuv8i16
|
|
{ 1415, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1415 = VMLAS
|
|
{ 1416, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1416 = VMLAfd
|
|
{ 1417, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1417 = VMLAfq
|
|
{ 1418, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1418 = VMLAhd
|
|
{ 1419, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1419 = VMLAhq
|
|
{ 1420, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1420 = VMLAslfd
|
|
{ 1421, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1421 = VMLAslfq
|
|
{ 1422, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1422 = VMLAslhd
|
|
{ 1423, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1423 = VMLAslhq
|
|
{ 1424, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1424 = VMLAslv2i32
|
|
{ 1425, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1425 = VMLAslv4i16
|
|
{ 1426, 7, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1426 = VMLAslv4i32
|
|
{ 1427, 7, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1427 = VMLAslv8i16
|
|
{ 1428, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1428 = VMLAv16i8
|
|
{ 1429, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1429 = VMLAv2i32
|
|
{ 1430, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1430 = VMLAv4i16
|
|
{ 1431, 6, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1431 = VMLAv4i32
|
|
{ 1432, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1432 = VMLAv8i16
|
|
{ 1433, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1433 = VMLAv8i8
|
|
{ 1434, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1434 = VMLSD
|
|
{ 1435, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1435 = VMLSH
|
|
{ 1436, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1436 = VMLSLslsv2i32
|
|
{ 1437, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1437 = VMLSLslsv4i16
|
|
{ 1438, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1438 = VMLSLsluv2i32
|
|
{ 1439, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1439 = VMLSLsluv4i16
|
|
{ 1440, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1440 = VMLSLsv2i64
|
|
{ 1441, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1441 = VMLSLsv4i32
|
|
{ 1442, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1442 = VMLSLsv8i16
|
|
{ 1443, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1443 = VMLSLuv2i64
|
|
{ 1444, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1444 = VMLSLuv4i32
|
|
{ 1445, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1445 = VMLSLuv8i16
|
|
{ 1446, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1446 = VMLSS
|
|
{ 1447, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1447 = VMLSfd
|
|
{ 1448, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1448 = VMLSfq
|
|
{ 1449, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1449 = VMLShd
|
|
{ 1450, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1450 = VMLShq
|
|
{ 1451, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1451 = VMLSslfd
|
|
{ 1452, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1452 = VMLSslfq
|
|
{ 1453, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1453 = VMLSslhd
|
|
{ 1454, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1454 = VMLSslhq
|
|
{ 1455, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1455 = VMLSslv2i32
|
|
{ 1456, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1456 = VMLSslv4i16
|
|
{ 1457, 7, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1457 = VMLSslv4i32
|
|
{ 1458, 7, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1458 = VMLSslv8i16
|
|
{ 1459, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1459 = VMLSv16i8
|
|
{ 1460, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1460 = VMLSv2i32
|
|
{ 1461, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1461 = VMLSv4i16
|
|
{ 1462, 6, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1462 = VMLSv4i32
|
|
{ 1463, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1463 = VMLSv8i16
|
|
{ 1464, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1464 = VMLSv8i8
|
|
{ 1465, 4, 1, 4, 509, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1465 = VMOVD
|
|
{ 1466, 1, 1, 4, 103, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1466 = VMOVD0
|
|
{ 1467, 5, 1, 4, 523, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::RegSequence), 0x18a80ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1467 = VMOVDRR
|
|
{ 1468, 5, 1, 0, 509, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1468 = VMOVDcc
|
|
{ 1469, 2, 1, 4, 22, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1469 = VMOVH
|
|
{ 1470, 4, 1, 4, 174, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8a00ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1470 = VMOVHR
|
|
{ 1471, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1471 = VMOVLsv2i64
|
|
{ 1472, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1472 = VMOVLsv4i32
|
|
{ 1473, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1473 = VMOVLsv8i16
|
|
{ 1474, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1474 = VMOVLuv2i64
|
|
{ 1475, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1475 = VMOVLuv4i32
|
|
{ 1476, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1476 = VMOVLuv8i16
|
|
{ 1477, 4, 1, 4, 514, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1477 = VMOVNv2i32
|
|
{ 1478, 4, 1, 4, 514, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1478 = VMOVNv4i16
|
|
{ 1479, 4, 1, 4, 514, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1479 = VMOVNv8i8
|
|
{ 1480, 1, 1, 4, 103, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1480 = VMOVQ0
|
|
{ 1481, 4, 1, 4, 177, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8900ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1481 = VMOVRH
|
|
{ 1482, 5, 2, 4, 522, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtractSubreg), 0x18980ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1482 = VMOVRRD
|
|
{ 1483, 6, 2, 4, 522, 0|(1ULL<<MCID::Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1483 = VMOVRRS
|
|
{ 1484, 4, 1, 4, 519, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1484 = VMOVRS
|
|
{ 1485, 4, 1, 4, 510, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1485 = VMOVS
|
|
{ 1486, 4, 1, 4, 520, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1486 = VMOVSR
|
|
{ 1487, 6, 2, 4, 524, 0|(1ULL<<MCID::Predicable), 0x18a80ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1487 = VMOVSRR
|
|
{ 1488, 5, 1, 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1488 = VMOVScc
|
|
{ 1489, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1489 = VMOVv16i8
|
|
{ 1490, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1490 = VMOVv1i64
|
|
{ 1491, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1491 = VMOVv2f32
|
|
{ 1492, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1492 = VMOVv2i32
|
|
{ 1493, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1493 = VMOVv2i64
|
|
{ 1494, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1494 = VMOVv4f32
|
|
{ 1495, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1495 = VMOVv4i16
|
|
{ 1496, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1496 = VMOVv4i32
|
|
{ 1497, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1497 = VMOVv8i16
|
|
{ 1498, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1498 = VMOVv8i8
|
|
{ 1499, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1499 = VMRS
|
|
{ 1500, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1500 = VMRS_FPEXC
|
|
{ 1501, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1501 = VMRS_FPINST
|
|
{ 1502, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1502 = VMRS_FPINST2
|
|
{ 1503, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1503 = VMRS_FPSID
|
|
{ 1504, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1504 = VMRS_MVFR0
|
|
{ 1505, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1505 = VMRS_MVFR1
|
|
{ 1506, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1506 = VMRS_MVFR2
|
|
{ 1507, 3, 0, 4, 528, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1507 = VMSR
|
|
{ 1508, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1508 = VMSR_FPEXC
|
|
{ 1509, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1509 = VMSR_FPINST
|
|
{ 1510, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1510 = VMSR_FPINST2
|
|
{ 1511, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1511 = VMSR_FPSID
|
|
{ 1512, 5, 1, 4, 478, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1512 = VMULD
|
|
{ 1513, 5, 1, 4, 180, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1513 = VMULH
|
|
{ 1514, 3, 1, 4, 468, 0, 0x11280ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1514 = VMULLp64
|
|
{ 1515, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1515 = VMULLp8
|
|
{ 1516, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1516 = VMULLslsv2i32
|
|
{ 1517, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1517 = VMULLslsv4i16
|
|
{ 1518, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1518 = VMULLsluv2i32
|
|
{ 1519, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1519 = VMULLsluv4i16
|
|
{ 1520, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1520 = VMULLsv2i64
|
|
{ 1521, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1521 = VMULLsv4i32
|
|
{ 1522, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1522 = VMULLsv8i16
|
|
{ 1523, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1523 = VMULLuv2i64
|
|
{ 1524, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1524 = VMULLuv4i32
|
|
{ 1525, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1525 = VMULLuv8i16
|
|
{ 1526, 5, 1, 4, 471, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1526 = VMULS
|
|
{ 1527, 5, 1, 4, 472, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1527 = VMULfd
|
|
{ 1528, 5, 1, 4, 473, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1528 = VMULfq
|
|
{ 1529, 5, 1, 4, 184, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1529 = VMULhd
|
|
{ 1530, 5, 1, 4, 185, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1530 = VMULhq
|
|
{ 1531, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1531 = VMULpd
|
|
{ 1532, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1532 = VMULpq
|
|
{ 1533, 6, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1533 = VMULslfd
|
|
{ 1534, 6, 1, 4, 476, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1534 = VMULslfq
|
|
{ 1535, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1535 = VMULslhd
|
|
{ 1536, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1536 = VMULslhq
|
|
{ 1537, 6, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1537 = VMULslv2i32
|
|
{ 1538, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1538 = VMULslv4i16
|
|
{ 1539, 6, 1, 4, 477, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1539 = VMULslv4i32
|
|
{ 1540, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1540 = VMULslv8i16
|
|
{ 1541, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1541 = VMULv16i8
|
|
{ 1542, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1542 = VMULv2i32
|
|
{ 1543, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1543 = VMULv4i16
|
|
{ 1544, 5, 1, 4, 477, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1544 = VMULv4i32
|
|
{ 1545, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1545 = VMULv8i16
|
|
{ 1546, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1546 = VMULv8i8
|
|
{ 1547, 4, 1, 4, 512, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1547 = VMVNd
|
|
{ 1548, 4, 1, 4, 512, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1548 = VMVNq
|
|
{ 1549, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1549 = VMVNv2i32
|
|
{ 1550, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1550 = VMVNv4i16
|
|
{ 1551, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1551 = VMVNv4i32
|
|
{ 1552, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1552 = VMVNv8i16
|
|
{ 1553, 4, 1, 4, 454, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1553 = VNEGD
|
|
{ 1554, 4, 1, 4, 22, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1554 = VNEGH
|
|
{ 1555, 4, 1, 4, 455, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1555 = VNEGS
|
|
{ 1556, 4, 1, 4, 407, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1556 = VNEGf32q
|
|
{ 1557, 4, 1, 4, 408, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1557 = VNEGfd
|
|
{ 1558, 4, 1, 4, 91, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1558 = VNEGhd
|
|
{ 1559, 4, 1, 4, 92, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1559 = VNEGhq
|
|
{ 1560, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1560 = VNEGs16d
|
|
{ 1561, 4, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1561 = VNEGs16q
|
|
{ 1562, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1562 = VNEGs32d
|
|
{ 1563, 4, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1563 = VNEGs32q
|
|
{ 1564, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1564 = VNEGs8d
|
|
{ 1565, 4, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1565 = VNEGs8q
|
|
{ 1566, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1566 = VNMLAD
|
|
{ 1567, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1567 = VNMLAH
|
|
{ 1568, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1568 = VNMLAS
|
|
{ 1569, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1569 = VNMLSD
|
|
{ 1570, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1570 = VNMLSH
|
|
{ 1571, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1571 = VNMLSS
|
|
{ 1572, 5, 1, 4, 478, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1572 = VNMULD
|
|
{ 1573, 5, 1, 4, 180, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1573 = VNMULH
|
|
{ 1574, 5, 1, 4, 471, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1574 = VNMULS
|
|
{ 1575, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1575 = VORNd
|
|
{ 1576, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1576 = VORNq
|
|
{ 1577, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1577 = VORRd
|
|
{ 1578, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1578 = VORRiv2i32
|
|
{ 1579, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1579 = VORRiv4i16
|
|
{ 1580, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1580 = VORRiv4i32
|
|
{ 1581, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1581 = VORRiv8i16
|
|
{ 1582, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1582 = VORRq
|
|
{ 1583, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1583 = VPADALsv16i8
|
|
{ 1584, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1584 = VPADALsv2i32
|
|
{ 1585, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1585 = VPADALsv4i16
|
|
{ 1586, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1586 = VPADALsv4i32
|
|
{ 1587, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1587 = VPADALsv8i16
|
|
{ 1588, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1588 = VPADALsv8i8
|
|
{ 1589, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1589 = VPADALuv16i8
|
|
{ 1590, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1590 = VPADALuv2i32
|
|
{ 1591, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1591 = VPADALuv4i16
|
|
{ 1592, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1592 = VPADALuv4i32
|
|
{ 1593, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1593 = VPADALuv8i16
|
|
{ 1594, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1594 = VPADALuv8i8
|
|
{ 1595, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1595 = VPADDLsv16i8
|
|
{ 1596, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1596 = VPADDLsv2i32
|
|
{ 1597, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1597 = VPADDLsv4i16
|
|
{ 1598, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1598 = VPADDLsv4i32
|
|
{ 1599, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1599 = VPADDLsv8i16
|
|
{ 1600, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1600 = VPADDLsv8i8
|
|
{ 1601, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1601 = VPADDLuv16i8
|
|
{ 1602, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1602 = VPADDLuv2i32
|
|
{ 1603, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1603 = VPADDLuv4i16
|
|
{ 1604, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1604 = VPADDLuv4i32
|
|
{ 1605, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1605 = VPADDLuv8i16
|
|
{ 1606, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1606 = VPADDLuv8i8
|
|
{ 1607, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1607 = VPADDf
|
|
{ 1608, 5, 1, 4, 191, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1608 = VPADDh
|
|
{ 1609, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1609 = VPADDi16
|
|
{ 1610, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1610 = VPADDi32
|
|
{ 1611, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1611 = VPADDi8
|
|
{ 1612, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1612 = VPMAXf
|
|
{ 1613, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1613 = VPMAXh
|
|
{ 1614, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1614 = VPMAXs16
|
|
{ 1615, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1615 = VPMAXs32
|
|
{ 1616, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1616 = VPMAXs8
|
|
{ 1617, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1617 = VPMAXu16
|
|
{ 1618, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1618 = VPMAXu32
|
|
{ 1619, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1619 = VPMAXu8
|
|
{ 1620, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1620 = VPMINf
|
|
{ 1621, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1621 = VPMINh
|
|
{ 1622, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1622 = VPMINs16
|
|
{ 1623, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1623 = VPMINs32
|
|
{ 1624, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1624 = VPMINs8
|
|
{ 1625, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1625 = VPMINu16
|
|
{ 1626, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1626 = VPMINu32
|
|
{ 1627, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1627 = VPMINu8
|
|
{ 1628, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1628 = VQABSv16i8
|
|
{ 1629, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1629 = VQABSv2i32
|
|
{ 1630, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1630 = VQABSv4i16
|
|
{ 1631, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1631 = VQABSv4i32
|
|
{ 1632, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1632 = VQABSv8i16
|
|
{ 1633, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1633 = VQABSv8i8
|
|
{ 1634, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1634 = VQADDsv16i8
|
|
{ 1635, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1635 = VQADDsv1i64
|
|
{ 1636, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1636 = VQADDsv2i32
|
|
{ 1637, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1637 = VQADDsv2i64
|
|
{ 1638, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1638 = VQADDsv4i16
|
|
{ 1639, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1639 = VQADDsv4i32
|
|
{ 1640, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1640 = VQADDsv8i16
|
|
{ 1641, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1641 = VQADDsv8i8
|
|
{ 1642, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1642 = VQADDuv16i8
|
|
{ 1643, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1643 = VQADDuv1i64
|
|
{ 1644, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1644 = VQADDuv2i32
|
|
{ 1645, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1645 = VQADDuv2i64
|
|
{ 1646, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1646 = VQADDuv4i16
|
|
{ 1647, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1647 = VQADDuv4i32
|
|
{ 1648, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1648 = VQADDuv8i16
|
|
{ 1649, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1649 = VQADDuv8i8
|
|
{ 1650, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1650 = VQDMLALslv2i32
|
|
{ 1651, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1651 = VQDMLALslv4i16
|
|
{ 1652, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1652 = VQDMLALv2i64
|
|
{ 1653, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1653 = VQDMLALv4i32
|
|
{ 1654, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1654 = VQDMLSLslv2i32
|
|
{ 1655, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1655 = VQDMLSLslv4i16
|
|
{ 1656, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1656 = VQDMLSLv2i64
|
|
{ 1657, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1657 = VQDMLSLv4i32
|
|
{ 1658, 6, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1658 = VQDMULHslv2i32
|
|
{ 1659, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1659 = VQDMULHslv4i16
|
|
{ 1660, 6, 1, 4, 477, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1660 = VQDMULHslv4i32
|
|
{ 1661, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1661 = VQDMULHslv8i16
|
|
{ 1662, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1662 = VQDMULHv2i32
|
|
{ 1663, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1663 = VQDMULHv4i16
|
|
{ 1664, 5, 1, 4, 477, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1664 = VQDMULHv4i32
|
|
{ 1665, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1665 = VQDMULHv8i16
|
|
{ 1666, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1666 = VQDMULLslv2i32
|
|
{ 1667, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1667 = VQDMULLslv4i16
|
|
{ 1668, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1668 = VQDMULLv2i64
|
|
{ 1669, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1669 = VQDMULLv4i32
|
|
{ 1670, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1670 = VQMOVNsuv2i32
|
|
{ 1671, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1671 = VQMOVNsuv4i16
|
|
{ 1672, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1672 = VQMOVNsuv8i8
|
|
{ 1673, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1673 = VQMOVNsv2i32
|
|
{ 1674, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1674 = VQMOVNsv4i16
|
|
{ 1675, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1675 = VQMOVNsv8i8
|
|
{ 1676, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1676 = VQMOVNuv2i32
|
|
{ 1677, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1677 = VQMOVNuv4i16
|
|
{ 1678, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1678 = VQMOVNuv8i8
|
|
{ 1679, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1679 = VQNEGv16i8
|
|
{ 1680, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1680 = VQNEGv2i32
|
|
{ 1681, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1681 = VQNEGv4i16
|
|
{ 1682, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1682 = VQNEGv4i32
|
|
{ 1683, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1683 = VQNEGv8i16
|
|
{ 1684, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1684 = VQNEGv8i8
|
|
{ 1685, 7, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1685 = VQRDMLAHslv2i32
|
|
{ 1686, 7, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1686 = VQRDMLAHslv4i16
|
|
{ 1687, 7, 1, 4, 171, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1687 = VQRDMLAHslv4i32
|
|
{ 1688, 7, 1, 4, 172, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1688 = VQRDMLAHslv8i16
|
|
{ 1689, 6, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1689 = VQRDMLAHv2i32
|
|
{ 1690, 6, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1690 = VQRDMLAHv4i16
|
|
{ 1691, 6, 1, 4, 171, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1691 = VQRDMLAHv4i32
|
|
{ 1692, 6, 1, 4, 172, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1692 = VQRDMLAHv8i16
|
|
{ 1693, 7, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1693 = VQRDMLSHslv2i32
|
|
{ 1694, 7, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1694 = VQRDMLSHslv4i16
|
|
{ 1695, 7, 1, 4, 171, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1695 = VQRDMLSHslv4i32
|
|
{ 1696, 7, 1, 4, 172, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1696 = VQRDMLSHslv8i16
|
|
{ 1697, 6, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1697 = VQRDMLSHv2i32
|
|
{ 1698, 6, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1698 = VQRDMLSHv4i16
|
|
{ 1699, 6, 1, 4, 171, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1699 = VQRDMLSHv4i32
|
|
{ 1700, 6, 1, 4, 172, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1700 = VQRDMLSHv8i16
|
|
{ 1701, 6, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1701 = VQRDMULHslv2i32
|
|
{ 1702, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1702 = VQRDMULHslv4i16
|
|
{ 1703, 6, 1, 4, 477, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1703 = VQRDMULHslv4i32
|
|
{ 1704, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1704 = VQRDMULHslv8i16
|
|
{ 1705, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1705 = VQRDMULHv2i32
|
|
{ 1706, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1706 = VQRDMULHv4i16
|
|
{ 1707, 5, 1, 4, 477, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1707 = VQRDMULHv4i32
|
|
{ 1708, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1708 = VQRDMULHv8i16
|
|
{ 1709, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1709 = VQRSHLsv16i8
|
|
{ 1710, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1710 = VQRSHLsv1i64
|
|
{ 1711, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1711 = VQRSHLsv2i32
|
|
{ 1712, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1712 = VQRSHLsv2i64
|
|
{ 1713, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1713 = VQRSHLsv4i16
|
|
{ 1714, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1714 = VQRSHLsv4i32
|
|
{ 1715, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1715 = VQRSHLsv8i16
|
|
{ 1716, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1716 = VQRSHLsv8i8
|
|
{ 1717, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1717 = VQRSHLuv16i8
|
|
{ 1718, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1718 = VQRSHLuv1i64
|
|
{ 1719, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1719 = VQRSHLuv2i32
|
|
{ 1720, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1720 = VQRSHLuv2i64
|
|
{ 1721, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1721 = VQRSHLuv4i16
|
|
{ 1722, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1722 = VQRSHLuv4i32
|
|
{ 1723, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1723 = VQRSHLuv8i16
|
|
{ 1724, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1724 = VQRSHLuv8i8
|
|
{ 1725, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1725 = VQRSHRNsv2i32
|
|
{ 1726, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1726 = VQRSHRNsv4i16
|
|
{ 1727, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1727 = VQRSHRNsv8i8
|
|
{ 1728, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1728 = VQRSHRNuv2i32
|
|
{ 1729, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1729 = VQRSHRNuv4i16
|
|
{ 1730, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1730 = VQRSHRNuv8i8
|
|
{ 1731, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1731 = VQRSHRUNv2i32
|
|
{ 1732, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1732 = VQRSHRUNv4i16
|
|
{ 1733, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1733 = VQRSHRUNv8i8
|
|
{ 1734, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1734 = VQSHLsiv16i8
|
|
{ 1735, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1735 = VQSHLsiv1i64
|
|
{ 1736, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1736 = VQSHLsiv2i32
|
|
{ 1737, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1737 = VQSHLsiv2i64
|
|
{ 1738, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1738 = VQSHLsiv4i16
|
|
{ 1739, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1739 = VQSHLsiv4i32
|
|
{ 1740, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1740 = VQSHLsiv8i16
|
|
{ 1741, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1741 = VQSHLsiv8i8
|
|
{ 1742, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1742 = VQSHLsuv16i8
|
|
{ 1743, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1743 = VQSHLsuv1i64
|
|
{ 1744, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1744 = VQSHLsuv2i32
|
|
{ 1745, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1745 = VQSHLsuv2i64
|
|
{ 1746, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1746 = VQSHLsuv4i16
|
|
{ 1747, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1747 = VQSHLsuv4i32
|
|
{ 1748, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1748 = VQSHLsuv8i16
|
|
{ 1749, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1749 = VQSHLsuv8i8
|
|
{ 1750, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1750 = VQSHLsv16i8
|
|
{ 1751, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1751 = VQSHLsv1i64
|
|
{ 1752, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1752 = VQSHLsv2i32
|
|
{ 1753, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1753 = VQSHLsv2i64
|
|
{ 1754, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1754 = VQSHLsv4i16
|
|
{ 1755, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1755 = VQSHLsv4i32
|
|
{ 1756, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1756 = VQSHLsv8i16
|
|
{ 1757, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1757 = VQSHLsv8i8
|
|
{ 1758, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1758 = VQSHLuiv16i8
|
|
{ 1759, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1759 = VQSHLuiv1i64
|
|
{ 1760, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1760 = VQSHLuiv2i32
|
|
{ 1761, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1761 = VQSHLuiv2i64
|
|
{ 1762, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1762 = VQSHLuiv4i16
|
|
{ 1763, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1763 = VQSHLuiv4i32
|
|
{ 1764, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1764 = VQSHLuiv8i16
|
|
{ 1765, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1765 = VQSHLuiv8i8
|
|
{ 1766, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1766 = VQSHLuv16i8
|
|
{ 1767, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1767 = VQSHLuv1i64
|
|
{ 1768, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1768 = VQSHLuv2i32
|
|
{ 1769, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1769 = VQSHLuv2i64
|
|
{ 1770, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1770 = VQSHLuv4i16
|
|
{ 1771, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1771 = VQSHLuv4i32
|
|
{ 1772, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1772 = VQSHLuv8i16
|
|
{ 1773, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1773 = VQSHLuv8i8
|
|
{ 1774, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1774 = VQSHRNsv2i32
|
|
{ 1775, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1775 = VQSHRNsv4i16
|
|
{ 1776, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1776 = VQSHRNsv8i8
|
|
{ 1777, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1777 = VQSHRNuv2i32
|
|
{ 1778, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1778 = VQSHRNuv4i16
|
|
{ 1779, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1779 = VQSHRNuv8i8
|
|
{ 1780, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1780 = VQSHRUNv2i32
|
|
{ 1781, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1781 = VQSHRUNv4i16
|
|
{ 1782, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1782 = VQSHRUNv8i8
|
|
{ 1783, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1783 = VQSUBsv16i8
|
|
{ 1784, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1784 = VQSUBsv1i64
|
|
{ 1785, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1785 = VQSUBsv2i32
|
|
{ 1786, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1786 = VQSUBsv2i64
|
|
{ 1787, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1787 = VQSUBsv4i16
|
|
{ 1788, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1788 = VQSUBsv4i32
|
|
{ 1789, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1789 = VQSUBsv8i16
|
|
{ 1790, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1790 = VQSUBsv8i8
|
|
{ 1791, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1791 = VQSUBuv16i8
|
|
{ 1792, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1792 = VQSUBuv1i64
|
|
{ 1793, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1793 = VQSUBuv2i32
|
|
{ 1794, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1794 = VQSUBuv2i64
|
|
{ 1795, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1795 = VQSUBuv4i16
|
|
{ 1796, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1796 = VQSUBuv4i32
|
|
{ 1797, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1797 = VQSUBuv8i16
|
|
{ 1798, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1798 = VQSUBuv8i8
|
|
{ 1799, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1799 = VRADDHNv2i32
|
|
{ 1800, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1800 = VRADDHNv4i16
|
|
{ 1801, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1801 = VRADDHNv8i8
|
|
{ 1802, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1802 = VRECPEd
|
|
{ 1803, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1803 = VRECPEfd
|
|
{ 1804, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1804 = VRECPEfq
|
|
{ 1805, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1805 = VRECPEhd
|
|
{ 1806, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1806 = VRECPEhq
|
|
{ 1807, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1807 = VRECPEq
|
|
{ 1808, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1808 = VRECPSfd
|
|
{ 1809, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1809 = VRECPSfq
|
|
{ 1810, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1810 = VRECPShd
|
|
{ 1811, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1811 = VRECPShq
|
|
{ 1812, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1812 = VREV16d8
|
|
{ 1813, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1813 = VREV16q8
|
|
{ 1814, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1814 = VREV32d16
|
|
{ 1815, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1815 = VREV32d8
|
|
{ 1816, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1816 = VREV32q16
|
|
{ 1817, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1817 = VREV32q8
|
|
{ 1818, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1818 = VREV64d16
|
|
{ 1819, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1819 = VREV64d32
|
|
{ 1820, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1820 = VREV64d8
|
|
{ 1821, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1821 = VREV64q16
|
|
{ 1822, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1822 = VREV64q32
|
|
{ 1823, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1823 = VREV64q8
|
|
{ 1824, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1824 = VRHADDsv16i8
|
|
{ 1825, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1825 = VRHADDsv2i32
|
|
{ 1826, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1826 = VRHADDsv4i16
|
|
{ 1827, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1827 = VRHADDsv4i32
|
|
{ 1828, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1828 = VRHADDsv8i16
|
|
{ 1829, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1829 = VRHADDsv8i8
|
|
{ 1830, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1830 = VRHADDuv16i8
|
|
{ 1831, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1831 = VRHADDuv2i32
|
|
{ 1832, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1832 = VRHADDuv4i16
|
|
{ 1833, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1833 = VRHADDuv4i32
|
|
{ 1834, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1834 = VRHADDuv8i16
|
|
{ 1835, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1835 = VRHADDuv8i8
|
|
{ 1836, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1836 = VRINTAD
|
|
{ 1837, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1837 = VRINTAH
|
|
{ 1838, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1838 = VRINTANDf
|
|
{ 1839, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1839 = VRINTANDh
|
|
{ 1840, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1840 = VRINTANQf
|
|
{ 1841, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1841 = VRINTANQh
|
|
{ 1842, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1842 = VRINTAS
|
|
{ 1843, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1843 = VRINTMD
|
|
{ 1844, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1844 = VRINTMH
|
|
{ 1845, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1845 = VRINTMNDf
|
|
{ 1846, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1846 = VRINTMNDh
|
|
{ 1847, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1847 = VRINTMNQf
|
|
{ 1848, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1848 = VRINTMNQh
|
|
{ 1849, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1849 = VRINTMS
|
|
{ 1850, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1850 = VRINTND
|
|
{ 1851, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1851 = VRINTNH
|
|
{ 1852, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1852 = VRINTNNDf
|
|
{ 1853, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1853 = VRINTNNDh
|
|
{ 1854, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1854 = VRINTNNQf
|
|
{ 1855, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1855 = VRINTNNQh
|
|
{ 1856, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1856 = VRINTNS
|
|
{ 1857, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1857 = VRINTPD
|
|
{ 1858, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1858 = VRINTPH
|
|
{ 1859, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1859 = VRINTPNDf
|
|
{ 1860, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1860 = VRINTPNDh
|
|
{ 1861, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1861 = VRINTPNQf
|
|
{ 1862, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1862 = VRINTPNQh
|
|
{ 1863, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1863 = VRINTPS
|
|
{ 1864, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1864 = VRINTRD
|
|
{ 1865, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1865 = VRINTRH
|
|
{ 1866, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1866 = VRINTRS
|
|
{ 1867, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1867 = VRINTXD
|
|
{ 1868, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1868 = VRINTXH
|
|
{ 1869, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1869 = VRINTXNDf
|
|
{ 1870, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1870 = VRINTXNDh
|
|
{ 1871, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1871 = VRINTXNQf
|
|
{ 1872, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1872 = VRINTXNQh
|
|
{ 1873, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1873 = VRINTXS
|
|
{ 1874, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1874 = VRINTZD
|
|
{ 1875, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1875 = VRINTZH
|
|
{ 1876, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1876 = VRINTZNDf
|
|
{ 1877, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1877 = VRINTZNDh
|
|
{ 1878, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1878 = VRINTZNQf
|
|
{ 1879, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1879 = VRINTZNQh
|
|
{ 1880, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1880 = VRINTZS
|
|
{ 1881, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1881 = VRSHLsv16i8
|
|
{ 1882, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1882 = VRSHLsv1i64
|
|
{ 1883, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1883 = VRSHLsv2i32
|
|
{ 1884, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1884 = VRSHLsv2i64
|
|
{ 1885, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1885 = VRSHLsv4i16
|
|
{ 1886, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1886 = VRSHLsv4i32
|
|
{ 1887, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1887 = VRSHLsv8i16
|
|
{ 1888, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1888 = VRSHLsv8i8
|
|
{ 1889, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1889 = VRSHLuv16i8
|
|
{ 1890, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1890 = VRSHLuv1i64
|
|
{ 1891, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1891 = VRSHLuv2i32
|
|
{ 1892, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1892 = VRSHLuv2i64
|
|
{ 1893, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1893 = VRSHLuv4i16
|
|
{ 1894, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1894 = VRSHLuv4i32
|
|
{ 1895, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1895 = VRSHLuv8i16
|
|
{ 1896, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1896 = VRSHLuv8i8
|
|
{ 1897, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1897 = VRSHRNv2i32
|
|
{ 1898, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1898 = VRSHRNv4i16
|
|
{ 1899, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1899 = VRSHRNv8i8
|
|
{ 1900, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1900 = VRSHRsv16i8
|
|
{ 1901, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1901 = VRSHRsv1i64
|
|
{ 1902, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1902 = VRSHRsv2i32
|
|
{ 1903, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1903 = VRSHRsv2i64
|
|
{ 1904, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1904 = VRSHRsv4i16
|
|
{ 1905, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1905 = VRSHRsv4i32
|
|
{ 1906, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1906 = VRSHRsv8i16
|
|
{ 1907, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1907 = VRSHRsv8i8
|
|
{ 1908, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1908 = VRSHRuv16i8
|
|
{ 1909, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1909 = VRSHRuv1i64
|
|
{ 1910, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1910 = VRSHRuv2i32
|
|
{ 1911, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1911 = VRSHRuv2i64
|
|
{ 1912, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1912 = VRSHRuv4i16
|
|
{ 1913, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1913 = VRSHRuv4i32
|
|
{ 1914, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1914 = VRSHRuv8i16
|
|
{ 1915, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1915 = VRSHRuv8i8
|
|
{ 1916, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1916 = VRSQRTEd
|
|
{ 1917, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1917 = VRSQRTEfd
|
|
{ 1918, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1918 = VRSQRTEfq
|
|
{ 1919, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1919 = VRSQRTEhd
|
|
{ 1920, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1920 = VRSQRTEhq
|
|
{ 1921, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1921 = VRSQRTEq
|
|
{ 1922, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1922 = VRSQRTSfd
|
|
{ 1923, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1923 = VRSQRTSfq
|
|
{ 1924, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1924 = VRSQRTShd
|
|
{ 1925, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1925 = VRSQRTShq
|
|
{ 1926, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1926 = VRSRAsv16i8
|
|
{ 1927, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1927 = VRSRAsv1i64
|
|
{ 1928, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1928 = VRSRAsv2i32
|
|
{ 1929, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1929 = VRSRAsv2i64
|
|
{ 1930, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1930 = VRSRAsv4i16
|
|
{ 1931, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1931 = VRSRAsv4i32
|
|
{ 1932, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1932 = VRSRAsv8i16
|
|
{ 1933, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1933 = VRSRAsv8i8
|
|
{ 1934, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1934 = VRSRAuv16i8
|
|
{ 1935, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1935 = VRSRAuv1i64
|
|
{ 1936, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1936 = VRSRAuv2i32
|
|
{ 1937, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1937 = VRSRAuv2i64
|
|
{ 1938, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1938 = VRSRAuv4i16
|
|
{ 1939, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1939 = VRSRAuv4i32
|
|
{ 1940, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1940 = VRSRAuv8i16
|
|
{ 1941, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1941 = VRSRAuv8i8
|
|
{ 1942, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1942 = VRSUBHNv2i32
|
|
{ 1943, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1943 = VRSUBHNv4i16
|
|
{ 1944, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1944 = VRSUBHNv8i8
|
|
{ 1945, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1945 = VSELEQD
|
|
{ 1946, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1946 = VSELEQH
|
|
{ 1947, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1947 = VSELEQS
|
|
{ 1948, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1948 = VSELGED
|
|
{ 1949, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1949 = VSELGEH
|
|
{ 1950, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1950 = VSELGES
|
|
{ 1951, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1951 = VSELGTD
|
|
{ 1952, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1952 = VSELGTH
|
|
{ 1953, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1953 = VSELGTS
|
|
{ 1954, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1954 = VSELVSD
|
|
{ 1955, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1955 = VSELVSH
|
|
{ 1956, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1956 = VSELVSS
|
|
{ 1957, 6, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1957 = VSETLNi16
|
|
{ 1958, 6, 1, 4, 521, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x10e00ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1958 = VSETLNi32
|
|
{ 1959, 6, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1959 = VSETLNi8
|
|
{ 1960, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1960 = VSHLLi16
|
|
{ 1961, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1961 = VSHLLi32
|
|
{ 1962, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1962 = VSHLLi8
|
|
{ 1963, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1963 = VSHLLsv2i64
|
|
{ 1964, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1964 = VSHLLsv4i32
|
|
{ 1965, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1965 = VSHLLsv8i16
|
|
{ 1966, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1966 = VSHLLuv2i64
|
|
{ 1967, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1967 = VSHLLuv4i32
|
|
{ 1968, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1968 = VSHLLuv8i16
|
|
{ 1969, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1969 = VSHLiv16i8
|
|
{ 1970, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1970 = VSHLiv1i64
|
|
{ 1971, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1971 = VSHLiv2i32
|
|
{ 1972, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1972 = VSHLiv2i64
|
|
{ 1973, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1973 = VSHLiv4i16
|
|
{ 1974, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1974 = VSHLiv4i32
|
|
{ 1975, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1975 = VSHLiv8i16
|
|
{ 1976, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1976 = VSHLiv8i8
|
|
{ 1977, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1977 = VSHLsv16i8
|
|
{ 1978, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1978 = VSHLsv1i64
|
|
{ 1979, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1979 = VSHLsv2i32
|
|
{ 1980, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1980 = VSHLsv2i64
|
|
{ 1981, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1981 = VSHLsv4i16
|
|
{ 1982, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1982 = VSHLsv4i32
|
|
{ 1983, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1983 = VSHLsv8i16
|
|
{ 1984, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1984 = VSHLsv8i8
|
|
{ 1985, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1985 = VSHLuv16i8
|
|
{ 1986, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1986 = VSHLuv1i64
|
|
{ 1987, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1987 = VSHLuv2i32
|
|
{ 1988, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1988 = VSHLuv2i64
|
|
{ 1989, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1989 = VSHLuv4i16
|
|
{ 1990, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1990 = VSHLuv4i32
|
|
{ 1991, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1991 = VSHLuv8i16
|
|
{ 1992, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1992 = VSHLuv8i8
|
|
{ 1993, 5, 1, 4, 439, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1993 = VSHRNv2i32
|
|
{ 1994, 5, 1, 4, 439, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1994 = VSHRNv4i16
|
|
{ 1995, 5, 1, 4, 439, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1995 = VSHRNv8i8
|
|
{ 1996, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1996 = VSHRsv16i8
|
|
{ 1997, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1997 = VSHRsv1i64
|
|
{ 1998, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1998 = VSHRsv2i32
|
|
{ 1999, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1999 = VSHRsv2i64
|
|
{ 2000, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2000 = VSHRsv4i16
|
|
{ 2001, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2001 = VSHRsv4i32
|
|
{ 2002, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2002 = VSHRsv8i16
|
|
{ 2003, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2003 = VSHRsv8i8
|
|
{ 2004, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2004 = VSHRuv16i8
|
|
{ 2005, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2005 = VSHRuv1i64
|
|
{ 2006, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2006 = VSHRuv2i32
|
|
{ 2007, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2007 = VSHRuv2i64
|
|
{ 2008, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2008 = VSHRuv4i16
|
|
{ 2009, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2009 = VSHRuv4i32
|
|
{ 2010, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2010 = VSHRuv8i16
|
|
{ 2011, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2011 = VSHRuv8i8
|
|
{ 2012, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2012 = VSHTOD
|
|
{ 2013, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2013 = VSHTOH
|
|
{ 2014, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2014 = VSHTOS
|
|
{ 2015, 4, 1, 4, 500, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2015 = VSITOD
|
|
{ 2016, 4, 1, 4, 501, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2016 = VSITOH
|
|
{ 2017, 4, 1, 4, 502, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2017 = VSITOS
|
|
{ 2018, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2018 = VSLIv16i8
|
|
{ 2019, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2019 = VSLIv1i64
|
|
{ 2020, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2020 = VSLIv2i32
|
|
{ 2021, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2021 = VSLIv2i64
|
|
{ 2022, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2022 = VSLIv4i16
|
|
{ 2023, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2023 = VSLIv4i32
|
|
{ 2024, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2024 = VSLIv8i16
|
|
{ 2025, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2025 = VSLIv8i8
|
|
{ 2026, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2026 = VSLTOD
|
|
{ 2027, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2027 = VSLTOH
|
|
{ 2028, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2028 = VSLTOS
|
|
{ 2029, 4, 1, 4, 611, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #2029 = VSQRTD
|
|
{ 2030, 4, 1, 4, 205, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2030 = VSQRTH
|
|
{ 2031, 4, 1, 4, 609, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2031 = VSQRTS
|
|
{ 2032, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2032 = VSRAsv16i8
|
|
{ 2033, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2033 = VSRAsv1i64
|
|
{ 2034, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2034 = VSRAsv2i32
|
|
{ 2035, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2035 = VSRAsv2i64
|
|
{ 2036, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2036 = VSRAsv4i16
|
|
{ 2037, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2037 = VSRAsv4i32
|
|
{ 2038, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2038 = VSRAsv8i16
|
|
{ 2039, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2039 = VSRAsv8i8
|
|
{ 2040, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2040 = VSRAuv16i8
|
|
{ 2041, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2041 = VSRAuv1i64
|
|
{ 2042, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2042 = VSRAuv2i32
|
|
{ 2043, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2043 = VSRAuv2i64
|
|
{ 2044, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2044 = VSRAuv4i16
|
|
{ 2045, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2045 = VSRAuv4i32
|
|
{ 2046, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2046 = VSRAuv8i16
|
|
{ 2047, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2047 = VSRAuv8i8
|
|
{ 2048, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2048 = VSRIv16i8
|
|
{ 2049, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2049 = VSRIv1i64
|
|
{ 2050, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2050 = VSRIv2i32
|
|
{ 2051, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2051 = VSRIv2i64
|
|
{ 2052, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2052 = VSRIv4i16
|
|
{ 2053, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2053 = VSRIv4i32
|
|
{ 2054, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2054 = VSRIv8i16
|
|
{ 2055, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2055 = VSRIv8i8
|
|
{ 2056, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #2056 = VST1LNd16
|
|
{ 2057, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2057 = VST1LNd16_UPD
|
|
{ 2058, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #2058 = VST1LNd32
|
|
{ 2059, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2059 = VST1LNd32_UPD
|
|
{ 2060, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #2060 = VST1LNd8
|
|
{ 2061, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2061 = VST1LNd8_UPD
|
|
{ 2062, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2062 = VST1LNdAsm_16
|
|
{ 2063, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2063 = VST1LNdAsm_32
|
|
{ 2064, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2064 = VST1LNdAsm_8
|
|
{ 2065, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2065 = VST1LNdWB_fixed_Asm_16
|
|
{ 2066, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2066 = VST1LNdWB_fixed_Asm_32
|
|
{ 2067, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2067 = VST1LNdWB_fixed_Asm_8
|
|
{ 2068, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2068 = VST1LNdWB_register_Asm_16
|
|
{ 2069, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2069 = VST1LNdWB_register_Asm_32
|
|
{ 2070, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2070 = VST1LNdWB_register_Asm_8
|
|
{ 2071, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2071 = VST1LNq16Pseudo
|
|
{ 2072, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2072 = VST1LNq16Pseudo_UPD
|
|
{ 2073, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2073 = VST1LNq32Pseudo
|
|
{ 2074, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2074 = VST1LNq32Pseudo_UPD
|
|
{ 2075, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2075 = VST1LNq8Pseudo
|
|
{ 2076, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2076 = VST1LNq8Pseudo_UPD
|
|
{ 2077, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2077 = VST1d16
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|
{ 2078, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2078 = VST1d16Q
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|
{ 2079, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2079 = VST1d16Qwb_fixed
|
|
{ 2080, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2080 = VST1d16Qwb_register
|
|
{ 2081, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2081 = VST1d16T
|
|
{ 2082, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2082 = VST1d16Twb_fixed
|
|
{ 2083, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2083 = VST1d16Twb_register
|
|
{ 2084, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2084 = VST1d16wb_fixed
|
|
{ 2085, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2085 = VST1d16wb_register
|
|
{ 2086, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2086 = VST1d32
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|
{ 2087, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2087 = VST1d32Q
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|
{ 2088, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2088 = VST1d32Qwb_fixed
|
|
{ 2089, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2089 = VST1d32Qwb_register
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|
{ 2090, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2090 = VST1d32T
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|
{ 2091, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2091 = VST1d32Twb_fixed
|
|
{ 2092, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2092 = VST1d32Twb_register
|
|
{ 2093, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2093 = VST1d32wb_fixed
|
|
{ 2094, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2094 = VST1d32wb_register
|
|
{ 2095, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2095 = VST1d64
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|
{ 2096, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2096 = VST1d64Q
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|
{ 2097, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2097 = VST1d64QPseudo
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|
{ 2098, 6, 1, 4, 590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2098 = VST1d64QPseudoWB_fixed
|
|
{ 2099, 7, 1, 4, 590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2099 = VST1d64QPseudoWB_register
|
|
{ 2100, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2100 = VST1d64Qwb_fixed
|
|
{ 2101, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2101 = VST1d64Qwb_register
|
|
{ 2102, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2102 = VST1d64T
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|
{ 2103, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2103 = VST1d64TPseudo
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|
{ 2104, 6, 1, 4, 587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2104 = VST1d64TPseudoWB_fixed
|
|
{ 2105, 7, 1, 4, 587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2105 = VST1d64TPseudoWB_register
|
|
{ 2106, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2106 = VST1d64Twb_fixed
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|
{ 2107, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2107 = VST1d64Twb_register
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|
{ 2108, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2108 = VST1d64wb_fixed
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|
{ 2109, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2109 = VST1d64wb_register
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|
{ 2110, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2110 = VST1d8
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|
{ 2111, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2111 = VST1d8Q
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|
{ 2112, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2112 = VST1d8Qwb_fixed
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|
{ 2113, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2113 = VST1d8Qwb_register
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|
{ 2114, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2114 = VST1d8T
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{ 2115, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2115 = VST1d8Twb_fixed
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|
{ 2116, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2116 = VST1d8Twb_register
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{ 2117, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2117 = VST1d8wb_fixed
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|
{ 2118, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2118 = VST1d8wb_register
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{ 2119, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2119 = VST1q16
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{ 2120, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2120 = VST1q16wb_fixed
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{ 2121, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2121 = VST1q16wb_register
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{ 2122, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2122 = VST1q32
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{ 2123, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2123 = VST1q32wb_fixed
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{ 2124, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2124 = VST1q32wb_register
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{ 2125, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2125 = VST1q64
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{ 2126, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2126 = VST1q64wb_fixed
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{ 2127, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2127 = VST1q64wb_register
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{ 2128, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2128 = VST1q8
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{ 2129, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2129 = VST1q8wb_fixed
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{ 2130, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2130 = VST1q8wb_register
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{ 2131, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2131 = VST2LNd16
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{ 2132, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2132 = VST2LNd16Pseudo
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{ 2133, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2133 = VST2LNd16Pseudo_UPD
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{ 2134, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2134 = VST2LNd16_UPD
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{ 2135, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2135 = VST2LNd32
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{ 2136, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2136 = VST2LNd32Pseudo
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{ 2137, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2137 = VST2LNd32Pseudo_UPD
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{ 2138, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2138 = VST2LNd32_UPD
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{ 2139, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2139 = VST2LNd8
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|
{ 2140, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2140 = VST2LNd8Pseudo
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{ 2141, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2141 = VST2LNd8Pseudo_UPD
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|
{ 2142, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2142 = VST2LNd8_UPD
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{ 2143, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2143 = VST2LNdAsm_16
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{ 2144, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2144 = VST2LNdAsm_32
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{ 2145, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2145 = VST2LNdAsm_8
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|
{ 2146, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2146 = VST2LNdWB_fixed_Asm_16
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|
{ 2147, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2147 = VST2LNdWB_fixed_Asm_32
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|
{ 2148, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2148 = VST2LNdWB_fixed_Asm_8
|
|
{ 2149, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2149 = VST2LNdWB_register_Asm_16
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|
{ 2150, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2150 = VST2LNdWB_register_Asm_32
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|
{ 2151, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2151 = VST2LNdWB_register_Asm_8
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{ 2152, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2152 = VST2LNq16
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{ 2153, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2153 = VST2LNq16Pseudo
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{ 2154, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2154 = VST2LNq16Pseudo_UPD
|
|
{ 2155, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2155 = VST2LNq16_UPD
|
|
{ 2156, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2156 = VST2LNq32
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|
{ 2157, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2157 = VST2LNq32Pseudo
|
|
{ 2158, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2158 = VST2LNq32Pseudo_UPD
|
|
{ 2159, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2159 = VST2LNq32_UPD
|
|
{ 2160, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2160 = VST2LNqAsm_16
|
|
{ 2161, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2161 = VST2LNqAsm_32
|
|
{ 2162, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2162 = VST2LNqWB_fixed_Asm_16
|
|
{ 2163, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2163 = VST2LNqWB_fixed_Asm_32
|
|
{ 2164, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2164 = VST2LNqWB_register_Asm_16
|
|
{ 2165, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2165 = VST2LNqWB_register_Asm_32
|
|
{ 2166, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2166 = VST2b16
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|
{ 2167, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2167 = VST2b16wb_fixed
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|
{ 2168, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2168 = VST2b16wb_register
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|
{ 2169, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2169 = VST2b32
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|
{ 2170, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2170 = VST2b32wb_fixed
|
|
{ 2171, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2171 = VST2b32wb_register
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|
{ 2172, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2172 = VST2b8
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|
{ 2173, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2173 = VST2b8wb_fixed
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|
{ 2174, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2174 = VST2b8wb_register
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|
{ 2175, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2175 = VST2d16
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|
{ 2176, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2176 = VST2d16wb_fixed
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|
{ 2177, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2177 = VST2d16wb_register
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|
{ 2178, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2178 = VST2d32
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|
{ 2179, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2179 = VST2d32wb_fixed
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|
{ 2180, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2180 = VST2d32wb_register
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|
{ 2181, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2181 = VST2d8
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|
{ 2182, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2182 = VST2d8wb_fixed
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|
{ 2183, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2183 = VST2d8wb_register
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|
{ 2184, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2184 = VST2q16
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|
{ 2185, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2185 = VST2q16Pseudo
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|
{ 2186, 6, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2186 = VST2q16PseudoWB_fixed
|
|
{ 2187, 7, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #2187 = VST2q16PseudoWB_register
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|
{ 2188, 6, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2188 = VST2q16wb_fixed
|
|
{ 2189, 7, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2189 = VST2q16wb_register
|
|
{ 2190, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2190 = VST2q32
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|
{ 2191, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2191 = VST2q32Pseudo
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|
{ 2192, 6, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2192 = VST2q32PseudoWB_fixed
|
|
{ 2193, 7, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #2193 = VST2q32PseudoWB_register
|
|
{ 2194, 6, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2194 = VST2q32wb_fixed
|
|
{ 2195, 7, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2195 = VST2q32wb_register
|
|
{ 2196, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2196 = VST2q8
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|
{ 2197, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2197 = VST2q8Pseudo
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|
{ 2198, 6, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2198 = VST2q8PseudoWB_fixed
|
|
{ 2199, 7, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #2199 = VST2q8PseudoWB_register
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|
{ 2200, 6, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2200 = VST2q8wb_fixed
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|
{ 2201, 7, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2201 = VST2q8wb_register
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|
{ 2202, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2202 = VST3LNd16
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|
{ 2203, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2203 = VST3LNd16Pseudo
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|
{ 2204, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2204 = VST3LNd16Pseudo_UPD
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{ 2205, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2205 = VST3LNd16_UPD
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|
{ 2206, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2206 = VST3LNd32
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|
{ 2207, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2207 = VST3LNd32Pseudo
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{ 2208, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2208 = VST3LNd32Pseudo_UPD
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{ 2209, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2209 = VST3LNd32_UPD
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|
{ 2210, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2210 = VST3LNd8
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{ 2211, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2211 = VST3LNd8Pseudo
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{ 2212, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2212 = VST3LNd8Pseudo_UPD
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{ 2213, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2213 = VST3LNd8_UPD
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|
{ 2214, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2214 = VST3LNdAsm_16
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{ 2215, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2215 = VST3LNdAsm_32
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{ 2216, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2216 = VST3LNdAsm_8
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{ 2217, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2217 = VST3LNdWB_fixed_Asm_16
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{ 2218, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2218 = VST3LNdWB_fixed_Asm_32
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{ 2219, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2219 = VST3LNdWB_fixed_Asm_8
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{ 2220, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2220 = VST3LNdWB_register_Asm_16
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{ 2221, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2221 = VST3LNdWB_register_Asm_32
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{ 2222, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2222 = VST3LNdWB_register_Asm_8
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{ 2223, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2223 = VST3LNq16
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{ 2224, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2224 = VST3LNq16Pseudo
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{ 2225, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2225 = VST3LNq16Pseudo_UPD
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{ 2226, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2226 = VST3LNq16_UPD
|
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{ 2227, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2227 = VST3LNq32
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{ 2228, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2228 = VST3LNq32Pseudo
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{ 2229, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2229 = VST3LNq32Pseudo_UPD
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{ 2230, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2230 = VST3LNq32_UPD
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{ 2231, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2231 = VST3LNqAsm_16
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{ 2232, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2232 = VST3LNqAsm_32
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{ 2233, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2233 = VST3LNqWB_fixed_Asm_16
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{ 2234, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2234 = VST3LNqWB_fixed_Asm_32
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{ 2235, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2235 = VST3LNqWB_register_Asm_16
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{ 2236, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2236 = VST3LNqWB_register_Asm_32
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{ 2237, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2237 = VST3d16
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|
{ 2238, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2238 = VST3d16Pseudo
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{ 2239, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2239 = VST3d16Pseudo_UPD
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{ 2240, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2240 = VST3d16_UPD
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|
{ 2241, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2241 = VST3d32
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{ 2242, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2242 = VST3d32Pseudo
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|
{ 2243, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2243 = VST3d32Pseudo_UPD
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|
{ 2244, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2244 = VST3d32_UPD
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|
{ 2245, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2245 = VST3d8
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|
{ 2246, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2246 = VST3d8Pseudo
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|
{ 2247, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2247 = VST3d8Pseudo_UPD
|
|
{ 2248, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2248 = VST3d8_UPD
|
|
{ 2249, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2249 = VST3dAsm_16
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|
{ 2250, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2250 = VST3dAsm_32
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|
{ 2251, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2251 = VST3dAsm_8
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|
{ 2252, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2252 = VST3dWB_fixed_Asm_16
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|
{ 2253, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2253 = VST3dWB_fixed_Asm_32
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|
{ 2254, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2254 = VST3dWB_fixed_Asm_8
|
|
{ 2255, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2255 = VST3dWB_register_Asm_16
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|
{ 2256, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2256 = VST3dWB_register_Asm_32
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|
{ 2257, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2257 = VST3dWB_register_Asm_8
|
|
{ 2258, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2258 = VST3q16
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|
{ 2259, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2259 = VST3q16Pseudo_UPD
|
|
{ 2260, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2260 = VST3q16_UPD
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|
{ 2261, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2261 = VST3q16oddPseudo
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|
{ 2262, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2262 = VST3q16oddPseudo_UPD
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|
{ 2263, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2263 = VST3q32
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|
{ 2264, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2264 = VST3q32Pseudo_UPD
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|
{ 2265, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2265 = VST3q32_UPD
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|
{ 2266, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2266 = VST3q32oddPseudo
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|
{ 2267, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2267 = VST3q32oddPseudo_UPD
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|
{ 2268, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2268 = VST3q8
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|
{ 2269, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2269 = VST3q8Pseudo_UPD
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|
{ 2270, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2270 = VST3q8_UPD
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|
{ 2271, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2271 = VST3q8oddPseudo
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|
{ 2272, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2272 = VST3q8oddPseudo_UPD
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|
{ 2273, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2273 = VST3qAsm_16
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|
{ 2274, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2274 = VST3qAsm_32
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|
{ 2275, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2275 = VST3qAsm_8
|
|
{ 2276, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2276 = VST3qWB_fixed_Asm_16
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|
{ 2277, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2277 = VST3qWB_fixed_Asm_32
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|
{ 2278, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2278 = VST3qWB_fixed_Asm_8
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|
{ 2279, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2279 = VST3qWB_register_Asm_16
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|
{ 2280, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2280 = VST3qWB_register_Asm_32
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|
{ 2281, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2281 = VST3qWB_register_Asm_8
|
|
{ 2282, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2282 = VST4LNd16
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{ 2283, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2283 = VST4LNd16Pseudo
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|
{ 2284, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2284 = VST4LNd16Pseudo_UPD
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|
{ 2285, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2285 = VST4LNd16_UPD
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|
{ 2286, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2286 = VST4LNd32
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|
{ 2287, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2287 = VST4LNd32Pseudo
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|
{ 2288, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2288 = VST4LNd32Pseudo_UPD
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|
{ 2289, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2289 = VST4LNd32_UPD
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|
{ 2290, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2290 = VST4LNd8
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|
{ 2291, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2291 = VST4LNd8Pseudo
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|
{ 2292, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2292 = VST4LNd8Pseudo_UPD
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|
{ 2293, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2293 = VST4LNd8_UPD
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|
{ 2294, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2294 = VST4LNdAsm_16
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|
{ 2295, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2295 = VST4LNdAsm_32
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|
{ 2296, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2296 = VST4LNdAsm_8
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|
{ 2297, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2297 = VST4LNdWB_fixed_Asm_16
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{ 2298, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2298 = VST4LNdWB_fixed_Asm_32
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|
{ 2299, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2299 = VST4LNdWB_fixed_Asm_8
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{ 2300, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2300 = VST4LNdWB_register_Asm_16
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{ 2301, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2301 = VST4LNdWB_register_Asm_32
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{ 2302, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2302 = VST4LNdWB_register_Asm_8
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|
{ 2303, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2303 = VST4LNq16
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{ 2304, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2304 = VST4LNq16Pseudo
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|
{ 2305, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2305 = VST4LNq16Pseudo_UPD
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|
{ 2306, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2306 = VST4LNq16_UPD
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|
{ 2307, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2307 = VST4LNq32
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|
{ 2308, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2308 = VST4LNq32Pseudo
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{ 2309, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2309 = VST4LNq32Pseudo_UPD
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|
{ 2310, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2310 = VST4LNq32_UPD
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|
{ 2311, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2311 = VST4LNqAsm_16
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|
{ 2312, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2312 = VST4LNqAsm_32
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|
{ 2313, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2313 = VST4LNqWB_fixed_Asm_16
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{ 2314, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2314 = VST4LNqWB_fixed_Asm_32
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{ 2315, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2315 = VST4LNqWB_register_Asm_16
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{ 2316, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2316 = VST4LNqWB_register_Asm_32
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{ 2317, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2317 = VST4d16
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{ 2318, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2318 = VST4d16Pseudo
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{ 2319, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2319 = VST4d16Pseudo_UPD
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{ 2320, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2320 = VST4d16_UPD
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|
{ 2321, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2321 = VST4d32
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{ 2322, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2322 = VST4d32Pseudo
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{ 2323, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2323 = VST4d32Pseudo_UPD
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|
{ 2324, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2324 = VST4d32_UPD
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|
{ 2325, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2325 = VST4d8
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|
{ 2326, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2326 = VST4d8Pseudo
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|
{ 2327, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2327 = VST4d8Pseudo_UPD
|
|
{ 2328, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2328 = VST4d8_UPD
|
|
{ 2329, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2329 = VST4dAsm_16
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|
{ 2330, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2330 = VST4dAsm_32
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|
{ 2331, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2331 = VST4dAsm_8
|
|
{ 2332, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2332 = VST4dWB_fixed_Asm_16
|
|
{ 2333, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2333 = VST4dWB_fixed_Asm_32
|
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{ 2334, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2334 = VST4dWB_fixed_Asm_8
|
|
{ 2335, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2335 = VST4dWB_register_Asm_16
|
|
{ 2336, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2336 = VST4dWB_register_Asm_32
|
|
{ 2337, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2337 = VST4dWB_register_Asm_8
|
|
{ 2338, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2338 = VST4q16
|
|
{ 2339, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2339 = VST4q16Pseudo_UPD
|
|
{ 2340, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2340 = VST4q16_UPD
|
|
{ 2341, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2341 = VST4q16oddPseudo
|
|
{ 2342, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2342 = VST4q16oddPseudo_UPD
|
|
{ 2343, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2343 = VST4q32
|
|
{ 2344, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2344 = VST4q32Pseudo_UPD
|
|
{ 2345, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2345 = VST4q32_UPD
|
|
{ 2346, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2346 = VST4q32oddPseudo
|
|
{ 2347, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2347 = VST4q32oddPseudo_UPD
|
|
{ 2348, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2348 = VST4q8
|
|
{ 2349, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2349 = VST4q8Pseudo_UPD
|
|
{ 2350, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2350 = VST4q8_UPD
|
|
{ 2351, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2351 = VST4q8oddPseudo
|
|
{ 2352, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2352 = VST4q8oddPseudo_UPD
|
|
{ 2353, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2353 = VST4qAsm_16
|
|
{ 2354, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2354 = VST4qAsm_32
|
|
{ 2355, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2355 = VST4qAsm_8
|
|
{ 2356, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2356 = VST4qWB_fixed_Asm_16
|
|
{ 2357, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2357 = VST4qWB_fixed_Asm_32
|
|
{ 2358, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2358 = VST4qWB_fixed_Asm_8
|
|
{ 2359, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2359 = VST4qWB_register_Asm_16
|
|
{ 2360, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2360 = VST4qWB_register_Asm_32
|
|
{ 2361, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2361 = VST4qWB_register_Asm_8
|
|
{ 2362, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2362 = VSTMDDB_UPD
|
|
{ 2363, 4, 0, 4, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2363 = VSTMDIA
|
|
{ 2364, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2364 = VSTMDIA_UPD
|
|
{ 2365, 4, 0, 4, 535, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2365 = VSTMQIA
|
|
{ 2366, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2366 = VSTMSDB_UPD
|
|
{ 2367, 4, 0, 4, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2367 = VSTMSIA
|
|
{ 2368, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2368 = VSTMSIA_UPD
|
|
{ 2369, 5, 0, 4, 532, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2369 = VSTRD
|
|
{ 2370, 5, 0, 4, 232, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x18b05ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2370 = VSTRH
|
|
{ 2371, 5, 0, 4, 533, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2371 = VSTRS
|
|
{ 2372, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2372 = VSUBD
|
|
{ 2373, 5, 1, 4, 96, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #2373 = VSUBH
|
|
{ 2374, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #2374 = VSUBHNv2i32
|
|
{ 2375, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #2375 = VSUBHNv4i16
|
|
{ 2376, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #2376 = VSUBHNv8i8
|
|
{ 2377, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2377 = VSUBLsv2i64
|
|
{ 2378, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2378 = VSUBLsv4i32
|
|
{ 2379, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2379 = VSUBLsv8i16
|
|
{ 2380, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2380 = VSUBLuv2i64
|
|
{ 2381, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2381 = VSUBLuv4i32
|
|
{ 2382, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2382 = VSUBLuv8i16
|
|
{ 2383, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #2383 = VSUBS
|
|
{ 2384, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2384 = VSUBWsv2i64
|
|
{ 2385, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2385 = VSUBWsv4i32
|
|
{ 2386, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2386 = VSUBWsv8i16
|
|
{ 2387, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2387 = VSUBWuv2i64
|
|
{ 2388, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2388 = VSUBWuv4i32
|
|
{ 2389, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2389 = VSUBWuv8i16
|
|
{ 2390, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2390 = VSUBfd
|
|
{ 2391, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2391 = VSUBfq
|
|
{ 2392, 5, 1, 4, 88, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2392 = VSUBhd
|
|
{ 2393, 5, 1, 4, 89, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2393 = VSUBhq
|
|
{ 2394, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2394 = VSUBv16i8
|
|
{ 2395, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2395 = VSUBv1i64
|
|
{ 2396, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2396 = VSUBv2i32
|
|
{ 2397, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2397 = VSUBv2i64
|
|
{ 2398, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2398 = VSUBv4i16
|
|
{ 2399, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2399 = VSUBv4i32
|
|
{ 2400, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2400 = VSUBv8i16
|
|
{ 2401, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2401 = VSUBv8i8
|
|
{ 2402, 6, 2, 4, 450, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2402 = VSWPd
|
|
{ 2403, 6, 2, 4, 450, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2403 = VSWPq
|
|
{ 2404, 5, 1, 4, 442, 0|(1ULL<<MCID::Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2404 = VTBL1
|
|
{ 2405, 5, 1, 4, 444, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2405 = VTBL2
|
|
{ 2406, 5, 1, 4, 446, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2406 = VTBL3
|
|
{ 2407, 5, 1, 4, 446, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2407 = VTBL3Pseudo
|
|
{ 2408, 5, 1, 4, 448, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2408 = VTBL4
|
|
{ 2409, 5, 1, 4, 448, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2409 = VTBL4Pseudo
|
|
{ 2410, 6, 1, 4, 443, 0|(1ULL<<MCID::Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #2410 = VTBX1
|
|
{ 2411, 6, 1, 4, 445, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2411 = VTBX2
|
|
{ 2412, 6, 1, 4, 447, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #2412 = VTBX3
|
|
{ 2413, 6, 1, 4, 447, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2413 = VTBX3Pseudo
|
|
{ 2414, 6, 1, 4, 449, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #2414 = VTBX4
|
|
{ 2415, 6, 1, 4, 449, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2415 = VTBX4Pseudo
|
|
{ 2416, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2416 = VTOSHD
|
|
{ 2417, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2417 = VTOSHH
|
|
{ 2418, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2418 = VTOSHS
|
|
{ 2419, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2419 = VTOSIRD
|
|
{ 2420, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2420 = VTOSIRH
|
|
{ 2421, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2421 = VTOSIRS
|
|
{ 2422, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2422 = VTOSIZD
|
|
{ 2423, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2423 = VTOSIZH
|
|
{ 2424, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2424 = VTOSIZS
|
|
{ 2425, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2425 = VTOSLD
|
|
{ 2426, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2426 = VTOSLH
|
|
{ 2427, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2427 = VTOSLS
|
|
{ 2428, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2428 = VTOUHD
|
|
{ 2429, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2429 = VTOUHH
|
|
{ 2430, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2430 = VTOUHS
|
|
{ 2431, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2431 = VTOUIRD
|
|
{ 2432, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2432 = VTOUIRH
|
|
{ 2433, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2433 = VTOUIRS
|
|
{ 2434, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2434 = VTOUIZD
|
|
{ 2435, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2435 = VTOUIZH
|
|
{ 2436, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2436 = VTOUIZS
|
|
{ 2437, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2437 = VTOULD
|
|
{ 2438, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2438 = VTOULH
|
|
{ 2439, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2439 = VTOULS
|
|
{ 2440, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2440 = VTRNd16
|
|
{ 2441, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2441 = VTRNd32
|
|
{ 2442, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2442 = VTRNd8
|
|
{ 2443, 6, 2, 4, 452, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2443 = VTRNq16
|
|
{ 2444, 6, 2, 4, 452, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2444 = VTRNq32
|
|
{ 2445, 6, 2, 4, 452, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2445 = VTRNq8
|
|
{ 2446, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2446 = VTSTv16i8
|
|
{ 2447, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2447 = VTSTv2i32
|
|
{ 2448, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2448 = VTSTv4i16
|
|
{ 2449, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2449 = VTSTv4i32
|
|
{ 2450, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2450 = VTSTv8i16
|
|
{ 2451, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2451 = VTSTv8i8
|
|
{ 2452, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2452 = VUHTOD
|
|
{ 2453, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2453 = VUHTOH
|
|
{ 2454, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2454 = VUHTOS
|
|
{ 2455, 4, 1, 4, 500, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2455 = VUITOD
|
|
{ 2456, 4, 1, 4, 501, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2456 = VUITOH
|
|
{ 2457, 4, 1, 4, 502, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2457 = VUITOS
|
|
{ 2458, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2458 = VULTOD
|
|
{ 2459, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2459 = VULTOH
|
|
{ 2460, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2460 = VULTOS
|
|
{ 2461, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2461 = VUZPd16
|
|
{ 2462, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2462 = VUZPd8
|
|
{ 2463, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2463 = VUZPq16
|
|
{ 2464, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2464 = VUZPq32
|
|
{ 2465, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2465 = VUZPq8
|
|
{ 2466, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2466 = VZIPd16
|
|
{ 2467, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2467 = VZIPd8
|
|
{ 2468, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2468 = VZIPq16
|
|
{ 2469, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2469 = VZIPq32
|
|
{ 2470, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2470 = VZIPq8
|
|
{ 2471, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #2471 = WIN__CHKSTK
|
|
{ 2472, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr }, // Inst #2472 = WIN__DBZCHK
|
|
{ 2473, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2473 = sysLDMDA
|
|
{ 2474, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2474 = sysLDMDA_UPD
|
|
{ 2475, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2475 = sysLDMDB
|
|
{ 2476, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2476 = sysLDMDB_UPD
|
|
{ 2477, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2477 = sysLDMIA
|
|
{ 2478, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2478 = sysLDMIA_UPD
|
|
{ 2479, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2479 = sysLDMIB
|
|
{ 2480, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2480 = sysLDMIB_UPD
|
|
{ 2481, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2481 = sysSTMDA
|
|
{ 2482, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2482 = sysSTMDA_UPD
|
|
{ 2483, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2483 = sysSTMDB
|
|
{ 2484, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2484 = sysSTMDB_UPD
|
|
{ 2485, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2485 = sysSTMIA
|
|
{ 2486, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2486 = sysSTMIA_UPD
|
|
{ 2487, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2487 = sysSTMIB
|
|
{ 2488, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2488 = sysSTMIB_UPD
|
|
{ 2489, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo273, -1 ,nullptr }, // Inst #2489 = t2ABS
|
|
{ 2490, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo274, -1 ,nullptr }, // Inst #2490 = t2ADCri
|
|
{ 2491, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo275, -1 ,nullptr }, // Inst #2491 = t2ADCrr
|
|
{ 2492, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo276, -1 ,nullptr }, // Inst #2492 = t2ADCrs
|
|
{ 2493, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo277, -1 ,nullptr }, // Inst #2493 = t2ADDSri
|
|
{ 2494, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo278, -1 ,nullptr }, // Inst #2494 = t2ADDSrr
|
|
{ 2495, 6, 1, 4, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo279, -1 ,nullptr }, // Inst #2495 = t2ADDSrs
|
|
{ 2496, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2496 = t2ADDri
|
|
{ 2497, 5, 1, 4, 1, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2497 = t2ADDri12
|
|
{ 2498, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2498 = t2ADDrr
|
|
{ 2499, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2499 = t2ADDrs
|
|
{ 2500, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2500 = t2ADR
|
|
{ 2501, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2501 = t2ANDri
|
|
{ 2502, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2502 = t2ANDrr
|
|
{ 2503, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2503 = t2ANDrs
|
|
{ 2504, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2504 = t2ASRri
|
|
{ 2505, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2505 = t2ASRrr
|
|
{ 2506, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2506 = t2B
|
|
{ 2507, 5, 1, 4, 311, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2507 = t2BFC
|
|
{ 2508, 6, 1, 4, 312, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2508 = t2BFI
|
|
{ 2509, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2509 = t2BICri
|
|
{ 2510, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2510 = t2BICrr
|
|
{ 2511, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2511 = t2BICrs
|
|
{ 2512, 3, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2512 = t2BR_JT
|
|
{ 2513, 3, 0, 4, 15, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2513 = t2BXJ
|
|
{ 2514, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2514 = t2Bcc
|
|
{ 2515, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2515 = t2CDP
|
|
{ 2516, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2516 = t2CDP2
|
|
{ 2517, 2, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2517 = t2CLREX
|
|
{ 2518, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2518 = t2CLZ
|
|
{ 2519, 4, 0, 4, 17, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2519 = t2CMNri
|
|
{ 2520, 4, 0, 4, 18, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2520 = t2CMNzrr
|
|
{ 2521, 5, 0, 4, 254, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2521 = t2CMNzrs
|
|
{ 2522, 4, 0, 4, 255, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2522 = t2CMPri
|
|
{ 2523, 4, 0, 4, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2523 = t2CMPrr
|
|
{ 2524, 5, 0, 4, 257, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2524 = t2CMPrs
|
|
{ 2525, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2525 = t2CPS1p
|
|
{ 2526, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #2526 = t2CPS2p
|
|
{ 2527, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2527 = t2CPS3p
|
|
{ 2528, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2528 = t2CRC32B
|
|
{ 2529, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2529 = t2CRC32CB
|
|
{ 2530, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2530 = t2CRC32CH
|
|
{ 2531, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2531 = t2CRC32CW
|
|
{ 2532, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2532 = t2CRC32H
|
|
{ 2533, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2533 = t2CRC32W
|
|
{ 2534, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2534 = t2DBG
|
|
{ 2535, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2535 = t2DCPS1
|
|
{ 2536, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2536 = t2DCPS2
|
|
{ 2537, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2537 = t2DCPS3
|
|
{ 2538, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2538 = t2DMB
|
|
{ 2539, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2539 = t2DSB
|
|
{ 2540, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2540 = t2EORri
|
|
{ 2541, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2541 = t2EORrr
|
|
{ 2542, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2542 = t2EORrs
|
|
{ 2543, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2543 = t2HINT
|
|
{ 2544, 1, 0, 4, 10, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2544 = t2HVC
|
|
{ 2545, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2545 = t2ISB
|
|
{ 2546, 2, 0, 2, 395, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList13, OperandInfo7, -1 ,&getITDeprecationInfo }, // Inst #2546 = t2IT
|
|
{ 2547, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList14, OperandInfo291, -1 ,nullptr }, // Inst #2547 = t2Int_eh_sjlj_setjmp
|
|
{ 2548, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList8, OperandInfo291, -1 ,nullptr }, // Inst #2548 = t2Int_eh_sjlj_setjmp_nofp
|
|
{ 2549, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2549 = t2LDA
|
|
{ 2550, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2550 = t2LDAB
|
|
{ 2551, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2551 = t2LDAEX
|
|
{ 2552, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2552 = t2LDAEXB
|
|
{ 2553, 5, 2, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2553 = t2LDAEXD
|
|
{ 2554, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2554 = t2LDAEXH
|
|
{ 2555, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2555 = t2LDAH
|
|
{ 2556, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2556 = t2LDC2L_OFFSET
|
|
{ 2557, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2557 = t2LDC2L_OPTION
|
|
{ 2558, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2558 = t2LDC2L_POST
|
|
{ 2559, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2559 = t2LDC2L_PRE
|
|
{ 2560, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2560 = t2LDC2_OFFSET
|
|
{ 2561, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2561 = t2LDC2_OPTION
|
|
{ 2562, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2562 = t2LDC2_POST
|
|
{ 2563, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2563 = t2LDC2_PRE
|
|
{ 2564, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2564 = t2LDCL_OFFSET
|
|
{ 2565, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2565 = t2LDCL_OPTION
|
|
{ 2566, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2566 = t2LDCL_POST
|
|
{ 2567, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2567 = t2LDCL_PRE
|
|
{ 2568, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2568 = t2LDC_OFFSET
|
|
{ 2569, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2569 = t2LDC_OPTION
|
|
{ 2570, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2570 = t2LDC_POST
|
|
{ 2571, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2571 = t2LDC_PRE
|
|
{ 2572, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2572 = t2LDMDB
|
|
{ 2573, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2573 = t2LDMDB_UPD
|
|
{ 2574, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2574 = t2LDMIA
|
|
{ 2575, 5, 1, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2575 = t2LDMIA_RET
|
|
{ 2576, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2576 = t2LDMIA_UPD
|
|
{ 2577, 5, 1, 4, 360, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2577 = t2LDRBT
|
|
{ 2578, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2578 = t2LDRB_POST
|
|
{ 2579, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2579 = t2LDRB_PRE
|
|
{ 2580, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2580 = t2LDRBi12
|
|
{ 2581, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2581 = t2LDRBi8
|
|
{ 2582, 4, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2582 = t2LDRBpci
|
|
{ 2583, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2583 = t2LDRBpcrel
|
|
{ 2584, 6, 1, 4, 340, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2584 = t2LDRBs
|
|
{ 2585, 7, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2585 = t2LDRD_POST
|
|
{ 2586, 7, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2586 = t2LDRD_PRE
|
|
{ 2587, 6, 2, 4, 365, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2587 = t2LDRDi8
|
|
{ 2588, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2588 = t2LDREX
|
|
{ 2589, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2589 = t2LDREXB
|
|
{ 2590, 5, 2, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2590 = t2LDREXD
|
|
{ 2591, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2591 = t2LDREXH
|
|
{ 2592, 5, 1, 4, 360, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2592 = t2LDRHT
|
|
{ 2593, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2593 = t2LDRH_POST
|
|
{ 2594, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2594 = t2LDRH_PRE
|
|
{ 2595, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2595 = t2LDRHi12
|
|
{ 2596, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2596 = t2LDRHi8
|
|
{ 2597, 4, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2597 = t2LDRHpci
|
|
{ 2598, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2598 = t2LDRHpcrel
|
|
{ 2599, 6, 1, 4, 340, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2599 = t2LDRHs
|
|
{ 2600, 5, 1, 4, 362, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2600 = t2LDRSBT
|
|
{ 2601, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2601 = t2LDRSB_POST
|
|
{ 2602, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2602 = t2LDRSB_PRE
|
|
{ 2603, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2603 = t2LDRSBi12
|
|
{ 2604, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2604 = t2LDRSBi8
|
|
{ 2605, 4, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2605 = t2LDRSBpci
|
|
{ 2606, 4, 0, 0, 352, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2606 = t2LDRSBpcrel
|
|
{ 2607, 6, 1, 4, 353, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2607 = t2LDRSBs
|
|
{ 2608, 5, 1, 4, 362, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2608 = t2LDRSHT
|
|
{ 2609, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2609 = t2LDRSH_POST
|
|
{ 2610, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2610 = t2LDRSH_PRE
|
|
{ 2611, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2611 = t2LDRSHi12
|
|
{ 2612, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2612 = t2LDRSHi8
|
|
{ 2613, 4, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2613 = t2LDRSHpci
|
|
{ 2614, 4, 0, 0, 352, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2614 = t2LDRSHpcrel
|
|
{ 2615, 6, 1, 4, 353, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2615 = t2LDRSHs
|
|
{ 2616, 5, 1, 4, 361, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2616 = t2LDRT
|
|
{ 2617, 6, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2617 = t2LDR_POST
|
|
{ 2618, 6, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2618 = t2LDR_PRE
|
|
{ 2619, 5, 1, 4, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2619 = t2LDRi12
|
|
{ 2620, 5, 1, 4, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2620 = t2LDRi8
|
|
{ 2621, 4, 1, 4, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #2621 = t2LDRpci
|
|
{ 2622, 3, 1, 0, 345, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2622 = t2LDRpci_pic
|
|
{ 2623, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #2623 = t2LDRpcrel
|
|
{ 2624, 6, 1, 4, 346, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #2624 = t2LDRs
|
|
{ 2625, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2625 = t2LEApcrel
|
|
{ 2626, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2626 = t2LEApcrelJT
|
|
{ 2627, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2627 = t2LSLri
|
|
{ 2628, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2628 = t2LSLrr
|
|
{ 2629, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2629 = t2LSRri
|
|
{ 2630, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2630 = t2LSRrr
|
|
{ 2631, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo72, -1 ,&getMCRDeprecationInfo }, // Inst #2631 = t2MCR
|
|
{ 2632, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2632 = t2MCR2
|
|
{ 2633, 7, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2633 = t2MCRR
|
|
{ 2634, 7, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2634 = t2MCRR2
|
|
{ 2635, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2635 = t2MLA
|
|
{ 2636, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2636 = t2MLS
|
|
{ 2637, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2637 = t2MOVCCasr
|
|
{ 2638, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2638 = t2MOVCCi
|
|
{ 2639, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2639 = t2MOVCCi16
|
|
{ 2640, 5, 1, 8, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #2640 = t2MOVCCi32imm
|
|
{ 2641, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2641 = t2MOVCClsl
|
|
{ 2642, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2642 = t2MOVCClsr
|
|
{ 2643, 5, 1, 4, 44, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2643 = t2MOVCCr
|
|
{ 2644, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2644 = t2MOVCCror
|
|
{ 2645, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #2645 = t2MOVSsi
|
|
{ 2646, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2646 = t2MOVSsr
|
|
{ 2647, 5, 1, 4, 42, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2647 = t2MOVTi16
|
|
{ 2648, 4, 1, 0, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #2648 = t2MOVTi16_ga_pcrel
|
|
{ 2649, 2, 1, 0, 308, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2649 = t2MOV_ga_pcrel
|
|
{ 2650, 5, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2650 = t2MOVi
|
|
{ 2651, 4, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2651 = t2MOVi16
|
|
{ 2652, 3, 1, 0, 309, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2652 = t2MOVi16_ga_pcrel
|
|
{ 2653, 2, 1, 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2653 = t2MOVi32imm
|
|
{ 2654, 5, 1, 4, 49, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2654 = t2MOVr
|
|
{ 2655, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #2655 = t2MOVsi
|
|
{ 2656, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2656 = t2MOVsr
|
|
{ 2657, 4, 1, 4, 51, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo287, -1 ,nullptr }, // Inst #2657 = t2MOVsra_flag
|
|
{ 2658, 4, 1, 4, 51, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo287, -1 ,nullptr }, // Inst #2658 = t2MOVsrl_flag
|
|
{ 2659, 8, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #2659 = t2MRC
|
|
{ 2660, 8, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #2660 = t2MRC2
|
|
{ 2661, 7, 2, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2661 = t2MRRC
|
|
{ 2662, 7, 2, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2662 = t2MRRC2
|
|
{ 2663, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2663 = t2MRS_AR
|
|
{ 2664, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2664 = t2MRS_M
|
|
{ 2665, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2665 = t2MRSbanked
|
|
{ 2666, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2666 = t2MRSsys_AR
|
|
{ 2667, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2667 = t2MSR_AR
|
|
{ 2668, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2668 = t2MSR_M
|
|
{ 2669, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2669 = t2MSRbanked
|
|
{ 2670, 5, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2670 = t2MUL
|
|
{ 2671, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2671 = t2MVNCCi
|
|
{ 2672, 5, 1, 4, 53, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2672 = t2MVNi
|
|
{ 2673, 5, 1, 4, 54, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2673 = t2MVNr
|
|
{ 2674, 6, 1, 4, 263, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2674 = t2MVNs
|
|
{ 2675, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2675 = t2ORNri
|
|
{ 2676, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2676 = t2ORNrr
|
|
{ 2677, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2677 = t2ORNrs
|
|
{ 2678, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2678 = t2ORRri
|
|
{ 2679, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2679 = t2ORRrr
|
|
{ 2680, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2680 = t2ORRrs
|
|
{ 2681, 6, 1, 4, 60, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2681 = t2PKHBT
|
|
{ 2682, 6, 1, 4, 60, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2682 = t2PKHTB
|
|
{ 2683, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2683 = t2PLDWi12
|
|
{ 2684, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2684 = t2PLDWi8
|
|
{ 2685, 5, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2685 = t2PLDWs
|
|
{ 2686, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2686 = t2PLDi12
|
|
{ 2687, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2687 = t2PLDi8
|
|
{ 2688, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2688 = t2PLDpci
|
|
{ 2689, 5, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2689 = t2PLDs
|
|
{ 2690, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2690 = t2PLIi12
|
|
{ 2691, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2691 = t2PLIi8
|
|
{ 2692, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2692 = t2PLIpci
|
|
{ 2693, 5, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2693 = t2PLIs
|
|
{ 2694, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2694 = t2QADD
|
|
{ 2695, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2695 = t2QADD16
|
|
{ 2696, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2696 = t2QADD8
|
|
{ 2697, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2697 = t2QASX
|
|
{ 2698, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2698 = t2QDADD
|
|
{ 2699, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2699 = t2QDSUB
|
|
{ 2700, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2700 = t2QSAX
|
|
{ 2701, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2701 = t2QSUB
|
|
{ 2702, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2702 = t2QSUB16
|
|
{ 2703, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2703 = t2QSUB8
|
|
{ 2704, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2704 = t2RBIT
|
|
{ 2705, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2705 = t2REV
|
|
{ 2706, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2706 = t2REV16
|
|
{ 2707, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2707 = t2REVSH
|
|
{ 2708, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2708 = t2RFEDB
|
|
{ 2709, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2709 = t2RFEDBW
|
|
{ 2710, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2710 = t2RFEIA
|
|
{ 2711, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2711 = t2RFEIAW
|
|
{ 2712, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2712 = t2RORri
|
|
{ 2713, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2713 = t2RORrr
|
|
{ 2714, 5, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2714 = t2RRX
|
|
{ 2715, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo321, -1 ,nullptr }, // Inst #2715 = t2RSBSri
|
|
{ 2716, 6, 1, 4, 59, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo322, -1 ,nullptr }, // Inst #2716 = t2RSBSrs
|
|
{ 2717, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2717 = t2RSBri
|
|
{ 2718, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2718 = t2RSBrr
|
|
{ 2719, 7, 1, 4, 264, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2719 = t2RSBrs
|
|
{ 2720, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2720 = t2SADD16
|
|
{ 2721, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2721 = t2SADD8
|
|
{ 2722, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2722 = t2SASX
|
|
{ 2723, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo274, -1 ,nullptr }, // Inst #2723 = t2SBCri
|
|
{ 2724, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo275, -1 ,nullptr }, // Inst #2724 = t2SBCrr
|
|
{ 2725, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo276, -1 ,nullptr }, // Inst #2725 = t2SBCrs
|
|
{ 2726, 6, 1, 4, 311, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2726 = t2SBFX
|
|
{ 2727, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2727 = t2SDIV
|
|
{ 2728, 5, 1, 4, 310, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #2728 = t2SEL
|
|
{ 2729, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2729 = t2SETPAN
|
|
{ 2730, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2730 = t2SG
|
|
{ 2731, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2731 = t2SHADD16
|
|
{ 2732, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2732 = t2SHADD8
|
|
{ 2733, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2733 = t2SHASX
|
|
{ 2734, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2734 = t2SHSAX
|
|
{ 2735, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2735 = t2SHSUB16
|
|
{ 2736, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2736 = t2SHSUB8
|
|
{ 2737, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2737 = t2SMC
|
|
{ 2738, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2738 = t2SMLABB
|
|
{ 2739, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2739 = t2SMLABT
|
|
{ 2740, 6, 1, 4, 334, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2740 = t2SMLAD
|
|
{ 2741, 6, 1, 4, 334, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2741 = t2SMLADX
|
|
{ 2742, 8, 2, 4, 337, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2742 = t2SMLAL
|
|
{ 2743, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2743 = t2SMLALBB
|
|
{ 2744, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2744 = t2SMLALBT
|
|
{ 2745, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2745 = t2SMLALD
|
|
{ 2746, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2746 = t2SMLALDX
|
|
{ 2747, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2747 = t2SMLALTB
|
|
{ 2748, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2748 = t2SMLALTT
|
|
{ 2749, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2749 = t2SMLATB
|
|
{ 2750, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2750 = t2SMLATT
|
|
{ 2751, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2751 = t2SMLAWB
|
|
{ 2752, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2752 = t2SMLAWT
|
|
{ 2753, 6, 1, 4, 332, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2753 = t2SMLSD
|
|
{ 2754, 6, 1, 4, 332, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2754 = t2SMLSDX
|
|
{ 2755, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2755 = t2SMLSLD
|
|
{ 2756, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2756 = t2SMLSLDX
|
|
{ 2757, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2757 = t2SMMLA
|
|
{ 2758, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2758 = t2SMMLAR
|
|
{ 2759, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2759 = t2SMMLS
|
|
{ 2760, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2760 = t2SMMLSR
|
|
{ 2761, 5, 1, 4, 324, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2761 = t2SMMUL
|
|
{ 2762, 5, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2762 = t2SMMULR
|
|
{ 2763, 5, 1, 4, 329, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2763 = t2SMUAD
|
|
{ 2764, 5, 1, 4, 329, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2764 = t2SMUADX
|
|
{ 2765, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2765 = t2SMULBB
|
|
{ 2766, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2766 = t2SMULBT
|
|
{ 2767, 6, 2, 4, 336, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2767 = t2SMULL
|
|
{ 2768, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2768 = t2SMULTB
|
|
{ 2769, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2769 = t2SMULTT
|
|
{ 2770, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2770 = t2SMULWB
|
|
{ 2771, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2771 = t2SMULWT
|
|
{ 2772, 5, 1, 4, 326, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2772 = t2SMUSD
|
|
{ 2773, 5, 1, 4, 326, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2773 = t2SMUSDX
|
|
{ 2774, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2774 = t2SRSDB
|
|
{ 2775, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2775 = t2SRSDB_UPD
|
|
{ 2776, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2776 = t2SRSIA
|
|
{ 2777, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2777 = t2SRSIA_UPD
|
|
{ 2778, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2778 = t2SSAT
|
|
{ 2779, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2779 = t2SSAT16
|
|
{ 2780, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2780 = t2SSAX
|
|
{ 2781, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2781 = t2SSUB16
|
|
{ 2782, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2782 = t2SSUB8
|
|
{ 2783, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2783 = t2STC2L_OFFSET
|
|
{ 2784, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2784 = t2STC2L_OPTION
|
|
{ 2785, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2785 = t2STC2L_POST
|
|
{ 2786, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2786 = t2STC2L_PRE
|
|
{ 2787, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2787 = t2STC2_OFFSET
|
|
{ 2788, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2788 = t2STC2_OPTION
|
|
{ 2789, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2789 = t2STC2_POST
|
|
{ 2790, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2790 = t2STC2_PRE
|
|
{ 2791, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2791 = t2STCL_OFFSET
|
|
{ 2792, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2792 = t2STCL_OPTION
|
|
{ 2793, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2793 = t2STCL_POST
|
|
{ 2794, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2794 = t2STCL_PRE
|
|
{ 2795, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2795 = t2STC_OFFSET
|
|
{ 2796, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2796 = t2STC_OPTION
|
|
{ 2797, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2797 = t2STC_POST
|
|
{ 2798, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2798 = t2STC_PRE
|
|
{ 2799, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2799 = t2STL
|
|
{ 2800, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2800 = t2STLB
|
|
{ 2801, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2801 = t2STLEX
|
|
{ 2802, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2802 = t2STLEXB
|
|
{ 2803, 6, 1, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2803 = t2STLEXD
|
|
{ 2804, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2804 = t2STLEXH
|
|
{ 2805, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2805 = t2STLH
|
|
{ 2806, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2806 = t2STMDB
|
|
{ 2807, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2807 = t2STMDB_UPD
|
|
{ 2808, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2808 = t2STMIA
|
|
{ 2809, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2809 = t2STMIA_UPD
|
|
{ 2810, 5, 1, 4, 384, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2810 = t2STRBT
|
|
{ 2811, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2811 = t2STRB_POST
|
|
{ 2812, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2812 = t2STRB_PRE
|
|
{ 2813, 6, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2813 = t2STRB_preidx
|
|
{ 2814, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2814 = t2STRBi12
|
|
{ 2815, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2815 = t2STRBi8
|
|
{ 2816, 6, 0, 4, 374, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2816 = t2STRBs
|
|
{ 2817, 7, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2817 = t2STRD_POST
|
|
{ 2818, 7, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2818 = t2STRD_PRE
|
|
{ 2819, 6, 0, 4, 386, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2819 = t2STRDi8
|
|
{ 2820, 6, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr }, // Inst #2820 = t2STREX
|
|
{ 2821, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2821 = t2STREXB
|
|
{ 2822, 6, 1, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2822 = t2STREXD
|
|
{ 2823, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2823 = t2STREXH
|
|
{ 2824, 5, 1, 4, 384, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2824 = t2STRHT
|
|
{ 2825, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2825 = t2STRH_POST
|
|
{ 2826, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2826 = t2STRH_PRE
|
|
{ 2827, 6, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2827 = t2STRH_preidx
|
|
{ 2828, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2828 = t2STRHi12
|
|
{ 2829, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2829 = t2STRHi8
|
|
{ 2830, 6, 0, 4, 374, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2830 = t2STRHs
|
|
{ 2831, 5, 1, 4, 385, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2831 = t2STRT
|
|
{ 2832, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2832 = t2STR_POST
|
|
{ 2833, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2833 = t2STR_PRE
|
|
{ 2834, 6, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2834 = t2STR_preidx
|
|
{ 2835, 5, 0, 4, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2835 = t2STRi12
|
|
{ 2836, 5, 0, 4, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2836 = t2STRi8
|
|
{ 2837, 6, 0, 4, 376, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #2837 = t2STRs
|
|
{ 2838, 3, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, ImplicitList4, OperandInfo49, -1 ,nullptr }, // Inst #2838 = t2SUBS_PC_LR
|
|
{ 2839, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo277, -1 ,nullptr }, // Inst #2839 = t2SUBSri
|
|
{ 2840, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo278, -1 ,nullptr }, // Inst #2840 = t2SUBSrr
|
|
{ 2841, 6, 1, 4, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo279, -1 ,nullptr }, // Inst #2841 = t2SUBSrs
|
|
{ 2842, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2842 = t2SUBri
|
|
{ 2843, 5, 1, 4, 1, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2843 = t2SUBri12
|
|
{ 2844, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2844 = t2SUBrr
|
|
{ 2845, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2845 = t2SUBrs
|
|
{ 2846, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2846 = t2SXTAB
|
|
{ 2847, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2847 = t2SXTAB16
|
|
{ 2848, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2848 = t2SXTAH
|
|
{ 2849, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2849 = t2SXTB
|
|
{ 2850, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2850 = t2SXTB16
|
|
{ 2851, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2851 = t2SXTH
|
|
{ 2852, 4, 0, 4, 14, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2852 = t2TBB
|
|
{ 2853, 4, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #2853 = t2TBB_JT
|
|
{ 2854, 4, 0, 4, 14, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2854 = t2TBH
|
|
{ 2855, 4, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #2855 = t2TBH_JT
|
|
{ 2856, 4, 0, 4, 269, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2856 = t2TEQri
|
|
{ 2857, 4, 0, 4, 270, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2857 = t2TEQrr
|
|
{ 2858, 5, 0, 4, 271, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2858 = t2TEQrs
|
|
{ 2859, 4, 0, 4, 269, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2859 = t2TSTri
|
|
{ 2860, 4, 0, 4, 270, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2860 = t2TSTrr
|
|
{ 2861, 5, 0, 4, 271, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2861 = t2TSTrs
|
|
{ 2862, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2862 = t2TT
|
|
{ 2863, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2863 = t2TTA
|
|
{ 2864, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2864 = t2TTAT
|
|
{ 2865, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2865 = t2TTT
|
|
{ 2866, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2866 = t2UADD16
|
|
{ 2867, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2867 = t2UADD8
|
|
{ 2868, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2868 = t2UASX
|
|
{ 2869, 6, 1, 4, 311, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2869 = t2UBFX
|
|
{ 2870, 1, 0, 4, 77, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2870 = t2UDF
|
|
{ 2871, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2871 = t2UDIV
|
|
{ 2872, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2872 = t2UHADD16
|
|
{ 2873, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2873 = t2UHADD8
|
|
{ 2874, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2874 = t2UHASX
|
|
{ 2875, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2875 = t2UHSAX
|
|
{ 2876, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2876 = t2UHSUB16
|
|
{ 2877, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2877 = t2UHSUB8
|
|
{ 2878, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2878 = t2UMAAL
|
|
{ 2879, 8, 2, 4, 337, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2879 = t2UMLAL
|
|
{ 2880, 6, 2, 4, 336, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2880 = t2UMULL
|
|
{ 2881, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2881 = t2UQADD16
|
|
{ 2882, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2882 = t2UQADD8
|
|
{ 2883, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2883 = t2UQASX
|
|
{ 2884, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2884 = t2UQSAX
|
|
{ 2885, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2885 = t2UQSUB16
|
|
{ 2886, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2886 = t2UQSUB8
|
|
{ 2887, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2887 = t2USAD8
|
|
{ 2888, 6, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2888 = t2USADA8
|
|
{ 2889, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2889 = t2USAT
|
|
{ 2890, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2890 = t2USAT16
|
|
{ 2891, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2891 = t2USAX
|
|
{ 2892, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2892 = t2USUB16
|
|
{ 2893, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2893 = t2USUB8
|
|
{ 2894, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2894 = t2UXTAB
|
|
{ 2895, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2895 = t2UXTAB16
|
|
{ 2896, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2896 = t2UXTAH
|
|
{ 2897, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2897 = t2UXTB
|
|
{ 2898, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2898 = t2UXTB16
|
|
{ 2899, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2899 = t2UXTH
|
|
{ 2900, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2900 = tADC
|
|
{ 2901, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo338, -1 ,nullptr }, // Inst #2901 = tADDframe
|
|
{ 2902, 5, 1, 2, 272, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #2902 = tADDhirr
|
|
{ 2903, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2903 = tADDi3
|
|
{ 2904, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2904 = tADDi8
|
|
{ 2905, 5, 1, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2905 = tADDrSP
|
|
{ 2906, 5, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2906 = tADDrSPi
|
|
{ 2907, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2907 = tADDrr
|
|
{ 2908, 5, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2908 = tADDspi
|
|
{ 2909, 5, 1, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #2909 = tADDspr
|
|
{ 2910, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #2910 = tADJCALLSTACKDOWN
|
|
{ 2911, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #2911 = tADJCALLSTACKUP
|
|
{ 2912, 4, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2912 = tADR
|
|
{ 2913, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2913 = tAND
|
|
{ 2914, 6, 2, 2, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2914 = tASRri
|
|
{ 2915, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2915 = tASRrr
|
|
{ 2916, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2916 = tB
|
|
{ 2917, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2917 = tBIC
|
|
{ 2918, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2918 = tBKPT
|
|
{ 2919, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo347, -1 ,nullptr }, // Inst #2919 = tBL
|
|
{ 2920, 3, 0, 2, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo348, -1 ,nullptr }, // Inst #2920 = tBLXNSr
|
|
{ 2921, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo347, -1 ,nullptr }, // Inst #2921 = tBLXi
|
|
{ 2922, 3, 0, 2, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo349, -1 ,nullptr }, // Inst #2922 = tBLXr
|
|
{ 2923, 3, 0, 2, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2923 = tBRIND
|
|
{ 2924, 2, 0, 2, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2924 = tBR_JTr
|
|
{ 2925, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2925 = tBX
|
|
{ 2926, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2926 = tBXNS
|
|
{ 2927, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #2927 = tBX_CALL
|
|
{ 2928, 2, 0, 2, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2928 = tBX_RET
|
|
{ 2929, 3, 0, 2, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2929 = tBX_RET_vararg
|
|
{ 2930, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2930 = tBcc
|
|
{ 2931, 3, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #2931 = tBfar
|
|
{ 2932, 2, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2932 = tCBNZ
|
|
{ 2933, 2, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2933 = tCBZ
|
|
{ 2934, 4, 0, 2, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo353, -1 ,nullptr }, // Inst #2934 = tCMNz
|
|
{ 2935, 4, 0, 2, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #2935 = tCMPhir
|
|
{ 2936, 4, 0, 2, 255, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo354, -1 ,nullptr }, // Inst #2936 = tCMPi8
|
|
{ 2937, 4, 0, 2, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo353, -1 ,nullptr }, // Inst #2937 = tCMPr
|
|
{ 2938, 2, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #2938 = tCPS
|
|
{ 2939, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2939 = tEOR
|
|
{ 2940, 3, 0, 2, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2940 = tHINT
|
|
{ 2941, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2941 = tHLT
|
|
{ 2942, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #2942 = tInt_eh_sjlj_longjmp
|
|
{ 2943, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList15, OperandInfo291, -1 ,nullptr }, // Inst #2943 = tInt_eh_sjlj_setjmp
|
|
{ 2944, 4, 0, 2, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2944 = tLDMIA
|
|
{ 2945, 5, 1, 2, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2945 = tLDMIA_UPD
|
|
{ 2946, 5, 1, 2, 343, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2946 = tLDRBi
|
|
{ 2947, 5, 1, 2, 347, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2947 = tLDRBr
|
|
{ 2948, 5, 1, 2, 343, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2948 = tLDRHi
|
|
{ 2949, 5, 1, 2, 347, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2949 = tLDRHr
|
|
{ 2950, 2, 1, 0, 391, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2950 = tLDRLIT_ga_abs
|
|
{ 2951, 2, 1, 0, 392, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2951 = tLDRLIT_ga_pcrel
|
|
{ 2952, 5, 1, 2, 354, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2952 = tLDRSB
|
|
{ 2953, 5, 1, 2, 354, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2953 = tLDRSH
|
|
{ 2954, 5, 1, 2, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2954 = tLDRi
|
|
{ 2955, 4, 1, 2, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2955 = tLDRpci
|
|
{ 2956, 3, 1, 0, 341, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2956 = tLDRpci_pic
|
|
{ 2957, 5, 1, 2, 348, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2957 = tLDRr
|
|
{ 2958, 5, 1, 2, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2958 = tLDRspi
|
|
{ 2959, 4, 1, 2, 273, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #2959 = tLEApcrel
|
|
{ 2960, 4, 1, 2, 273, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #2960 = tLEApcrelJT
|
|
{ 2961, 6, 2, 2, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2961 = tLSLri
|
|
{ 2962, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2962 = tLSLrr
|
|
{ 2963, 6, 2, 2, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2963 = tLSRri
|
|
{ 2964, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2964 = tLSRrr
|
|
{ 2965, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo360, -1 ,nullptr }, // Inst #2965 = tMOVCCr_pseudo
|
|
{ 2966, 2, 1, 2, 49, 0, 0xc80ULL, nullptr, ImplicitList1, OperandInfo291, -1 ,nullptr }, // Inst #2966 = tMOVSr
|
|
{ 2967, 5, 2, 2, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo361, -1 ,nullptr }, // Inst #2967 = tMOVi8
|
|
{ 2968, 4, 1, 2, 49, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #2968 = tMOVr
|
|
{ 2969, 6, 2, 2, 52, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #2969 = tMUL
|
|
{ 2970, 5, 2, 2, 54, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #2970 = tMVN
|
|
{ 2971, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2971 = tORR
|
|
{ 2972, 3, 1, 2, 272, 0|(1ULL<<MCID::NotDuplicable), 0xc80ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2972 = tPICADD
|
|
{ 2973, 3, 0, 2, 370, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo365, -1 ,nullptr }, // Inst #2973 = tPOP
|
|
{ 2974, 3, 0, 2, 371, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2974 = tPOP_RET
|
|
{ 2975, 3, 0, 2, 390, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo365, -1 ,nullptr }, // Inst #2975 = tPUSH
|
|
{ 2976, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2976 = tREV
|
|
{ 2977, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2977 = tREV16
|
|
{ 2978, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2978 = tREVSH
|
|
{ 2979, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2979 = tROR
|
|
{ 2980, 5, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #2980 = tRSB
|
|
{ 2981, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2981 = tSBC
|
|
{ 2982, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, ARM::HasV8Ops ,nullptr }, // Inst #2982 = tSETEND
|
|
{ 2983, 5, 1, 2, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #2983 = tSTMIA_UPD
|
|
{ 2984, 5, 0, 2, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2984 = tSTRBi
|
|
{ 2985, 5, 0, 2, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2985 = tSTRBr
|
|
{ 2986, 5, 0, 2, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2986 = tSTRHi
|
|
{ 2987, 5, 0, 2, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2987 = tSTRHr
|
|
{ 2988, 5, 0, 2, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2988 = tSTRi
|
|
{ 2989, 5, 0, 2, 372, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2989 = tSTRr
|
|
{ 2990, 5, 0, 2, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2990 = tSTRspi
|
|
{ 2991, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2991 = tSUBi3
|
|
{ 2992, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2992 = tSUBi8
|
|
{ 2993, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2993 = tSUBrr
|
|
{ 2994, 5, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2994 = tSUBspi
|
|
{ 2995, 3, 0, 2, 10, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2995 = tSVC
|
|
{ 2996, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2996 = tSXTB
|
|
{ 2997, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2997 = tSXTH
|
|
{ 2998, 3, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2998 = tTAILJMPd
|
|
{ 2999, 3, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2999 = tTAILJMPdND
|
|
{ 3000, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #3000 = tTAILJMPr
|
|
{ 3001, 0, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #3001 = tTPsoft
|
|
{ 3002, 0, 0, 2, 10, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3002 = tTRAP
|
|
{ 3003, 4, 0, 2, 277, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo353, -1 ,nullptr }, // Inst #3003 = tTST
|
|
{ 3004, 1, 0, 2, 77, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #3004 = tUDF
|
|
{ 3005, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #3005 = tUXTB
|
|
{ 3006, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #3006 = tUXTH
|
|
};
|
|
|
|
static inline void InitARMMCInstrInfo(MCInstrInfo *II) {
|
|
II->InitMCInstrInfo(ARMInsts, NULL, NULL, 3007);
|
|
}
|
|
|
|
} // end llvm namespace
|
|
#endif // GET_INSTRINFO_MC_DESC
|
|
|
|
|
|
#ifdef GET_INSTRINFO_HEADER
|
|
#undef GET_INSTRINFO_HEADER
|
|
namespace llvm_ks {
|
|
struct ARMGenInstrInfo : public TargetInstrInfo {
|
|
explicit ARMGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1);
|
|
~ARMGenInstrInfo() override {}
|
|
};
|
|
} // end llvm namespace
|
|
#endif // GET_INSTRINFO_HEADER
|
|
|
|
|
|
#ifdef GET_INSTRINFO_OPERAND_ENUM
|
|
#undef GET_INSTRINFO_OPERAND_ENUM
|
|
namespace llvm_ks {
|
|
namespace ARM {
|
|
namespace OpName {
|
|
enum {
|
|
OPERAND_LAST
|
|
};
|
|
} // end namespace OpName
|
|
} // end namespace ARM
|
|
} // end namespace llvm_ks
|
|
#endif //GET_INSTRINFO_OPERAND_ENUM
|
|
#ifdef GET_INSTRINFO_NAMED_OPS
|
|
#undef GET_INSTRINFO_NAMED_OPS
|
|
namespace llvm_ks {
|
|
namespace ARM {
|
|
LLVM_READONLY
|
|
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
|
|
return -1;
|
|
}
|
|
} // end namespace ARM
|
|
} // end namespace llvm_ks
|
|
#endif //GET_INSTRINFO_NAMED_OPS
|
|
|
|
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
|
|
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
|
|
namespace llvm_ks {
|
|
namespace ARM {
|
|
namespace OpTypes {
|
|
enum OperandType {
|
|
VecListFourDByteIndexed = 0,
|
|
VecListFourDHWordIndexed = 1,
|
|
VecListFourDWordIndexed = 2,
|
|
VecListFourQHWordIndexed = 3,
|
|
VecListFourQWordIndexed = 4,
|
|
VecListOneDByteIndexed = 5,
|
|
VecListOneDHWordIndexed = 6,
|
|
VecListOneDWordIndexed = 7,
|
|
VecListThreeDByteIndexed = 8,
|
|
VecListThreeDHWordIndexed = 9,
|
|
VecListThreeDWordIndexed = 10,
|
|
VecListThreeQHWordIndexed = 11,
|
|
VecListThreeQWordIndexed = 12,
|
|
VecListTwoDByteIndexed = 13,
|
|
VecListTwoDHWordIndexed = 14,
|
|
VecListTwoDWordIndexed = 15,
|
|
VecListTwoQHWordIndexed = 16,
|
|
VecListTwoQWordIndexed = 17,
|
|
VectorIndex16 = 18,
|
|
VectorIndex32 = 19,
|
|
VectorIndex8 = 20,
|
|
addr_offset_none = 21,
|
|
addrmode2 = 22,
|
|
addrmode3 = 23,
|
|
addrmode3_pre = 24,
|
|
addrmode5 = 25,
|
|
addrmode5_pre = 26,
|
|
addrmode5fp16 = 27,
|
|
addrmode6 = 28,
|
|
addrmode6align16 = 29,
|
|
addrmode6align32 = 30,
|
|
addrmode6align64 = 31,
|
|
addrmode6align64or128 = 32,
|
|
addrmode6align64or128or256 = 33,
|
|
addrmode6alignNone = 34,
|
|
addrmode6dup = 35,
|
|
addrmode6dupalign16 = 36,
|
|
addrmode6dupalign32 = 37,
|
|
addrmode6dupalign64 = 38,
|
|
addrmode6dupalign64or128 = 39,
|
|
addrmode6dupalignNone = 40,
|
|
addrmode6oneL32 = 41,
|
|
addrmode_imm12 = 42,
|
|
addrmode_imm12_pre = 43,
|
|
addrmode_tbb = 44,
|
|
addrmode_tbh = 45,
|
|
addrmodepc = 46,
|
|
adrlabel = 47,
|
|
am2offset_imm = 48,
|
|
am2offset_reg = 49,
|
|
am3offset = 50,
|
|
am6offset = 51,
|
|
banked_reg = 52,
|
|
bf_inv_mask_imm = 53,
|
|
bl_target = 54,
|
|
bltarget = 55,
|
|
blx_target = 56,
|
|
br_target = 57,
|
|
brtarget = 58,
|
|
c_imm = 59,
|
|
cc_out = 60,
|
|
cmovpred = 61,
|
|
coproc_option_imm = 62,
|
|
cpinst_operand = 63,
|
|
dpr_reglist = 64,
|
|
f32imm = 65,
|
|
f64imm = 66,
|
|
fbits16 = 67,
|
|
fbits32 = 68,
|
|
i16imm = 69,
|
|
i1imm = 70,
|
|
i32imm = 71,
|
|
i64imm = 72,
|
|
i8imm = 73,
|
|
iflags_op = 74,
|
|
imm0_1 = 75,
|
|
imm0_15 = 76,
|
|
imm0_239 = 77,
|
|
imm0_255 = 78,
|
|
imm0_3 = 79,
|
|
imm0_31 = 80,
|
|
imm0_32 = 81,
|
|
imm0_4095 = 82,
|
|
imm0_4095_neg = 83,
|
|
imm0_63 = 84,
|
|
imm0_65535 = 85,
|
|
imm0_65535_expr = 86,
|
|
imm0_65535_neg = 87,
|
|
imm0_7 = 88,
|
|
imm16 = 89,
|
|
imm1_15 = 90,
|
|
imm1_16 = 91,
|
|
imm1_31 = 92,
|
|
imm1_32 = 93,
|
|
imm1_7 = 94,
|
|
imm24b = 95,
|
|
imm256_65535_expr = 96,
|
|
imm32 = 97,
|
|
imm8 = 98,
|
|
imm_sr = 99,
|
|
imod_op = 100,
|
|
instsyncb_opt = 101,
|
|
it_mask = 102,
|
|
it_pred = 103,
|
|
ldst_so_reg = 104,
|
|
ldstm_mode = 105,
|
|
memb_opt = 106,
|
|
mod_imm = 107,
|
|
mod_imm_neg = 108,
|
|
mod_imm_not = 109,
|
|
msr_mask = 110,
|
|
nImmSplatI16 = 111,
|
|
nImmSplatI32 = 112,
|
|
nImmSplatI64 = 113,
|
|
nImmSplatI8 = 114,
|
|
nImmSplatNotI16 = 115,
|
|
nImmSplatNotI32 = 116,
|
|
nImmVMOVF32 = 117,
|
|
nImmVMOVI16ByteReplicate = 118,
|
|
nImmVMOVI32 = 119,
|
|
nImmVMOVI32ByteReplicate = 120,
|
|
nImmVMOVI32Neg = 121,
|
|
nImmVMVNI16ByteReplicate = 122,
|
|
nImmVMVNI32ByteReplicate = 123,
|
|
nModImm = 124,
|
|
neon_vcvt_imm32 = 125,
|
|
nohash_imm = 126,
|
|
p_imm = 127,
|
|
pclabel = 128,
|
|
pkh_asr_amt = 129,
|
|
pkh_lsl_amt = 130,
|
|
postidx_imm8 = 131,
|
|
postidx_imm8s4 = 132,
|
|
postidx_reg = 133,
|
|
pred = 134,
|
|
reglist = 135,
|
|
rot_imm = 136,
|
|
s_cc_out = 137,
|
|
setend_op = 138,
|
|
shift_imm = 139,
|
|
shift_so_reg_imm = 140,
|
|
shift_so_reg_reg = 141,
|
|
shr_imm16 = 142,
|
|
shr_imm32 = 143,
|
|
shr_imm64 = 144,
|
|
shr_imm8 = 145,
|
|
so_reg_imm = 146,
|
|
so_reg_reg = 147,
|
|
spr_reglist = 148,
|
|
t2_shift_imm = 149,
|
|
t2_so_imm = 150,
|
|
t2_so_imm_neg = 151,
|
|
t2_so_imm_not = 152,
|
|
t2_so_imm_notSext = 153,
|
|
t2_so_reg = 154,
|
|
t2addrmode_imm0_1020s4 = 155,
|
|
t2addrmode_imm12 = 156,
|
|
t2addrmode_imm8 = 157,
|
|
t2addrmode_imm8_pre = 158,
|
|
t2addrmode_imm8s4 = 159,
|
|
t2addrmode_imm8s4_pre = 160,
|
|
t2addrmode_negimm8 = 161,
|
|
t2addrmode_posimm8 = 162,
|
|
t2addrmode_so_reg = 163,
|
|
t2adrlabel = 164,
|
|
t2am_imm8_offset = 165,
|
|
t2am_imm8s4_offset = 166,
|
|
t2ldr_pcrel_imm12 = 167,
|
|
t2ldrlabel = 168,
|
|
t_addrmode_is1 = 169,
|
|
t_addrmode_is2 = 170,
|
|
t_addrmode_is4 = 171,
|
|
t_addrmode_pc = 172,
|
|
t_addrmode_rr = 173,
|
|
t_addrmode_rrs1 = 174,
|
|
t_addrmode_rrs2 = 175,
|
|
t_addrmode_rrs4 = 176,
|
|
t_addrmode_sp = 177,
|
|
t_adrlabel = 178,
|
|
t_bcctarget = 179,
|
|
t_bltarget = 180,
|
|
t_blxtarget = 181,
|
|
t_brtarget = 182,
|
|
t_cbtarget = 183,
|
|
t_imm0_1020s4 = 184,
|
|
t_imm0_508s4 = 185,
|
|
t_imm0_508s4_neg = 186,
|
|
uncondbrtarget = 187,
|
|
vfp_f16imm = 188,
|
|
vfp_f32imm = 189,
|
|
vfp_f64imm = 190,
|
|
OPERAND_TYPE_LIST_END
|
|
};
|
|
} // end namespace OpTypes
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} // end namespace ARM
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} // end namespace llvm_ks
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#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
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