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1526 lines
39 KiB
1526 lines
39 KiB
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Target Register Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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namespace llvm_ks {
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class MCRegisterClass;
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extern const MCRegisterClass HexagonMCRegisterClasses[];
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namespace Hexagon {
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enum {
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NoRegister,
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CS = 1,
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GP = 2,
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PC = 3,
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UGP = 4,
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UPC = 5,
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UPCH = 6,
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UPCL = 7,
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USR = 8,
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USR_OVF = 9,
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C5 = 10,
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C6 = 11,
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C7 = 12,
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CS0 = 13,
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CS1 = 14,
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D0 = 15,
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D1 = 16,
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D2 = 17,
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D3 = 18,
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D4 = 19,
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D5 = 20,
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D6 = 21,
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D7 = 22,
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D8 = 23,
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D9 = 24,
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D10 = 25,
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D11 = 26,
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D12 = 27,
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D13 = 28,
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D14 = 29,
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D15 = 30,
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LC0 = 31,
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LC1 = 32,
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M0 = 33,
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M1 = 34,
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P0 = 35,
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P1 = 36,
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P2 = 37,
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P3 = 38,
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Q0 = 39,
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Q1 = 40,
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Q2 = 41,
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Q3 = 42,
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R0 = 43,
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R1 = 44,
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R2 = 45,
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R3 = 46,
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R4 = 47,
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R5 = 48,
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R6 = 49,
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R7 = 50,
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R8 = 51,
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R9 = 52,
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R10 = 53,
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R11 = 54,
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R12 = 55,
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R13 = 56,
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R14 = 57,
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R15 = 58,
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R16 = 59,
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R17 = 60,
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R18 = 61,
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R19 = 62,
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R20 = 63,
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R21 = 64,
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R22 = 65,
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R23 = 66,
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R24 = 67,
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R25 = 68,
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R26 = 69,
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R27 = 70,
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R28 = 71,
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R29 = 72,
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R30 = 73,
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R31 = 74,
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SA0 = 75,
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SA1 = 76,
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V0 = 77,
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V1 = 78,
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V2 = 79,
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V3 = 80,
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V4 = 81,
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V5 = 82,
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V6 = 83,
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V7 = 84,
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V8 = 85,
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V9 = 86,
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V10 = 87,
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V11 = 88,
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V12 = 89,
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V13 = 90,
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V14 = 91,
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V15 = 92,
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V16 = 93,
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V17 = 94,
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V18 = 95,
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V19 = 96,
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V20 = 97,
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V21 = 98,
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V22 = 99,
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V23 = 100,
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V24 = 101,
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V25 = 102,
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V26 = 103,
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V27 = 104,
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V28 = 105,
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V29 = 106,
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V30 = 107,
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V31 = 108,
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W0 = 109,
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W1 = 110,
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W2 = 111,
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W3 = 112,
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W4 = 113,
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W5 = 114,
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W6 = 115,
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W7 = 116,
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W8 = 117,
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W9 = 118,
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W10 = 119,
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W11 = 120,
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W12 = 121,
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W13 = 122,
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W14 = 123,
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W15 = 124,
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C1_0 = 125,
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C3_2 = 126,
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C7_6 = 127,
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C9_8 = 128,
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C11_10 = 129,
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P3_0 = 130,
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NUM_TARGET_REGS // 131
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};
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}
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// Register classes
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namespace Hexagon {
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enum {
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IntRegsRegClassID = 0,
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CtrRegsRegClassID = 1,
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IntRegsLow8RegClassID = 2,
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PredRegsRegClassID = 3,
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ModRegsRegClassID = 4,
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CtrRegs_with_subreg_overflowRegClassID = 5,
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DoubleRegsRegClassID = 6,
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CtrRegs64RegClassID = 7,
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DoubleRegs_with_subreg_hireg_in_IntRegsLow8RegClassID = 8,
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CtrRegs64_with_subreg_overflowRegClassID = 9,
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VectorRegsRegClassID = 10,
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VecPredRegsRegClassID = 11,
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VectorRegs128BRegClassID = 12,
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VecDblRegsRegClassID = 13,
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VecPredRegs128BRegClassID = 14,
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VecDblRegs128BRegClassID = 15,
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};
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}
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// Subregister indices
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namespace Hexagon {
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enum {
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NoSubRegister,
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subreg_hireg, // 1
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subreg_loreg, // 2
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subreg_overflow, // 3
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NUM_TARGET_SUBREGS
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};
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}
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} // End llvm namespace
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* MC Register Information *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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namespace llvm_ks {
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extern const MCPhysReg HexagonRegDiffLists[] = {
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/* 0 */ 0, 0,
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/* 2 */ 0, 1, 0,
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/* 5 */ 45, 1, 1, 1, 0,
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/* 10 */ 5, 1, 0,
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/* 13 */ 9, 1, 0,
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/* 16 */ 12, 1, 0,
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/* 19 */ 28, 1, 0,
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/* 22 */ 29, 1, 0,
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/* 25 */ 30, 1, 0,
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/* 28 */ 31, 1, 0,
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/* 31 */ 32, 1, 0,
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/* 34 */ 33, 1, 0,
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/* 37 */ 34, 1, 0,
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/* 40 */ 35, 1, 0,
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/* 43 */ 36, 1, 0,
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/* 46 */ 37, 1, 0,
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/* 49 */ 38, 1, 0,
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/* 52 */ 39, 1, 0,
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/* 55 */ 40, 1, 0,
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/* 58 */ 41, 1, 0,
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/* 61 */ 42, 1, 0,
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/* 64 */ 43, 1, 0,
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/* 67 */ 65373, 1, 0,
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/* 70 */ 65420, 1, 0,
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/* 73 */ 65504, 1, 0,
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/* 76 */ 65505, 1, 0,
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/* 79 */ 65506, 1, 0,
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/* 82 */ 65507, 1, 0,
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/* 85 */ 65508, 1, 0,
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/* 88 */ 65509, 1, 0,
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/* 91 */ 65510, 1, 0,
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/* 94 */ 65511, 1, 0,
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/* 97 */ 65512, 1, 0,
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/* 100 */ 65513, 1, 0,
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/* 103 */ 65514, 1, 0,
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/* 106 */ 65515, 1, 0,
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/* 109 */ 65516, 1, 0,
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/* 112 */ 65517, 1, 0,
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/* 115 */ 65518, 1, 0,
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/* 118 */ 65519, 1, 0,
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/* 121 */ 2, 2, 0,
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/* 124 */ 3, 4, 0,
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/* 127 */ 6, 0,
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/* 129 */ 7, 0,
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/* 131 */ 65454, 10, 0,
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/* 134 */ 12, 0,
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/* 136 */ 16, 0,
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/* 138 */ 17, 0,
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/* 140 */ 18, 0,
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/* 142 */ 19, 0,
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/* 144 */ 20, 0,
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/* 146 */ 21, 0,
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/* 148 */ 22, 0,
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/* 150 */ 23, 0,
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/* 152 */ 24, 0,
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/* 154 */ 25, 0,
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/* 156 */ 26, 0,
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/* 158 */ 27, 0,
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/* 160 */ 28, 0,
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/* 162 */ 29, 0,
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/* 164 */ 30, 0,
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/* 166 */ 31, 0,
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/* 168 */ 32, 0,
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/* 170 */ 50, 0,
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/* 172 */ 94, 0,
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/* 174 */ 115, 0,
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/* 176 */ 116, 0,
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/* 178 */ 65535, 120, 0,
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/* 181 */ 125, 0,
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/* 183 */ 127, 0,
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/* 185 */ 65486, 65492, 0,
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/* 188 */ 65493, 0,
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/* 190 */ 65494, 0,
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/* 192 */ 65495, 0,
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/* 194 */ 65496, 0,
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/* 196 */ 65497, 0,
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/* 198 */ 65498, 0,
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/* 200 */ 65499, 0,
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/* 202 */ 65500, 0,
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/* 204 */ 65501, 0,
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/* 206 */ 65502, 0,
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/* 208 */ 65503, 0,
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/* 210 */ 65504, 0,
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/* 212 */ 65505, 0,
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/* 214 */ 65506, 0,
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/* 216 */ 65507, 0,
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/* 218 */ 65508, 0,
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/* 220 */ 65512, 0,
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/* 222 */ 65514, 0,
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/* 224 */ 65523, 0,
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/* 226 */ 65524, 0,
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/* 228 */ 65527, 0,
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/* 230 */ 65416, 1, 65530, 0,
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/* 234 */ 65411, 65534, 0,
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/* 237 */ 2, 65535, 0,
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};
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extern const unsigned HexagonLaneMaskLists[] = {
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/* 0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ~0u,
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/* 5 */ 0x00000002, 0x00000001, ~0u,
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/* 8 */ 0x00000001, 0x00000002, ~0u,
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};
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extern const uint16_t HexagonSubRegIdxLists[] = {
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/* 0 */ 2, 1, 0,
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/* 3 */ 2, 3, 1, 0,
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/* 7 */ 3, 0,
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};
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extern const MCRegisterInfo::SubRegCoveredBits HexagonSubRegIdxRanges[] = {
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{ 65535, 65535 },
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{ 32, 32 }, // subreg_hireg
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{ 0, 32 }, // subreg_loreg
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{ 0, 1 }, // subreg_overflow
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};
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extern const char HexagonRegStrings[] = {
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/* 0 */ 'D', '1', '0', 0,
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/* 4 */ 'R', '1', '0', 0,
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/* 8 */ 'V', '1', '0', 0,
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/* 12 */ 'W', '1', '0', 0,
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/* 16 */ 'C', '1', '1', '_', '1', '0', 0,
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/* 23 */ 'R', '2', '0', 0,
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/* 27 */ 'V', '2', '0', 0,
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/* 31 */ 'R', '3', '0', 0,
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/* 35 */ 'V', '3', '0', 0,
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/* 39 */ 'S', 'A', '0', 0,
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/* 43 */ 'L', 'C', '0', 0,
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/* 47 */ 'D', '0', 0,
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/* 50 */ 'M', '0', 0,
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/* 53 */ 'P', '0', 0,
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/* 56 */ 'Q', '0', 0,
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/* 59 */ 'R', '0', 0,
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/* 62 */ 'C', 'S', '0', 0,
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/* 66 */ 'V', '0', 0,
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/* 69 */ 'W', '0', 0,
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/* 72 */ 'C', '1', '_', '0', 0,
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/* 77 */ 'P', '3', '_', '0', 0,
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/* 82 */ 'D', '1', '1', 0,
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/* 86 */ 'R', '1', '1', 0,
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/* 90 */ 'V', '1', '1', 0,
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/* 94 */ 'W', '1', '1', 0,
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/* 98 */ 'R', '2', '1', 0,
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/* 102 */ 'V', '2', '1', 0,
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/* 106 */ 'R', '3', '1', 0,
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/* 110 */ 'V', '3', '1', 0,
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/* 114 */ 'S', 'A', '1', 0,
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/* 118 */ 'L', 'C', '1', 0,
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/* 122 */ 'D', '1', 0,
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/* 125 */ 'M', '1', 0,
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/* 128 */ 'P', '1', 0,
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/* 131 */ 'Q', '1', 0,
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/* 134 */ 'R', '1', 0,
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/* 137 */ 'C', 'S', '1', 0,
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/* 141 */ 'V', '1', 0,
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/* 144 */ 'W', '1', 0,
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/* 147 */ 'D', '1', '2', 0,
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/* 151 */ 'R', '1', '2', 0,
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/* 155 */ 'V', '1', '2', 0,
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/* 159 */ 'W', '1', '2', 0,
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/* 163 */ 'R', '2', '2', 0,
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/* 167 */ 'V', '2', '2', 0,
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/* 171 */ 'D', '2', 0,
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/* 174 */ 'P', '2', 0,
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/* 177 */ 'Q', '2', 0,
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/* 180 */ 'R', '2', 0,
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/* 183 */ 'V', '2', 0,
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/* 186 */ 'W', '2', 0,
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/* 189 */ 'C', '3', '_', '2', 0,
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/* 194 */ 'D', '1', '3', 0,
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/* 198 */ 'R', '1', '3', 0,
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/* 202 */ 'V', '1', '3', 0,
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/* 206 */ 'W', '1', '3', 0,
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/* 210 */ 'R', '2', '3', 0,
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/* 214 */ 'V', '2', '3', 0,
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/* 218 */ 'D', '3', 0,
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/* 221 */ 'P', '3', 0,
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/* 224 */ 'Q', '3', 0,
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/* 227 */ 'R', '3', 0,
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/* 230 */ 'V', '3', 0,
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/* 233 */ 'W', '3', 0,
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/* 236 */ 'D', '1', '4', 0,
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/* 240 */ 'R', '1', '4', 0,
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/* 244 */ 'V', '1', '4', 0,
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/* 248 */ 'W', '1', '4', 0,
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/* 252 */ 'R', '2', '4', 0,
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/* 256 */ 'V', '2', '4', 0,
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/* 260 */ 'D', '4', 0,
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/* 263 */ 'R', '4', 0,
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/* 266 */ 'V', '4', 0,
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/* 269 */ 'W', '4', 0,
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/* 272 */ 'D', '1', '5', 0,
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/* 276 */ 'R', '1', '5', 0,
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/* 280 */ 'V', '1', '5', 0,
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/* 284 */ 'W', '1', '5', 0,
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/* 288 */ 'R', '2', '5', 0,
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/* 292 */ 'V', '2', '5', 0,
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/* 296 */ 'C', '5', 0,
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/* 299 */ 'D', '5', 0,
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/* 302 */ 'R', '5', 0,
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/* 305 */ 'V', '5', 0,
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/* 308 */ 'W', '5', 0,
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/* 311 */ 'R', '1', '6', 0,
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/* 315 */ 'V', '1', '6', 0,
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/* 319 */ 'R', '2', '6', 0,
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/* 323 */ 'V', '2', '6', 0,
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/* 327 */ 'C', '6', 0,
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/* 330 */ 'D', '6', 0,
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/* 333 */ 'R', '6', 0,
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/* 336 */ 'V', '6', 0,
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/* 339 */ 'W', '6', 0,
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/* 342 */ 'C', '7', '_', '6', 0,
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/* 347 */ 'R', '1', '7', 0,
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/* 351 */ 'V', '1', '7', 0,
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/* 355 */ 'R', '2', '7', 0,
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/* 359 */ 'V', '2', '7', 0,
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/* 363 */ 'C', '7', 0,
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/* 366 */ 'D', '7', 0,
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/* 369 */ 'R', '7', 0,
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/* 372 */ 'V', '7', 0,
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/* 375 */ 'W', '7', 0,
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/* 378 */ 'R', '1', '8', 0,
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/* 382 */ 'V', '1', '8', 0,
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/* 386 */ 'R', '2', '8', 0,
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/* 390 */ 'V', '2', '8', 0,
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/* 394 */ 'D', '8', 0,
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/* 397 */ 'R', '8', 0,
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/* 400 */ 'V', '8', 0,
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/* 403 */ 'W', '8', 0,
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/* 406 */ 'C', '9', '_', '8', 0,
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/* 411 */ 'R', '1', '9', 0,
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/* 415 */ 'V', '1', '9', 0,
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/* 419 */ 'R', '2', '9', 0,
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/* 423 */ 'V', '2', '9', 0,
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/* 427 */ 'D', '9', 0,
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/* 430 */ 'R', '9', 0,
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/* 433 */ 'V', '9', 0,
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/* 436 */ 'W', '9', 0,
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/* 439 */ 'U', 'P', 'C', 0,
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/* 443 */ 'U', 'S', 'R', '_', 'O', 'V', 'F', 0,
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/* 451 */ 'U', 'P', 'C', 'H', 0,
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/* 456 */ 'U', 'P', 'C', 'L', 0,
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/* 461 */ 'U', 'G', 'P', 0,
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/* 465 */ 'U', 'S', 'R', 0,
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/* 469 */ 'C', 'S', 0,
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};
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extern const MCRegisterDesc HexagonRegDesc[] = { // Descriptors
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{ 3, 0, 0, 0, 0, 0 },
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{ 469, 16, 1, 0, 32, 5 },
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{ 462, 1, 183, 2, 1, 3 },
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{ 440, 1, 181, 2, 1, 3 },
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{ 461, 1, 181, 2, 1, 3 },
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{ 439, 237, 1, 0, 160, 5 },
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{ 451, 1, 238, 2, 2032, 3 },
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{ 456, 1, 235, 2, 3650, 3 },
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{ 465, 3, 179, 7, 2064, 9 },
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{ 443, 1, 178, 2, 2064, 3 },
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{ 296, 1, 1, 2, 3761, 3 },
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{ 327, 1, 176, 2, 3761, 3 },
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{ 363, 1, 174, 2, 3761, 3 },
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{ 62, 1, 226, 2, 3585, 3 },
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{ 137, 1, 224, 2, 3585, 3 },
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{ 47, 19, 1, 0, 1794, 5 },
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{ 122, 22, 1, 0, 1794, 5 },
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{ 171, 25, 1, 0, 1794, 5 },
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{ 218, 28, 1, 0, 1794, 5 },
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{ 260, 31, 1, 0, 1794, 5 },
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{ 299, 34, 1, 0, 1794, 5 },
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{ 330, 37, 1, 0, 1794, 5 },
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{ 366, 40, 1, 0, 1794, 5 },
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{ 394, 43, 1, 0, 1794, 5 },
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{ 427, 46, 1, 0, 1794, 5 },
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{ 0, 49, 1, 0, 1794, 5 },
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{ 82, 52, 1, 0, 1794, 5 },
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{ 147, 55, 1, 0, 1794, 5 },
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{ 194, 58, 1, 0, 1794, 5 },
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{ 236, 61, 1, 0, 1794, 5 },
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{ 272, 64, 1, 0, 1794, 5 },
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{ 43, 1, 172, 2, 2145, 3 },
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{ 118, 1, 172, 2, 2145, 3 },
|
|
{ 50, 1, 1, 2, 3521, 3 },
|
|
{ 125, 1, 1, 2, 3521, 3 },
|
|
{ 53, 1, 1, 2, 2113, 3 },
|
|
{ 128, 1, 1, 2, 2113, 3 },
|
|
{ 174, 1, 1, 2, 2113, 3 },
|
|
{ 221, 1, 1, 2, 2113, 3 },
|
|
{ 56, 1, 1, 2, 2113, 3 },
|
|
{ 131, 1, 1, 2, 2113, 3 },
|
|
{ 177, 1, 1, 2, 2113, 3 },
|
|
{ 224, 1, 1, 2, 2113, 3 },
|
|
{ 59, 1, 218, 2, 3361, 3 },
|
|
{ 134, 1, 216, 2, 3361, 3 },
|
|
{ 180, 1, 216, 2, 3361, 3 },
|
|
{ 227, 1, 214, 2, 3361, 3 },
|
|
{ 263, 1, 214, 2, 3361, 3 },
|
|
{ 302, 1, 212, 2, 3361, 3 },
|
|
{ 333, 1, 212, 2, 3361, 3 },
|
|
{ 369, 1, 210, 2, 3361, 3 },
|
|
{ 397, 1, 210, 2, 3361, 3 },
|
|
{ 430, 1, 208, 2, 3361, 3 },
|
|
{ 4, 1, 208, 2, 3361, 3 },
|
|
{ 86, 1, 206, 2, 3361, 3 },
|
|
{ 151, 1, 206, 2, 3361, 3 },
|
|
{ 198, 1, 204, 2, 3361, 3 },
|
|
{ 240, 1, 204, 2, 3361, 3 },
|
|
{ 276, 1, 202, 2, 3361, 3 },
|
|
{ 311, 1, 202, 2, 3361, 3 },
|
|
{ 347, 1, 200, 2, 3361, 3 },
|
|
{ 378, 1, 200, 2, 3361, 3 },
|
|
{ 411, 1, 198, 2, 3361, 3 },
|
|
{ 23, 1, 198, 2, 3361, 3 },
|
|
{ 98, 1, 196, 2, 3361, 3 },
|
|
{ 163, 1, 196, 2, 3361, 3 },
|
|
{ 210, 1, 194, 2, 3361, 3 },
|
|
{ 252, 1, 194, 2, 3361, 3 },
|
|
{ 288, 1, 192, 2, 3361, 3 },
|
|
{ 319, 1, 192, 2, 3361, 3 },
|
|
{ 355, 1, 190, 2, 3361, 3 },
|
|
{ 386, 1, 190, 2, 3361, 3 },
|
|
{ 419, 1, 188, 2, 3361, 3 },
|
|
{ 31, 1, 188, 2, 3361, 3 },
|
|
{ 106, 1, 186, 2, 3361, 3 },
|
|
{ 39, 1, 170, 2, 3553, 3 },
|
|
{ 114, 1, 170, 2, 3553, 3 },
|
|
{ 66, 1, 168, 2, 3553, 3 },
|
|
{ 141, 1, 166, 2, 3553, 3 },
|
|
{ 183, 1, 166, 2, 3553, 3 },
|
|
{ 230, 1, 164, 2, 3553, 3 },
|
|
{ 266, 1, 164, 2, 3553, 3 },
|
|
{ 305, 1, 162, 2, 3553, 3 },
|
|
{ 336, 1, 162, 2, 3553, 3 },
|
|
{ 372, 1, 160, 2, 3553, 3 },
|
|
{ 400, 1, 160, 2, 3553, 3 },
|
|
{ 433, 1, 158, 2, 3553, 3 },
|
|
{ 8, 1, 158, 2, 3553, 3 },
|
|
{ 90, 1, 156, 2, 3553, 3 },
|
|
{ 155, 1, 156, 2, 3553, 3 },
|
|
{ 202, 1, 154, 2, 3553, 3 },
|
|
{ 244, 1, 154, 2, 3553, 3 },
|
|
{ 280, 1, 152, 2, 3553, 3 },
|
|
{ 315, 1, 152, 2, 3553, 3 },
|
|
{ 351, 1, 150, 2, 3553, 3 },
|
|
{ 382, 1, 150, 2, 3553, 3 },
|
|
{ 415, 1, 148, 2, 3553, 3 },
|
|
{ 27, 1, 148, 2, 3553, 3 },
|
|
{ 102, 1, 146, 2, 3553, 3 },
|
|
{ 167, 1, 146, 2, 3553, 3 },
|
|
{ 214, 1, 144, 2, 3553, 3 },
|
|
{ 256, 1, 144, 2, 3553, 3 },
|
|
{ 292, 1, 142, 2, 3553, 3 },
|
|
{ 323, 1, 142, 2, 3553, 3 },
|
|
{ 359, 1, 140, 2, 3553, 3 },
|
|
{ 390, 1, 140, 2, 3553, 3 },
|
|
{ 423, 1, 138, 2, 3553, 3 },
|
|
{ 35, 1, 138, 2, 3553, 3 },
|
|
{ 110, 1, 136, 2, 3553, 3 },
|
|
{ 69, 73, 1, 0, 1074, 5 },
|
|
{ 144, 76, 1, 0, 1074, 5 },
|
|
{ 186, 79, 1, 0, 1074, 5 },
|
|
{ 233, 82, 1, 0, 1074, 5 },
|
|
{ 269, 85, 1, 0, 1074, 5 },
|
|
{ 308, 88, 1, 0, 1074, 5 },
|
|
{ 339, 91, 1, 0, 1074, 5 },
|
|
{ 375, 94, 1, 0, 1074, 5 },
|
|
{ 403, 97, 1, 0, 1074, 5 },
|
|
{ 436, 100, 1, 0, 1074, 5 },
|
|
{ 12, 103, 1, 0, 1074, 5 },
|
|
{ 94, 106, 1, 0, 1074, 5 },
|
|
{ 159, 109, 1, 0, 1074, 5 },
|
|
{ 206, 112, 1, 0, 1074, 5 },
|
|
{ 248, 115, 1, 0, 1074, 5 },
|
|
{ 284, 118, 1, 0, 1074, 5 },
|
|
{ 72, 185, 1, 0, 2097, 8 },
|
|
{ 189, 185, 1, 0, 2097, 8 },
|
|
{ 342, 70, 1, 0, 208, 5 },
|
|
{ 406, 230, 1, 3, 1984, 8 },
|
|
{ 16, 234, 1, 0, 1936, 8 },
|
|
{ 77, 1, 1, 2, 80, 0 },
|
|
};
|
|
|
|
extern const MCPhysReg HexagonRegUnitRoots[][2] = {
|
|
{ Hexagon::CS0 },
|
|
{ Hexagon::CS1 },
|
|
{ Hexagon::GP },
|
|
{ Hexagon::PC },
|
|
{ Hexagon::UGP },
|
|
{ Hexagon::UPCL },
|
|
{ Hexagon::UPCH },
|
|
{ Hexagon::USR_OVF },
|
|
{ Hexagon::C5 },
|
|
{ Hexagon::C6, Hexagon::M0 },
|
|
{ Hexagon::C7, Hexagon::M1 },
|
|
{ Hexagon::R0 },
|
|
{ Hexagon::R1 },
|
|
{ Hexagon::R2 },
|
|
{ Hexagon::R3 },
|
|
{ Hexagon::R4 },
|
|
{ Hexagon::R5 },
|
|
{ Hexagon::R6 },
|
|
{ Hexagon::R7 },
|
|
{ Hexagon::R8 },
|
|
{ Hexagon::R9 },
|
|
{ Hexagon::R10 },
|
|
{ Hexagon::R11 },
|
|
{ Hexagon::R12 },
|
|
{ Hexagon::R13 },
|
|
{ Hexagon::R14 },
|
|
{ Hexagon::R15 },
|
|
{ Hexagon::R16 },
|
|
{ Hexagon::R17 },
|
|
{ Hexagon::R18 },
|
|
{ Hexagon::R19 },
|
|
{ Hexagon::R20 },
|
|
{ Hexagon::R21 },
|
|
{ Hexagon::R22 },
|
|
{ Hexagon::R23 },
|
|
{ Hexagon::R24 },
|
|
{ Hexagon::R25 },
|
|
{ Hexagon::R26 },
|
|
{ Hexagon::R27 },
|
|
{ Hexagon::R28 },
|
|
{ Hexagon::R29 },
|
|
{ Hexagon::R30 },
|
|
{ Hexagon::R31 },
|
|
{ Hexagon::LC0 },
|
|
{ Hexagon::LC1 },
|
|
{ Hexagon::P0, Hexagon::P3_0 },
|
|
{ Hexagon::P1, Hexagon::P3_0 },
|
|
{ Hexagon::P2, Hexagon::P3_0 },
|
|
{ Hexagon::P3, Hexagon::P3_0 },
|
|
{ Hexagon::Q0 },
|
|
{ Hexagon::Q1 },
|
|
{ Hexagon::Q2 },
|
|
{ Hexagon::Q3 },
|
|
{ Hexagon::SA0 },
|
|
{ Hexagon::SA1 },
|
|
{ Hexagon::V0 },
|
|
{ Hexagon::V1 },
|
|
{ Hexagon::V2 },
|
|
{ Hexagon::V3 },
|
|
{ Hexagon::V4 },
|
|
{ Hexagon::V5 },
|
|
{ Hexagon::V6 },
|
|
{ Hexagon::V7 },
|
|
{ Hexagon::V8 },
|
|
{ Hexagon::V9 },
|
|
{ Hexagon::V10 },
|
|
{ Hexagon::V11 },
|
|
{ Hexagon::V12 },
|
|
{ Hexagon::V13 },
|
|
{ Hexagon::V14 },
|
|
{ Hexagon::V15 },
|
|
{ Hexagon::V16 },
|
|
{ Hexagon::V17 },
|
|
{ Hexagon::V18 },
|
|
{ Hexagon::V19 },
|
|
{ Hexagon::V20 },
|
|
{ Hexagon::V21 },
|
|
{ Hexagon::V22 },
|
|
{ Hexagon::V23 },
|
|
{ Hexagon::V24 },
|
|
{ Hexagon::V25 },
|
|
{ Hexagon::V26 },
|
|
{ Hexagon::V27 },
|
|
{ Hexagon::V28 },
|
|
{ Hexagon::V29 },
|
|
{ Hexagon::V30 },
|
|
{ Hexagon::V31 },
|
|
};
|
|
|
|
namespace { // Register classes...
|
|
// IntRegs Register Class...
|
|
const MCPhysReg IntRegs[] = {
|
|
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, Hexagon::R12, Hexagon::R13, Hexagon::R14, Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R10, Hexagon::R11, Hexagon::R29, Hexagon::R30, Hexagon::R31,
|
|
};
|
|
|
|
// IntRegs Bit set.
|
|
const uint8_t IntRegsBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
|
};
|
|
|
|
// CtrRegs Register Class...
|
|
const MCPhysReg CtrRegs[] = {
|
|
Hexagon::LC0, Hexagon::SA0, Hexagon::LC1, Hexagon::SA1, Hexagon::P3_0, Hexagon::M0, Hexagon::M1, Hexagon::C6, Hexagon::C7, Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH, Hexagon::USR, Hexagon::USR_OVF, Hexagon::UGP, Hexagon::GP, Hexagon::PC,
|
|
};
|
|
|
|
// CtrRegs Bit set.
|
|
const uint8_t CtrRegsBits[] = {
|
|
0xdc, 0x7b, 0x00, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
|
};
|
|
|
|
// IntRegsLow8 Register Class...
|
|
const MCPhysReg IntRegsLow8[] = {
|
|
Hexagon::R7, Hexagon::R6, Hexagon::R5, Hexagon::R4, Hexagon::R3, Hexagon::R2, Hexagon::R1, Hexagon::R0,
|
|
};
|
|
|
|
// IntRegsLow8 Bit set.
|
|
const uint8_t IntRegsLow8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
|
};
|
|
|
|
// PredRegs Register Class...
|
|
const MCPhysReg PredRegs[] = {
|
|
Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3,
|
|
};
|
|
|
|
// PredRegs Bit set.
|
|
const uint8_t PredRegsBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x78,
|
|
};
|
|
|
|
// ModRegs Register Class...
|
|
const MCPhysReg ModRegs[] = {
|
|
Hexagon::M0, Hexagon::M1,
|
|
};
|
|
|
|
// ModRegs Bit set.
|
|
const uint8_t ModRegsBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x06,
|
|
};
|
|
|
|
// CtrRegs_with_subreg_overflow Register Class...
|
|
const MCPhysReg CtrRegs_with_subreg_overflow[] = {
|
|
Hexagon::USR,
|
|
};
|
|
|
|
// CtrRegs_with_subreg_overflow Bit set.
|
|
const uint8_t CtrRegs_with_subreg_overflowBits[] = {
|
|
0x00, 0x01,
|
|
};
|
|
|
|
// DoubleRegs Register Class...
|
|
const MCPhysReg DoubleRegs[] = {
|
|
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D6, Hexagon::D7, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, Hexagon::D5, Hexagon::D14, Hexagon::D15,
|
|
};
|
|
|
|
// DoubleRegs Bit set.
|
|
const uint8_t DoubleRegsBits[] = {
|
|
0x00, 0x80, 0xff, 0x7f,
|
|
};
|
|
|
|
// CtrRegs64 Register Class...
|
|
const MCPhysReg CtrRegs64[] = {
|
|
Hexagon::C1_0, Hexagon::C3_2, Hexagon::C7_6, Hexagon::C9_8, Hexagon::C11_10, Hexagon::CS, Hexagon::UPC,
|
|
};
|
|
|
|
// CtrRegs64 Bit set.
|
|
const uint8_t CtrRegs64Bits[] = {
|
|
0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03,
|
|
};
|
|
|
|
// DoubleRegs_with_subreg_hireg_in_IntRegsLow8 Register Class...
|
|
const MCPhysReg DoubleRegs_with_subreg_hireg_in_IntRegsLow8[] = {
|
|
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
|
|
};
|
|
|
|
// DoubleRegs_with_subreg_hireg_in_IntRegsLow8 Bit set.
|
|
const uint8_t DoubleRegs_with_subreg_hireg_in_IntRegsLow8Bits[] = {
|
|
0x00, 0x80, 0x07,
|
|
};
|
|
|
|
// CtrRegs64_with_subreg_overflow Register Class...
|
|
const MCPhysReg CtrRegs64_with_subreg_overflow[] = {
|
|
Hexagon::C9_8,
|
|
};
|
|
|
|
// CtrRegs64_with_subreg_overflow Bit set.
|
|
const uint8_t CtrRegs64_with_subreg_overflowBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
|
};
|
|
|
|
// VectorRegs Register Class...
|
|
const MCPhysReg VectorRegs[] = {
|
|
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31,
|
|
};
|
|
|
|
// VectorRegs Bit set.
|
|
const uint8_t VectorRegsBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
|
|
};
|
|
|
|
// VecPredRegs Register Class...
|
|
const MCPhysReg VecPredRegs[] = {
|
|
Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3,
|
|
};
|
|
|
|
// VecPredRegs Bit set.
|
|
const uint8_t VecPredRegsBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
|
|
};
|
|
|
|
// VectorRegs128B Register Class...
|
|
const MCPhysReg VectorRegs128B[] = {
|
|
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, Hexagon::V30, Hexagon::V31,
|
|
};
|
|
|
|
// VectorRegs128B Bit set.
|
|
const uint8_t VectorRegs128BBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
|
|
};
|
|
|
|
// VecDblRegs Register Class...
|
|
const MCPhysReg VecDblRegs[] = {
|
|
Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15,
|
|
};
|
|
|
|
// VecDblRegs Bit set.
|
|
const uint8_t VecDblRegsBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
|
|
};
|
|
|
|
// VecPredRegs128B Register Class...
|
|
const MCPhysReg VecPredRegs128B[] = {
|
|
Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3,
|
|
};
|
|
|
|
// VecPredRegs128B Bit set.
|
|
const uint8_t VecPredRegs128BBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
|
|
};
|
|
|
|
// VecDblRegs128B Register Class...
|
|
const MCPhysReg VecDblRegs128B[] = {
|
|
Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7, Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11, Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15,
|
|
};
|
|
|
|
// VecDblRegs128B Bit set.
|
|
const uint8_t VecDblRegs128BBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
|
|
};
|
|
|
|
}
|
|
|
|
extern const char HexagonRegClassStrings[] = {
|
|
/* 0 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', 0,
|
|
/* 10 */ 'D', 'o', 'u', 'b', 'l', 'e', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'h', 'i', 'r', 'e', 'g', '_', 'i', 'n', '_', 'I', 'n', 't', 'R', 'e', 'g', 's', 'L', 'o', 'w', '8', 0,
|
|
/* 54 */ 'V', 'e', 'c', 'P', 'r', 'e', 'd', 'R', 'e', 'g', 's', '1', '2', '8', 'B', 0,
|
|
/* 70 */ 'V', 'e', 'c', 'D', 'b', 'l', 'R', 'e', 'g', 's', '1', '2', '8', 'B', 0,
|
|
/* 85 */ 'V', 'e', 'c', 't', 'o', 'r', 'R', 'e', 'g', 's', '1', '2', '8', 'B', 0,
|
|
/* 100 */ 'V', 'e', 'c', 'P', 'r', 'e', 'd', 'R', 'e', 'g', 's', 0,
|
|
/* 112 */ 'M', 'o', 'd', 'R', 'e', 'g', 's', 0,
|
|
/* 120 */ 'D', 'o', 'u', 'b', 'l', 'e', 'R', 'e', 'g', 's', 0,
|
|
/* 131 */ 'V', 'e', 'c', 'D', 'b', 'l', 'R', 'e', 'g', 's', 0,
|
|
/* 142 */ 'V', 'e', 'c', 't', 'o', 'r', 'R', 'e', 'g', 's', 0,
|
|
/* 153 */ 'C', 't', 'r', 'R', 'e', 'g', 's', 0,
|
|
/* 161 */ 'I', 'n', 't', 'R', 'e', 'g', 's', 0,
|
|
/* 169 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'o', 'v', 'e', 'r', 'f', 'l', 'o', 'w', 0,
|
|
/* 200 */ 'C', 't', 'r', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'r', 'e', 'g', '_', 'o', 'v', 'e', 'r', 'f', 'l', 'o', 'w', 0,
|
|
};
|
|
|
|
extern const MCRegisterClass HexagonMCRegisterClasses[] = {
|
|
{ IntRegs, IntRegsBits, 161, 32, sizeof(IntRegsBits), Hexagon::IntRegsRegClassID, 4, 4, 1, 1 },
|
|
{ CtrRegs, CtrRegsBits, 153, 18, sizeof(CtrRegsBits), Hexagon::CtrRegsRegClassID, 4, 4, 1, 0 },
|
|
{ IntRegsLow8, IntRegsLow8Bits, 42, 8, sizeof(IntRegsLow8Bits), Hexagon::IntRegsLow8RegClassID, 4, 4, 1, 1 },
|
|
{ PredRegs, PredRegsBits, 103, 4, sizeof(PredRegsBits), Hexagon::PredRegsRegClassID, 4, 4, 1, 1 },
|
|
{ ModRegs, ModRegsBits, 112, 2, sizeof(ModRegsBits), Hexagon::ModRegsRegClassID, 4, 4, 1, 1 },
|
|
{ CtrRegs_with_subreg_overflow, CtrRegs_with_subreg_overflowBits, 200, 1, sizeof(CtrRegs_with_subreg_overflowBits), Hexagon::CtrRegs_with_subreg_overflowRegClassID, 4, 4, 1, 0 },
|
|
{ DoubleRegs, DoubleRegsBits, 120, 16, sizeof(DoubleRegsBits), Hexagon::DoubleRegsRegClassID, 8, 8, 1, 1 },
|
|
{ CtrRegs64, CtrRegs64Bits, 0, 7, sizeof(CtrRegs64Bits), Hexagon::CtrRegs64RegClassID, 8, 8, 1, 0 },
|
|
{ DoubleRegs_with_subreg_hireg_in_IntRegsLow8, DoubleRegs_with_subreg_hireg_in_IntRegsLow8Bits, 10, 4, sizeof(DoubleRegs_with_subreg_hireg_in_IntRegsLow8Bits), Hexagon::DoubleRegs_with_subreg_hireg_in_IntRegsLow8RegClassID, 8, 8, 1, 1 },
|
|
{ CtrRegs64_with_subreg_overflow, CtrRegs64_with_subreg_overflowBits, 169, 1, sizeof(CtrRegs64_with_subreg_overflowBits), Hexagon::CtrRegs64_with_subreg_overflowRegClassID, 8, 8, 1, 0 },
|
|
{ VectorRegs, VectorRegsBits, 142, 32, sizeof(VectorRegsBits), Hexagon::VectorRegsRegClassID, 64, 64, 1, 1 },
|
|
{ VecPredRegs, VecPredRegsBits, 100, 4, sizeof(VecPredRegsBits), Hexagon::VecPredRegsRegClassID, 64, 64, 1, 1 },
|
|
{ VectorRegs128B, VectorRegs128BBits, 85, 32, sizeof(VectorRegs128BBits), Hexagon::VectorRegs128BRegClassID, 128, 128, 1, 1 },
|
|
{ VecDblRegs, VecDblRegsBits, 131, 16, sizeof(VecDblRegsBits), Hexagon::VecDblRegsRegClassID, 128, 128, 1, 1 },
|
|
{ VecPredRegs128B, VecPredRegs128BBits, 54, 4, sizeof(VecPredRegs128BBits), Hexagon::VecPredRegs128BRegClassID, 128, 128, 1, 1 },
|
|
{ VecDblRegs128B, VecDblRegs128BBits, 70, 16, sizeof(VecDblRegs128BBits), Hexagon::VecDblRegs128BRegClassID, 256, 256, 1, 1 },
|
|
};
|
|
|
|
// Hexagon Dwarf<->LLVM register mappings.
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[] = {
|
|
{ 0U, Hexagon::R0 },
|
|
{ 1U, Hexagon::R1 },
|
|
{ 2U, Hexagon::R2 },
|
|
{ 3U, Hexagon::R3 },
|
|
{ 4U, Hexagon::R4 },
|
|
{ 5U, Hexagon::R5 },
|
|
{ 6U, Hexagon::R6 },
|
|
{ 7U, Hexagon::R7 },
|
|
{ 8U, Hexagon::R8 },
|
|
{ 9U, Hexagon::R9 },
|
|
{ 10U, Hexagon::R10 },
|
|
{ 11U, Hexagon::R11 },
|
|
{ 12U, Hexagon::R12 },
|
|
{ 13U, Hexagon::R13 },
|
|
{ 14U, Hexagon::R14 },
|
|
{ 15U, Hexagon::R15 },
|
|
{ 16U, Hexagon::R16 },
|
|
{ 17U, Hexagon::R17 },
|
|
{ 18U, Hexagon::R18 },
|
|
{ 19U, Hexagon::R19 },
|
|
{ 20U, Hexagon::R20 },
|
|
{ 21U, Hexagon::R21 },
|
|
{ 22U, Hexagon::R22 },
|
|
{ 23U, Hexagon::R23 },
|
|
{ 24U, Hexagon::R24 },
|
|
{ 25U, Hexagon::R25 },
|
|
{ 26U, Hexagon::R26 },
|
|
{ 27U, Hexagon::R27 },
|
|
{ 28U, Hexagon::R28 },
|
|
{ 29U, Hexagon::R29 },
|
|
{ 30U, Hexagon::R30 },
|
|
{ 31U, Hexagon::R31 },
|
|
{ 32U, Hexagon::D0 },
|
|
{ 34U, Hexagon::D1 },
|
|
{ 36U, Hexagon::D2 },
|
|
{ 38U, Hexagon::D3 },
|
|
{ 40U, Hexagon::D4 },
|
|
{ 42U, Hexagon::D5 },
|
|
{ 44U, Hexagon::D6 },
|
|
{ 46U, Hexagon::D7 },
|
|
{ 48U, Hexagon::D8 },
|
|
{ 50U, Hexagon::D9 },
|
|
{ 52U, Hexagon::D10 },
|
|
{ 54U, Hexagon::D11 },
|
|
{ 56U, Hexagon::D12 },
|
|
{ 58U, Hexagon::D13 },
|
|
{ 60U, Hexagon::D14 },
|
|
{ 62U, Hexagon::D15 },
|
|
{ 63U, Hexagon::P0 },
|
|
{ 64U, Hexagon::P1 },
|
|
{ 65U, Hexagon::P2 },
|
|
{ 66U, Hexagon::P3 },
|
|
{ 67U, Hexagon::C1_0 },
|
|
{ 68U, Hexagon::LC0 },
|
|
{ 69U, Hexagon::C3_2 },
|
|
{ 70U, Hexagon::LC1 },
|
|
{ 71U, Hexagon::P3_0 },
|
|
{ 72U, Hexagon::C7_6 },
|
|
{ 73U, Hexagon::M1 },
|
|
{ 74U, Hexagon::C9_8 },
|
|
{ 75U, Hexagon::USR },
|
|
{ 76U, Hexagon::C11_10 },
|
|
{ 77U, Hexagon::UGP },
|
|
{ 78U, Hexagon::GP },
|
|
{ 79U, Hexagon::CS0 },
|
|
{ 80U, Hexagon::CS1 },
|
|
{ 81U, Hexagon::UPCL },
|
|
{ 82U, Hexagon::UPCH },
|
|
{ 99U, Hexagon::W0 },
|
|
{ 100U, Hexagon::V1 },
|
|
{ 101U, Hexagon::W1 },
|
|
{ 102U, Hexagon::V3 },
|
|
{ 103U, Hexagon::W2 },
|
|
{ 104U, Hexagon::V5 },
|
|
{ 105U, Hexagon::W3 },
|
|
{ 106U, Hexagon::V7 },
|
|
{ 107U, Hexagon::W4 },
|
|
{ 108U, Hexagon::V9 },
|
|
{ 109U, Hexagon::W5 },
|
|
{ 110U, Hexagon::V11 },
|
|
{ 111U, Hexagon::W6 },
|
|
{ 112U, Hexagon::V13 },
|
|
{ 113U, Hexagon::W7 },
|
|
{ 114U, Hexagon::V15 },
|
|
{ 115U, Hexagon::W8 },
|
|
{ 116U, Hexagon::V17 },
|
|
{ 117U, Hexagon::W9 },
|
|
{ 118U, Hexagon::V19 },
|
|
{ 119U, Hexagon::W10 },
|
|
{ 120U, Hexagon::V21 },
|
|
{ 121U, Hexagon::W11 },
|
|
{ 122U, Hexagon::V23 },
|
|
{ 123U, Hexagon::W12 },
|
|
{ 124U, Hexagon::V25 },
|
|
{ 125U, Hexagon::W13 },
|
|
{ 126U, Hexagon::V27 },
|
|
{ 127U, Hexagon::W14 },
|
|
{ 128U, Hexagon::V29 },
|
|
{ 129U, Hexagon::W15 },
|
|
{ 130U, Hexagon::V31 },
|
|
{ 131U, Hexagon::Q0 },
|
|
{ 132U, Hexagon::Q1 },
|
|
{ 133U, Hexagon::Q2 },
|
|
{ 134U, Hexagon::Q3 },
|
|
};
|
|
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize = array_lengthof(HexagonDwarfFlavour0Dwarf2L);
|
|
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[] = {
|
|
{ 0U, Hexagon::R0 },
|
|
{ 1U, Hexagon::R1 },
|
|
{ 2U, Hexagon::R2 },
|
|
{ 3U, Hexagon::R3 },
|
|
{ 4U, Hexagon::R4 },
|
|
{ 5U, Hexagon::R5 },
|
|
{ 6U, Hexagon::R6 },
|
|
{ 7U, Hexagon::R7 },
|
|
{ 8U, Hexagon::R8 },
|
|
{ 9U, Hexagon::R9 },
|
|
{ 10U, Hexagon::R10 },
|
|
{ 11U, Hexagon::R11 },
|
|
{ 12U, Hexagon::R12 },
|
|
{ 13U, Hexagon::R13 },
|
|
{ 14U, Hexagon::R14 },
|
|
{ 15U, Hexagon::R15 },
|
|
{ 16U, Hexagon::R16 },
|
|
{ 17U, Hexagon::R17 },
|
|
{ 18U, Hexagon::R18 },
|
|
{ 19U, Hexagon::R19 },
|
|
{ 20U, Hexagon::R20 },
|
|
{ 21U, Hexagon::R21 },
|
|
{ 22U, Hexagon::R22 },
|
|
{ 23U, Hexagon::R23 },
|
|
{ 24U, Hexagon::R24 },
|
|
{ 25U, Hexagon::R25 },
|
|
{ 26U, Hexagon::R26 },
|
|
{ 27U, Hexagon::R27 },
|
|
{ 28U, Hexagon::R28 },
|
|
{ 29U, Hexagon::R29 },
|
|
{ 30U, Hexagon::R30 },
|
|
{ 31U, Hexagon::R31 },
|
|
{ 32U, Hexagon::D0 },
|
|
{ 34U, Hexagon::D1 },
|
|
{ 36U, Hexagon::D2 },
|
|
{ 38U, Hexagon::D3 },
|
|
{ 40U, Hexagon::D4 },
|
|
{ 42U, Hexagon::D5 },
|
|
{ 44U, Hexagon::D6 },
|
|
{ 46U, Hexagon::D7 },
|
|
{ 48U, Hexagon::D8 },
|
|
{ 50U, Hexagon::D9 },
|
|
{ 52U, Hexagon::D10 },
|
|
{ 54U, Hexagon::D11 },
|
|
{ 56U, Hexagon::D12 },
|
|
{ 58U, Hexagon::D13 },
|
|
{ 60U, Hexagon::D14 },
|
|
{ 62U, Hexagon::D15 },
|
|
{ 63U, Hexagon::P0 },
|
|
{ 64U, Hexagon::P1 },
|
|
{ 65U, Hexagon::P2 },
|
|
{ 66U, Hexagon::P3 },
|
|
{ 67U, Hexagon::C1_0 },
|
|
{ 68U, Hexagon::LC0 },
|
|
{ 69U, Hexagon::C3_2 },
|
|
{ 70U, Hexagon::LC1 },
|
|
{ 71U, Hexagon::P3_0 },
|
|
{ 72U, Hexagon::C7_6 },
|
|
{ 73U, Hexagon::M1 },
|
|
{ 74U, Hexagon::C9_8 },
|
|
{ 75U, Hexagon::USR },
|
|
{ 76U, Hexagon::C11_10 },
|
|
{ 77U, Hexagon::UGP },
|
|
{ 78U, Hexagon::GP },
|
|
{ 79U, Hexagon::CS0 },
|
|
{ 80U, Hexagon::CS1 },
|
|
{ 81U, Hexagon::UPCL },
|
|
{ 82U, Hexagon::UPCH },
|
|
{ 99U, Hexagon::W0 },
|
|
{ 100U, Hexagon::V1 },
|
|
{ 101U, Hexagon::W1 },
|
|
{ 102U, Hexagon::V3 },
|
|
{ 103U, Hexagon::W2 },
|
|
{ 104U, Hexagon::V5 },
|
|
{ 105U, Hexagon::W3 },
|
|
{ 106U, Hexagon::V7 },
|
|
{ 107U, Hexagon::W4 },
|
|
{ 108U, Hexagon::V9 },
|
|
{ 109U, Hexagon::W5 },
|
|
{ 110U, Hexagon::V11 },
|
|
{ 111U, Hexagon::W6 },
|
|
{ 112U, Hexagon::V13 },
|
|
{ 113U, Hexagon::W7 },
|
|
{ 114U, Hexagon::V15 },
|
|
{ 115U, Hexagon::W8 },
|
|
{ 116U, Hexagon::V17 },
|
|
{ 117U, Hexagon::W9 },
|
|
{ 118U, Hexagon::V19 },
|
|
{ 119U, Hexagon::W10 },
|
|
{ 120U, Hexagon::V21 },
|
|
{ 121U, Hexagon::W11 },
|
|
{ 122U, Hexagon::V23 },
|
|
{ 123U, Hexagon::W12 },
|
|
{ 124U, Hexagon::V25 },
|
|
{ 125U, Hexagon::W13 },
|
|
{ 126U, Hexagon::V27 },
|
|
{ 127U, Hexagon::W14 },
|
|
{ 128U, Hexagon::V29 },
|
|
{ 129U, Hexagon::W15 },
|
|
{ 130U, Hexagon::V31 },
|
|
{ 131U, Hexagon::Q0 },
|
|
{ 132U, Hexagon::Q1 },
|
|
{ 133U, Hexagon::Q2 },
|
|
{ 134U, Hexagon::Q3 },
|
|
};
|
|
extern const unsigned HexagonEHFlavour0Dwarf2LSize = array_lengthof(HexagonEHFlavour0Dwarf2L);
|
|
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[] = {
|
|
{ Hexagon::CS, 78U },
|
|
{ Hexagon::GP, 78U },
|
|
{ Hexagon::PC, 76U },
|
|
{ Hexagon::UGP, 77U },
|
|
{ Hexagon::UPC, 80U },
|
|
{ Hexagon::UPCH, 82U },
|
|
{ Hexagon::UPCL, 81U },
|
|
{ Hexagon::USR, 75U },
|
|
{ Hexagon::C5, 72U },
|
|
{ Hexagon::C6, 73U },
|
|
{ Hexagon::C7, 74U },
|
|
{ Hexagon::CS0, 79U },
|
|
{ Hexagon::CS1, 80U },
|
|
{ Hexagon::D0, 32U },
|
|
{ Hexagon::D1, 34U },
|
|
{ Hexagon::D2, 36U },
|
|
{ Hexagon::D3, 38U },
|
|
{ Hexagon::D4, 40U },
|
|
{ Hexagon::D5, 42U },
|
|
{ Hexagon::D6, 44U },
|
|
{ Hexagon::D7, 46U },
|
|
{ Hexagon::D8, 48U },
|
|
{ Hexagon::D9, 50U },
|
|
{ Hexagon::D10, 52U },
|
|
{ Hexagon::D11, 54U },
|
|
{ Hexagon::D12, 56U },
|
|
{ Hexagon::D13, 58U },
|
|
{ Hexagon::D14, 60U },
|
|
{ Hexagon::D15, 62U },
|
|
{ Hexagon::LC0, 68U },
|
|
{ Hexagon::LC1, 70U },
|
|
{ Hexagon::M0, 72U },
|
|
{ Hexagon::M1, 73U },
|
|
{ Hexagon::P0, 63U },
|
|
{ Hexagon::P1, 64U },
|
|
{ Hexagon::P2, 65U },
|
|
{ Hexagon::P3, 66U },
|
|
{ Hexagon::Q0, 131U },
|
|
{ Hexagon::Q1, 132U },
|
|
{ Hexagon::Q2, 133U },
|
|
{ Hexagon::Q3, 134U },
|
|
{ Hexagon::R0, 0U },
|
|
{ Hexagon::R1, 1U },
|
|
{ Hexagon::R2, 2U },
|
|
{ Hexagon::R3, 3U },
|
|
{ Hexagon::R4, 4U },
|
|
{ Hexagon::R5, 5U },
|
|
{ Hexagon::R6, 6U },
|
|
{ Hexagon::R7, 7U },
|
|
{ Hexagon::R8, 8U },
|
|
{ Hexagon::R9, 9U },
|
|
{ Hexagon::R10, 10U },
|
|
{ Hexagon::R11, 11U },
|
|
{ Hexagon::R12, 12U },
|
|
{ Hexagon::R13, 13U },
|
|
{ Hexagon::R14, 14U },
|
|
{ Hexagon::R15, 15U },
|
|
{ Hexagon::R16, 16U },
|
|
{ Hexagon::R17, 17U },
|
|
{ Hexagon::R18, 18U },
|
|
{ Hexagon::R19, 19U },
|
|
{ Hexagon::R20, 20U },
|
|
{ Hexagon::R21, 21U },
|
|
{ Hexagon::R22, 22U },
|
|
{ Hexagon::R23, 23U },
|
|
{ Hexagon::R24, 24U },
|
|
{ Hexagon::R25, 25U },
|
|
{ Hexagon::R26, 26U },
|
|
{ Hexagon::R27, 27U },
|
|
{ Hexagon::R28, 28U },
|
|
{ Hexagon::R29, 29U },
|
|
{ Hexagon::R30, 30U },
|
|
{ Hexagon::R31, 31U },
|
|
{ Hexagon::SA0, 67U },
|
|
{ Hexagon::SA1, 69U },
|
|
{ Hexagon::V0, 99U },
|
|
{ Hexagon::V1, 100U },
|
|
{ Hexagon::V2, 101U },
|
|
{ Hexagon::V3, 102U },
|
|
{ Hexagon::V4, 103U },
|
|
{ Hexagon::V5, 104U },
|
|
{ Hexagon::V6, 105U },
|
|
{ Hexagon::V7, 106U },
|
|
{ Hexagon::V8, 107U },
|
|
{ Hexagon::V9, 108U },
|
|
{ Hexagon::V10, 109U },
|
|
{ Hexagon::V11, 110U },
|
|
{ Hexagon::V12, 111U },
|
|
{ Hexagon::V13, 112U },
|
|
{ Hexagon::V14, 113U },
|
|
{ Hexagon::V15, 114U },
|
|
{ Hexagon::V16, 115U },
|
|
{ Hexagon::V17, 116U },
|
|
{ Hexagon::V18, 117U },
|
|
{ Hexagon::V19, 118U },
|
|
{ Hexagon::V20, 119U },
|
|
{ Hexagon::V21, 120U },
|
|
{ Hexagon::V22, 121U },
|
|
{ Hexagon::V23, 122U },
|
|
{ Hexagon::V24, 123U },
|
|
{ Hexagon::V25, 124U },
|
|
{ Hexagon::V26, 125U },
|
|
{ Hexagon::V27, 126U },
|
|
{ Hexagon::V28, 127U },
|
|
{ Hexagon::V29, 128U },
|
|
{ Hexagon::V30, 129U },
|
|
{ Hexagon::V31, 130U },
|
|
{ Hexagon::W0, 99U },
|
|
{ Hexagon::W1, 101U },
|
|
{ Hexagon::W2, 103U },
|
|
{ Hexagon::W3, 105U },
|
|
{ Hexagon::W4, 107U },
|
|
{ Hexagon::W5, 109U },
|
|
{ Hexagon::W6, 111U },
|
|
{ Hexagon::W7, 113U },
|
|
{ Hexagon::W8, 115U },
|
|
{ Hexagon::W9, 117U },
|
|
{ Hexagon::W10, 119U },
|
|
{ Hexagon::W11, 121U },
|
|
{ Hexagon::W12, 123U },
|
|
{ Hexagon::W13, 125U },
|
|
{ Hexagon::W14, 127U },
|
|
{ Hexagon::W15, 129U },
|
|
{ Hexagon::C1_0, 67U },
|
|
{ Hexagon::C3_2, 69U },
|
|
{ Hexagon::C7_6, 72U },
|
|
{ Hexagon::C9_8, 74U },
|
|
{ Hexagon::C11_10, 76U },
|
|
{ Hexagon::P3_0, 71U },
|
|
};
|
|
extern const unsigned HexagonDwarfFlavour0L2DwarfSize = array_lengthof(HexagonDwarfFlavour0L2Dwarf);
|
|
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[] = {
|
|
{ Hexagon::CS, 78U },
|
|
{ Hexagon::GP, 78U },
|
|
{ Hexagon::PC, 76U },
|
|
{ Hexagon::UGP, 77U },
|
|
{ Hexagon::UPC, 80U },
|
|
{ Hexagon::UPCH, 82U },
|
|
{ Hexagon::UPCL, 81U },
|
|
{ Hexagon::USR, 75U },
|
|
{ Hexagon::C5, 72U },
|
|
{ Hexagon::C6, 73U },
|
|
{ Hexagon::C7, 74U },
|
|
{ Hexagon::CS0, 79U },
|
|
{ Hexagon::CS1, 80U },
|
|
{ Hexagon::D0, 32U },
|
|
{ Hexagon::D1, 34U },
|
|
{ Hexagon::D2, 36U },
|
|
{ Hexagon::D3, 38U },
|
|
{ Hexagon::D4, 40U },
|
|
{ Hexagon::D5, 42U },
|
|
{ Hexagon::D6, 44U },
|
|
{ Hexagon::D7, 46U },
|
|
{ Hexagon::D8, 48U },
|
|
{ Hexagon::D9, 50U },
|
|
{ Hexagon::D10, 52U },
|
|
{ Hexagon::D11, 54U },
|
|
{ Hexagon::D12, 56U },
|
|
{ Hexagon::D13, 58U },
|
|
{ Hexagon::D14, 60U },
|
|
{ Hexagon::D15, 62U },
|
|
{ Hexagon::LC0, 68U },
|
|
{ Hexagon::LC1, 70U },
|
|
{ Hexagon::M0, 72U },
|
|
{ Hexagon::M1, 73U },
|
|
{ Hexagon::P0, 63U },
|
|
{ Hexagon::P1, 64U },
|
|
{ Hexagon::P2, 65U },
|
|
{ Hexagon::P3, 66U },
|
|
{ Hexagon::Q0, 131U },
|
|
{ Hexagon::Q1, 132U },
|
|
{ Hexagon::Q2, 133U },
|
|
{ Hexagon::Q3, 134U },
|
|
{ Hexagon::R0, 0U },
|
|
{ Hexagon::R1, 1U },
|
|
{ Hexagon::R2, 2U },
|
|
{ Hexagon::R3, 3U },
|
|
{ Hexagon::R4, 4U },
|
|
{ Hexagon::R5, 5U },
|
|
{ Hexagon::R6, 6U },
|
|
{ Hexagon::R7, 7U },
|
|
{ Hexagon::R8, 8U },
|
|
{ Hexagon::R9, 9U },
|
|
{ Hexagon::R10, 10U },
|
|
{ Hexagon::R11, 11U },
|
|
{ Hexagon::R12, 12U },
|
|
{ Hexagon::R13, 13U },
|
|
{ Hexagon::R14, 14U },
|
|
{ Hexagon::R15, 15U },
|
|
{ Hexagon::R16, 16U },
|
|
{ Hexagon::R17, 17U },
|
|
{ Hexagon::R18, 18U },
|
|
{ Hexagon::R19, 19U },
|
|
{ Hexagon::R20, 20U },
|
|
{ Hexagon::R21, 21U },
|
|
{ Hexagon::R22, 22U },
|
|
{ Hexagon::R23, 23U },
|
|
{ Hexagon::R24, 24U },
|
|
{ Hexagon::R25, 25U },
|
|
{ Hexagon::R26, 26U },
|
|
{ Hexagon::R27, 27U },
|
|
{ Hexagon::R28, 28U },
|
|
{ Hexagon::R29, 29U },
|
|
{ Hexagon::R30, 30U },
|
|
{ Hexagon::R31, 31U },
|
|
{ Hexagon::SA0, 67U },
|
|
{ Hexagon::SA1, 69U },
|
|
{ Hexagon::V0, 99U },
|
|
{ Hexagon::V1, 100U },
|
|
{ Hexagon::V2, 101U },
|
|
{ Hexagon::V3, 102U },
|
|
{ Hexagon::V4, 103U },
|
|
{ Hexagon::V5, 104U },
|
|
{ Hexagon::V6, 105U },
|
|
{ Hexagon::V7, 106U },
|
|
{ Hexagon::V8, 107U },
|
|
{ Hexagon::V9, 108U },
|
|
{ Hexagon::V10, 109U },
|
|
{ Hexagon::V11, 110U },
|
|
{ Hexagon::V12, 111U },
|
|
{ Hexagon::V13, 112U },
|
|
{ Hexagon::V14, 113U },
|
|
{ Hexagon::V15, 114U },
|
|
{ Hexagon::V16, 115U },
|
|
{ Hexagon::V17, 116U },
|
|
{ Hexagon::V18, 117U },
|
|
{ Hexagon::V19, 118U },
|
|
{ Hexagon::V20, 119U },
|
|
{ Hexagon::V21, 120U },
|
|
{ Hexagon::V22, 121U },
|
|
{ Hexagon::V23, 122U },
|
|
{ Hexagon::V24, 123U },
|
|
{ Hexagon::V25, 124U },
|
|
{ Hexagon::V26, 125U },
|
|
{ Hexagon::V27, 126U },
|
|
{ Hexagon::V28, 127U },
|
|
{ Hexagon::V29, 128U },
|
|
{ Hexagon::V30, 129U },
|
|
{ Hexagon::V31, 130U },
|
|
{ Hexagon::W0, 99U },
|
|
{ Hexagon::W1, 101U },
|
|
{ Hexagon::W2, 103U },
|
|
{ Hexagon::W3, 105U },
|
|
{ Hexagon::W4, 107U },
|
|
{ Hexagon::W5, 109U },
|
|
{ Hexagon::W6, 111U },
|
|
{ Hexagon::W7, 113U },
|
|
{ Hexagon::W8, 115U },
|
|
{ Hexagon::W9, 117U },
|
|
{ Hexagon::W10, 119U },
|
|
{ Hexagon::W11, 121U },
|
|
{ Hexagon::W12, 123U },
|
|
{ Hexagon::W13, 125U },
|
|
{ Hexagon::W14, 127U },
|
|
{ Hexagon::W15, 129U },
|
|
{ Hexagon::C1_0, 67U },
|
|
{ Hexagon::C3_2, 69U },
|
|
{ Hexagon::C7_6, 72U },
|
|
{ Hexagon::C9_8, 74U },
|
|
{ Hexagon::C11_10, 76U },
|
|
{ Hexagon::P3_0, 71U },
|
|
};
|
|
extern const unsigned HexagonEHFlavour0L2DwarfSize = array_lengthof(HexagonEHFlavour0L2Dwarf);
|
|
|
|
extern const uint16_t HexagonRegEncodingTable[] = {
|
|
0,
|
|
12,
|
|
11,
|
|
9,
|
|
10,
|
|
14,
|
|
15,
|
|
14,
|
|
8,
|
|
0,
|
|
5,
|
|
6,
|
|
7,
|
|
12,
|
|
13,
|
|
0,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
14,
|
|
16,
|
|
18,
|
|
20,
|
|
22,
|
|
24,
|
|
26,
|
|
28,
|
|
30,
|
|
1,
|
|
3,
|
|
0,
|
|
1,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
2,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
14,
|
|
16,
|
|
18,
|
|
20,
|
|
22,
|
|
24,
|
|
26,
|
|
28,
|
|
30,
|
|
0,
|
|
2,
|
|
6,
|
|
8,
|
|
10,
|
|
4,
|
|
};
|
|
static inline void InitHexagonMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
|
|
RI->InitMCRegisterInfo(HexagonRegDesc, 131, RA, PC, HexagonMCRegisterClasses, 16, HexagonRegUnitRoots, 87, HexagonRegDiffLists, HexagonLaneMaskLists, HexagonRegStrings, HexagonRegClassStrings, HexagonSubRegIdxLists, 4,
|
|
HexagonSubRegIdxRanges, HexagonRegEncodingTable);
|
|
|
|
switch (DwarfFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
|
|
break;
|
|
}
|
|
switch (EHFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
|
|
break;
|
|
}
|
|
switch (DwarfFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
|
|
break;
|
|
}
|
|
switch (EHFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
|
|
break;
|
|
}
|
|
}
|
|
|
|
} // End llvm namespace
|
|
#endif // GET_REGINFO_MC_DESC
|