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10686 lines
346 KiB
10686 lines
346 KiB
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Machine Code Emitter *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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static const uint64_t InstBits[] = {
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(44040192), // ADCri
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UINT64_C(10485760), // ADCrr
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UINT64_C(10485760), // ADCrsi
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UINT64_C(10485776), // ADCrsr
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(41943040), // ADDri
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UINT64_C(8388608), // ADDrr
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UINT64_C(8388608), // ADDrsi
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UINT64_C(8388624), // ADDrsr
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(34537472), // ADR
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UINT64_C(4088398656), // AESD
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UINT64_C(4088398592), // AESE
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UINT64_C(4088398784), // AESIMC
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UINT64_C(4088398720), // AESMC
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UINT64_C(33554432), // ANDri
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UINT64_C(0), // ANDrr
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UINT64_C(0), // ANDrsi
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UINT64_C(16), // ANDrsr
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(130023455), // BFC
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UINT64_C(130023440), // BFI
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UINT64_C(62914560), // BICri
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UINT64_C(29360128), // BICrr
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UINT64_C(29360128), // BICrsi
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UINT64_C(29360144), // BICrsr
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UINT64_C(3776970864), // BKPT
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UINT64_C(3942645760), // BL
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UINT64_C(3778019120), // BLX
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UINT64_C(19922736), // BLX_pred
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UINT64_C(4194304000), // BLXi
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UINT64_C(184549376), // BL_pred
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(3778019088), // BX
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UINT64_C(19922720), // BXJ
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UINT64_C(0),
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UINT64_C(19922718), // BX_RET
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UINT64_C(19922704), // BX_pred
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UINT64_C(167772160), // Bcc
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UINT64_C(234881024), // CDP
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UINT64_C(4261412864), // CDP2
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UINT64_C(4118802463), // CLREX
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UINT64_C(24055568), // CLZ
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UINT64_C(57671680), // CMNri
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UINT64_C(24117248), // CMNzrr
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UINT64_C(24117248), // CMNzrsi
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UINT64_C(24117264), // CMNzrsr
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UINT64_C(55574528), // CMPri
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UINT64_C(22020096), // CMPrr
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UINT64_C(22020096), // CMPrsi
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UINT64_C(22020112), // CMPrsr
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(4043440128), // CPS1p
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UINT64_C(4043309056), // CPS2p
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UINT64_C(4043440128), // CPS3p
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UINT64_C(3774873664), // CRC32B
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UINT64_C(3774874176), // CRC32CB
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UINT64_C(3776971328), // CRC32CH
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UINT64_C(3779068480), // CRC32CW
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UINT64_C(3776970816), // CRC32H
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UINT64_C(3779067968), // CRC32W
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UINT64_C(52490480), // DBG
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UINT64_C(4118802512), // DMB
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UINT64_C(4118802496), // DSB
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UINT64_C(35651584), // EORri
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UINT64_C(2097152), // EORrr
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UINT64_C(2097152), // EORrsi
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UINT64_C(2097168), // EORrsr
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UINT64_C(23068782), // ERET
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UINT64_C(246418176), // FCONSTD
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UINT64_C(246417664), // FCONSTH
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UINT64_C(246417920), // FCONSTS
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UINT64_C(221252353), // FLDMXDB_UPD
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UINT64_C(210766593), // FLDMXIA
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UINT64_C(212863745), // FLDMXIA_UPD
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UINT64_C(250739216), // FMSTAT
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UINT64_C(220203777), // FSTMXDB_UPD
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UINT64_C(209718017), // FSTMXIA
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UINT64_C(211815169), // FSTMXIA_UPD
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UINT64_C(52490240), // HINT
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UINT64_C(3774873712), // HLT
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UINT64_C(3779068016), // HVC
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UINT64_C(4118802528), // ISB
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(26217631), // LDA
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UINT64_C(30411935), // LDAB
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UINT64_C(26218143), // LDAEX
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UINT64_C(30412447), // LDAEXB
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UINT64_C(28315295), // LDAEXD
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UINT64_C(32509599), // LDAEXH
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UINT64_C(32509087), // LDAH
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UINT64_C(4249878528), // LDC2L_OFFSET
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UINT64_C(4241489920), // LDC2L_OPTION
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UINT64_C(4235198464), // LDC2L_POST
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UINT64_C(4251975680), // LDC2L_PRE
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UINT64_C(4245684224), // LDC2_OFFSET
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UINT64_C(4237295616), // LDC2_OPTION
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UINT64_C(4231004160), // LDC2_POST
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UINT64_C(4247781376), // LDC2_PRE
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UINT64_C(223346688), // LDCL_OFFSET
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UINT64_C(214958080), // LDCL_OPTION
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UINT64_C(208666624), // LDCL_POST
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UINT64_C(225443840), // LDCL_PRE
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UINT64_C(219152384), // LDC_OFFSET
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UINT64_C(210763776), // LDC_OPTION
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UINT64_C(204472320), // LDC_POST
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UINT64_C(221249536), // LDC_PRE
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UINT64_C(135266304), // LDMDA
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UINT64_C(137363456), // LDMDA_UPD
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UINT64_C(152043520), // LDMDB
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UINT64_C(154140672), // LDMDB_UPD
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UINT64_C(143654912), // LDMIA
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UINT64_C(0),
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UINT64_C(145752064), // LDMIA_UPD
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UINT64_C(160432128), // LDMIB
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UINT64_C(162529280), // LDMIB_UPD
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UINT64_C(0),
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UINT64_C(74448896), // LDRBT_POST_IMM
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UINT64_C(108003328), // LDRBT_POST_REG
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UINT64_C(72351744), // LDRB_POST_IMM
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UINT64_C(105906176), // LDRB_POST_REG
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UINT64_C(91226112), // LDRB_PRE_IMM
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UINT64_C(124780544), // LDRB_PRE_REG
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UINT64_C(89128960), // LDRBi12
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UINT64_C(122683392), // LDRBrs
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UINT64_C(16777424), // LDRD
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UINT64_C(208), // LDRD_POST
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UINT64_C(18874576), // LDRD_PRE
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UINT64_C(26218399), // LDREX
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UINT64_C(30412703), // LDREXB
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UINT64_C(28315551), // LDREXD
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UINT64_C(32509855), // LDREXH
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UINT64_C(17825968), // LDRH
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UINT64_C(7340208), // LDRHTi
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UINT64_C(3145904), // LDRHTr
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UINT64_C(1048752), // LDRH_POST
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UINT64_C(19923120), // LDRH_PRE
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(17826000), // LDRSB
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UINT64_C(7340240), // LDRSBTi
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UINT64_C(3145936), // LDRSBTr
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UINT64_C(1048784), // LDRSB_POST
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UINT64_C(19923152), // LDRSB_PRE
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UINT64_C(17826032), // LDRSH
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UINT64_C(7340272), // LDRSHTi
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UINT64_C(3145968), // LDRSHTr
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UINT64_C(1048816), // LDRSH_POST
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UINT64_C(19923184), // LDRSH_PRE
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UINT64_C(0),
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UINT64_C(70254592), // LDRT_POST_IMM
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UINT64_C(103809024), // LDRT_POST_REG
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UINT64_C(68157440), // LDR_POST_IMM
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UINT64_C(101711872), // LDR_POST_REG
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UINT64_C(87031808), // LDR_PRE_IMM
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UINT64_C(120586240), // LDR_PRE_REG
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UINT64_C(85917696), // LDRcp
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UINT64_C(84934656), // LDRi12
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UINT64_C(118489088), // LDRrs
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(234881040), // MCR
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UINT64_C(4261412880), // MCR2
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UINT64_C(205520896), // MCRR
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UINT64_C(4232052736), // MCRR2
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UINT64_C(0),
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UINT64_C(2097296), // MLA
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UINT64_C(0),
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UINT64_C(6291600), // MLS
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(27324430), // MOVPCLR
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UINT64_C(0),
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UINT64_C(54525952), // MOVTi16
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(60817408), // MOVi
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UINT64_C(50331648), // MOVi16
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(27262976), // MOVr
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UINT64_C(27262976), // MOVr_TC
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UINT64_C(27262976), // MOVsi
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UINT64_C(27262992), // MOVsr
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(235929616), // MRC
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UINT64_C(4262461456), // MRC2
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UINT64_C(206569472), // MRRC
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UINT64_C(4233101312), // MRRC2
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UINT64_C(17760256), // MRS
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UINT64_C(16777728), // MRSbanked
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UINT64_C(21954560), // MRSsys
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UINT64_C(18935808), // MSR
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UINT64_C(18936320), // MSRbanked
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UINT64_C(52490240), // MSRi
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UINT64_C(144), // MUL
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(65011712), // MVNi
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UINT64_C(31457280), // MVNr
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UINT64_C(31457280), // MVNsi
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UINT64_C(31457296), // MVNsr
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UINT64_C(58720256), // ORRri
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UINT64_C(25165824), // ORRrr
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UINT64_C(25165824), // ORRrsi
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UINT64_C(25165840), // ORRrsr
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(109051920), // PKHBT
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UINT64_C(109051984), // PKHTB
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UINT64_C(4111527936), // PLDWi12
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UINT64_C(4145082368), // PLDWrs
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UINT64_C(4115722240), // PLDi12
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UINT64_C(4149276672), // PLDrs
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UINT64_C(4098945024), // PLIi12
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UINT64_C(4132499456), // PLIrs
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UINT64_C(16777296), // QADD
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UINT64_C(102764304), // QADD16
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UINT64_C(102764432), // QADD8
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UINT64_C(102764336), // QASX
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UINT64_C(20971600), // QDADD
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UINT64_C(23068752), // QDSUB
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UINT64_C(102764368), // QSAX
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UINT64_C(18874448), // QSUB
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UINT64_C(102764400), // QSUB16
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UINT64_C(102764528), // QSUB8
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UINT64_C(117378864), // RBIT
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UINT64_C(113184560), // REV
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UINT64_C(113184688), // REV16
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UINT64_C(117378992), // REVSH
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UINT64_C(4161800704), // RFEDA
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UINT64_C(4163897856), // RFEDA_UPD
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UINT64_C(4178577920), // RFEDB
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UINT64_C(4180675072), // RFEDB_UPD
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UINT64_C(4170189312), // RFEIA
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UINT64_C(4172286464), // RFEIA_UPD
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UINT64_C(4186966528), // RFEIB
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UINT64_C(4189063680), // RFEIB_UPD
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(0),
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UINT64_C(39845888), // RSBri
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UINT64_C(6291456), // RSBrr
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UINT64_C(6291456), // RSBrsi
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UINT64_C(6291472), // RSBrsr
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UINT64_C(48234496), // RSCri
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UINT64_C(14680064), // RSCrr
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UINT64_C(14680064), // RSCrsi
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UINT64_C(14680080), // RSCrsr
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UINT64_C(101715728), // SADD16
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UINT64_C(101715856), // SADD8
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UINT64_C(101715760), // SASX
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UINT64_C(46137344), // SBCri
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UINT64_C(12582912), // SBCrr
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UINT64_C(12582912), // SBCrsi
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UINT64_C(12582928), // SBCrsr
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UINT64_C(127926352), // SBFX
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UINT64_C(118550544), // SDIV
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UINT64_C(109055920), // SEL
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|
UINT64_C(4043374592), // SETEND
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UINT64_C(4044357632), // SETPAN
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UINT64_C(4060089408), // SHA1C
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UINT64_C(4088988352), // SHA1H
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UINT64_C(4062186560), // SHA1M
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UINT64_C(4061137984), // SHA1P
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UINT64_C(4063235136), // SHA1SU0
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UINT64_C(4089054080), // SHA1SU1
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UINT64_C(4076866624), // SHA256H
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UINT64_C(4077915200), // SHA256H2
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UINT64_C(4089054144), // SHA256SU0
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UINT64_C(4078963776), // SHA256SU1
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UINT64_C(103812880), // SHADD16
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UINT64_C(103813008), // SHADD8
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UINT64_C(103812912), // SHASX
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UINT64_C(103812944), // SHSAX
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UINT64_C(103812976), // SHSUB16
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UINT64_C(103813104), // SHSUB8
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UINT64_C(23068784), // SMC
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UINT64_C(16777344), // SMLABB
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UINT64_C(16777408), // SMLABT
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UINT64_C(117440528), // SMLAD
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UINT64_C(117440560), // SMLADX
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UINT64_C(14680208), // SMLAL
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UINT64_C(20971648), // SMLALBB
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UINT64_C(20971712), // SMLALBT
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UINT64_C(121634832), // SMLALD
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UINT64_C(121634864), // SMLALDX
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UINT64_C(20971680), // SMLALTB
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UINT64_C(20971744), // SMLALTT
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UINT64_C(0),
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UINT64_C(16777376), // SMLATB
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UINT64_C(16777440), // SMLATT
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UINT64_C(18874496), // SMLAWB
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UINT64_C(18874560), // SMLAWT
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UINT64_C(117440592), // SMLSD
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UINT64_C(117440624), // SMLSDX
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UINT64_C(121634896), // SMLSLD
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UINT64_C(121634928), // SMLSLDX
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UINT64_C(122683408), // SMMLA
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UINT64_C(122683440), // SMMLAR
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UINT64_C(122683600), // SMMLS
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UINT64_C(122683632), // SMMLSR
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UINT64_C(122744848), // SMMUL
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UINT64_C(122744880), // SMMULR
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UINT64_C(117501968), // SMUAD
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UINT64_C(117502000), // SMUADX
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UINT64_C(23068800), // SMULBB
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UINT64_C(23068864), // SMULBT
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UINT64_C(12583056), // SMULL
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UINT64_C(0),
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UINT64_C(23068832), // SMULTB
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UINT64_C(23068896), // SMULTT
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UINT64_C(18874528), // SMULWB
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UINT64_C(18874592), // SMULWT
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UINT64_C(117502032), // SMUSD
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UINT64_C(117502064), // SMUSDX
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UINT64_C(0),
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UINT64_C(4165797120), // SRSDA
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UINT64_C(4167894272), // SRSDA_UPD
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UINT64_C(4182574336), // SRSDB
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|
UINT64_C(4184671488), // SRSDB_UPD
|
|
UINT64_C(4174185728), // SRSIA
|
|
UINT64_C(4176282880), // SRSIA_UPD
|
|
UINT64_C(4190962944), // SRSIB
|
|
UINT64_C(4193060096), // SRSIB_UPD
|
|
UINT64_C(111149072), // SSAT
|
|
UINT64_C(111152944), // SSAT16
|
|
UINT64_C(101715792), // SSAX
|
|
UINT64_C(101715824), // SSUB16
|
|
UINT64_C(101715952), // SSUB8
|
|
UINT64_C(4248829952), // STC2L_OFFSET
|
|
UINT64_C(4240441344), // STC2L_OPTION
|
|
UINT64_C(4234149888), // STC2L_POST
|
|
UINT64_C(4250927104), // STC2L_PRE
|
|
UINT64_C(4244635648), // STC2_OFFSET
|
|
UINT64_C(4236247040), // STC2_OPTION
|
|
UINT64_C(4229955584), // STC2_POST
|
|
UINT64_C(4246732800), // STC2_PRE
|
|
UINT64_C(222298112), // STCL_OFFSET
|
|
UINT64_C(213909504), // STCL_OPTION
|
|
UINT64_C(207618048), // STCL_POST
|
|
UINT64_C(224395264), // STCL_PRE
|
|
UINT64_C(218103808), // STC_OFFSET
|
|
UINT64_C(209715200), // STC_OPTION
|
|
UINT64_C(203423744), // STC_POST
|
|
UINT64_C(220200960), // STC_PRE
|
|
UINT64_C(25230480), // STL
|
|
UINT64_C(29424784), // STLB
|
|
UINT64_C(25169552), // STLEX
|
|
UINT64_C(29363856), // STLEXB
|
|
UINT64_C(27266704), // STLEXD
|
|
UINT64_C(31461008), // STLEXH
|
|
UINT64_C(31521936), // STLH
|
|
UINT64_C(134217728), // STMDA
|
|
UINT64_C(136314880), // STMDA_UPD
|
|
UINT64_C(150994944), // STMDB
|
|
UINT64_C(153092096), // STMDB_UPD
|
|
UINT64_C(142606336), // STMIA
|
|
UINT64_C(144703488), // STMIA_UPD
|
|
UINT64_C(159383552), // STMIB
|
|
UINT64_C(161480704), // STMIB_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(73400320), // STRBT_POST_IMM
|
|
UINT64_C(106954752), // STRBT_POST_REG
|
|
UINT64_C(71303168), // STRB_POST_IMM
|
|
UINT64_C(104857600), // STRB_POST_REG
|
|
UINT64_C(90177536), // STRB_PRE_IMM
|
|
UINT64_C(123731968), // STRB_PRE_REG
|
|
UINT64_C(88080384), // STRBi12
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(121634816), // STRBrs
|
|
UINT64_C(16777456), // STRD
|
|
UINT64_C(240), // STRD_POST
|
|
UINT64_C(18874608), // STRD_PRE
|
|
UINT64_C(25169808), // STREX
|
|
UINT64_C(29364112), // STREXB
|
|
UINT64_C(27266960), // STREXD
|
|
UINT64_C(31461264), // STREXH
|
|
UINT64_C(16777392), // STRH
|
|
UINT64_C(6291632), // STRHTi
|
|
UINT64_C(2097328), // STRHTr
|
|
UINT64_C(176), // STRH_POST
|
|
UINT64_C(18874544), // STRH_PRE
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(69206016), // STRT_POST_IMM
|
|
UINT64_C(102760448), // STRT_POST_REG
|
|
UINT64_C(67108864), // STR_POST_IMM
|
|
UINT64_C(100663296), // STR_POST_REG
|
|
UINT64_C(85983232), // STR_PRE_IMM
|
|
UINT64_C(119537664), // STR_PRE_REG
|
|
UINT64_C(83886080), // STRi12
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(117440512), // STRrs
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(37748736), // SUBri
|
|
UINT64_C(4194304), // SUBrr
|
|
UINT64_C(4194304), // SUBrsi
|
|
UINT64_C(4194320), // SUBrsr
|
|
UINT64_C(251658240), // SVC
|
|
UINT64_C(16777360), // SWP
|
|
UINT64_C(20971664), // SWPB
|
|
UINT64_C(111149168), // SXTAB
|
|
UINT64_C(109052016), // SXTAB16
|
|
UINT64_C(112197744), // SXTAH
|
|
UINT64_C(112132208), // SXTB
|
|
UINT64_C(110035056), // SXTB16
|
|
UINT64_C(113180784), // SXTH
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(53477376), // TEQri
|
|
UINT64_C(19922944), // TEQrr
|
|
UINT64_C(19922944), // TEQrsi
|
|
UINT64_C(19922960), // TEQrsr
|
|
UINT64_C(0),
|
|
UINT64_C(3892305662), // TRAP
|
|
UINT64_C(3892240112), // TRAPNaCl
|
|
UINT64_C(51380224), // TSTri
|
|
UINT64_C(17825792), // TSTrr
|
|
UINT64_C(17825792), // TSTrsi
|
|
UINT64_C(17825808), // TSTrsr
|
|
UINT64_C(105910032), // UADD16
|
|
UINT64_C(105910160), // UADD8
|
|
UINT64_C(105910064), // UASX
|
|
UINT64_C(132120656), // UBFX
|
|
UINT64_C(3891265776), // UDF
|
|
UINT64_C(120647696), // UDIV
|
|
UINT64_C(108007184), // UHADD16
|
|
UINT64_C(108007312), // UHADD8
|
|
UINT64_C(108007216), // UHASX
|
|
UINT64_C(108007248), // UHSAX
|
|
UINT64_C(108007280), // UHSUB16
|
|
UINT64_C(108007408), // UHSUB8
|
|
UINT64_C(4194448), // UMAAL
|
|
UINT64_C(10485904), // UMLAL
|
|
UINT64_C(0),
|
|
UINT64_C(8388752), // UMULL
|
|
UINT64_C(0),
|
|
UINT64_C(106958608), // UQADD16
|
|
UINT64_C(106958736), // UQADD8
|
|
UINT64_C(106958640), // UQASX
|
|
UINT64_C(106958672), // UQSAX
|
|
UINT64_C(106958704), // UQSUB16
|
|
UINT64_C(106958832), // UQSUB8
|
|
UINT64_C(125890576), // USAD8
|
|
UINT64_C(125829136), // USADA8
|
|
UINT64_C(115343376), // USAT
|
|
UINT64_C(115347248), // USAT16
|
|
UINT64_C(105910096), // USAX
|
|
UINT64_C(105910128), // USUB16
|
|
UINT64_C(105910256), // USUB8
|
|
UINT64_C(115343472), // UXTAB
|
|
UINT64_C(113246320), // UXTAB16
|
|
UINT64_C(116392048), // UXTAH
|
|
UINT64_C(116326512), // UXTB
|
|
UINT64_C(114229360), // UXTB16
|
|
UINT64_C(117375088), // UXTH
|
|
UINT64_C(4070573312), // VABALsv2i64
|
|
UINT64_C(4069524736), // VABALsv4i32
|
|
UINT64_C(4068476160), // VABALsv8i16
|
|
UINT64_C(4087350528), // VABALuv2i64
|
|
UINT64_C(4086301952), // VABALuv4i32
|
|
UINT64_C(4085253376), // VABALuv8i16
|
|
UINT64_C(4060088144), // VABAsv16i8
|
|
UINT64_C(4062185232), // VABAsv2i32
|
|
UINT64_C(4061136656), // VABAsv4i16
|
|
UINT64_C(4062185296), // VABAsv4i32
|
|
UINT64_C(4061136720), // VABAsv8i16
|
|
UINT64_C(4060088080), // VABAsv8i8
|
|
UINT64_C(4076865360), // VABAuv16i8
|
|
UINT64_C(4078962448), // VABAuv2i32
|
|
UINT64_C(4077913872), // VABAuv4i16
|
|
UINT64_C(4078962512), // VABAuv4i32
|
|
UINT64_C(4077913936), // VABAuv8i16
|
|
UINT64_C(4076865296), // VABAuv8i8
|
|
UINT64_C(4070573824), // VABDLsv2i64
|
|
UINT64_C(4069525248), // VABDLsv4i32
|
|
UINT64_C(4068476672), // VABDLsv8i16
|
|
UINT64_C(4087351040), // VABDLuv2i64
|
|
UINT64_C(4086302464), // VABDLuv4i32
|
|
UINT64_C(4085253888), // VABDLuv8i16
|
|
UINT64_C(4078963968), // VABDfd
|
|
UINT64_C(4078964032), // VABDfq
|
|
UINT64_C(4080012544), // VABDhd
|
|
UINT64_C(4080012608), // VABDhq
|
|
UINT64_C(4060088128), // VABDsv16i8
|
|
UINT64_C(4062185216), // VABDsv2i32
|
|
UINT64_C(4061136640), // VABDsv4i16
|
|
UINT64_C(4062185280), // VABDsv4i32
|
|
UINT64_C(4061136704), // VABDsv8i16
|
|
UINT64_C(4060088064), // VABDsv8i8
|
|
UINT64_C(4076865344), // VABDuv16i8
|
|
UINT64_C(4078962432), // VABDuv2i32
|
|
UINT64_C(4077913856), // VABDuv4i16
|
|
UINT64_C(4078962496), // VABDuv4i32
|
|
UINT64_C(4077913920), // VABDuv8i16
|
|
UINT64_C(4076865280), // VABDuv8i8
|
|
UINT64_C(246418368), // VABSD
|
|
UINT64_C(246417856), // VABSH
|
|
UINT64_C(246418112), // VABSS
|
|
UINT64_C(4088989440), // VABSfd
|
|
UINT64_C(4088989504), // VABSfq
|
|
UINT64_C(4088727296), // VABShd
|
|
UINT64_C(4088727360), // VABShq
|
|
UINT64_C(4088464192), // VABSv16i8
|
|
UINT64_C(4088988416), // VABSv2i32
|
|
UINT64_C(4088726272), // VABSv4i16
|
|
UINT64_C(4088988480), // VABSv4i32
|
|
UINT64_C(4088726336), // VABSv8i16
|
|
UINT64_C(4088464128), // VABSv8i8
|
|
UINT64_C(4076867088), // VACGEfd
|
|
UINT64_C(4076867152), // VACGEfq
|
|
UINT64_C(4077915664), // VACGEhd
|
|
UINT64_C(4077915728), // VACGEhq
|
|
UINT64_C(4078964240), // VACGTfd
|
|
UINT64_C(4078964304), // VACGTfq
|
|
UINT64_C(4080012816), // VACGThd
|
|
UINT64_C(4080012880), // VACGThq
|
|
UINT64_C(238029568), // VADDD
|
|
UINT64_C(238029056), // VADDH
|
|
UINT64_C(4070573056), // VADDHNv2i32
|
|
UINT64_C(4069524480), // VADDHNv4i16
|
|
UINT64_C(4068475904), // VADDHNv8i8
|
|
UINT64_C(4070572032), // VADDLsv2i64
|
|
UINT64_C(4069523456), // VADDLsv4i32
|
|
UINT64_C(4068474880), // VADDLsv8i16
|
|
UINT64_C(4087349248), // VADDLuv2i64
|
|
UINT64_C(4086300672), // VADDLuv4i32
|
|
UINT64_C(4085252096), // VADDLuv8i16
|
|
UINT64_C(238029312), // VADDS
|
|
UINT64_C(4070572288), // VADDWsv2i64
|
|
UINT64_C(4069523712), // VADDWsv4i32
|
|
UINT64_C(4068475136), // VADDWsv8i16
|
|
UINT64_C(4087349504), // VADDWuv2i64
|
|
UINT64_C(4086300928), // VADDWuv4i32
|
|
UINT64_C(4085252352), // VADDWuv8i16
|
|
UINT64_C(4060089600), // VADDfd
|
|
UINT64_C(4060089664), // VADDfq
|
|
UINT64_C(4061138176), // VADDhd
|
|
UINT64_C(4061138240), // VADDhq
|
|
UINT64_C(4060088384), // VADDv16i8
|
|
UINT64_C(4063234048), // VADDv1i64
|
|
UINT64_C(4062185472), // VADDv2i32
|
|
UINT64_C(4063234112), // VADDv2i64
|
|
UINT64_C(4061136896), // VADDv4i16
|
|
UINT64_C(4062185536), // VADDv4i32
|
|
UINT64_C(4061136960), // VADDv8i16
|
|
UINT64_C(4060088320), // VADDv8i8
|
|
UINT64_C(4060086544), // VANDd
|
|
UINT64_C(4060086608), // VANDq
|
|
UINT64_C(4061135120), // VBICd
|
|
UINT64_C(4068475184), // VBICiv2i32
|
|
UINT64_C(4068477232), // VBICiv4i16
|
|
UINT64_C(4068475248), // VBICiv4i32
|
|
UINT64_C(4068477296), // VBICiv8i16
|
|
UINT64_C(4061135184), // VBICq
|
|
UINT64_C(4080009488), // VBIFd
|
|
UINT64_C(4080009552), // VBIFq
|
|
UINT64_C(4078960912), // VBITd
|
|
UINT64_C(4078960976), // VBITq
|
|
UINT64_C(4077912336), // VBSLd
|
|
UINT64_C(4077912400), // VBSLq
|
|
UINT64_C(4060089856), // VCEQfd
|
|
UINT64_C(4060089920), // VCEQfq
|
|
UINT64_C(4061138432), // VCEQhd
|
|
UINT64_C(4061138496), // VCEQhq
|
|
UINT64_C(4076865616), // VCEQv16i8
|
|
UINT64_C(4078962704), // VCEQv2i32
|
|
UINT64_C(4077914128), // VCEQv4i16
|
|
UINT64_C(4078962768), // VCEQv4i32
|
|
UINT64_C(4077914192), // VCEQv8i16
|
|
UINT64_C(4076865552), // VCEQv8i8
|
|
UINT64_C(4088463680), // VCEQzv16i8
|
|
UINT64_C(4088988928), // VCEQzv2f32
|
|
UINT64_C(4088987904), // VCEQzv2i32
|
|
UINT64_C(4088726784), // VCEQzv4f16
|
|
UINT64_C(4088988992), // VCEQzv4f32
|
|
UINT64_C(4088725760), // VCEQzv4i16
|
|
UINT64_C(4088987968), // VCEQzv4i32
|
|
UINT64_C(4088726848), // VCEQzv8f16
|
|
UINT64_C(4088725824), // VCEQzv8i16
|
|
UINT64_C(4088463616), // VCEQzv8i8
|
|
UINT64_C(4076867072), // VCGEfd
|
|
UINT64_C(4076867136), // VCGEfq
|
|
UINT64_C(4077915648), // VCGEhd
|
|
UINT64_C(4077915712), // VCGEhq
|
|
UINT64_C(4060087120), // VCGEsv16i8
|
|
UINT64_C(4062184208), // VCGEsv2i32
|
|
UINT64_C(4061135632), // VCGEsv4i16
|
|
UINT64_C(4062184272), // VCGEsv4i32
|
|
UINT64_C(4061135696), // VCGEsv8i16
|
|
UINT64_C(4060087056), // VCGEsv8i8
|
|
UINT64_C(4076864336), // VCGEuv16i8
|
|
UINT64_C(4078961424), // VCGEuv2i32
|
|
UINT64_C(4077912848), // VCGEuv4i16
|
|
UINT64_C(4078961488), // VCGEuv4i32
|
|
UINT64_C(4077912912), // VCGEuv8i16
|
|
UINT64_C(4076864272), // VCGEuv8i8
|
|
UINT64_C(4088463552), // VCGEzv16i8
|
|
UINT64_C(4088988800), // VCGEzv2f32
|
|
UINT64_C(4088987776), // VCGEzv2i32
|
|
UINT64_C(4088726656), // VCGEzv4f16
|
|
UINT64_C(4088988864), // VCGEzv4f32
|
|
UINT64_C(4088725632), // VCGEzv4i16
|
|
UINT64_C(4088987840), // VCGEzv4i32
|
|
UINT64_C(4088726720), // VCGEzv8f16
|
|
UINT64_C(4088725696), // VCGEzv8i16
|
|
UINT64_C(4088463488), // VCGEzv8i8
|
|
UINT64_C(4078964224), // VCGTfd
|
|
UINT64_C(4078964288), // VCGTfq
|
|
UINT64_C(4080012800), // VCGThd
|
|
UINT64_C(4080012864), // VCGThq
|
|
UINT64_C(4060087104), // VCGTsv16i8
|
|
UINT64_C(4062184192), // VCGTsv2i32
|
|
UINT64_C(4061135616), // VCGTsv4i16
|
|
UINT64_C(4062184256), // VCGTsv4i32
|
|
UINT64_C(4061135680), // VCGTsv8i16
|
|
UINT64_C(4060087040), // VCGTsv8i8
|
|
UINT64_C(4076864320), // VCGTuv16i8
|
|
UINT64_C(4078961408), // VCGTuv2i32
|
|
UINT64_C(4077912832), // VCGTuv4i16
|
|
UINT64_C(4078961472), // VCGTuv4i32
|
|
UINT64_C(4077912896), // VCGTuv8i16
|
|
UINT64_C(4076864256), // VCGTuv8i8
|
|
UINT64_C(4088463424), // VCGTzv16i8
|
|
UINT64_C(4088988672), // VCGTzv2f32
|
|
UINT64_C(4088987648), // VCGTzv2i32
|
|
UINT64_C(4088726528), // VCGTzv4f16
|
|
UINT64_C(4088988736), // VCGTzv4f32
|
|
UINT64_C(4088725504), // VCGTzv4i16
|
|
UINT64_C(4088987712), // VCGTzv4i32
|
|
UINT64_C(4088726592), // VCGTzv8f16
|
|
UINT64_C(4088725568), // VCGTzv8i16
|
|
UINT64_C(4088463360), // VCGTzv8i8
|
|
UINT64_C(4088463808), // VCLEzv16i8
|
|
UINT64_C(4088989056), // VCLEzv2f32
|
|
UINT64_C(4088988032), // VCLEzv2i32
|
|
UINT64_C(4088726912), // VCLEzv4f16
|
|
UINT64_C(4088989120), // VCLEzv4f32
|
|
UINT64_C(4088725888), // VCLEzv4i16
|
|
UINT64_C(4088988096), // VCLEzv4i32
|
|
UINT64_C(4088726976), // VCLEzv8f16
|
|
UINT64_C(4088725952), // VCLEzv8i16
|
|
UINT64_C(4088463744), // VCLEzv8i8
|
|
UINT64_C(4088398912), // VCLSv16i8
|
|
UINT64_C(4088923136), // VCLSv2i32
|
|
UINT64_C(4088660992), // VCLSv4i16
|
|
UINT64_C(4088923200), // VCLSv4i32
|
|
UINT64_C(4088661056), // VCLSv8i16
|
|
UINT64_C(4088398848), // VCLSv8i8
|
|
UINT64_C(4088463936), // VCLTzv16i8
|
|
UINT64_C(4088989184), // VCLTzv2f32
|
|
UINT64_C(4088988160), // VCLTzv2i32
|
|
UINT64_C(4088727040), // VCLTzv4f16
|
|
UINT64_C(4088989248), // VCLTzv4f32
|
|
UINT64_C(4088726016), // VCLTzv4i16
|
|
UINT64_C(4088988224), // VCLTzv4i32
|
|
UINT64_C(4088727104), // VCLTzv8f16
|
|
UINT64_C(4088726080), // VCLTzv8i16
|
|
UINT64_C(4088463872), // VCLTzv8i8
|
|
UINT64_C(4088399040), // VCLZv16i8
|
|
UINT64_C(4088923264), // VCLZv2i32
|
|
UINT64_C(4088661120), // VCLZv4i16
|
|
UINT64_C(4088923328), // VCLZv4i32
|
|
UINT64_C(4088661184), // VCLZv8i16
|
|
UINT64_C(4088398976), // VCLZv8i8
|
|
UINT64_C(246680384), // VCMPD
|
|
UINT64_C(246680512), // VCMPED
|
|
UINT64_C(246680000), // VCMPEH
|
|
UINT64_C(246680256), // VCMPES
|
|
UINT64_C(246746048), // VCMPEZD
|
|
UINT64_C(246745536), // VCMPEZH
|
|
UINT64_C(246745792), // VCMPEZS
|
|
UINT64_C(246679872), // VCMPH
|
|
UINT64_C(246680128), // VCMPS
|
|
UINT64_C(246745920), // VCMPZD
|
|
UINT64_C(246745408), // VCMPZH
|
|
UINT64_C(246745664), // VCMPZS
|
|
UINT64_C(4088399104), // VCNTd
|
|
UINT64_C(4088399168), // VCNTq
|
|
UINT64_C(4089118720), // VCVTANSDf
|
|
UINT64_C(4088856576), // VCVTANSDh
|
|
UINT64_C(4089118784), // VCVTANSQf
|
|
UINT64_C(4088856640), // VCVTANSQh
|
|
UINT64_C(4089118848), // VCVTANUDf
|
|
UINT64_C(4088856704), // VCVTANUDh
|
|
UINT64_C(4089118912), // VCVTANUQf
|
|
UINT64_C(4088856768), // VCVTANUQh
|
|
UINT64_C(4273736640), // VCVTASD
|
|
UINT64_C(4273736128), // VCVTASH
|
|
UINT64_C(4273736384), // VCVTASS
|
|
UINT64_C(4273736512), // VCVTAUD
|
|
UINT64_C(4273736000), // VCVTAUH
|
|
UINT64_C(4273736256), // VCVTAUS
|
|
UINT64_C(246614848), // VCVTBDH
|
|
UINT64_C(246549312), // VCVTBHD
|
|
UINT64_C(246549056), // VCVTBHS
|
|
UINT64_C(246614592), // VCVTBSH
|
|
UINT64_C(246876864), // VCVTDS
|
|
UINT64_C(4089119488), // VCVTMNSDf
|
|
UINT64_C(4088857344), // VCVTMNSDh
|
|
UINT64_C(4089119552), // VCVTMNSQf
|
|
UINT64_C(4088857408), // VCVTMNSQh
|
|
UINT64_C(4089119616), // VCVTMNUDf
|
|
UINT64_C(4088857472), // VCVTMNUDh
|
|
UINT64_C(4089119680), // VCVTMNUQf
|
|
UINT64_C(4088857536), // VCVTMNUQh
|
|
UINT64_C(4273933248), // VCVTMSD
|
|
UINT64_C(4273932736), // VCVTMSH
|
|
UINT64_C(4273932992), // VCVTMSS
|
|
UINT64_C(4273933120), // VCVTMUD
|
|
UINT64_C(4273932608), // VCVTMUH
|
|
UINT64_C(4273932864), // VCVTMUS
|
|
UINT64_C(4089118976), // VCVTNNSDf
|
|
UINT64_C(4088856832), // VCVTNNSDh
|
|
UINT64_C(4089119040), // VCVTNNSQf
|
|
UINT64_C(4088856896), // VCVTNNSQh
|
|
UINT64_C(4089119104), // VCVTNNUDf
|
|
UINT64_C(4088856960), // VCVTNNUDh
|
|
UINT64_C(4089119168), // VCVTNNUQf
|
|
UINT64_C(4088857024), // VCVTNNUQh
|
|
UINT64_C(4273802176), // VCVTNSD
|
|
UINT64_C(4273801664), // VCVTNSH
|
|
UINT64_C(4273801920), // VCVTNSS
|
|
UINT64_C(4273802048), // VCVTNUD
|
|
UINT64_C(4273801536), // VCVTNUH
|
|
UINT64_C(4273801792), // VCVTNUS
|
|
UINT64_C(4089119232), // VCVTPNSDf
|
|
UINT64_C(4088857088), // VCVTPNSDh
|
|
UINT64_C(4089119296), // VCVTPNSQf
|
|
UINT64_C(4088857152), // VCVTPNSQh
|
|
UINT64_C(4089119360), // VCVTPNUDf
|
|
UINT64_C(4088857216), // VCVTPNUDh
|
|
UINT64_C(4089119424), // VCVTPNUQf
|
|
UINT64_C(4088857280), // VCVTPNUQh
|
|
UINT64_C(4273867712), // VCVTPSD
|
|
UINT64_C(4273867200), // VCVTPSH
|
|
UINT64_C(4273867456), // VCVTPSS
|
|
UINT64_C(4273867584), // VCVTPUD
|
|
UINT64_C(4273867072), // VCVTPUH
|
|
UINT64_C(4273867328), // VCVTPUS
|
|
UINT64_C(246877120), // VCVTSD
|
|
UINT64_C(246614976), // VCVTTDH
|
|
UINT64_C(246549440), // VCVTTHD
|
|
UINT64_C(246549184), // VCVTTHS
|
|
UINT64_C(246614720), // VCVTTSH
|
|
UINT64_C(4088792576), // VCVTf2h
|
|
UINT64_C(4089120512), // VCVTf2sd
|
|
UINT64_C(4089120576), // VCVTf2sq
|
|
UINT64_C(4089120640), // VCVTf2ud
|
|
UINT64_C(4089120704), // VCVTf2uq
|
|
UINT64_C(4068478736), // VCVTf2xsd
|
|
UINT64_C(4068478800), // VCVTf2xsq
|
|
UINT64_C(4085255952), // VCVTf2xud
|
|
UINT64_C(4085256016), // VCVTf2xuq
|
|
UINT64_C(4088792832), // VCVTh2f
|
|
UINT64_C(4088858368), // VCVTh2sd
|
|
UINT64_C(4088858432), // VCVTh2sq
|
|
UINT64_C(4088858496), // VCVTh2ud
|
|
UINT64_C(4088858560), // VCVTh2uq
|
|
UINT64_C(4068478224), // VCVTh2xsd
|
|
UINT64_C(4068478288), // VCVTh2xsq
|
|
UINT64_C(4085255440), // VCVTh2xud
|
|
UINT64_C(4085255504), // VCVTh2xuq
|
|
UINT64_C(4089120256), // VCVTs2fd
|
|
UINT64_C(4089120320), // VCVTs2fq
|
|
UINT64_C(4088858112), // VCVTs2hd
|
|
UINT64_C(4088858176), // VCVTs2hq
|
|
UINT64_C(4089120384), // VCVTu2fd
|
|
UINT64_C(4089120448), // VCVTu2fq
|
|
UINT64_C(4088858240), // VCVTu2hd
|
|
UINT64_C(4088858304), // VCVTu2hq
|
|
UINT64_C(4068478480), // VCVTxs2fd
|
|
UINT64_C(4068478544), // VCVTxs2fq
|
|
UINT64_C(4068477968), // VCVTxs2hd
|
|
UINT64_C(4068478032), // VCVTxs2hq
|
|
UINT64_C(4085255696), // VCVTxu2fd
|
|
UINT64_C(4085255760), // VCVTxu2fq
|
|
UINT64_C(4085255184), // VCVTxu2hd
|
|
UINT64_C(4085255248), // VCVTxu2hq
|
|
UINT64_C(243272448), // VDIVD
|
|
UINT64_C(243271936), // VDIVH
|
|
UINT64_C(243272192), // VDIVS
|
|
UINT64_C(243272496), // VDUP16d
|
|
UINT64_C(245369648), // VDUP16q
|
|
UINT64_C(243272464), // VDUP32d
|
|
UINT64_C(245369616), // VDUP32q
|
|
UINT64_C(247466768), // VDUP8d
|
|
UINT64_C(249563920), // VDUP8q
|
|
UINT64_C(4088531968), // VDUPLN16d
|
|
UINT64_C(4088532032), // VDUPLN16q
|
|
UINT64_C(4088663040), // VDUPLN32d
|
|
UINT64_C(4088663104), // VDUPLN32q
|
|
UINT64_C(4088466432), // VDUPLN8d
|
|
UINT64_C(4088466496), // VDUPLN8q
|
|
UINT64_C(4076863760), // VEORd
|
|
UINT64_C(4076863824), // VEORq
|
|
UINT64_C(4071620608), // VEXTd16
|
|
UINT64_C(4071620608), // VEXTd32
|
|
UINT64_C(4071620608), // VEXTd8
|
|
UINT64_C(4071620672), // VEXTq16
|
|
UINT64_C(4071620672), // VEXTq32
|
|
UINT64_C(4071620672), // VEXTq64
|
|
UINT64_C(4071620672), // VEXTq8
|
|
UINT64_C(245369600), // VFMAD
|
|
UINT64_C(245369088), // VFMAH
|
|
UINT64_C(245369344), // VFMAS
|
|
UINT64_C(4060089360), // VFMAfd
|
|
UINT64_C(4060089424), // VFMAfq
|
|
UINT64_C(4061137936), // VFMAhd
|
|
UINT64_C(4061138000), // VFMAhq
|
|
UINT64_C(245369664), // VFMSD
|
|
UINT64_C(245369152), // VFMSH
|
|
UINT64_C(245369408), // VFMSS
|
|
UINT64_C(4062186512), // VFMSfd
|
|
UINT64_C(4062186576), // VFMSfq
|
|
UINT64_C(4063235088), // VFMShd
|
|
UINT64_C(4063235152), // VFMShq
|
|
UINT64_C(244321088), // VFNMAD
|
|
UINT64_C(244320576), // VFNMAH
|
|
UINT64_C(244320832), // VFNMAS
|
|
UINT64_C(244321024), // VFNMSD
|
|
UINT64_C(244320512), // VFNMSH
|
|
UINT64_C(244320768), // VFNMSS
|
|
UINT64_C(235932432), // VGETLNi32
|
|
UINT64_C(235932464), // VGETLNs16
|
|
UINT64_C(240126736), // VGETLNs8
|
|
UINT64_C(244321072), // VGETLNu16
|
|
UINT64_C(248515344), // VGETLNu8
|
|
UINT64_C(4060086336), // VHADDsv16i8
|
|
UINT64_C(4062183424), // VHADDsv2i32
|
|
UINT64_C(4061134848), // VHADDsv4i16
|
|
UINT64_C(4062183488), // VHADDsv4i32
|
|
UINT64_C(4061134912), // VHADDsv8i16
|
|
UINT64_C(4060086272), // VHADDsv8i8
|
|
UINT64_C(4076863552), // VHADDuv16i8
|
|
UINT64_C(4078960640), // VHADDuv2i32
|
|
UINT64_C(4077912064), // VHADDuv4i16
|
|
UINT64_C(4078960704), // VHADDuv4i32
|
|
UINT64_C(4077912128), // VHADDuv8i16
|
|
UINT64_C(4076863488), // VHADDuv8i8
|
|
UINT64_C(4060086848), // VHSUBsv16i8
|
|
UINT64_C(4062183936), // VHSUBsv2i32
|
|
UINT64_C(4061135360), // VHSUBsv4i16
|
|
UINT64_C(4062184000), // VHSUBsv4i32
|
|
UINT64_C(4061135424), // VHSUBsv8i16
|
|
UINT64_C(4060086784), // VHSUBsv8i8
|
|
UINT64_C(4076864064), // VHSUBuv16i8
|
|
UINT64_C(4078961152), // VHSUBuv2i32
|
|
UINT64_C(4077912576), // VHSUBuv4i16
|
|
UINT64_C(4078961216), // VHSUBuv4i32
|
|
UINT64_C(4077912640), // VHSUBuv8i16
|
|
UINT64_C(4076864000), // VHSUBuv8i8
|
|
UINT64_C(4272949952), // VINSH
|
|
UINT64_C(4104129615), // VLD1DUPd16
|
|
UINT64_C(4104129613), // VLD1DUPd16wb_fixed
|
|
UINT64_C(4104129600), // VLD1DUPd16wb_register
|
|
UINT64_C(4104129679), // VLD1DUPd32
|
|
UINT64_C(4104129677), // VLD1DUPd32wb_fixed
|
|
UINT64_C(4104129664), // VLD1DUPd32wb_register
|
|
UINT64_C(4104129551), // VLD1DUPd8
|
|
UINT64_C(4104129549), // VLD1DUPd8wb_fixed
|
|
UINT64_C(4104129536), // VLD1DUPd8wb_register
|
|
UINT64_C(4104129647), // VLD1DUPq16
|
|
UINT64_C(4104129645), // VLD1DUPq16wb_fixed
|
|
UINT64_C(4104129632), // VLD1DUPq16wb_register
|
|
UINT64_C(4104129711), // VLD1DUPq32
|
|
UINT64_C(4104129709), // VLD1DUPq32wb_fixed
|
|
UINT64_C(4104129696), // VLD1DUPq32wb_register
|
|
UINT64_C(4104129583), // VLD1DUPq8
|
|
UINT64_C(4104129581), // VLD1DUPq8wb_fixed
|
|
UINT64_C(4104129568), // VLD1DUPq8wb_register
|
|
UINT64_C(4104127503), // VLD1LNd16
|
|
UINT64_C(4104127488), // VLD1LNd16_UPD
|
|
UINT64_C(4104128527), // VLD1LNd32
|
|
UINT64_C(4104128512), // VLD1LNd32_UPD
|
|
UINT64_C(4104126479), // VLD1LNd8
|
|
UINT64_C(4104126464), // VLD1LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0), // VLD1LNq16Pseudo
|
|
UINT64_C(0), // VLD1LNq16Pseudo_UPD
|
|
UINT64_C(0), // VLD1LNq32Pseudo
|
|
UINT64_C(0), // VLD1LNq32Pseudo_UPD
|
|
UINT64_C(0), // VLD1LNq8Pseudo
|
|
UINT64_C(0), // VLD1LNq8Pseudo_UPD
|
|
UINT64_C(4095739727), // VLD1d16
|
|
UINT64_C(4095738447), // VLD1d16Q
|
|
UINT64_C(4095738445), // VLD1d16Qwb_fixed
|
|
UINT64_C(4095738432), // VLD1d16Qwb_register
|
|
UINT64_C(4095739471), // VLD1d16T
|
|
UINT64_C(4095739469), // VLD1d16Twb_fixed
|
|
UINT64_C(4095739456), // VLD1d16Twb_register
|
|
UINT64_C(4095739725), // VLD1d16wb_fixed
|
|
UINT64_C(4095739712), // VLD1d16wb_register
|
|
UINT64_C(4095739791), // VLD1d32
|
|
UINT64_C(4095738511), // VLD1d32Q
|
|
UINT64_C(4095738509), // VLD1d32Qwb_fixed
|
|
UINT64_C(4095738496), // VLD1d32Qwb_register
|
|
UINT64_C(4095739535), // VLD1d32T
|
|
UINT64_C(4095739533), // VLD1d32Twb_fixed
|
|
UINT64_C(4095739520), // VLD1d32Twb_register
|
|
UINT64_C(4095739789), // VLD1d32wb_fixed
|
|
UINT64_C(4095739776), // VLD1d32wb_register
|
|
UINT64_C(4095739855), // VLD1d64
|
|
UINT64_C(4095738575), // VLD1d64Q
|
|
UINT64_C(0), // VLD1d64QPseudo
|
|
UINT64_C(0), // VLD1d64QPseudoWB_fixed
|
|
UINT64_C(0), // VLD1d64QPseudoWB_register
|
|
UINT64_C(4095738573), // VLD1d64Qwb_fixed
|
|
UINT64_C(4095738560), // VLD1d64Qwb_register
|
|
UINT64_C(4095739599), // VLD1d64T
|
|
UINT64_C(0), // VLD1d64TPseudo
|
|
UINT64_C(0), // VLD1d64TPseudoWB_fixed
|
|
UINT64_C(0), // VLD1d64TPseudoWB_register
|
|
UINT64_C(4095739597), // VLD1d64Twb_fixed
|
|
UINT64_C(4095739584), // VLD1d64Twb_register
|
|
UINT64_C(4095739853), // VLD1d64wb_fixed
|
|
UINT64_C(4095739840), // VLD1d64wb_register
|
|
UINT64_C(4095739663), // VLD1d8
|
|
UINT64_C(4095738383), // VLD1d8Q
|
|
UINT64_C(4095738381), // VLD1d8Qwb_fixed
|
|
UINT64_C(4095738368), // VLD1d8Qwb_register
|
|
UINT64_C(4095739407), // VLD1d8T
|
|
UINT64_C(4095739405), // VLD1d8Twb_fixed
|
|
UINT64_C(4095739392), // VLD1d8Twb_register
|
|
UINT64_C(4095739661), // VLD1d8wb_fixed
|
|
UINT64_C(4095739648), // VLD1d8wb_register
|
|
UINT64_C(4095740495), // VLD1q16
|
|
UINT64_C(4095740493), // VLD1q16wb_fixed
|
|
UINT64_C(4095740480), // VLD1q16wb_register
|
|
UINT64_C(4095740559), // VLD1q32
|
|
UINT64_C(4095740557), // VLD1q32wb_fixed
|
|
UINT64_C(4095740544), // VLD1q32wb_register
|
|
UINT64_C(4095740623), // VLD1q64
|
|
UINT64_C(4095740621), // VLD1q64wb_fixed
|
|
UINT64_C(4095740608), // VLD1q64wb_register
|
|
UINT64_C(4095740431), // VLD1q8
|
|
UINT64_C(4095740429), // VLD1q8wb_fixed
|
|
UINT64_C(4095740416), // VLD1q8wb_register
|
|
UINT64_C(4104129871), // VLD2DUPd16
|
|
UINT64_C(4104129869), // VLD2DUPd16wb_fixed
|
|
UINT64_C(4104129856), // VLD2DUPd16wb_register
|
|
UINT64_C(4104129903), // VLD2DUPd16x2
|
|
UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed
|
|
UINT64_C(4104129888), // VLD2DUPd16x2wb_register
|
|
UINT64_C(4104129935), // VLD2DUPd32
|
|
UINT64_C(4104129933), // VLD2DUPd32wb_fixed
|
|
UINT64_C(4104129920), // VLD2DUPd32wb_register
|
|
UINT64_C(4104129967), // VLD2DUPd32x2
|
|
UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed
|
|
UINT64_C(4104129952), // VLD2DUPd32x2wb_register
|
|
UINT64_C(4104129807), // VLD2DUPd8
|
|
UINT64_C(4104129805), // VLD2DUPd8wb_fixed
|
|
UINT64_C(4104129792), // VLD2DUPd8wb_register
|
|
UINT64_C(4104129839), // VLD2DUPd8x2
|
|
UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed
|
|
UINT64_C(4104129824), // VLD2DUPd8x2wb_register
|
|
UINT64_C(4104127759), // VLD2LNd16
|
|
UINT64_C(0), // VLD2LNd16Pseudo
|
|
UINT64_C(0), // VLD2LNd16Pseudo_UPD
|
|
UINT64_C(4104127744), // VLD2LNd16_UPD
|
|
UINT64_C(4104128783), // VLD2LNd32
|
|
UINT64_C(0), // VLD2LNd32Pseudo
|
|
UINT64_C(0), // VLD2LNd32Pseudo_UPD
|
|
UINT64_C(4104128768), // VLD2LNd32_UPD
|
|
UINT64_C(4104126735), // VLD2LNd8
|
|
UINT64_C(0), // VLD2LNd8Pseudo
|
|
UINT64_C(0), // VLD2LNd8Pseudo_UPD
|
|
UINT64_C(4104126720), // VLD2LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104127791), // VLD2LNq16
|
|
UINT64_C(0), // VLD2LNq16Pseudo
|
|
UINT64_C(0), // VLD2LNq16Pseudo_UPD
|
|
UINT64_C(4104127776), // VLD2LNq16_UPD
|
|
UINT64_C(4104128847), // VLD2LNq32
|
|
UINT64_C(0), // VLD2LNq32Pseudo
|
|
UINT64_C(0), // VLD2LNq32Pseudo_UPD
|
|
UINT64_C(4104128832), // VLD2LNq32_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4095740239), // VLD2b16
|
|
UINT64_C(4095740237), // VLD2b16wb_fixed
|
|
UINT64_C(4095740224), // VLD2b16wb_register
|
|
UINT64_C(4095740303), // VLD2b32
|
|
UINT64_C(4095740301), // VLD2b32wb_fixed
|
|
UINT64_C(4095740288), // VLD2b32wb_register
|
|
UINT64_C(4095740175), // VLD2b8
|
|
UINT64_C(4095740173), // VLD2b8wb_fixed
|
|
UINT64_C(4095740160), // VLD2b8wb_register
|
|
UINT64_C(4095739983), // VLD2d16
|
|
UINT64_C(4095739981), // VLD2d16wb_fixed
|
|
UINT64_C(4095739968), // VLD2d16wb_register
|
|
UINT64_C(4095740047), // VLD2d32
|
|
UINT64_C(4095740045), // VLD2d32wb_fixed
|
|
UINT64_C(4095740032), // VLD2d32wb_register
|
|
UINT64_C(4095739919), // VLD2d8
|
|
UINT64_C(4095739917), // VLD2d8wb_fixed
|
|
UINT64_C(4095739904), // VLD2d8wb_register
|
|
UINT64_C(4095738703), // VLD2q16
|
|
UINT64_C(0), // VLD2q16Pseudo
|
|
UINT64_C(0), // VLD2q16PseudoWB_fixed
|
|
UINT64_C(0), // VLD2q16PseudoWB_register
|
|
UINT64_C(4095738701), // VLD2q16wb_fixed
|
|
UINT64_C(4095738688), // VLD2q16wb_register
|
|
UINT64_C(4095738767), // VLD2q32
|
|
UINT64_C(0), // VLD2q32Pseudo
|
|
UINT64_C(0), // VLD2q32PseudoWB_fixed
|
|
UINT64_C(0), // VLD2q32PseudoWB_register
|
|
UINT64_C(4095738765), // VLD2q32wb_fixed
|
|
UINT64_C(4095738752), // VLD2q32wb_register
|
|
UINT64_C(4095738639), // VLD2q8
|
|
UINT64_C(0), // VLD2q8Pseudo
|
|
UINT64_C(0), // VLD2q8PseudoWB_fixed
|
|
UINT64_C(0), // VLD2q8PseudoWB_register
|
|
UINT64_C(4095738637), // VLD2q8wb_fixed
|
|
UINT64_C(4095738624), // VLD2q8wb_register
|
|
UINT64_C(4104130127), // VLD3DUPd16
|
|
UINT64_C(0), // VLD3DUPd16Pseudo
|
|
UINT64_C(0), // VLD3DUPd16Pseudo_UPD
|
|
UINT64_C(4104130112), // VLD3DUPd16_UPD
|
|
UINT64_C(4104130191), // VLD3DUPd32
|
|
UINT64_C(0), // VLD3DUPd32Pseudo
|
|
UINT64_C(0), // VLD3DUPd32Pseudo_UPD
|
|
UINT64_C(4104130176), // VLD3DUPd32_UPD
|
|
UINT64_C(4104130063), // VLD3DUPd8
|
|
UINT64_C(0), // VLD3DUPd8Pseudo
|
|
UINT64_C(0), // VLD3DUPd8Pseudo_UPD
|
|
UINT64_C(4104130048), // VLD3DUPd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104130159), // VLD3DUPq16
|
|
UINT64_C(4104130144), // VLD3DUPq16_UPD
|
|
UINT64_C(4104130223), // VLD3DUPq32
|
|
UINT64_C(4104130208), // VLD3DUPq32_UPD
|
|
UINT64_C(4104130095), // VLD3DUPq8
|
|
UINT64_C(4104130080), // VLD3DUPq8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104128015), // VLD3LNd16
|
|
UINT64_C(0), // VLD3LNd16Pseudo
|
|
UINT64_C(0), // VLD3LNd16Pseudo_UPD
|
|
UINT64_C(4104128000), // VLD3LNd16_UPD
|
|
UINT64_C(4104129039), // VLD3LNd32
|
|
UINT64_C(0), // VLD3LNd32Pseudo
|
|
UINT64_C(0), // VLD3LNd32Pseudo_UPD
|
|
UINT64_C(4104129024), // VLD3LNd32_UPD
|
|
UINT64_C(4104126991), // VLD3LNd8
|
|
UINT64_C(0), // VLD3LNd8Pseudo
|
|
UINT64_C(0), // VLD3LNd8Pseudo_UPD
|
|
UINT64_C(4104126976), // VLD3LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104128047), // VLD3LNq16
|
|
UINT64_C(0), // VLD3LNq16Pseudo
|
|
UINT64_C(0), // VLD3LNq16Pseudo_UPD
|
|
UINT64_C(4104128032), // VLD3LNq16_UPD
|
|
UINT64_C(4104129103), // VLD3LNq32
|
|
UINT64_C(0), // VLD3LNq32Pseudo
|
|
UINT64_C(0), // VLD3LNq32Pseudo_UPD
|
|
UINT64_C(4104129088), // VLD3LNq32_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4095738959), // VLD3d16
|
|
UINT64_C(0), // VLD3d16Pseudo
|
|
UINT64_C(0), // VLD3d16Pseudo_UPD
|
|
UINT64_C(4095738944), // VLD3d16_UPD
|
|
UINT64_C(4095739023), // VLD3d32
|
|
UINT64_C(0), // VLD3d32Pseudo
|
|
UINT64_C(0), // VLD3d32Pseudo_UPD
|
|
UINT64_C(4095739008), // VLD3d32_UPD
|
|
UINT64_C(4095738895), // VLD3d8
|
|
UINT64_C(0), // VLD3d8Pseudo
|
|
UINT64_C(0), // VLD3d8Pseudo_UPD
|
|
UINT64_C(4095738880), // VLD3d8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4095739215), // VLD3q16
|
|
UINT64_C(0), // VLD3q16Pseudo_UPD
|
|
UINT64_C(4095739200), // VLD3q16_UPD
|
|
UINT64_C(0), // VLD3q16oddPseudo
|
|
UINT64_C(0), // VLD3q16oddPseudo_UPD
|
|
UINT64_C(4095739279), // VLD3q32
|
|
UINT64_C(0), // VLD3q32Pseudo_UPD
|
|
UINT64_C(4095739264), // VLD3q32_UPD
|
|
UINT64_C(0), // VLD3q32oddPseudo
|
|
UINT64_C(0), // VLD3q32oddPseudo_UPD
|
|
UINT64_C(4095739151), // VLD3q8
|
|
UINT64_C(0), // VLD3q8Pseudo_UPD
|
|
UINT64_C(4095739136), // VLD3q8_UPD
|
|
UINT64_C(0), // VLD3q8oddPseudo
|
|
UINT64_C(0), // VLD3q8oddPseudo_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104130383), // VLD4DUPd16
|
|
UINT64_C(0), // VLD4DUPd16Pseudo
|
|
UINT64_C(0), // VLD4DUPd16Pseudo_UPD
|
|
UINT64_C(4104130368), // VLD4DUPd16_UPD
|
|
UINT64_C(4104130447), // VLD4DUPd32
|
|
UINT64_C(0), // VLD4DUPd32Pseudo
|
|
UINT64_C(0), // VLD4DUPd32Pseudo_UPD
|
|
UINT64_C(4104130432), // VLD4DUPd32_UPD
|
|
UINT64_C(4104130319), // VLD4DUPd8
|
|
UINT64_C(0), // VLD4DUPd8Pseudo
|
|
UINT64_C(0), // VLD4DUPd8Pseudo_UPD
|
|
UINT64_C(4104130304), // VLD4DUPd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104130415), // VLD4DUPq16
|
|
UINT64_C(4104130400), // VLD4DUPq16_UPD
|
|
UINT64_C(4104130479), // VLD4DUPq32
|
|
UINT64_C(4104130464), // VLD4DUPq32_UPD
|
|
UINT64_C(4104130351), // VLD4DUPq8
|
|
UINT64_C(4104130336), // VLD4DUPq8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104128271), // VLD4LNd16
|
|
UINT64_C(0), // VLD4LNd16Pseudo
|
|
UINT64_C(0), // VLD4LNd16Pseudo_UPD
|
|
UINT64_C(4104128256), // VLD4LNd16_UPD
|
|
UINT64_C(4104129295), // VLD4LNd32
|
|
UINT64_C(0), // VLD4LNd32Pseudo
|
|
UINT64_C(0), // VLD4LNd32Pseudo_UPD
|
|
UINT64_C(4104129280), // VLD4LNd32_UPD
|
|
UINT64_C(4104127247), // VLD4LNd8
|
|
UINT64_C(0), // VLD4LNd8Pseudo
|
|
UINT64_C(0), // VLD4LNd8Pseudo_UPD
|
|
UINT64_C(4104127232), // VLD4LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4104128303), // VLD4LNq16
|
|
UINT64_C(0), // VLD4LNq16Pseudo
|
|
UINT64_C(0), // VLD4LNq16Pseudo_UPD
|
|
UINT64_C(4104128288), // VLD4LNq16_UPD
|
|
UINT64_C(4104129359), // VLD4LNq32
|
|
UINT64_C(0), // VLD4LNq32Pseudo
|
|
UINT64_C(0), // VLD4LNq32Pseudo_UPD
|
|
UINT64_C(4104129344), // VLD4LNq32_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4095737935), // VLD4d16
|
|
UINT64_C(0), // VLD4d16Pseudo
|
|
UINT64_C(0), // VLD4d16Pseudo_UPD
|
|
UINT64_C(4095737920), // VLD4d16_UPD
|
|
UINT64_C(4095737999), // VLD4d32
|
|
UINT64_C(0), // VLD4d32Pseudo
|
|
UINT64_C(0), // VLD4d32Pseudo_UPD
|
|
UINT64_C(4095737984), // VLD4d32_UPD
|
|
UINT64_C(4095737871), // VLD4d8
|
|
UINT64_C(0), // VLD4d8Pseudo
|
|
UINT64_C(0), // VLD4d8Pseudo_UPD
|
|
UINT64_C(4095737856), // VLD4d8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4095738191), // VLD4q16
|
|
UINT64_C(0), // VLD4q16Pseudo_UPD
|
|
UINT64_C(4095738176), // VLD4q16_UPD
|
|
UINT64_C(0), // VLD4q16oddPseudo
|
|
UINT64_C(0), // VLD4q16oddPseudo_UPD
|
|
UINT64_C(4095738255), // VLD4q32
|
|
UINT64_C(0), // VLD4q32Pseudo_UPD
|
|
UINT64_C(4095738240), // VLD4q32_UPD
|
|
UINT64_C(0), // VLD4q32oddPseudo
|
|
UINT64_C(0), // VLD4q32oddPseudo_UPD
|
|
UINT64_C(4095738127), // VLD4q8
|
|
UINT64_C(0), // VLD4q8Pseudo_UPD
|
|
UINT64_C(4095738112), // VLD4q8_UPD
|
|
UINT64_C(0), // VLD4q8oddPseudo
|
|
UINT64_C(0), // VLD4q8oddPseudo_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(221252352), // VLDMDDB_UPD
|
|
UINT64_C(210766592), // VLDMDIA
|
|
UINT64_C(212863744), // VLDMDIA_UPD
|
|
UINT64_C(0), // VLDMQIA
|
|
UINT64_C(221252096), // VLDMSDB_UPD
|
|
UINT64_C(210766336), // VLDMSIA
|
|
UINT64_C(212863488), // VLDMSIA_UPD
|
|
UINT64_C(219155200), // VLDRD
|
|
UINT64_C(219154688), // VLDRH
|
|
UINT64_C(219154944), // VLDRS
|
|
UINT64_C(204474880), // VLLDM
|
|
UINT64_C(203426304), // VLSTM
|
|
UINT64_C(4269804288), // VMAXNMD
|
|
UINT64_C(4269803776), // VMAXNMH
|
|
UINT64_C(4076867344), // VMAXNMNDf
|
|
UINT64_C(4077915920), // VMAXNMNDh
|
|
UINT64_C(4076867408), // VMAXNMNQf
|
|
UINT64_C(4077915984), // VMAXNMNQh
|
|
UINT64_C(4269804032), // VMAXNMS
|
|
UINT64_C(4060090112), // VMAXfd
|
|
UINT64_C(4060090176), // VMAXfq
|
|
UINT64_C(4061138688), // VMAXhd
|
|
UINT64_C(4061138752), // VMAXhq
|
|
UINT64_C(4060087872), // VMAXsv16i8
|
|
UINT64_C(4062184960), // VMAXsv2i32
|
|
UINT64_C(4061136384), // VMAXsv4i16
|
|
UINT64_C(4062185024), // VMAXsv4i32
|
|
UINT64_C(4061136448), // VMAXsv8i16
|
|
UINT64_C(4060087808), // VMAXsv8i8
|
|
UINT64_C(4076865088), // VMAXuv16i8
|
|
UINT64_C(4078962176), // VMAXuv2i32
|
|
UINT64_C(4077913600), // VMAXuv4i16
|
|
UINT64_C(4078962240), // VMAXuv4i32
|
|
UINT64_C(4077913664), // VMAXuv8i16
|
|
UINT64_C(4076865024), // VMAXuv8i8
|
|
UINT64_C(4269804352), // VMINNMD
|
|
UINT64_C(4269803840), // VMINNMH
|
|
UINT64_C(4078964496), // VMINNMNDf
|
|
UINT64_C(4080013072), // VMINNMNDh
|
|
UINT64_C(4078964560), // VMINNMNQf
|
|
UINT64_C(4080013136), // VMINNMNQh
|
|
UINT64_C(4269804096), // VMINNMS
|
|
UINT64_C(4062187264), // VMINfd
|
|
UINT64_C(4062187328), // VMINfq
|
|
UINT64_C(4063235840), // VMINhd
|
|
UINT64_C(4063235904), // VMINhq
|
|
UINT64_C(4060087888), // VMINsv16i8
|
|
UINT64_C(4062184976), // VMINsv2i32
|
|
UINT64_C(4061136400), // VMINsv4i16
|
|
UINT64_C(4062185040), // VMINsv4i32
|
|
UINT64_C(4061136464), // VMINsv8i16
|
|
UINT64_C(4060087824), // VMINsv8i8
|
|
UINT64_C(4076865104), // VMINuv16i8
|
|
UINT64_C(4078962192), // VMINuv2i32
|
|
UINT64_C(4077913616), // VMINuv4i16
|
|
UINT64_C(4078962256), // VMINuv4i32
|
|
UINT64_C(4077913680), // VMINuv8i16
|
|
UINT64_C(4076865040), // VMINuv8i8
|
|
UINT64_C(234883840), // VMLAD
|
|
UINT64_C(234883328), // VMLAH
|
|
UINT64_C(4070572608), // VMLALslsv2i32
|
|
UINT64_C(4069524032), // VMLALslsv4i16
|
|
UINT64_C(4087349824), // VMLALsluv2i32
|
|
UINT64_C(4086301248), // VMLALsluv4i16
|
|
UINT64_C(4070574080), // VMLALsv2i64
|
|
UINT64_C(4069525504), // VMLALsv4i32
|
|
UINT64_C(4068476928), // VMLALsv8i16
|
|
UINT64_C(4087351296), // VMLALuv2i64
|
|
UINT64_C(4086302720), // VMLALuv4i32
|
|
UINT64_C(4085254144), // VMLALuv8i16
|
|
UINT64_C(234883584), // VMLAS
|
|
UINT64_C(4060089616), // VMLAfd
|
|
UINT64_C(4060089680), // VMLAfq
|
|
UINT64_C(4061138192), // VMLAhd
|
|
UINT64_C(4061138256), // VMLAhq
|
|
UINT64_C(4070572352), // VMLAslfd
|
|
UINT64_C(4087349568), // VMLAslfq
|
|
UINT64_C(4069523776), // VMLAslhd
|
|
UINT64_C(4086300992), // VMLAslhq
|
|
UINT64_C(4070572096), // VMLAslv2i32
|
|
UINT64_C(4069523520), // VMLAslv4i16
|
|
UINT64_C(4087349312), // VMLAslv4i32
|
|
UINT64_C(4086300736), // VMLAslv8i16
|
|
UINT64_C(4060088640), // VMLAv16i8
|
|
UINT64_C(4062185728), // VMLAv2i32
|
|
UINT64_C(4061137152), // VMLAv4i16
|
|
UINT64_C(4062185792), // VMLAv4i32
|
|
UINT64_C(4061137216), // VMLAv8i16
|
|
UINT64_C(4060088576), // VMLAv8i8
|
|
UINT64_C(234883904), // VMLSD
|
|
UINT64_C(234883392), // VMLSH
|
|
UINT64_C(4070573632), // VMLSLslsv2i32
|
|
UINT64_C(4069525056), // VMLSLslsv4i16
|
|
UINT64_C(4087350848), // VMLSLsluv2i32
|
|
UINT64_C(4086302272), // VMLSLsluv4i16
|
|
UINT64_C(4070574592), // VMLSLsv2i64
|
|
UINT64_C(4069526016), // VMLSLsv4i32
|
|
UINT64_C(4068477440), // VMLSLsv8i16
|
|
UINT64_C(4087351808), // VMLSLuv2i64
|
|
UINT64_C(4086303232), // VMLSLuv4i32
|
|
UINT64_C(4085254656), // VMLSLuv8i16
|
|
UINT64_C(234883648), // VMLSS
|
|
UINT64_C(4062186768), // VMLSfd
|
|
UINT64_C(4062186832), // VMLSfq
|
|
UINT64_C(4063235344), // VMLShd
|
|
UINT64_C(4063235408), // VMLShq
|
|
UINT64_C(4070573376), // VMLSslfd
|
|
UINT64_C(4087350592), // VMLSslfq
|
|
UINT64_C(4069524800), // VMLSslhd
|
|
UINT64_C(4086302016), // VMLSslhq
|
|
UINT64_C(4070573120), // VMLSslv2i32
|
|
UINT64_C(4069524544), // VMLSslv4i16
|
|
UINT64_C(4087350336), // VMLSslv4i32
|
|
UINT64_C(4086301760), // VMLSslv8i16
|
|
UINT64_C(4076865856), // VMLSv16i8
|
|
UINT64_C(4078962944), // VMLSv2i32
|
|
UINT64_C(4077914368), // VMLSv4i16
|
|
UINT64_C(4078963008), // VMLSv4i32
|
|
UINT64_C(4077914432), // VMLSv8i16
|
|
UINT64_C(4076865792), // VMLSv8i8
|
|
UINT64_C(246418240), // VMOVD
|
|
UINT64_C(0),
|
|
UINT64_C(205523728), // VMOVDRR
|
|
UINT64_C(0),
|
|
UINT64_C(4272949824), // VMOVH
|
|
UINT64_C(234883344), // VMOVHR
|
|
UINT64_C(4070574608), // VMOVLsv2i64
|
|
UINT64_C(4069526032), // VMOVLsv4i32
|
|
UINT64_C(4069001744), // VMOVLsv8i16
|
|
UINT64_C(4087351824), // VMOVLuv2i64
|
|
UINT64_C(4086303248), // VMOVLuv4i32
|
|
UINT64_C(4085778960), // VMOVLuv8i16
|
|
UINT64_C(4089053696), // VMOVNv2i32
|
|
UINT64_C(4088791552), // VMOVNv4i16
|
|
UINT64_C(4088529408), // VMOVNv8i8
|
|
UINT64_C(0),
|
|
UINT64_C(235931920), // VMOVRH
|
|
UINT64_C(206572304), // VMOVRRD
|
|
UINT64_C(206572048), // VMOVRRS
|
|
UINT64_C(235932176), // VMOVRS
|
|
UINT64_C(246417984), // VMOVS
|
|
UINT64_C(234883600), // VMOVSR
|
|
UINT64_C(205523472), // VMOVSRR
|
|
UINT64_C(0),
|
|
UINT64_C(4068478544), // VMOVv16i8
|
|
UINT64_C(4068478512), // VMOVv1i64
|
|
UINT64_C(4068478736), // VMOVv2f32
|
|
UINT64_C(4068474896), // VMOVv2i32
|
|
UINT64_C(4068478576), // VMOVv2i64
|
|
UINT64_C(4068478800), // VMOVv4f32
|
|
UINT64_C(4068476944), // VMOVv4i16
|
|
UINT64_C(4068474960), // VMOVv4i32
|
|
UINT64_C(4068477008), // VMOVv8i16
|
|
UINT64_C(4068478480), // VMOVv8i8
|
|
UINT64_C(250677776), // VMRS
|
|
UINT64_C(251136528), // VMRS_FPEXC
|
|
UINT64_C(251202064), // VMRS_FPINST
|
|
UINT64_C(251267600), // VMRS_FPINST2
|
|
UINT64_C(250612240), // VMRS_FPSID
|
|
UINT64_C(251070992), // VMRS_MVFR0
|
|
UINT64_C(251005456), // VMRS_MVFR1
|
|
UINT64_C(250939920), // VMRS_MVFR2
|
|
UINT64_C(249629200), // VMSR
|
|
UINT64_C(250087952), // VMSR_FPEXC
|
|
UINT64_C(250153488), // VMSR_FPINST
|
|
UINT64_C(250219024), // VMSR_FPINST2
|
|
UINT64_C(249563664), // VMSR_FPSID
|
|
UINT64_C(236980992), // VMULD
|
|
UINT64_C(236980480), // VMULH
|
|
UINT64_C(4070575616), // VMULLp64
|
|
UINT64_C(4068478464), // VMULLp8
|
|
UINT64_C(4070574656), // VMULLslsv2i32
|
|
UINT64_C(4069526080), // VMULLslsv4i16
|
|
UINT64_C(4087351872), // VMULLsluv2i32
|
|
UINT64_C(4086303296), // VMULLsluv4i16
|
|
UINT64_C(4070575104), // VMULLsv2i64
|
|
UINT64_C(4069526528), // VMULLsv4i32
|
|
UINT64_C(4068477952), // VMULLsv8i16
|
|
UINT64_C(4087352320), // VMULLuv2i64
|
|
UINT64_C(4086303744), // VMULLuv4i32
|
|
UINT64_C(4085255168), // VMULLuv8i16
|
|
UINT64_C(236980736), // VMULS
|
|
UINT64_C(4076866832), // VMULfd
|
|
UINT64_C(4076866896), // VMULfq
|
|
UINT64_C(4077915408), // VMULhd
|
|
UINT64_C(4077915472), // VMULhq
|
|
UINT64_C(4076865808), // VMULpd
|
|
UINT64_C(4076865872), // VMULpq
|
|
UINT64_C(4070574400), // VMULslfd
|
|
UINT64_C(4087351616), // VMULslfq
|
|
UINT64_C(4069525824), // VMULslhd
|
|
UINT64_C(4086303040), // VMULslhq
|
|
UINT64_C(4070574144), // VMULslv2i32
|
|
UINT64_C(4069525568), // VMULslv4i16
|
|
UINT64_C(4087351360), // VMULslv4i32
|
|
UINT64_C(4086302784), // VMULslv8i16
|
|
UINT64_C(4060088656), // VMULv16i8
|
|
UINT64_C(4062185744), // VMULv2i32
|
|
UINT64_C(4061137168), // VMULv4i16
|
|
UINT64_C(4062185808), // VMULv4i32
|
|
UINT64_C(4061137232), // VMULv8i16
|
|
UINT64_C(4060088592), // VMULv8i8
|
|
UINT64_C(4088399232), // VMVNd
|
|
UINT64_C(4088399296), // VMVNq
|
|
UINT64_C(4068474928), // VMVNv2i32
|
|
UINT64_C(4068476976), // VMVNv4i16
|
|
UINT64_C(4068474992), // VMVNv4i32
|
|
UINT64_C(4068477040), // VMVNv8i16
|
|
UINT64_C(246483776), // VNEGD
|
|
UINT64_C(246483264), // VNEGH
|
|
UINT64_C(246483520), // VNEGS
|
|
UINT64_C(4088989632), // VNEGf32q
|
|
UINT64_C(4088989568), // VNEGfd
|
|
UINT64_C(4088727424), // VNEGhd
|
|
UINT64_C(4088727488), // VNEGhq
|
|
UINT64_C(4088726400), // VNEGs16d
|
|
UINT64_C(4088726464), // VNEGs16q
|
|
UINT64_C(4088988544), // VNEGs32d
|
|
UINT64_C(4088988608), // VNEGs32q
|
|
UINT64_C(4088464256), // VNEGs8d
|
|
UINT64_C(4088464320), // VNEGs8q
|
|
UINT64_C(235932480), // VNMLAD
|
|
UINT64_C(235931968), // VNMLAH
|
|
UINT64_C(235932224), // VNMLAS
|
|
UINT64_C(235932416), // VNMLSD
|
|
UINT64_C(235931904), // VNMLSH
|
|
UINT64_C(235932160), // VNMLSS
|
|
UINT64_C(236981056), // VNMULD
|
|
UINT64_C(236980544), // VNMULH
|
|
UINT64_C(236980800), // VNMULS
|
|
UINT64_C(4063232272), // VORNd
|
|
UINT64_C(4063232336), // VORNq
|
|
UINT64_C(4062183696), // VORRd
|
|
UINT64_C(4068475152), // VORRiv2i32
|
|
UINT64_C(4068477200), // VORRiv4i16
|
|
UINT64_C(4068475216), // VORRiv4i32
|
|
UINT64_C(4068477264), // VORRiv8i16
|
|
UINT64_C(4062183760), // VORRq
|
|
UINT64_C(4088399424), // VPADALsv16i8
|
|
UINT64_C(4088923648), // VPADALsv2i32
|
|
UINT64_C(4088661504), // VPADALsv4i16
|
|
UINT64_C(4088923712), // VPADALsv4i32
|
|
UINT64_C(4088661568), // VPADALsv8i16
|
|
UINT64_C(4088399360), // VPADALsv8i8
|
|
UINT64_C(4088399552), // VPADALuv16i8
|
|
UINT64_C(4088923776), // VPADALuv2i32
|
|
UINT64_C(4088661632), // VPADALuv4i16
|
|
UINT64_C(4088923840), // VPADALuv4i32
|
|
UINT64_C(4088661696), // VPADALuv8i16
|
|
UINT64_C(4088399488), // VPADALuv8i8
|
|
UINT64_C(4088398400), // VPADDLsv16i8
|
|
UINT64_C(4088922624), // VPADDLsv2i32
|
|
UINT64_C(4088660480), // VPADDLsv4i16
|
|
UINT64_C(4088922688), // VPADDLsv4i32
|
|
UINT64_C(4088660544), // VPADDLsv8i16
|
|
UINT64_C(4088398336), // VPADDLsv8i8
|
|
UINT64_C(4088398528), // VPADDLuv16i8
|
|
UINT64_C(4088922752), // VPADDLuv2i32
|
|
UINT64_C(4088660608), // VPADDLuv4i16
|
|
UINT64_C(4088922816), // VPADDLuv4i32
|
|
UINT64_C(4088660672), // VPADDLuv8i16
|
|
UINT64_C(4088398464), // VPADDLuv8i8
|
|
UINT64_C(4076866816), // VPADDf
|
|
UINT64_C(4077915392), // VPADDh
|
|
UINT64_C(4061137680), // VPADDi16
|
|
UINT64_C(4062186256), // VPADDi32
|
|
UINT64_C(4060089104), // VPADDi8
|
|
UINT64_C(4076867328), // VPMAXf
|
|
UINT64_C(4077915904), // VPMAXh
|
|
UINT64_C(4061137408), // VPMAXs16
|
|
UINT64_C(4062185984), // VPMAXs32
|
|
UINT64_C(4060088832), // VPMAXs8
|
|
UINT64_C(4077914624), // VPMAXu16
|
|
UINT64_C(4078963200), // VPMAXu32
|
|
UINT64_C(4076866048), // VPMAXu8
|
|
UINT64_C(4078964480), // VPMINf
|
|
UINT64_C(4080013056), // VPMINh
|
|
UINT64_C(4061137424), // VPMINs16
|
|
UINT64_C(4062186000), // VPMINs32
|
|
UINT64_C(4060088848), // VPMINs8
|
|
UINT64_C(4077914640), // VPMINu16
|
|
UINT64_C(4078963216), // VPMINu32
|
|
UINT64_C(4076866064), // VPMINu8
|
|
UINT64_C(4088399680), // VQABSv16i8
|
|
UINT64_C(4088923904), // VQABSv2i32
|
|
UINT64_C(4088661760), // VQABSv4i16
|
|
UINT64_C(4088923968), // VQABSv4i32
|
|
UINT64_C(4088661824), // VQABSv8i16
|
|
UINT64_C(4088399616), // VQABSv8i8
|
|
UINT64_C(4060086352), // VQADDsv16i8
|
|
UINT64_C(4063232016), // VQADDsv1i64
|
|
UINT64_C(4062183440), // VQADDsv2i32
|
|
UINT64_C(4063232080), // VQADDsv2i64
|
|
UINT64_C(4061134864), // VQADDsv4i16
|
|
UINT64_C(4062183504), // VQADDsv4i32
|
|
UINT64_C(4061134928), // VQADDsv8i16
|
|
UINT64_C(4060086288), // VQADDsv8i8
|
|
UINT64_C(4076863568), // VQADDuv16i8
|
|
UINT64_C(4080009232), // VQADDuv1i64
|
|
UINT64_C(4078960656), // VQADDuv2i32
|
|
UINT64_C(4080009296), // VQADDuv2i64
|
|
UINT64_C(4077912080), // VQADDuv4i16
|
|
UINT64_C(4078960720), // VQADDuv4i32
|
|
UINT64_C(4077912144), // VQADDuv8i16
|
|
UINT64_C(4076863504), // VQADDuv8i8
|
|
UINT64_C(4070572864), // VQDMLALslv2i32
|
|
UINT64_C(4069524288), // VQDMLALslv4i16
|
|
UINT64_C(4070574336), // VQDMLALv2i64
|
|
UINT64_C(4069525760), // VQDMLALv4i32
|
|
UINT64_C(4070573888), // VQDMLSLslv2i32
|
|
UINT64_C(4069525312), // VQDMLSLslv4i16
|
|
UINT64_C(4070574848), // VQDMLSLv2i64
|
|
UINT64_C(4069526272), // VQDMLSLv4i32
|
|
UINT64_C(4070575168), // VQDMULHslv2i32
|
|
UINT64_C(4069526592), // VQDMULHslv4i16
|
|
UINT64_C(4087352384), // VQDMULHslv4i32
|
|
UINT64_C(4086303808), // VQDMULHslv8i16
|
|
UINT64_C(4062186240), // VQDMULHv2i32
|
|
UINT64_C(4061137664), // VQDMULHv4i16
|
|
UINT64_C(4062186304), // VQDMULHv4i32
|
|
UINT64_C(4061137728), // VQDMULHv8i16
|
|
UINT64_C(4070574912), // VQDMULLslv2i32
|
|
UINT64_C(4069526336), // VQDMULLslv4i16
|
|
UINT64_C(4070575360), // VQDMULLv2i64
|
|
UINT64_C(4069526784), // VQDMULLv4i32
|
|
UINT64_C(4089053760), // VQMOVNsuv2i32
|
|
UINT64_C(4088791616), // VQMOVNsuv4i16
|
|
UINT64_C(4088529472), // VQMOVNsuv8i8
|
|
UINT64_C(4089053824), // VQMOVNsv2i32
|
|
UINT64_C(4088791680), // VQMOVNsv4i16
|
|
UINT64_C(4088529536), // VQMOVNsv8i8
|
|
UINT64_C(4089053888), // VQMOVNuv2i32
|
|
UINT64_C(4088791744), // VQMOVNuv4i16
|
|
UINT64_C(4088529600), // VQMOVNuv8i8
|
|
UINT64_C(4088399808), // VQNEGv16i8
|
|
UINT64_C(4088924032), // VQNEGv2i32
|
|
UINT64_C(4088661888), // VQNEGv4i16
|
|
UINT64_C(4088924096), // VQNEGv4i32
|
|
UINT64_C(4088661952), // VQNEGv8i16
|
|
UINT64_C(4088399744), // VQNEGv8i8
|
|
UINT64_C(4070575680), // VQRDMLAHslv2i32
|
|
UINT64_C(4069527104), // VQRDMLAHslv4i16
|
|
UINT64_C(4087352896), // VQRDMLAHslv4i32
|
|
UINT64_C(4086304320), // VQRDMLAHslv8i16
|
|
UINT64_C(4078963472), // VQRDMLAHv2i32
|
|
UINT64_C(4077914896), // VQRDMLAHv4i16
|
|
UINT64_C(4078963536), // VQRDMLAHv4i32
|
|
UINT64_C(4077914960), // VQRDMLAHv8i16
|
|
UINT64_C(4070575936), // VQRDMLSHslv2i32
|
|
UINT64_C(4069527360), // VQRDMLSHslv4i16
|
|
UINT64_C(4087353152), // VQRDMLSHslv4i32
|
|
UINT64_C(4086304576), // VQRDMLSHslv8i16
|
|
UINT64_C(4078963728), // VQRDMLSHv2i32
|
|
UINT64_C(4077915152), // VQRDMLSHv4i16
|
|
UINT64_C(4078963792), // VQRDMLSHv4i32
|
|
UINT64_C(4077915216), // VQRDMLSHv8i16
|
|
UINT64_C(4070575424), // VQRDMULHslv2i32
|
|
UINT64_C(4069526848), // VQRDMULHslv4i16
|
|
UINT64_C(4087352640), // VQRDMULHslv4i32
|
|
UINT64_C(4086304064), // VQRDMULHslv8i16
|
|
UINT64_C(4078963456), // VQRDMULHv2i32
|
|
UINT64_C(4077914880), // VQRDMULHv4i16
|
|
UINT64_C(4078963520), // VQRDMULHv4i32
|
|
UINT64_C(4077914944), // VQRDMULHv8i16
|
|
UINT64_C(4060087632), // VQRSHLsv16i8
|
|
UINT64_C(4063233296), // VQRSHLsv1i64
|
|
UINT64_C(4062184720), // VQRSHLsv2i32
|
|
UINT64_C(4063233360), // VQRSHLsv2i64
|
|
UINT64_C(4061136144), // VQRSHLsv4i16
|
|
UINT64_C(4062184784), // VQRSHLsv4i32
|
|
UINT64_C(4061136208), // VQRSHLsv8i16
|
|
UINT64_C(4060087568), // VQRSHLsv8i8
|
|
UINT64_C(4076864848), // VQRSHLuv16i8
|
|
UINT64_C(4080010512), // VQRSHLuv1i64
|
|
UINT64_C(4078961936), // VQRSHLuv2i32
|
|
UINT64_C(4080010576), // VQRSHLuv2i64
|
|
UINT64_C(4077913360), // VQRSHLuv4i16
|
|
UINT64_C(4078962000), // VQRSHLuv4i32
|
|
UINT64_C(4077913424), // VQRSHLuv8i16
|
|
UINT64_C(4076864784), // VQRSHLuv8i8
|
|
UINT64_C(4070574416), // VQRSHRNsv2i32
|
|
UINT64_C(4069525840), // VQRSHRNsv4i16
|
|
UINT64_C(4069001552), // VQRSHRNsv8i8
|
|
UINT64_C(4087351632), // VQRSHRNuv2i32
|
|
UINT64_C(4086303056), // VQRSHRNuv4i16
|
|
UINT64_C(4085778768), // VQRSHRNuv8i8
|
|
UINT64_C(4087351376), // VQRSHRUNv2i32
|
|
UINT64_C(4086302800), // VQRSHRUNv4i16
|
|
UINT64_C(4085778512), // VQRSHRUNv8i8
|
|
UINT64_C(4069001040), // VQSHLsiv16i8
|
|
UINT64_C(4068476816), // VQSHLsiv1i64
|
|
UINT64_C(4070573840), // VQSHLsiv2i32
|
|
UINT64_C(4068476880), // VQSHLsiv2i64
|
|
UINT64_C(4069525264), // VQSHLsiv4i16
|
|
UINT64_C(4070573904), // VQSHLsiv4i32
|
|
UINT64_C(4069525328), // VQSHLsiv8i16
|
|
UINT64_C(4069000976), // VQSHLsiv8i8
|
|
UINT64_C(4085778000), // VQSHLsuv16i8
|
|
UINT64_C(4085253776), // VQSHLsuv1i64
|
|
UINT64_C(4087350800), // VQSHLsuv2i32
|
|
UINT64_C(4085253840), // VQSHLsuv2i64
|
|
UINT64_C(4086302224), // VQSHLsuv4i16
|
|
UINT64_C(4087350864), // VQSHLsuv4i32
|
|
UINT64_C(4086302288), // VQSHLsuv8i16
|
|
UINT64_C(4085777936), // VQSHLsuv8i8
|
|
UINT64_C(4060087376), // VQSHLsv16i8
|
|
UINT64_C(4063233040), // VQSHLsv1i64
|
|
UINT64_C(4062184464), // VQSHLsv2i32
|
|
UINT64_C(4063233104), // VQSHLsv2i64
|
|
UINT64_C(4061135888), // VQSHLsv4i16
|
|
UINT64_C(4062184528), // VQSHLsv4i32
|
|
UINT64_C(4061135952), // VQSHLsv8i16
|
|
UINT64_C(4060087312), // VQSHLsv8i8
|
|
UINT64_C(4085778256), // VQSHLuiv16i8
|
|
UINT64_C(4085254032), // VQSHLuiv1i64
|
|
UINT64_C(4087351056), // VQSHLuiv2i32
|
|
UINT64_C(4085254096), // VQSHLuiv2i64
|
|
UINT64_C(4086302480), // VQSHLuiv4i16
|
|
UINT64_C(4087351120), // VQSHLuiv4i32
|
|
UINT64_C(4086302544), // VQSHLuiv8i16
|
|
UINT64_C(4085778192), // VQSHLuiv8i8
|
|
UINT64_C(4076864592), // VQSHLuv16i8
|
|
UINT64_C(4080010256), // VQSHLuv1i64
|
|
UINT64_C(4078961680), // VQSHLuv2i32
|
|
UINT64_C(4080010320), // VQSHLuv2i64
|
|
UINT64_C(4077913104), // VQSHLuv4i16
|
|
UINT64_C(4078961744), // VQSHLuv4i32
|
|
UINT64_C(4077913168), // VQSHLuv8i16
|
|
UINT64_C(4076864528), // VQSHLuv8i8
|
|
UINT64_C(4070574352), // VQSHRNsv2i32
|
|
UINT64_C(4069525776), // VQSHRNsv4i16
|
|
UINT64_C(4069001488), // VQSHRNsv8i8
|
|
UINT64_C(4087351568), // VQSHRNuv2i32
|
|
UINT64_C(4086302992), // VQSHRNuv4i16
|
|
UINT64_C(4085778704), // VQSHRNuv8i8
|
|
UINT64_C(4087351312), // VQSHRUNv2i32
|
|
UINT64_C(4086302736), // VQSHRUNv4i16
|
|
UINT64_C(4085778448), // VQSHRUNv8i8
|
|
UINT64_C(4060086864), // VQSUBsv16i8
|
|
UINT64_C(4063232528), // VQSUBsv1i64
|
|
UINT64_C(4062183952), // VQSUBsv2i32
|
|
UINT64_C(4063232592), // VQSUBsv2i64
|
|
UINT64_C(4061135376), // VQSUBsv4i16
|
|
UINT64_C(4062184016), // VQSUBsv4i32
|
|
UINT64_C(4061135440), // VQSUBsv8i16
|
|
UINT64_C(4060086800), // VQSUBsv8i8
|
|
UINT64_C(4076864080), // VQSUBuv16i8
|
|
UINT64_C(4080009744), // VQSUBuv1i64
|
|
UINT64_C(4078961168), // VQSUBuv2i32
|
|
UINT64_C(4080009808), // VQSUBuv2i64
|
|
UINT64_C(4077912592), // VQSUBuv4i16
|
|
UINT64_C(4078961232), // VQSUBuv4i32
|
|
UINT64_C(4077912656), // VQSUBuv8i16
|
|
UINT64_C(4076864016), // VQSUBuv8i8
|
|
UINT64_C(4087350272), // VRADDHNv2i32
|
|
UINT64_C(4086301696), // VRADDHNv4i16
|
|
UINT64_C(4085253120), // VRADDHNv8i8
|
|
UINT64_C(4089119744), // VRECPEd
|
|
UINT64_C(4089120000), // VRECPEfd
|
|
UINT64_C(4089120064), // VRECPEfq
|
|
UINT64_C(4088857856), // VRECPEhd
|
|
UINT64_C(4088857920), // VRECPEhq
|
|
UINT64_C(4089119808), // VRECPEq
|
|
UINT64_C(4060090128), // VRECPSfd
|
|
UINT64_C(4060090192), // VRECPSfq
|
|
UINT64_C(4061138704), // VRECPShd
|
|
UINT64_C(4061138768), // VRECPShq
|
|
UINT64_C(4088398080), // VREV16d8
|
|
UINT64_C(4088398144), // VREV16q8
|
|
UINT64_C(4088660096), // VREV32d16
|
|
UINT64_C(4088397952), // VREV32d8
|
|
UINT64_C(4088660160), // VREV32q16
|
|
UINT64_C(4088398016), // VREV32q8
|
|
UINT64_C(4088659968), // VREV64d16
|
|
UINT64_C(4088922112), // VREV64d32
|
|
UINT64_C(4088397824), // VREV64d8
|
|
UINT64_C(4088660032), // VREV64q16
|
|
UINT64_C(4088922176), // VREV64q32
|
|
UINT64_C(4088397888), // VREV64q8
|
|
UINT64_C(4060086592), // VRHADDsv16i8
|
|
UINT64_C(4062183680), // VRHADDsv2i32
|
|
UINT64_C(4061135104), // VRHADDsv4i16
|
|
UINT64_C(4062183744), // VRHADDsv4i32
|
|
UINT64_C(4061135168), // VRHADDsv8i16
|
|
UINT64_C(4060086528), // VRHADDsv8i8
|
|
UINT64_C(4076863808), // VRHADDuv16i8
|
|
UINT64_C(4078960896), // VRHADDuv2i32
|
|
UINT64_C(4077912320), // VRHADDuv4i16
|
|
UINT64_C(4078960960), // VRHADDuv4i32
|
|
UINT64_C(4077912384), // VRHADDuv8i16
|
|
UINT64_C(4076863744), // VRHADDuv8i8
|
|
UINT64_C(4273474368), // VRINTAD
|
|
UINT64_C(4273473856), // VRINTAH
|
|
UINT64_C(4089054464), // VRINTANDf
|
|
UINT64_C(4088792320), // VRINTANDh
|
|
UINT64_C(4089054528), // VRINTANQf
|
|
UINT64_C(4088792384), // VRINTANQh
|
|
UINT64_C(4273474112), // VRINTAS
|
|
UINT64_C(4273670976), // VRINTMD
|
|
UINT64_C(4273670464), // VRINTMH
|
|
UINT64_C(4089054848), // VRINTMNDf
|
|
UINT64_C(4088792704), // VRINTMNDh
|
|
UINT64_C(4089054912), // VRINTMNQf
|
|
UINT64_C(4088792768), // VRINTMNQh
|
|
UINT64_C(4273670720), // VRINTMS
|
|
UINT64_C(4273539904), // VRINTND
|
|
UINT64_C(4273539392), // VRINTNH
|
|
UINT64_C(4089054208), // VRINTNNDf
|
|
UINT64_C(4088792064), // VRINTNNDh
|
|
UINT64_C(4089054272), // VRINTNNQf
|
|
UINT64_C(4088792128), // VRINTNNQh
|
|
UINT64_C(4273539648), // VRINTNS
|
|
UINT64_C(4273605440), // VRINTPD
|
|
UINT64_C(4273604928), // VRINTPH
|
|
UINT64_C(4089055104), // VRINTPNDf
|
|
UINT64_C(4088792960), // VRINTPNDh
|
|
UINT64_C(4089055168), // VRINTPNQf
|
|
UINT64_C(4088793024), // VRINTPNQh
|
|
UINT64_C(4273605184), // VRINTPS
|
|
UINT64_C(246811456), // VRINTRD
|
|
UINT64_C(246810944), // VRINTRH
|
|
UINT64_C(246811200), // VRINTRS
|
|
UINT64_C(246876992), // VRINTXD
|
|
UINT64_C(246876480), // VRINTXH
|
|
UINT64_C(4089054336), // VRINTXNDf
|
|
UINT64_C(4088792192), // VRINTXNDh
|
|
UINT64_C(4089054400), // VRINTXNQf
|
|
UINT64_C(4088792256), // VRINTXNQh
|
|
UINT64_C(246876736), // VRINTXS
|
|
UINT64_C(246811584), // VRINTZD
|
|
UINT64_C(246811072), // VRINTZH
|
|
UINT64_C(4089054592), // VRINTZNDf
|
|
UINT64_C(4088792448), // VRINTZNDh
|
|
UINT64_C(4089054656), // VRINTZNQf
|
|
UINT64_C(4088792512), // VRINTZNQh
|
|
UINT64_C(246811328), // VRINTZS
|
|
UINT64_C(4060087616), // VRSHLsv16i8
|
|
UINT64_C(4063233280), // VRSHLsv1i64
|
|
UINT64_C(4062184704), // VRSHLsv2i32
|
|
UINT64_C(4063233344), // VRSHLsv2i64
|
|
UINT64_C(4061136128), // VRSHLsv4i16
|
|
UINT64_C(4062184768), // VRSHLsv4i32
|
|
UINT64_C(4061136192), // VRSHLsv8i16
|
|
UINT64_C(4060087552), // VRSHLsv8i8
|
|
UINT64_C(4076864832), // VRSHLuv16i8
|
|
UINT64_C(4080010496), // VRSHLuv1i64
|
|
UINT64_C(4078961920), // VRSHLuv2i32
|
|
UINT64_C(4080010560), // VRSHLuv2i64
|
|
UINT64_C(4077913344), // VRSHLuv4i16
|
|
UINT64_C(4078961984), // VRSHLuv4i32
|
|
UINT64_C(4077913408), // VRSHLuv8i16
|
|
UINT64_C(4076864768), // VRSHLuv8i8
|
|
UINT64_C(4070574160), // VRSHRNv2i32
|
|
UINT64_C(4069525584), // VRSHRNv4i16
|
|
UINT64_C(4069001296), // VRSHRNv8i8
|
|
UINT64_C(4068999760), // VRSHRsv16i8
|
|
UINT64_C(4068475536), // VRSHRsv1i64
|
|
UINT64_C(4070572560), // VRSHRsv2i32
|
|
UINT64_C(4068475600), // VRSHRsv2i64
|
|
UINT64_C(4069523984), // VRSHRsv4i16
|
|
UINT64_C(4070572624), // VRSHRsv4i32
|
|
UINT64_C(4069524048), // VRSHRsv8i16
|
|
UINT64_C(4068999696), // VRSHRsv8i8
|
|
UINT64_C(4085776976), // VRSHRuv16i8
|
|
UINT64_C(4085252752), // VRSHRuv1i64
|
|
UINT64_C(4087349776), // VRSHRuv2i32
|
|
UINT64_C(4085252816), // VRSHRuv2i64
|
|
UINT64_C(4086301200), // VRSHRuv4i16
|
|
UINT64_C(4087349840), // VRSHRuv4i32
|
|
UINT64_C(4086301264), // VRSHRuv8i16
|
|
UINT64_C(4085776912), // VRSHRuv8i8
|
|
UINT64_C(4089119872), // VRSQRTEd
|
|
UINT64_C(4089120128), // VRSQRTEfd
|
|
UINT64_C(4089120192), // VRSQRTEfq
|
|
UINT64_C(4088857984), // VRSQRTEhd
|
|
UINT64_C(4088858048), // VRSQRTEhq
|
|
UINT64_C(4089119936), // VRSQRTEq
|
|
UINT64_C(4062187280), // VRSQRTSfd
|
|
UINT64_C(4062187344), // VRSQRTSfq
|
|
UINT64_C(4063235856), // VRSQRTShd
|
|
UINT64_C(4063235920), // VRSQRTShq
|
|
UINT64_C(4069000016), // VRSRAsv16i8
|
|
UINT64_C(4068475792), // VRSRAsv1i64
|
|
UINT64_C(4070572816), // VRSRAsv2i32
|
|
UINT64_C(4068475856), // VRSRAsv2i64
|
|
UINT64_C(4069524240), // VRSRAsv4i16
|
|
UINT64_C(4070572880), // VRSRAsv4i32
|
|
UINT64_C(4069524304), // VRSRAsv8i16
|
|
UINT64_C(4068999952), // VRSRAsv8i8
|
|
UINT64_C(4085777232), // VRSRAuv16i8
|
|
UINT64_C(4085253008), // VRSRAuv1i64
|
|
UINT64_C(4087350032), // VRSRAuv2i32
|
|
UINT64_C(4085253072), // VRSRAuv2i64
|
|
UINT64_C(4086301456), // VRSRAuv4i16
|
|
UINT64_C(4087350096), // VRSRAuv4i32
|
|
UINT64_C(4086301520), // VRSRAuv8i16
|
|
UINT64_C(4085777168), // VRSRAuv8i8
|
|
UINT64_C(4087350784), // VRSUBHNv2i32
|
|
UINT64_C(4086302208), // VRSUBHNv4i16
|
|
UINT64_C(4085253632), // VRSUBHNv8i8
|
|
UINT64_C(4261415680), // VSELEQD
|
|
UINT64_C(4261415168), // VSELEQH
|
|
UINT64_C(4261415424), // VSELEQS
|
|
UINT64_C(4263512832), // VSELGED
|
|
UINT64_C(4263512320), // VSELGEH
|
|
UINT64_C(4263512576), // VSELGES
|
|
UINT64_C(4264561408), // VSELGTD
|
|
UINT64_C(4264560896), // VSELGTH
|
|
UINT64_C(4264561152), // VSELGTS
|
|
UINT64_C(4262464256), // VSELVSD
|
|
UINT64_C(4262463744), // VSELVSH
|
|
UINT64_C(4262464000), // VSELVSS
|
|
UINT64_C(234883888), // VSETLNi16
|
|
UINT64_C(234883856), // VSETLNi32
|
|
UINT64_C(239078160), // VSETLNi8
|
|
UINT64_C(4088791808), // VSHLLi16
|
|
UINT64_C(4089053952), // VSHLLi32
|
|
UINT64_C(4088529664), // VSHLLi8
|
|
UINT64_C(4070574608), // VSHLLsv2i64
|
|
UINT64_C(4069526032), // VSHLLsv4i32
|
|
UINT64_C(4069001744), // VSHLLsv8i16
|
|
UINT64_C(4087351824), // VSHLLuv2i64
|
|
UINT64_C(4086303248), // VSHLLuv4i32
|
|
UINT64_C(4085778960), // VSHLLuv8i16
|
|
UINT64_C(4069000528), // VSHLiv16i8
|
|
UINT64_C(4068476304), // VSHLiv1i64
|
|
UINT64_C(4070573328), // VSHLiv2i32
|
|
UINT64_C(4068476368), // VSHLiv2i64
|
|
UINT64_C(4069524752), // VSHLiv4i16
|
|
UINT64_C(4070573392), // VSHLiv4i32
|
|
UINT64_C(4069524816), // VSHLiv8i16
|
|
UINT64_C(4069000464), // VSHLiv8i8
|
|
UINT64_C(4060087360), // VSHLsv16i8
|
|
UINT64_C(4063233024), // VSHLsv1i64
|
|
UINT64_C(4062184448), // VSHLsv2i32
|
|
UINT64_C(4063233088), // VSHLsv2i64
|
|
UINT64_C(4061135872), // VSHLsv4i16
|
|
UINT64_C(4062184512), // VSHLsv4i32
|
|
UINT64_C(4061135936), // VSHLsv8i16
|
|
UINT64_C(4060087296), // VSHLsv8i8
|
|
UINT64_C(4076864576), // VSHLuv16i8
|
|
UINT64_C(4080010240), // VSHLuv1i64
|
|
UINT64_C(4078961664), // VSHLuv2i32
|
|
UINT64_C(4080010304), // VSHLuv2i64
|
|
UINT64_C(4077913088), // VSHLuv4i16
|
|
UINT64_C(4078961728), // VSHLuv4i32
|
|
UINT64_C(4077913152), // VSHLuv8i16
|
|
UINT64_C(4076864512), // VSHLuv8i8
|
|
UINT64_C(4070574096), // VSHRNv2i32
|
|
UINT64_C(4069525520), // VSHRNv4i16
|
|
UINT64_C(4069001232), // VSHRNv8i8
|
|
UINT64_C(4068999248), // VSHRsv16i8
|
|
UINT64_C(4068475024), // VSHRsv1i64
|
|
UINT64_C(4070572048), // VSHRsv2i32
|
|
UINT64_C(4068475088), // VSHRsv2i64
|
|
UINT64_C(4069523472), // VSHRsv4i16
|
|
UINT64_C(4070572112), // VSHRsv4i32
|
|
UINT64_C(4069523536), // VSHRsv8i16
|
|
UINT64_C(4068999184), // VSHRsv8i8
|
|
UINT64_C(4085776464), // VSHRuv16i8
|
|
UINT64_C(4085252240), // VSHRuv1i64
|
|
UINT64_C(4087349264), // VSHRuv2i32
|
|
UINT64_C(4085252304), // VSHRuv2i64
|
|
UINT64_C(4086300688), // VSHRuv4i16
|
|
UINT64_C(4087349328), // VSHRuv4i32
|
|
UINT64_C(4086300752), // VSHRuv8i16
|
|
UINT64_C(4085776400), // VSHRuv8i8
|
|
UINT64_C(247073600), // VSHTOD
|
|
UINT64_C(247073088), // VSHTOH
|
|
UINT64_C(247073344), // VSHTOS
|
|
UINT64_C(246942656), // VSITOD
|
|
UINT64_C(246942144), // VSITOH
|
|
UINT64_C(246942400), // VSITOS
|
|
UINT64_C(4085777744), // VSLIv16i8
|
|
UINT64_C(4085253520), // VSLIv1i64
|
|
UINT64_C(4087350544), // VSLIv2i32
|
|
UINT64_C(4085253584), // VSLIv2i64
|
|
UINT64_C(4086301968), // VSLIv4i16
|
|
UINT64_C(4087350608), // VSLIv4i32
|
|
UINT64_C(4086302032), // VSLIv8i16
|
|
UINT64_C(4085777680), // VSLIv8i8
|
|
UINT64_C(247073728), // VSLTOD
|
|
UINT64_C(247073216), // VSLTOH
|
|
UINT64_C(247073472), // VSLTOS
|
|
UINT64_C(246483904), // VSQRTD
|
|
UINT64_C(246483392), // VSQRTH
|
|
UINT64_C(246483648), // VSQRTS
|
|
UINT64_C(4068999504), // VSRAsv16i8
|
|
UINT64_C(4068475280), // VSRAsv1i64
|
|
UINT64_C(4070572304), // VSRAsv2i32
|
|
UINT64_C(4068475344), // VSRAsv2i64
|
|
UINT64_C(4069523728), // VSRAsv4i16
|
|
UINT64_C(4070572368), // VSRAsv4i32
|
|
UINT64_C(4069523792), // VSRAsv8i16
|
|
UINT64_C(4068999440), // VSRAsv8i8
|
|
UINT64_C(4085776720), // VSRAuv16i8
|
|
UINT64_C(4085252496), // VSRAuv1i64
|
|
UINT64_C(4087349520), // VSRAuv2i32
|
|
UINT64_C(4085252560), // VSRAuv2i64
|
|
UINT64_C(4086300944), // VSRAuv4i16
|
|
UINT64_C(4087349584), // VSRAuv4i32
|
|
UINT64_C(4086301008), // VSRAuv8i16
|
|
UINT64_C(4085776656), // VSRAuv8i8
|
|
UINT64_C(4085777488), // VSRIv16i8
|
|
UINT64_C(4085253264), // VSRIv1i64
|
|
UINT64_C(4087350288), // VSRIv2i32
|
|
UINT64_C(4085253328), // VSRIv2i64
|
|
UINT64_C(4086301712), // VSRIv4i16
|
|
UINT64_C(4087350352), // VSRIv4i32
|
|
UINT64_C(4086301776), // VSRIv8i16
|
|
UINT64_C(4085777424), // VSRIv8i8
|
|
UINT64_C(4102030351), // VST1LNd16
|
|
UINT64_C(4102030336), // VST1LNd16_UPD
|
|
UINT64_C(4102031375), // VST1LNd32
|
|
UINT64_C(4102031360), // VST1LNd32_UPD
|
|
UINT64_C(4102029327), // VST1LNd8
|
|
UINT64_C(4102029312), // VST1LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0), // VST1LNq16Pseudo
|
|
UINT64_C(0), // VST1LNq16Pseudo_UPD
|
|
UINT64_C(0), // VST1LNq32Pseudo
|
|
UINT64_C(0), // VST1LNq32Pseudo_UPD
|
|
UINT64_C(0), // VST1LNq8Pseudo
|
|
UINT64_C(0), // VST1LNq8Pseudo_UPD
|
|
UINT64_C(4093642575), // VST1d16
|
|
UINT64_C(4093641295), // VST1d16Q
|
|
UINT64_C(4093641293), // VST1d16Qwb_fixed
|
|
UINT64_C(4093641280), // VST1d16Qwb_register
|
|
UINT64_C(4093642319), // VST1d16T
|
|
UINT64_C(4093642317), // VST1d16Twb_fixed
|
|
UINT64_C(4093642304), // VST1d16Twb_register
|
|
UINT64_C(4093642573), // VST1d16wb_fixed
|
|
UINT64_C(4093642560), // VST1d16wb_register
|
|
UINT64_C(4093642639), // VST1d32
|
|
UINT64_C(4093641359), // VST1d32Q
|
|
UINT64_C(4093641357), // VST1d32Qwb_fixed
|
|
UINT64_C(4093641344), // VST1d32Qwb_register
|
|
UINT64_C(4093642383), // VST1d32T
|
|
UINT64_C(4093642381), // VST1d32Twb_fixed
|
|
UINT64_C(4093642368), // VST1d32Twb_register
|
|
UINT64_C(4093642637), // VST1d32wb_fixed
|
|
UINT64_C(4093642624), // VST1d32wb_register
|
|
UINT64_C(4093642703), // VST1d64
|
|
UINT64_C(4093641423), // VST1d64Q
|
|
UINT64_C(0), // VST1d64QPseudo
|
|
UINT64_C(0), // VST1d64QPseudoWB_fixed
|
|
UINT64_C(0), // VST1d64QPseudoWB_register
|
|
UINT64_C(4093641421), // VST1d64Qwb_fixed
|
|
UINT64_C(4093641408), // VST1d64Qwb_register
|
|
UINT64_C(4093642447), // VST1d64T
|
|
UINT64_C(0), // VST1d64TPseudo
|
|
UINT64_C(0), // VST1d64TPseudoWB_fixed
|
|
UINT64_C(0), // VST1d64TPseudoWB_register
|
|
UINT64_C(4093642445), // VST1d64Twb_fixed
|
|
UINT64_C(4093642432), // VST1d64Twb_register
|
|
UINT64_C(4093642701), // VST1d64wb_fixed
|
|
UINT64_C(4093642688), // VST1d64wb_register
|
|
UINT64_C(4093642511), // VST1d8
|
|
UINT64_C(4093641231), // VST1d8Q
|
|
UINT64_C(4093641229), // VST1d8Qwb_fixed
|
|
UINT64_C(4093641216), // VST1d8Qwb_register
|
|
UINT64_C(4093642255), // VST1d8T
|
|
UINT64_C(4093642253), // VST1d8Twb_fixed
|
|
UINT64_C(4093642240), // VST1d8Twb_register
|
|
UINT64_C(4093642509), // VST1d8wb_fixed
|
|
UINT64_C(4093642496), // VST1d8wb_register
|
|
UINT64_C(4093643343), // VST1q16
|
|
UINT64_C(4093643341), // VST1q16wb_fixed
|
|
UINT64_C(4093643328), // VST1q16wb_register
|
|
UINT64_C(4093643407), // VST1q32
|
|
UINT64_C(4093643405), // VST1q32wb_fixed
|
|
UINT64_C(4093643392), // VST1q32wb_register
|
|
UINT64_C(4093643471), // VST1q64
|
|
UINT64_C(4093643469), // VST1q64wb_fixed
|
|
UINT64_C(4093643456), // VST1q64wb_register
|
|
UINT64_C(4093643279), // VST1q8
|
|
UINT64_C(4093643277), // VST1q8wb_fixed
|
|
UINT64_C(4093643264), // VST1q8wb_register
|
|
UINT64_C(4102030607), // VST2LNd16
|
|
UINT64_C(0), // VST2LNd16Pseudo
|
|
UINT64_C(0), // VST2LNd16Pseudo_UPD
|
|
UINT64_C(4102030592), // VST2LNd16_UPD
|
|
UINT64_C(4102031631), // VST2LNd32
|
|
UINT64_C(0), // VST2LNd32Pseudo
|
|
UINT64_C(0), // VST2LNd32Pseudo_UPD
|
|
UINT64_C(4102031616), // VST2LNd32_UPD
|
|
UINT64_C(4102029583), // VST2LNd8
|
|
UINT64_C(0), // VST2LNd8Pseudo
|
|
UINT64_C(0), // VST2LNd8Pseudo_UPD
|
|
UINT64_C(4102029568), // VST2LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4102030639), // VST2LNq16
|
|
UINT64_C(0), // VST2LNq16Pseudo
|
|
UINT64_C(0), // VST2LNq16Pseudo_UPD
|
|
UINT64_C(4102030624), // VST2LNq16_UPD
|
|
UINT64_C(4102031695), // VST2LNq32
|
|
UINT64_C(0), // VST2LNq32Pseudo
|
|
UINT64_C(0), // VST2LNq32Pseudo_UPD
|
|
UINT64_C(4102031680), // VST2LNq32_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4093643087), // VST2b16
|
|
UINT64_C(4093643085), // VST2b16wb_fixed
|
|
UINT64_C(4093643072), // VST2b16wb_register
|
|
UINT64_C(4093643151), // VST2b32
|
|
UINT64_C(4093643149), // VST2b32wb_fixed
|
|
UINT64_C(4093643136), // VST2b32wb_register
|
|
UINT64_C(4093643023), // VST2b8
|
|
UINT64_C(4093643021), // VST2b8wb_fixed
|
|
UINT64_C(4093643008), // VST2b8wb_register
|
|
UINT64_C(4093642831), // VST2d16
|
|
UINT64_C(4093642829), // VST2d16wb_fixed
|
|
UINT64_C(4093642816), // VST2d16wb_register
|
|
UINT64_C(4093642895), // VST2d32
|
|
UINT64_C(4093642893), // VST2d32wb_fixed
|
|
UINT64_C(4093642880), // VST2d32wb_register
|
|
UINT64_C(4093642767), // VST2d8
|
|
UINT64_C(4093642765), // VST2d8wb_fixed
|
|
UINT64_C(4093642752), // VST2d8wb_register
|
|
UINT64_C(4093641551), // VST2q16
|
|
UINT64_C(0), // VST2q16Pseudo
|
|
UINT64_C(0), // VST2q16PseudoWB_fixed
|
|
UINT64_C(0), // VST2q16PseudoWB_register
|
|
UINT64_C(4093641549), // VST2q16wb_fixed
|
|
UINT64_C(4093641536), // VST2q16wb_register
|
|
UINT64_C(4093641615), // VST2q32
|
|
UINT64_C(0), // VST2q32Pseudo
|
|
UINT64_C(0), // VST2q32PseudoWB_fixed
|
|
UINT64_C(0), // VST2q32PseudoWB_register
|
|
UINT64_C(4093641613), // VST2q32wb_fixed
|
|
UINT64_C(4093641600), // VST2q32wb_register
|
|
UINT64_C(4093641487), // VST2q8
|
|
UINT64_C(0), // VST2q8Pseudo
|
|
UINT64_C(0), // VST2q8PseudoWB_fixed
|
|
UINT64_C(0), // VST2q8PseudoWB_register
|
|
UINT64_C(4093641485), // VST2q8wb_fixed
|
|
UINT64_C(4093641472), // VST2q8wb_register
|
|
UINT64_C(4102030863), // VST3LNd16
|
|
UINT64_C(0), // VST3LNd16Pseudo
|
|
UINT64_C(0), // VST3LNd16Pseudo_UPD
|
|
UINT64_C(4102030848), // VST3LNd16_UPD
|
|
UINT64_C(4102031887), // VST3LNd32
|
|
UINT64_C(0), // VST3LNd32Pseudo
|
|
UINT64_C(0), // VST3LNd32Pseudo_UPD
|
|
UINT64_C(4102031872), // VST3LNd32_UPD
|
|
UINT64_C(4102029839), // VST3LNd8
|
|
UINT64_C(0), // VST3LNd8Pseudo
|
|
UINT64_C(0), // VST3LNd8Pseudo_UPD
|
|
UINT64_C(4102029824), // VST3LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4102030895), // VST3LNq16
|
|
UINT64_C(0), // VST3LNq16Pseudo
|
|
UINT64_C(0), // VST3LNq16Pseudo_UPD
|
|
UINT64_C(4102030880), // VST3LNq16_UPD
|
|
UINT64_C(4102031951), // VST3LNq32
|
|
UINT64_C(0), // VST3LNq32Pseudo
|
|
UINT64_C(0), // VST3LNq32Pseudo_UPD
|
|
UINT64_C(4102031936), // VST3LNq32_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4093641807), // VST3d16
|
|
UINT64_C(0), // VST3d16Pseudo
|
|
UINT64_C(0), // VST3d16Pseudo_UPD
|
|
UINT64_C(4093641792), // VST3d16_UPD
|
|
UINT64_C(4093641871), // VST3d32
|
|
UINT64_C(0), // VST3d32Pseudo
|
|
UINT64_C(0), // VST3d32Pseudo_UPD
|
|
UINT64_C(4093641856), // VST3d32_UPD
|
|
UINT64_C(4093641743), // VST3d8
|
|
UINT64_C(0), // VST3d8Pseudo
|
|
UINT64_C(0), // VST3d8Pseudo_UPD
|
|
UINT64_C(4093641728), // VST3d8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4093642063), // VST3q16
|
|
UINT64_C(0), // VST3q16Pseudo_UPD
|
|
UINT64_C(4093642048), // VST3q16_UPD
|
|
UINT64_C(0), // VST3q16oddPseudo
|
|
UINT64_C(0), // VST3q16oddPseudo_UPD
|
|
UINT64_C(4093642127), // VST3q32
|
|
UINT64_C(0), // VST3q32Pseudo_UPD
|
|
UINT64_C(4093642112), // VST3q32_UPD
|
|
UINT64_C(0), // VST3q32oddPseudo
|
|
UINT64_C(0), // VST3q32oddPseudo_UPD
|
|
UINT64_C(4093641999), // VST3q8
|
|
UINT64_C(0), // VST3q8Pseudo_UPD
|
|
UINT64_C(4093641984), // VST3q8_UPD
|
|
UINT64_C(0), // VST3q8oddPseudo
|
|
UINT64_C(0), // VST3q8oddPseudo_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4102031119), // VST4LNd16
|
|
UINT64_C(0), // VST4LNd16Pseudo
|
|
UINT64_C(0), // VST4LNd16Pseudo_UPD
|
|
UINT64_C(4102031104), // VST4LNd16_UPD
|
|
UINT64_C(4102032143), // VST4LNd32
|
|
UINT64_C(0), // VST4LNd32Pseudo
|
|
UINT64_C(0), // VST4LNd32Pseudo_UPD
|
|
UINT64_C(4102032128), // VST4LNd32_UPD
|
|
UINT64_C(4102030095), // VST4LNd8
|
|
UINT64_C(0), // VST4LNd8Pseudo
|
|
UINT64_C(0), // VST4LNd8Pseudo_UPD
|
|
UINT64_C(4102030080), // VST4LNd8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4102031151), // VST4LNq16
|
|
UINT64_C(0), // VST4LNq16Pseudo
|
|
UINT64_C(0), // VST4LNq16Pseudo_UPD
|
|
UINT64_C(4102031136), // VST4LNq16_UPD
|
|
UINT64_C(4102032207), // VST4LNq32
|
|
UINT64_C(0), // VST4LNq32Pseudo
|
|
UINT64_C(0), // VST4LNq32Pseudo_UPD
|
|
UINT64_C(4102032192), // VST4LNq32_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4093640783), // VST4d16
|
|
UINT64_C(0), // VST4d16Pseudo
|
|
UINT64_C(0), // VST4d16Pseudo_UPD
|
|
UINT64_C(4093640768), // VST4d16_UPD
|
|
UINT64_C(4093640847), // VST4d32
|
|
UINT64_C(0), // VST4d32Pseudo
|
|
UINT64_C(0), // VST4d32Pseudo_UPD
|
|
UINT64_C(4093640832), // VST4d32_UPD
|
|
UINT64_C(4093640719), // VST4d8
|
|
UINT64_C(0), // VST4d8Pseudo
|
|
UINT64_C(0), // VST4d8Pseudo_UPD
|
|
UINT64_C(4093640704), // VST4d8_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4093641039), // VST4q16
|
|
UINT64_C(0), // VST4q16Pseudo_UPD
|
|
UINT64_C(4093641024), // VST4q16_UPD
|
|
UINT64_C(0), // VST4q16oddPseudo
|
|
UINT64_C(0), // VST4q16oddPseudo_UPD
|
|
UINT64_C(4093641103), // VST4q32
|
|
UINT64_C(0), // VST4q32Pseudo_UPD
|
|
UINT64_C(4093641088), // VST4q32_UPD
|
|
UINT64_C(0), // VST4q32oddPseudo
|
|
UINT64_C(0), // VST4q32oddPseudo_UPD
|
|
UINT64_C(4093640975), // VST4q8
|
|
UINT64_C(0), // VST4q8Pseudo_UPD
|
|
UINT64_C(4093640960), // VST4q8_UPD
|
|
UINT64_C(0), // VST4q8oddPseudo
|
|
UINT64_C(0), // VST4q8oddPseudo_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(220203776), // VSTMDDB_UPD
|
|
UINT64_C(209718016), // VSTMDIA
|
|
UINT64_C(211815168), // VSTMDIA_UPD
|
|
UINT64_C(0), // VSTMQIA
|
|
UINT64_C(220203520), // VSTMSDB_UPD
|
|
UINT64_C(209717760), // VSTMSIA
|
|
UINT64_C(211814912), // VSTMSIA_UPD
|
|
UINT64_C(218106624), // VSTRD
|
|
UINT64_C(218106112), // VSTRH
|
|
UINT64_C(218106368), // VSTRS
|
|
UINT64_C(238029632), // VSUBD
|
|
UINT64_C(238029120), // VSUBH
|
|
UINT64_C(4070573568), // VSUBHNv2i32
|
|
UINT64_C(4069524992), // VSUBHNv4i16
|
|
UINT64_C(4068476416), // VSUBHNv8i8
|
|
UINT64_C(4070572544), // VSUBLsv2i64
|
|
UINT64_C(4069523968), // VSUBLsv4i32
|
|
UINT64_C(4068475392), // VSUBLsv8i16
|
|
UINT64_C(4087349760), // VSUBLuv2i64
|
|
UINT64_C(4086301184), // VSUBLuv4i32
|
|
UINT64_C(4085252608), // VSUBLuv8i16
|
|
UINT64_C(238029376), // VSUBS
|
|
UINT64_C(4070572800), // VSUBWsv2i64
|
|
UINT64_C(4069524224), // VSUBWsv4i32
|
|
UINT64_C(4068475648), // VSUBWsv8i16
|
|
UINT64_C(4087350016), // VSUBWuv2i64
|
|
UINT64_C(4086301440), // VSUBWuv4i32
|
|
UINT64_C(4085252864), // VSUBWuv8i16
|
|
UINT64_C(4062186752), // VSUBfd
|
|
UINT64_C(4062186816), // VSUBfq
|
|
UINT64_C(4063235328), // VSUBhd
|
|
UINT64_C(4063235392), // VSUBhq
|
|
UINT64_C(4076865600), // VSUBv16i8
|
|
UINT64_C(4080011264), // VSUBv1i64
|
|
UINT64_C(4078962688), // VSUBv2i32
|
|
UINT64_C(4080011328), // VSUBv2i64
|
|
UINT64_C(4077914112), // VSUBv4i16
|
|
UINT64_C(4078962752), // VSUBv4i32
|
|
UINT64_C(4077914176), // VSUBv8i16
|
|
UINT64_C(4076865536), // VSUBv8i8
|
|
UINT64_C(4088528896), // VSWPd
|
|
UINT64_C(4088528960), // VSWPq
|
|
UINT64_C(4088399872), // VTBL1
|
|
UINT64_C(4088400128), // VTBL2
|
|
UINT64_C(4088400384), // VTBL3
|
|
UINT64_C(0), // VTBL3Pseudo
|
|
UINT64_C(4088400640), // VTBL4
|
|
UINT64_C(0), // VTBL4Pseudo
|
|
UINT64_C(4088399936), // VTBX1
|
|
UINT64_C(4088400192), // VTBX2
|
|
UINT64_C(4088400448), // VTBX3
|
|
UINT64_C(0), // VTBX3Pseudo
|
|
UINT64_C(4088400704), // VTBX4
|
|
UINT64_C(0), // VTBX4Pseudo
|
|
UINT64_C(247335744), // VTOSHD
|
|
UINT64_C(247335232), // VTOSHH
|
|
UINT64_C(247335488), // VTOSHS
|
|
UINT64_C(247270208), // VTOSIRD
|
|
UINT64_C(247269696), // VTOSIRH
|
|
UINT64_C(247269952), // VTOSIRS
|
|
UINT64_C(247270336), // VTOSIZD
|
|
UINT64_C(247269824), // VTOSIZH
|
|
UINT64_C(247270080), // VTOSIZS
|
|
UINT64_C(247335872), // VTOSLD
|
|
UINT64_C(247335360), // VTOSLH
|
|
UINT64_C(247335616), // VTOSLS
|
|
UINT64_C(247401280), // VTOUHD
|
|
UINT64_C(247400768), // VTOUHH
|
|
UINT64_C(247401024), // VTOUHS
|
|
UINT64_C(247204672), // VTOUIRD
|
|
UINT64_C(247204160), // VTOUIRH
|
|
UINT64_C(247204416), // VTOUIRS
|
|
UINT64_C(247204800), // VTOUIZD
|
|
UINT64_C(247204288), // VTOUIZH
|
|
UINT64_C(247204544), // VTOUIZS
|
|
UINT64_C(247401408), // VTOULD
|
|
UINT64_C(247400896), // VTOULH
|
|
UINT64_C(247401152), // VTOULS
|
|
UINT64_C(4088791168), // VTRNd16
|
|
UINT64_C(4089053312), // VTRNd32
|
|
UINT64_C(4088529024), // VTRNd8
|
|
UINT64_C(4088791232), // VTRNq16
|
|
UINT64_C(4089053376), // VTRNq32
|
|
UINT64_C(4088529088), // VTRNq8
|
|
UINT64_C(4060088400), // VTSTv16i8
|
|
UINT64_C(4062185488), // VTSTv2i32
|
|
UINT64_C(4061136912), // VTSTv4i16
|
|
UINT64_C(4062185552), // VTSTv4i32
|
|
UINT64_C(4061136976), // VTSTv8i16
|
|
UINT64_C(4060088336), // VTSTv8i8
|
|
UINT64_C(247139136), // VUHTOD
|
|
UINT64_C(247138624), // VUHTOH
|
|
UINT64_C(247138880), // VUHTOS
|
|
UINT64_C(246942528), // VUITOD
|
|
UINT64_C(246942016), // VUITOH
|
|
UINT64_C(246942272), // VUITOS
|
|
UINT64_C(247139264), // VULTOD
|
|
UINT64_C(247138752), // VULTOH
|
|
UINT64_C(247139008), // VULTOS
|
|
UINT64_C(4088791296), // VUZPd16
|
|
UINT64_C(4088529152), // VUZPd8
|
|
UINT64_C(4088791360), // VUZPq16
|
|
UINT64_C(4089053504), // VUZPq32
|
|
UINT64_C(4088529216), // VUZPq8
|
|
UINT64_C(4088791424), // VZIPd16
|
|
UINT64_C(4088529280), // VZIPd8
|
|
UINT64_C(4088791488), // VZIPq16
|
|
UINT64_C(4089053632), // VZIPq32
|
|
UINT64_C(4088529344), // VZIPq8
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(139460608), // sysLDMDA
|
|
UINT64_C(141557760), // sysLDMDA_UPD
|
|
UINT64_C(156237824), // sysLDMDB
|
|
UINT64_C(158334976), // sysLDMDB_UPD
|
|
UINT64_C(147849216), // sysLDMIA
|
|
UINT64_C(149946368), // sysLDMIA_UPD
|
|
UINT64_C(164626432), // sysLDMIB
|
|
UINT64_C(166723584), // sysLDMIB_UPD
|
|
UINT64_C(138412032), // sysSTMDA
|
|
UINT64_C(140509184), // sysSTMDA_UPD
|
|
UINT64_C(155189248), // sysSTMDB
|
|
UINT64_C(157286400), // sysSTMDB_UPD
|
|
UINT64_C(146800640), // sysSTMIA
|
|
UINT64_C(148897792), // sysSTMIA_UPD
|
|
UINT64_C(163577856), // sysSTMIB
|
|
UINT64_C(165675008), // sysSTMIB_UPD
|
|
UINT64_C(0),
|
|
UINT64_C(4047503360), // t2ADCri
|
|
UINT64_C(3946840064), // t2ADCrr
|
|
UINT64_C(3946840064), // t2ADCrs
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4043309056), // t2ADDri
|
|
UINT64_C(4060086272), // t2ADDri12
|
|
UINT64_C(3942645760), // t2ADDrr
|
|
UINT64_C(3942645760), // t2ADDrs
|
|
UINT64_C(4061069312), // t2ADR
|
|
UINT64_C(4026531840), // t2ANDri
|
|
UINT64_C(3925868544), // t2ANDrr
|
|
UINT64_C(3925868544), // t2ANDrs
|
|
UINT64_C(3931045920), // t2ASRri
|
|
UINT64_C(4198559744), // t2ASRrr
|
|
UINT64_C(4026568704), // t2B
|
|
UINT64_C(4084137984), // t2BFC
|
|
UINT64_C(4083154944), // t2BFI
|
|
UINT64_C(4028628992), // t2BICri
|
|
UINT64_C(3927965696), // t2BICrr
|
|
UINT64_C(3927965696), // t2BICrs
|
|
UINT64_C(0),
|
|
UINT64_C(4089483008), // t2BXJ
|
|
UINT64_C(4026564608), // t2Bcc
|
|
UINT64_C(3992977408), // t2CDP
|
|
UINT64_C(4261412864), // t2CDP2
|
|
UINT64_C(4089417519), // t2CLREX
|
|
UINT64_C(4205899904), // t2CLZ
|
|
UINT64_C(4044361472), // t2CMNri
|
|
UINT64_C(3943698176), // t2CMNzrr
|
|
UINT64_C(3943698176), // t2CMNzrs
|
|
UINT64_C(4054847232), // t2CMPri
|
|
UINT64_C(3954183936), // t2CMPrr
|
|
UINT64_C(3954183936), // t2CMPrs
|
|
UINT64_C(4088365312), // t2CPS1p
|
|
UINT64_C(4088365056), // t2CPS2p
|
|
UINT64_C(4088365312), // t2CPS3p
|
|
UINT64_C(4206948480), // t2CRC32B
|
|
UINT64_C(4207997056), // t2CRC32CB
|
|
UINT64_C(4207997072), // t2CRC32CH
|
|
UINT64_C(4207997088), // t2CRC32CW
|
|
UINT64_C(4206948496), // t2CRC32H
|
|
UINT64_C(4206948512), // t2CRC32W
|
|
UINT64_C(4088365296), // t2DBG
|
|
UINT64_C(4153376769), // t2DCPS1
|
|
UINT64_C(4153376770), // t2DCPS2
|
|
UINT64_C(4153376771), // t2DCPS3
|
|
UINT64_C(4089417552), // t2DMB
|
|
UINT64_C(4089417536), // t2DSB
|
|
UINT64_C(4034920448), // t2EORri
|
|
UINT64_C(3934257152), // t2EORrr
|
|
UINT64_C(3934257152), // t2EORrs
|
|
UINT64_C(4088365056), // t2HINT
|
|
UINT64_C(4158685184), // t2HVC
|
|
UINT64_C(4089417568), // t2ISB
|
|
UINT64_C(48896), // t2IT
|
|
UINT64_C(0), // t2Int_eh_sjlj_setjmp
|
|
UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp
|
|
UINT64_C(3905949615), // t2LDA
|
|
UINT64_C(3905949583), // t2LDAB
|
|
UINT64_C(3905949679), // t2LDAEX
|
|
UINT64_C(3905949647), // t2LDAEXB
|
|
UINT64_C(3905945855), // t2LDAEXD
|
|
UINT64_C(3905949663), // t2LDAEXH
|
|
UINT64_C(3905949599), // t2LDAH
|
|
UINT64_C(4249878528), // t2LDC2L_OFFSET
|
|
UINT64_C(4241489920), // t2LDC2L_OPTION
|
|
UINT64_C(4235198464), // t2LDC2L_POST
|
|
UINT64_C(4251975680), // t2LDC2L_PRE
|
|
UINT64_C(4245684224), // t2LDC2_OFFSET
|
|
UINT64_C(4237295616), // t2LDC2_OPTION
|
|
UINT64_C(4231004160), // t2LDC2_POST
|
|
UINT64_C(4247781376), // t2LDC2_PRE
|
|
UINT64_C(3981443072), // t2LDCL_OFFSET
|
|
UINT64_C(3973054464), // t2LDCL_OPTION
|
|
UINT64_C(3966763008), // t2LDCL_POST
|
|
UINT64_C(3983540224), // t2LDCL_PRE
|
|
UINT64_C(3977248768), // t2LDC_OFFSET
|
|
UINT64_C(3968860160), // t2LDC_OPTION
|
|
UINT64_C(3962568704), // t2LDC_POST
|
|
UINT64_C(3979345920), // t2LDC_PRE
|
|
UINT64_C(3910139904), // t2LDMDB
|
|
UINT64_C(3912237056), // t2LDMDB_UPD
|
|
UINT64_C(3901751296), // t2LDMIA
|
|
UINT64_C(0),
|
|
UINT64_C(3903848448), // t2LDMIA_UPD
|
|
UINT64_C(4161801728), // t2LDRBT
|
|
UINT64_C(4161800448), // t2LDRB_POST
|
|
UINT64_C(4161801472), // t2LDRB_PRE
|
|
UINT64_C(4170186752), // t2LDRBi12
|
|
UINT64_C(4161801216), // t2LDRBi8
|
|
UINT64_C(4162781184), // t2LDRBpci
|
|
UINT64_C(0),
|
|
UINT64_C(4161798144), // t2LDRBs
|
|
UINT64_C(3899654144), // t2LDRD_POST
|
|
UINT64_C(3916431360), // t2LDRD_PRE
|
|
UINT64_C(3914334208), // t2LDRDi8
|
|
UINT64_C(3897560832), // t2LDREX
|
|
UINT64_C(3905949519), // t2LDREXB
|
|
UINT64_C(3905945727), // t2LDREXD
|
|
UINT64_C(3905949535), // t2LDREXH
|
|
UINT64_C(4163898880), // t2LDRHT
|
|
UINT64_C(4163897600), // t2LDRH_POST
|
|
UINT64_C(4163898624), // t2LDRH_PRE
|
|
UINT64_C(4172283904), // t2LDRHi12
|
|
UINT64_C(4163898368), // t2LDRHi8
|
|
UINT64_C(4164878336), // t2LDRHpci
|
|
UINT64_C(0),
|
|
UINT64_C(4163895296), // t2LDRHs
|
|
UINT64_C(4178578944), // t2LDRSBT
|
|
UINT64_C(4178577664), // t2LDRSB_POST
|
|
UINT64_C(4178578688), // t2LDRSB_PRE
|
|
UINT64_C(4186963968), // t2LDRSBi12
|
|
UINT64_C(4178578432), // t2LDRSBi8
|
|
UINT64_C(4179558400), // t2LDRSBpci
|
|
UINT64_C(0),
|
|
UINT64_C(4178575360), // t2LDRSBs
|
|
UINT64_C(4180676096), // t2LDRSHT
|
|
UINT64_C(4180674816), // t2LDRSH_POST
|
|
UINT64_C(4180675840), // t2LDRSH_PRE
|
|
UINT64_C(4189061120), // t2LDRSHi12
|
|
UINT64_C(4180675584), // t2LDRSHi8
|
|
UINT64_C(4181655552), // t2LDRSHpci
|
|
UINT64_C(0),
|
|
UINT64_C(4180672512), // t2LDRSHs
|
|
UINT64_C(4165996032), // t2LDRT
|
|
UINT64_C(4165994752), // t2LDR_POST
|
|
UINT64_C(4165995776), // t2LDR_PRE
|
|
UINT64_C(4174381056), // t2LDRi12
|
|
UINT64_C(4165995520), // t2LDRi8
|
|
UINT64_C(4166975488), // t2LDRpci
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4165992448), // t2LDRs
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(3931045888), // t2LSLri
|
|
UINT64_C(4194365440), // t2LSLrr
|
|
UINT64_C(3931045904), // t2LSRri
|
|
UINT64_C(4196462592), // t2LSRrr
|
|
UINT64_C(3992977424), // t2MCR
|
|
UINT64_C(4261412880), // t2MCR2
|
|
UINT64_C(3963617280), // t2MCRR
|
|
UINT64_C(4232052736), // t2MCRR2
|
|
UINT64_C(4211081216), // t2MLA
|
|
UINT64_C(4211081232), // t2MLS
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4072669184), // t2MOVTi16
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4031709184), // t2MOVi
|
|
UINT64_C(4064280576), // t2MOVi16
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(3931045888), // t2MOVr
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(3932094560), // t2MOVsra_flag
|
|
UINT64_C(3932094544), // t2MOVsrl_flag
|
|
UINT64_C(3994026000), // t2MRC
|
|
UINT64_C(4262461456), // t2MRC2
|
|
UINT64_C(3964665856), // t2MRRC
|
|
UINT64_C(4233101312), // t2MRRC2
|
|
UINT64_C(4092559360), // t2MRS_AR
|
|
UINT64_C(4092559360), // t2MRS_M
|
|
UINT64_C(4091576352), // t2MRSbanked
|
|
UINT64_C(4093607936), // t2MRSsys_AR
|
|
UINT64_C(4085284864), // t2MSR_AR
|
|
UINT64_C(4085284864), // t2MSR_M
|
|
UINT64_C(4085284896), // t2MSRbanked
|
|
UINT64_C(4211142656), // t2MUL
|
|
UINT64_C(0),
|
|
UINT64_C(4033806336), // t2MVNi
|
|
UINT64_C(3933143040), // t2MVNr
|
|
UINT64_C(3933143040), // t2MVNs
|
|
UINT64_C(4032823296), // t2ORNri
|
|
UINT64_C(3932160000), // t2ORNrr
|
|
UINT64_C(3932160000), // t2ORNrs
|
|
UINT64_C(4030726144), // t2ORRri
|
|
UINT64_C(3930062848), // t2ORRrr
|
|
UINT64_C(3930062848), // t2ORRrs
|
|
UINT64_C(3938451456), // t2PKHBT
|
|
UINT64_C(3938451488), // t2PKHTB
|
|
UINT64_C(4172345344), // t2PLDWi12
|
|
UINT64_C(4163959808), // t2PLDWi8
|
|
UINT64_C(4163956736), // t2PLDWs
|
|
UINT64_C(4170248192), // t2PLDi12
|
|
UINT64_C(4161862656), // t2PLDi8
|
|
UINT64_C(4162842624), // t2PLDpci
|
|
UINT64_C(4161859584), // t2PLDs
|
|
UINT64_C(4187025408), // t2PLIi12
|
|
UINT64_C(4178639872), // t2PLIi8
|
|
UINT64_C(4179619840), // t2PLIpci
|
|
UINT64_C(4178636800), // t2PLIs
|
|
UINT64_C(4202754176), // t2QADD
|
|
UINT64_C(4203802640), // t2QADD16
|
|
UINT64_C(4202754064), // t2QADD8
|
|
UINT64_C(4204851216), // t2QASX
|
|
UINT64_C(4202754192), // t2QDADD
|
|
UINT64_C(4202754224), // t2QDSUB
|
|
UINT64_C(4209045520), // t2QSAX
|
|
UINT64_C(4202754208), // t2QSUB
|
|
UINT64_C(4207996944), // t2QSUB16
|
|
UINT64_C(4206948368), // t2QSUB8
|
|
UINT64_C(4203802784), // t2RBIT
|
|
UINT64_C(4203802752), // t2REV
|
|
UINT64_C(4203802768), // t2REV16
|
|
UINT64_C(4203802800), // t2REVSH
|
|
UINT64_C(3893411840), // t2RFEDB
|
|
UINT64_C(3895508992), // t2RFEDBW
|
|
UINT64_C(3918577664), // t2RFEIA
|
|
UINT64_C(3920674816), // t2RFEIAW
|
|
UINT64_C(3931045936), // t2RORri
|
|
UINT64_C(4200656896), // t2RORrr
|
|
UINT64_C(3931045936), // t2RRX
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4055891968), // t2RSBri
|
|
UINT64_C(3955228672), // t2RSBrr
|
|
UINT64_C(3955228672), // t2RSBrs
|
|
UINT64_C(4203802624), // t2SADD16
|
|
UINT64_C(4202754048), // t2SADD8
|
|
UINT64_C(4204851200), // t2SASX
|
|
UINT64_C(4049600512), // t2SBCri
|
|
UINT64_C(3948937216), // t2SBCrr
|
|
UINT64_C(3948937216), // t2SBCrs
|
|
UINT64_C(4081057792), // t2SBFX
|
|
UINT64_C(4220580080), // t2SDIV
|
|
UINT64_C(4204851328), // t2SEL
|
|
UINT64_C(46608), // t2SETPAN
|
|
UINT64_C(3917474175), // t2SG
|
|
UINT64_C(4203802656), // t2SHADD16
|
|
UINT64_C(4202754080), // t2SHADD8
|
|
UINT64_C(4204851232), // t2SHASX
|
|
UINT64_C(4209045536), // t2SHSAX
|
|
UINT64_C(4207996960), // t2SHSUB16
|
|
UINT64_C(4206948384), // t2SHSUB8
|
|
UINT64_C(4159733760), // t2SMC
|
|
UINT64_C(4212129792), // t2SMLABB
|
|
UINT64_C(4212129808), // t2SMLABT
|
|
UINT64_C(4213178368), // t2SMLAD
|
|
UINT64_C(4213178384), // t2SMLADX
|
|
UINT64_C(4223664128), // t2SMLAL
|
|
UINT64_C(4223664256), // t2SMLALBB
|
|
UINT64_C(4223664272), // t2SMLALBT
|
|
UINT64_C(4223664320), // t2SMLALD
|
|
UINT64_C(4223664336), // t2SMLALDX
|
|
UINT64_C(4223664288), // t2SMLALTB
|
|
UINT64_C(4223664304), // t2SMLALTT
|
|
UINT64_C(4212129824), // t2SMLATB
|
|
UINT64_C(4212129840), // t2SMLATT
|
|
UINT64_C(4214226944), // t2SMLAWB
|
|
UINT64_C(4214226960), // t2SMLAWT
|
|
UINT64_C(4215275520), // t2SMLSD
|
|
UINT64_C(4215275536), // t2SMLSDX
|
|
UINT64_C(4224712896), // t2SMLSLD
|
|
UINT64_C(4224712912), // t2SMLSLDX
|
|
UINT64_C(4216324096), // t2SMMLA
|
|
UINT64_C(4216324112), // t2SMMLAR
|
|
UINT64_C(4217372672), // t2SMMLS
|
|
UINT64_C(4217372688), // t2SMMLSR
|
|
UINT64_C(4216385536), // t2SMMUL
|
|
UINT64_C(4216385552), // t2SMMULR
|
|
UINT64_C(4213239808), // t2SMUAD
|
|
UINT64_C(4213239824), // t2SMUADX
|
|
UINT64_C(4212191232), // t2SMULBB
|
|
UINT64_C(4212191248), // t2SMULBT
|
|
UINT64_C(4219469824), // t2SMULL
|
|
UINT64_C(4212191264), // t2SMULTB
|
|
UINT64_C(4212191280), // t2SMULTT
|
|
UINT64_C(4214288384), // t2SMULWB
|
|
UINT64_C(4214288400), // t2SMULWT
|
|
UINT64_C(4215336960), // t2SMUSD
|
|
UINT64_C(4215336976), // t2SMUSDX
|
|
UINT64_C(3893215232), // t2SRSDB
|
|
UINT64_C(3895312384), // t2SRSDB_UPD
|
|
UINT64_C(3918381056), // t2SRSIA
|
|
UINT64_C(3920478208), // t2SRSIA_UPD
|
|
UINT64_C(4076863488), // t2SSAT
|
|
UINT64_C(4078960640), // t2SSAT16
|
|
UINT64_C(4209045504), // t2SSAX
|
|
UINT64_C(4207996928), // t2SSUB16
|
|
UINT64_C(4206948352), // t2SSUB8
|
|
UINT64_C(4248829952), // t2STC2L_OFFSET
|
|
UINT64_C(4240441344), // t2STC2L_OPTION
|
|
UINT64_C(4234149888), // t2STC2L_POST
|
|
UINT64_C(4250927104), // t2STC2L_PRE
|
|
UINT64_C(4244635648), // t2STC2_OFFSET
|
|
UINT64_C(4236247040), // t2STC2_OPTION
|
|
UINT64_C(4229955584), // t2STC2_POST
|
|
UINT64_C(4246732800), // t2STC2_PRE
|
|
UINT64_C(3980394496), // t2STCL_OFFSET
|
|
UINT64_C(3972005888), // t2STCL_OPTION
|
|
UINT64_C(3965714432), // t2STCL_POST
|
|
UINT64_C(3982491648), // t2STCL_PRE
|
|
UINT64_C(3976200192), // t2STC_OFFSET
|
|
UINT64_C(3967811584), // t2STC_OPTION
|
|
UINT64_C(3961520128), // t2STC_POST
|
|
UINT64_C(3978297344), // t2STC_PRE
|
|
UINT64_C(3904901039), // t2STL
|
|
UINT64_C(3904901007), // t2STLB
|
|
UINT64_C(3904901088), // t2STLEX
|
|
UINT64_C(3904901056), // t2STLEXB
|
|
UINT64_C(3904897264), // t2STLEXD
|
|
UINT64_C(3904901072), // t2STLEXH
|
|
UINT64_C(3904901023), // t2STLH
|
|
UINT64_C(3909091328), // t2STMDB
|
|
UINT64_C(3911188480), // t2STMDB_UPD
|
|
UINT64_C(3900702720), // t2STMIA
|
|
UINT64_C(3902799872), // t2STMIA_UPD
|
|
UINT64_C(4160753152), // t2STRBT
|
|
UINT64_C(4160751872), // t2STRB_POST
|
|
UINT64_C(4160752896), // t2STRB_PRE
|
|
UINT64_C(0),
|
|
UINT64_C(4169138176), // t2STRBi12
|
|
UINT64_C(4160752640), // t2STRBi8
|
|
UINT64_C(4160749568), // t2STRBs
|
|
UINT64_C(3898605568), // t2STRD_POST
|
|
UINT64_C(3915382784), // t2STRD_PRE
|
|
UINT64_C(3913285632), // t2STRDi8
|
|
UINT64_C(3896508416), // t2STREX
|
|
UINT64_C(3904900928), // t2STREXB
|
|
UINT64_C(3904897136), // t2STREXD
|
|
UINT64_C(3904900944), // t2STREXH
|
|
UINT64_C(4162850304), // t2STRHT
|
|
UINT64_C(4162849024), // t2STRH_POST
|
|
UINT64_C(4162850048), // t2STRH_PRE
|
|
UINT64_C(0),
|
|
UINT64_C(4171235328), // t2STRHi12
|
|
UINT64_C(4162849792), // t2STRHi8
|
|
UINT64_C(4162846720), // t2STRHs
|
|
UINT64_C(4164947456), // t2STRT
|
|
UINT64_C(4164946176), // t2STR_POST
|
|
UINT64_C(4164947200), // t2STR_PRE
|
|
UINT64_C(0),
|
|
UINT64_C(4173332480), // t2STRi12
|
|
UINT64_C(4164946944), // t2STRi8
|
|
UINT64_C(4164943872), // t2STRs
|
|
UINT64_C(4091449088), // t2SUBS_PC_LR
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(4053794816), // t2SUBri
|
|
UINT64_C(4070572032), // t2SUBri12
|
|
UINT64_C(3953131520), // t2SUBrr
|
|
UINT64_C(3953131520), // t2SUBrs
|
|
UINT64_C(4198559872), // t2SXTAB
|
|
UINT64_C(4196462720), // t2SXTAB16
|
|
UINT64_C(4194365568), // t2SXTAH
|
|
UINT64_C(4199542912), // t2SXTB
|
|
UINT64_C(4197445760), // t2SXTB16
|
|
UINT64_C(4195348608), // t2SXTH
|
|
UINT64_C(3906007040), // t2TBB
|
|
UINT64_C(0),
|
|
UINT64_C(3906007056), // t2TBH
|
|
UINT64_C(0),
|
|
UINT64_C(4035972864), // t2TEQri
|
|
UINT64_C(3935309568), // t2TEQrr
|
|
UINT64_C(3935309568), // t2TEQrs
|
|
UINT64_C(4027584256), // t2TSTri
|
|
UINT64_C(3926920960), // t2TSTrr
|
|
UINT64_C(3926920960), // t2TSTrs
|
|
UINT64_C(3896569856), // t2TT
|
|
UINT64_C(3896569984), // t2TTA
|
|
UINT64_C(3896570048), // t2TTAT
|
|
UINT64_C(3896569920), // t2TTT
|
|
UINT64_C(4203802688), // t2UADD16
|
|
UINT64_C(4202754112), // t2UADD8
|
|
UINT64_C(4204851264), // t2UASX
|
|
UINT64_C(4089446400), // t2UBFX
|
|
UINT64_C(4159741952), // t2UDF
|
|
UINT64_C(4222677232), // t2UDIV
|
|
UINT64_C(4203802720), // t2UHADD16
|
|
UINT64_C(4202754144), // t2UHADD8
|
|
UINT64_C(4204851296), // t2UHASX
|
|
UINT64_C(4209045600), // t2UHSAX
|
|
UINT64_C(4207997024), // t2UHSUB16
|
|
UINT64_C(4206948448), // t2UHSUB8
|
|
UINT64_C(4225761376), // t2UMAAL
|
|
UINT64_C(4225761280), // t2UMLAL
|
|
UINT64_C(4221566976), // t2UMULL
|
|
UINT64_C(4203802704), // t2UQADD16
|
|
UINT64_C(4202754128), // t2UQADD8
|
|
UINT64_C(4204851280), // t2UQASX
|
|
UINT64_C(4209045584), // t2UQSAX
|
|
UINT64_C(4207997008), // t2UQSUB16
|
|
UINT64_C(4206948432), // t2UQSUB8
|
|
UINT64_C(4218482688), // t2USAD8
|
|
UINT64_C(4218421248), // t2USADA8
|
|
UINT64_C(4085252096), // t2USAT
|
|
UINT64_C(4087349248), // t2USAT16
|
|
UINT64_C(4209045568), // t2USAX
|
|
UINT64_C(4207996992), // t2USUB16
|
|
UINT64_C(4206948416), // t2USUB8
|
|
UINT64_C(4199608448), // t2UXTAB
|
|
UINT64_C(4197511296), // t2UXTAB16
|
|
UINT64_C(4195414144), // t2UXTAH
|
|
UINT64_C(4200591488), // t2UXTB
|
|
UINT64_C(4198494336), // t2UXTB16
|
|
UINT64_C(4196397184), // t2UXTH
|
|
UINT64_C(16704), // tADC
|
|
UINT64_C(0),
|
|
UINT64_C(17408), // tADDhirr
|
|
UINT64_C(7168), // tADDi3
|
|
UINT64_C(12288), // tADDi8
|
|
UINT64_C(17512), // tADDrSP
|
|
UINT64_C(43008), // tADDrSPi
|
|
UINT64_C(6144), // tADDrr
|
|
UINT64_C(45056), // tADDspi
|
|
UINT64_C(17541), // tADDspr
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(40960), // tADR
|
|
UINT64_C(16384), // tAND
|
|
UINT64_C(4096), // tASRri
|
|
UINT64_C(16640), // tASRrr
|
|
UINT64_C(57344), // tB
|
|
UINT64_C(17280), // tBIC
|
|
UINT64_C(48640), // tBKPT
|
|
UINT64_C(4026585088), // tBL
|
|
UINT64_C(18308), // tBLXNSr
|
|
UINT64_C(4026580992), // tBLXi
|
|
UINT64_C(18304), // tBLXr
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(18176), // tBX
|
|
UINT64_C(18180), // tBXNS
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(53248), // tBcc
|
|
UINT64_C(0),
|
|
UINT64_C(47360), // tCBNZ
|
|
UINT64_C(45312), // tCBZ
|
|
UINT64_C(17088), // tCMNz
|
|
UINT64_C(17664), // tCMPhir
|
|
UINT64_C(10240), // tCMPi8
|
|
UINT64_C(17024), // tCMPr
|
|
UINT64_C(46688), // tCPS
|
|
UINT64_C(16448), // tEOR
|
|
UINT64_C(48896), // tHINT
|
|
UINT64_C(47744), // tHLT
|
|
UINT64_C(0), // tInt_eh_sjlj_longjmp
|
|
UINT64_C(0), // tInt_eh_sjlj_setjmp
|
|
UINT64_C(51200), // tLDMIA
|
|
UINT64_C(0),
|
|
UINT64_C(30720), // tLDRBi
|
|
UINT64_C(23552), // tLDRBr
|
|
UINT64_C(34816), // tLDRHi
|
|
UINT64_C(23040), // tLDRHr
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(22016), // tLDRSB
|
|
UINT64_C(24064), // tLDRSH
|
|
UINT64_C(26624), // tLDRi
|
|
UINT64_C(18432), // tLDRpci
|
|
UINT64_C(0),
|
|
UINT64_C(22528), // tLDRr
|
|
UINT64_C(38912), // tLDRspi
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0), // tLSLri
|
|
UINT64_C(16512), // tLSLrr
|
|
UINT64_C(2048), // tLSRri
|
|
UINT64_C(16576), // tLSRrr
|
|
UINT64_C(0),
|
|
UINT64_C(0), // tMOVSr
|
|
UINT64_C(8192), // tMOVi8
|
|
UINT64_C(17920), // tMOVr
|
|
UINT64_C(17216), // tMUL
|
|
UINT64_C(17344), // tMVN
|
|
UINT64_C(17152), // tORR
|
|
UINT64_C(17528), // tPICADD
|
|
UINT64_C(48128), // tPOP
|
|
UINT64_C(0),
|
|
UINT64_C(46080), // tPUSH
|
|
UINT64_C(47616), // tREV
|
|
UINT64_C(47680), // tREV16
|
|
UINT64_C(47808), // tREVSH
|
|
UINT64_C(16832), // tROR
|
|
UINT64_C(16960), // tRSB
|
|
UINT64_C(16768), // tSBC
|
|
UINT64_C(46672), // tSETEND
|
|
UINT64_C(49152), // tSTMIA_UPD
|
|
UINT64_C(28672), // tSTRBi
|
|
UINT64_C(21504), // tSTRBr
|
|
UINT64_C(32768), // tSTRHi
|
|
UINT64_C(20992), // tSTRHr
|
|
UINT64_C(24576), // tSTRi
|
|
UINT64_C(20480), // tSTRr
|
|
UINT64_C(36864), // tSTRspi
|
|
UINT64_C(7680), // tSUBi3
|
|
UINT64_C(14336), // tSUBi8
|
|
UINT64_C(6656), // tSUBrr
|
|
UINT64_C(45184), // tSUBspi
|
|
UINT64_C(57088), // tSVC
|
|
UINT64_C(45632), // tSXTB
|
|
UINT64_C(45568), // tSXTH
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(0),
|
|
UINT64_C(57086), // tTRAP
|
|
UINT64_C(16896), // tTST
|
|
UINT64_C(56832), // tUDF
|
|
UINT64_C(45760), // tUXTB
|
|
UINT64_C(45696), // tUXTH
|
|
UINT64_C(0)
|
|
};
|
|
const unsigned opcode = MI.getOpcode();
|
|
uint64_t Value = InstBits[opcode];
|
|
uint64_t op = 0;
|
|
(void)op; // suppress warning
|
|
switch (opcode) {
|
|
case ARM::CLREX:
|
|
case ARM::TRAP:
|
|
case ARM::TRAPNaCl:
|
|
case ARM::VLD1LNq16Pseudo:
|
|
case ARM::VLD1LNq16Pseudo_UPD:
|
|
case ARM::VLD1LNq32Pseudo:
|
|
case ARM::VLD1LNq32Pseudo_UPD:
|
|
case ARM::VLD1LNq8Pseudo:
|
|
case ARM::VLD1LNq8Pseudo_UPD:
|
|
case ARM::VLD1d64QPseudo:
|
|
case ARM::VLD1d64QPseudoWB_fixed:
|
|
case ARM::VLD1d64QPseudoWB_register:
|
|
case ARM::VLD1d64TPseudo:
|
|
case ARM::VLD1d64TPseudoWB_fixed:
|
|
case ARM::VLD1d64TPseudoWB_register:
|
|
case ARM::VLD2LNd16Pseudo:
|
|
case ARM::VLD2LNd16Pseudo_UPD:
|
|
case ARM::VLD2LNd32Pseudo:
|
|
case ARM::VLD2LNd32Pseudo_UPD:
|
|
case ARM::VLD2LNd8Pseudo:
|
|
case ARM::VLD2LNd8Pseudo_UPD:
|
|
case ARM::VLD2LNq16Pseudo:
|
|
case ARM::VLD2LNq16Pseudo_UPD:
|
|
case ARM::VLD2LNq32Pseudo:
|
|
case ARM::VLD2LNq32Pseudo_UPD:
|
|
case ARM::VLD2q16Pseudo:
|
|
case ARM::VLD2q16PseudoWB_fixed:
|
|
case ARM::VLD2q16PseudoWB_register:
|
|
case ARM::VLD2q32Pseudo:
|
|
case ARM::VLD2q32PseudoWB_fixed:
|
|
case ARM::VLD2q32PseudoWB_register:
|
|
case ARM::VLD2q8Pseudo:
|
|
case ARM::VLD2q8PseudoWB_fixed:
|
|
case ARM::VLD2q8PseudoWB_register:
|
|
case ARM::VLD3DUPd16Pseudo:
|
|
case ARM::VLD3DUPd16Pseudo_UPD:
|
|
case ARM::VLD3DUPd32Pseudo:
|
|
case ARM::VLD3DUPd32Pseudo_UPD:
|
|
case ARM::VLD3DUPd8Pseudo:
|
|
case ARM::VLD3DUPd8Pseudo_UPD:
|
|
case ARM::VLD3LNd16Pseudo:
|
|
case ARM::VLD3LNd16Pseudo_UPD:
|
|
case ARM::VLD3LNd32Pseudo:
|
|
case ARM::VLD3LNd32Pseudo_UPD:
|
|
case ARM::VLD3LNd8Pseudo:
|
|
case ARM::VLD3LNd8Pseudo_UPD:
|
|
case ARM::VLD3LNq16Pseudo:
|
|
case ARM::VLD3LNq16Pseudo_UPD:
|
|
case ARM::VLD3LNq32Pseudo:
|
|
case ARM::VLD3LNq32Pseudo_UPD:
|
|
case ARM::VLD3d16Pseudo:
|
|
case ARM::VLD3d16Pseudo_UPD:
|
|
case ARM::VLD3d32Pseudo:
|
|
case ARM::VLD3d32Pseudo_UPD:
|
|
case ARM::VLD3d8Pseudo:
|
|
case ARM::VLD3d8Pseudo_UPD:
|
|
case ARM::VLD3q16Pseudo_UPD:
|
|
case ARM::VLD3q16oddPseudo:
|
|
case ARM::VLD3q16oddPseudo_UPD:
|
|
case ARM::VLD3q32Pseudo_UPD:
|
|
case ARM::VLD3q32oddPseudo:
|
|
case ARM::VLD3q32oddPseudo_UPD:
|
|
case ARM::VLD3q8Pseudo_UPD:
|
|
case ARM::VLD3q8oddPseudo:
|
|
case ARM::VLD3q8oddPseudo_UPD:
|
|
case ARM::VLD4DUPd16Pseudo:
|
|
case ARM::VLD4DUPd16Pseudo_UPD:
|
|
case ARM::VLD4DUPd32Pseudo:
|
|
case ARM::VLD4DUPd32Pseudo_UPD:
|
|
case ARM::VLD4DUPd8Pseudo:
|
|
case ARM::VLD4DUPd8Pseudo_UPD:
|
|
case ARM::VLD4LNd16Pseudo:
|
|
case ARM::VLD4LNd16Pseudo_UPD:
|
|
case ARM::VLD4LNd32Pseudo:
|
|
case ARM::VLD4LNd32Pseudo_UPD:
|
|
case ARM::VLD4LNd8Pseudo:
|
|
case ARM::VLD4LNd8Pseudo_UPD:
|
|
case ARM::VLD4LNq16Pseudo:
|
|
case ARM::VLD4LNq16Pseudo_UPD:
|
|
case ARM::VLD4LNq32Pseudo:
|
|
case ARM::VLD4LNq32Pseudo_UPD:
|
|
case ARM::VLD4d16Pseudo:
|
|
case ARM::VLD4d16Pseudo_UPD:
|
|
case ARM::VLD4d32Pseudo:
|
|
case ARM::VLD4d32Pseudo_UPD:
|
|
case ARM::VLD4d8Pseudo:
|
|
case ARM::VLD4d8Pseudo_UPD:
|
|
case ARM::VLD4q16Pseudo_UPD:
|
|
case ARM::VLD4q16oddPseudo:
|
|
case ARM::VLD4q16oddPseudo_UPD:
|
|
case ARM::VLD4q32Pseudo_UPD:
|
|
case ARM::VLD4q32oddPseudo:
|
|
case ARM::VLD4q32oddPseudo_UPD:
|
|
case ARM::VLD4q8Pseudo_UPD:
|
|
case ARM::VLD4q8oddPseudo:
|
|
case ARM::VLD4q8oddPseudo_UPD:
|
|
case ARM::VLDMQIA:
|
|
case ARM::VST1LNq16Pseudo:
|
|
case ARM::VST1LNq16Pseudo_UPD:
|
|
case ARM::VST1LNq32Pseudo:
|
|
case ARM::VST1LNq32Pseudo_UPD:
|
|
case ARM::VST1LNq8Pseudo:
|
|
case ARM::VST1LNq8Pseudo_UPD:
|
|
case ARM::VST1d64QPseudo:
|
|
case ARM::VST1d64QPseudoWB_fixed:
|
|
case ARM::VST1d64QPseudoWB_register:
|
|
case ARM::VST1d64TPseudo:
|
|
case ARM::VST1d64TPseudoWB_fixed:
|
|
case ARM::VST1d64TPseudoWB_register:
|
|
case ARM::VST2LNd16Pseudo:
|
|
case ARM::VST2LNd16Pseudo_UPD:
|
|
case ARM::VST2LNd32Pseudo:
|
|
case ARM::VST2LNd32Pseudo_UPD:
|
|
case ARM::VST2LNd8Pseudo:
|
|
case ARM::VST2LNd8Pseudo_UPD:
|
|
case ARM::VST2LNq16Pseudo:
|
|
case ARM::VST2LNq16Pseudo_UPD:
|
|
case ARM::VST2LNq32Pseudo:
|
|
case ARM::VST2LNq32Pseudo_UPD:
|
|
case ARM::VST2q16Pseudo:
|
|
case ARM::VST2q16PseudoWB_fixed:
|
|
case ARM::VST2q16PseudoWB_register:
|
|
case ARM::VST2q32Pseudo:
|
|
case ARM::VST2q32PseudoWB_fixed:
|
|
case ARM::VST2q32PseudoWB_register:
|
|
case ARM::VST2q8Pseudo:
|
|
case ARM::VST2q8PseudoWB_fixed:
|
|
case ARM::VST2q8PseudoWB_register:
|
|
case ARM::VST3LNd16Pseudo:
|
|
case ARM::VST3LNd16Pseudo_UPD:
|
|
case ARM::VST3LNd32Pseudo:
|
|
case ARM::VST3LNd32Pseudo_UPD:
|
|
case ARM::VST3LNd8Pseudo:
|
|
case ARM::VST3LNd8Pseudo_UPD:
|
|
case ARM::VST3LNq16Pseudo:
|
|
case ARM::VST3LNq16Pseudo_UPD:
|
|
case ARM::VST3LNq32Pseudo:
|
|
case ARM::VST3LNq32Pseudo_UPD:
|
|
case ARM::VST3d16Pseudo:
|
|
case ARM::VST3d16Pseudo_UPD:
|
|
case ARM::VST3d32Pseudo:
|
|
case ARM::VST3d32Pseudo_UPD:
|
|
case ARM::VST3d8Pseudo:
|
|
case ARM::VST3d8Pseudo_UPD:
|
|
case ARM::VST3q16Pseudo_UPD:
|
|
case ARM::VST3q16oddPseudo:
|
|
case ARM::VST3q16oddPseudo_UPD:
|
|
case ARM::VST3q32Pseudo_UPD:
|
|
case ARM::VST3q32oddPseudo:
|
|
case ARM::VST3q32oddPseudo_UPD:
|
|
case ARM::VST3q8Pseudo_UPD:
|
|
case ARM::VST3q8oddPseudo:
|
|
case ARM::VST3q8oddPseudo_UPD:
|
|
case ARM::VST4LNd16Pseudo:
|
|
case ARM::VST4LNd16Pseudo_UPD:
|
|
case ARM::VST4LNd32Pseudo:
|
|
case ARM::VST4LNd32Pseudo_UPD:
|
|
case ARM::VST4LNd8Pseudo:
|
|
case ARM::VST4LNd8Pseudo_UPD:
|
|
case ARM::VST4LNq16Pseudo:
|
|
case ARM::VST4LNq16Pseudo_UPD:
|
|
case ARM::VST4LNq32Pseudo:
|
|
case ARM::VST4LNq32Pseudo_UPD:
|
|
case ARM::VST4d16Pseudo:
|
|
case ARM::VST4d16Pseudo_UPD:
|
|
case ARM::VST4d32Pseudo:
|
|
case ARM::VST4d32Pseudo_UPD:
|
|
case ARM::VST4d8Pseudo:
|
|
case ARM::VST4d8Pseudo_UPD:
|
|
case ARM::VST4q16Pseudo_UPD:
|
|
case ARM::VST4q16oddPseudo:
|
|
case ARM::VST4q16oddPseudo_UPD:
|
|
case ARM::VST4q32Pseudo_UPD:
|
|
case ARM::VST4q32oddPseudo:
|
|
case ARM::VST4q32oddPseudo_UPD:
|
|
case ARM::VST4q8Pseudo_UPD:
|
|
case ARM::VST4q8oddPseudo:
|
|
case ARM::VST4q8oddPseudo_UPD:
|
|
case ARM::VSTMQIA:
|
|
case ARM::VTBL3Pseudo:
|
|
case ARM::VTBL4Pseudo:
|
|
case ARM::VTBX3Pseudo:
|
|
case ARM::VTBX4Pseudo:
|
|
case ARM::t2CLREX:
|
|
case ARM::t2DCPS1:
|
|
case ARM::t2DCPS2:
|
|
case ARM::t2DCPS3:
|
|
case ARM::t2Int_eh_sjlj_setjmp:
|
|
case ARM::t2Int_eh_sjlj_setjmp_nofp:
|
|
case ARM::t2SG:
|
|
case ARM::tInt_eh_sjlj_longjmp:
|
|
case ARM::tInt_eh_sjlj_setjmp:
|
|
case ARM::tTRAP: {
|
|
break;
|
|
}
|
|
case ARM::VRINTAD:
|
|
case ARM::VRINTMD:
|
|
case ARM::VRINTND:
|
|
case ARM::VRINTPD: {
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::VMAXNMD:
|
|
case ARM::VMINNMD:
|
|
case ARM::VSELEQD:
|
|
case ARM::VSELGED:
|
|
case ARM::VSELGTD:
|
|
case ARM::VSELVSD: {
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Dn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::CRC32B:
|
|
case ARM::CRC32CB:
|
|
case ARM::CRC32CH:
|
|
case ARM::CRC32CW:
|
|
case ARM::CRC32H:
|
|
case ARM::CRC32W: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2MRS_AR:
|
|
case ARM::t2MRSsys_AR: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
break;
|
|
}
|
|
case ARM::t2CLZ:
|
|
case ARM::t2RBIT:
|
|
case ARM::t2REV:
|
|
case ARM::t2REV16:
|
|
case ARM::t2REVSH: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2MOVsra_flag:
|
|
case ARM::t2MOVsrl_flag: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2SXTB:
|
|
case ARM::t2SXTB16:
|
|
case ARM::t2SXTH:
|
|
case ARM::t2UXTB:
|
|
case ARM::t2UXTB16:
|
|
case ARM::t2UXTH: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: rot
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 4;
|
|
break;
|
|
}
|
|
case ARM::t2CRC32B:
|
|
case ARM::t2CRC32CB:
|
|
case ARM::t2CRC32CH:
|
|
case ARM::t2CRC32CW:
|
|
case ARM::t2CRC32H:
|
|
case ARM::t2CRC32W:
|
|
case ARM::t2MUL:
|
|
case ARM::t2QADD16:
|
|
case ARM::t2QADD8:
|
|
case ARM::t2QASX:
|
|
case ARM::t2QSAX:
|
|
case ARM::t2QSUB16:
|
|
case ARM::t2QSUB8:
|
|
case ARM::t2SADD16:
|
|
case ARM::t2SADD8:
|
|
case ARM::t2SASX:
|
|
case ARM::t2SDIV:
|
|
case ARM::t2SEL:
|
|
case ARM::t2SHADD16:
|
|
case ARM::t2SHADD8:
|
|
case ARM::t2SHASX:
|
|
case ARM::t2SHSAX:
|
|
case ARM::t2SHSUB16:
|
|
case ARM::t2SHSUB8:
|
|
case ARM::t2SMMUL:
|
|
case ARM::t2SMMULR:
|
|
case ARM::t2SMUAD:
|
|
case ARM::t2SMUADX:
|
|
case ARM::t2SMULBB:
|
|
case ARM::t2SMULBT:
|
|
case ARM::t2SMULTB:
|
|
case ARM::t2SMULTT:
|
|
case ARM::t2SMULWB:
|
|
case ARM::t2SMULWT:
|
|
case ARM::t2SMUSD:
|
|
case ARM::t2SMUSDX:
|
|
case ARM::t2SSAX:
|
|
case ARM::t2SSUB16:
|
|
case ARM::t2SSUB8:
|
|
case ARM::t2UADD16:
|
|
case ARM::t2UADD8:
|
|
case ARM::t2UASX:
|
|
case ARM::t2UDIV:
|
|
case ARM::t2UHADD16:
|
|
case ARM::t2UHADD8:
|
|
case ARM::t2UHASX:
|
|
case ARM::t2UHSAX:
|
|
case ARM::t2UHSUB16:
|
|
case ARM::t2UHSUB8:
|
|
case ARM::t2UQADD16:
|
|
case ARM::t2UQADD8:
|
|
case ARM::t2UQASX:
|
|
case ARM::t2UQSAX:
|
|
case ARM::t2UQSUB16:
|
|
case ARM::t2UQSUB8:
|
|
case ARM::t2USAD8:
|
|
case ARM::t2USAX:
|
|
case ARM::t2USUB16:
|
|
case ARM::t2USUB8: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2MLA:
|
|
case ARM::t2MLS:
|
|
case ARM::t2SMLABB:
|
|
case ARM::t2SMLABT:
|
|
case ARM::t2SMLAD:
|
|
case ARM::t2SMLADX:
|
|
case ARM::t2SMLATB:
|
|
case ARM::t2SMLATT:
|
|
case ARM::t2SMLAWB:
|
|
case ARM::t2SMLAWT:
|
|
case ARM::t2SMLSD:
|
|
case ARM::t2SMLSDX:
|
|
case ARM::t2SMMLA:
|
|
case ARM::t2SMMLAR:
|
|
case ARM::t2SMMLS:
|
|
case ARM::t2SMMLSR:
|
|
case ARM::t2USADA8: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::t2SXTAB:
|
|
case ARM::t2SXTAB16:
|
|
case ARM::t2SXTAH:
|
|
case ARM::t2UXTAB:
|
|
case ARM::t2UXTAB16:
|
|
case ARM::t2UXTAH: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: rot
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 4;
|
|
break;
|
|
}
|
|
case ARM::t2PKHBT:
|
|
case ARM::t2PKHTB: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: sh
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(28)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
break;
|
|
}
|
|
case ARM::t2ADDri12:
|
|
case ARM::t2SUBri12: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(2048)) << 15;
|
|
Value |= (op & UINT64_C(1792)) << 4;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2QADD:
|
|
case ARM::t2QDADD:
|
|
case ARM::t2QDSUB:
|
|
case ARM::t2QSUB: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2BFI: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(28)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value |= (op & UINT64_C(992)) >> 5;
|
|
break;
|
|
}
|
|
case ARM::t2SSAT16:
|
|
case ARM::t2USAT16: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: sat_imm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2SSAT:
|
|
case ARM::t2USAT: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: sat_imm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(31);
|
|
// op: sh
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(32)) << 16;
|
|
Value |= (op & UINT64_C(28)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
break;
|
|
}
|
|
case ARM::t2STREX: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(3840)) << 8;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2MRS_M: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: SYSm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2ADR: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: addr
|
|
op = getT2AdrLabelOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(2048)) << 15;
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(4096)) << 9;
|
|
Value |= (op & UINT64_C(1792)) << 4;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2BFC: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: imm
|
|
op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(28)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value |= (op & UINT64_C(992)) >> 5;
|
|
break;
|
|
}
|
|
case ARM::t2MOVi16: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: imm
|
|
op = getHiLo16ImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(2048)) << 15;
|
|
Value |= (op & UINT64_C(61440)) << 4;
|
|
Value |= (op & UINT64_C(1792)) << 4;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2MOVTi16: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: imm
|
|
op = getHiLo16ImmOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(2048)) << 15;
|
|
Value |= (op & UINT64_C(61440)) << 4;
|
|
Value |= (op & UINT64_C(1792)) << 4;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2SBFX:
|
|
case ARM::t2UBFX: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: msb
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(31);
|
|
// op: lsb
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(28)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::tADR: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: addr
|
|
op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tMOVi8: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: imm8
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tMOVr: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(8)) << 4;
|
|
Value |= op & UINT64_C(7);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 3;
|
|
break;
|
|
}
|
|
case ARM::t2STLEX: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::t2STLEXB:
|
|
case ARM::t2STLEXH:
|
|
case ARM::t2STREXB:
|
|
case ARM::t2STREXH: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::t2STLEXD:
|
|
case ARM::t2STREXD: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
break;
|
|
}
|
|
case ARM::tMOVSr: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
break;
|
|
}
|
|
case ARM::tADDi3:
|
|
case ARM::tSUBi3: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
// op: imm3
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 6;
|
|
break;
|
|
}
|
|
case ARM::tASRri:
|
|
case ARM::tLSLri:
|
|
case ARM::tLSRri: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
// op: imm5
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 6;
|
|
break;
|
|
}
|
|
case ARM::tMUL:
|
|
case ARM::tMVN:
|
|
case ARM::tRSB: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
break;
|
|
}
|
|
case ARM::t2SMLALBB:
|
|
case ARM::t2SMLALBT:
|
|
case ARM::t2SMLALD:
|
|
case ARM::t2SMLALDX:
|
|
case ARM::t2SMLALTB:
|
|
case ARM::t2SMLALTT:
|
|
case ARM::t2SMLSLD: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::t2SMLSLDX: {
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::t2SMLAL:
|
|
case ARM::t2SMULL:
|
|
case ARM::t2UMAAL:
|
|
case ARM::t2UMLAL:
|
|
case ARM::t2UMULL: {
|
|
// op: RdLo
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: RdHi
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::tADDi8:
|
|
case ARM::tSUBi8: {
|
|
// op: Rdn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: imm8
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tADDrSP: {
|
|
// op: Rdn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(8)) << 4;
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::tADDhirr: {
|
|
// op: Rdn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(8)) << 4;
|
|
Value |= op & UINT64_C(7);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 3;
|
|
break;
|
|
}
|
|
case ARM::tADC:
|
|
case ARM::tAND:
|
|
case ARM::tASRrr:
|
|
case ARM::tBIC:
|
|
case ARM::tEOR:
|
|
case ARM::tLSLrr:
|
|
case ARM::tLSRrr:
|
|
case ARM::tORR:
|
|
case ARM::tROR:
|
|
case ARM::tSBC: {
|
|
// op: Rdn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
break;
|
|
}
|
|
case ARM::tBX:
|
|
case ARM::tBXNS: {
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 3;
|
|
break;
|
|
}
|
|
case ARM::tCMPhir: {
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 3;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(8)) << 4;
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::tREV:
|
|
case ARM::tREV16:
|
|
case ARM::tREVSH:
|
|
case ARM::tSXTB:
|
|
case ARM::tSXTH:
|
|
case ARM::tUXTB:
|
|
case ARM::tUXTH: {
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::tCMNz:
|
|
case ARM::tCMPr:
|
|
case ARM::tTST: {
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::tADDspr: {
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 3;
|
|
break;
|
|
}
|
|
case ARM::tADDrr:
|
|
case ARM::tSUBrr: {
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 6;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 3;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::RFEDA:
|
|
case ARM::RFEDA_UPD:
|
|
case ARM::RFEDB:
|
|
case ARM::RFEDB_UPD:
|
|
case ARM::RFEIA:
|
|
case ARM::RFEIA_UPD:
|
|
case ARM::RFEIB:
|
|
case ARM::RFEIB_UPD:
|
|
case ARM::t2RFEDB:
|
|
case ARM::t2RFEDBW:
|
|
case ARM::t2RFEIA:
|
|
case ARM::t2RFEIAW: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::t2CMNzrr:
|
|
case ARM::t2CMPrr:
|
|
case ARM::t2TBB:
|
|
case ARM::t2TBH:
|
|
case ARM::t2TEQrr:
|
|
case ARM::t2TSTrr: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2CMNzrs:
|
|
case ARM::t2CMPrs:
|
|
case ARM::t2TEQrs:
|
|
case ARM::t2TSTrs: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: ShiftedRm
|
|
op = getT2SORegOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(3584)) << 3;
|
|
Value |= (op & UINT64_C(480)) >> 1;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2CMNri:
|
|
case ARM::t2CMPri:
|
|
case ARM::t2TEQri:
|
|
case ARM::t2TSTri: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getT2SOImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(2048)) << 15;
|
|
Value |= (op & UINT64_C(1792)) << 4;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2STMDB:
|
|
case ARM::t2STMIA: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(16384);
|
|
Value |= op & UINT64_C(8191);
|
|
break;
|
|
}
|
|
case ARM::t2LDMDB:
|
|
case ARM::t2LDMIA: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(65535);
|
|
break;
|
|
}
|
|
case ARM::tCMPi8: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: imm8
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tLDMIA: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2TT:
|
|
case ARM::t2TTA:
|
|
case ARM::t2TTAT:
|
|
case ARM::t2TTT: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
break;
|
|
}
|
|
case ARM::t2STMDB_UPD:
|
|
case ARM::t2STMIA_UPD: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 4, Fixups, STI);
|
|
Value |= op & UINT64_C(16384);
|
|
Value |= op & UINT64_C(8191);
|
|
break;
|
|
}
|
|
case ARM::t2LDMDB_UPD:
|
|
case ARM::t2LDMIA_UPD: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 4, Fixups, STI);
|
|
Value |= op & UINT64_C(65535);
|
|
break;
|
|
}
|
|
case ARM::tSTMIA_UPD: {
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 4, Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRB_POST:
|
|
case ARM::t2LDRH_POST:
|
|
case ARM::t2LDRSB_POST:
|
|
case ARM::t2LDRSH_POST:
|
|
case ARM::t2LDR_POST: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: offset
|
|
op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 1;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2MRRC:
|
|
case ARM::t2MRRC2: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 4;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2LDRD_POST: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getT2Imm8s4OpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRDi8:
|
|
case ARM::t2STRDi8: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: addr
|
|
op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRD_PRE: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: addr
|
|
op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRBi12:
|
|
case ARM::t2LDRHi12:
|
|
case ARM::t2LDRSBi12:
|
|
case ARM::t2LDRSHi12:
|
|
case ARM::t2LDRi12:
|
|
case ARM::t2STRBi12:
|
|
case ARM::t2STRHi12:
|
|
case ARM::t2STRi12: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::t2LDRBpci:
|
|
case ARM::t2LDRHpci:
|
|
case ARM::t2LDRSBpci:
|
|
case ARM::t2LDRSHpci:
|
|
case ARM::t2LDRpci: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::t2LDA:
|
|
case ARM::t2LDAB:
|
|
case ARM::t2LDAEX:
|
|
case ARM::t2LDAH:
|
|
case ARM::t2STL:
|
|
case ARM::t2STLB:
|
|
case ARM::t2STLH: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::t2LDREX: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(3840)) << 8;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRBi8:
|
|
case ARM::t2LDRHi8:
|
|
case ARM::t2LDRSBi8:
|
|
case ARM::t2LDRSHi8:
|
|
case ARM::t2LDRi8:
|
|
case ARM::t2STRBi8:
|
|
case ARM::t2STRHi8:
|
|
case ARM::t2STRi8: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(256)) << 1;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRBT:
|
|
case ARM::t2LDRHT:
|
|
case ARM::t2LDRSBT:
|
|
case ARM::t2LDRSHT:
|
|
case ARM::t2LDRT:
|
|
case ARM::t2STRBT:
|
|
case ARM::t2STRHT:
|
|
case ARM::t2STRT: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRB_PRE:
|
|
case ARM::t2LDRH_PRE:
|
|
case ARM::t2LDRSB_PRE:
|
|
case ARM::t2LDRSH_PRE:
|
|
case ARM::t2LDR_PRE: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(256)) << 1;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2LDRBs:
|
|
case ARM::t2LDRHs:
|
|
case ARM::t2LDRSBs:
|
|
case ARM::t2LDRSHs:
|
|
case ARM::t2LDRs:
|
|
case ARM::t2STRBs:
|
|
case ARM::t2STRHs:
|
|
case ARM::t2STRs: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(960)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 4;
|
|
Value |= (op & UINT64_C(60)) >> 2;
|
|
break;
|
|
}
|
|
case ARM::MRC2:
|
|
case ARM::t2MRC:
|
|
case ARM::t2MRC2: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 21;
|
|
// op: opc2
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: CRn
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::tLDRpci: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: addr
|
|
op = getAddrModePCOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tLDRspi:
|
|
case ARM::tSTRspi: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: addr
|
|
op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tLDRBi:
|
|
case ARM::tLDRHi:
|
|
case ARM::tLDRi:
|
|
case ARM::tSTRBi:
|
|
case ARM::tSTRHi:
|
|
case ARM::tSTRi: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: addr
|
|
op = getAddrModeISOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(255)) << 3;
|
|
break;
|
|
}
|
|
case ARM::tLDRBr:
|
|
case ARM::tLDRHr:
|
|
case ARM::tLDRSB:
|
|
case ARM::tLDRSH:
|
|
case ARM::tLDRr:
|
|
case ARM::tSTRBr:
|
|
case ARM::tSTRHr:
|
|
case ARM::tSTRr: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: addr
|
|
op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(63)) << 3;
|
|
break;
|
|
}
|
|
case ARM::t2STRB_POST:
|
|
case ARM::t2STRH_POST:
|
|
case ARM::t2STR_POST: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: offset
|
|
op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 1;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2STRD_POST: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getT2Imm8s4OpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2STRD_PRE: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: addr
|
|
op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2STRB_PRE:
|
|
case ARM::t2STRH_PRE:
|
|
case ARM::t2STR_PRE: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(256)) << 1;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::MCRR2:
|
|
case ARM::MRRC2:
|
|
case ARM::t2MCRR:
|
|
case ARM::t2MCRR2: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 4;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MCR2:
|
|
case ARM::t2MCR:
|
|
case ARM::t2MCR2: {
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 21;
|
|
// op: opc2
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: CRn
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::t2MSR_M: {
|
|
// op: SYSm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(3072);
|
|
Value |= op & UINT64_C(255);
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::VCVTASD:
|
|
case ARM::VCVTAUD:
|
|
case ARM::VCVTMSD:
|
|
case ARM::VCVTMUD:
|
|
case ARM::VCVTNSD:
|
|
case ARM::VCVTNUD:
|
|
case ARM::VCVTPSD:
|
|
case ARM::VCVTPUD: {
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::VCVTASH:
|
|
case ARM::VCVTASS:
|
|
case ARM::VCVTAUH:
|
|
case ARM::VCVTAUS:
|
|
case ARM::VCVTMSH:
|
|
case ARM::VCVTMSS:
|
|
case ARM::VCVTMUH:
|
|
case ARM::VCVTMUS:
|
|
case ARM::VCVTNSH:
|
|
case ARM::VCVTNSS:
|
|
case ARM::VCVTNUH:
|
|
case ARM::VCVTNUS:
|
|
case ARM::VCVTPSH:
|
|
case ARM::VCVTPSS:
|
|
case ARM::VCVTPUH:
|
|
case ARM::VCVTPUS:
|
|
case ARM::VINSH:
|
|
case ARM::VMOVH:
|
|
case ARM::VRINTAH:
|
|
case ARM::VRINTAS:
|
|
case ARM::VRINTMH:
|
|
case ARM::VRINTMS:
|
|
case ARM::VRINTNH:
|
|
case ARM::VRINTNS:
|
|
case ARM::VRINTPH:
|
|
case ARM::VRINTPS: {
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: Sm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
break;
|
|
}
|
|
case ARM::VMAXNMH:
|
|
case ARM::VMAXNMS:
|
|
case ARM::VMINNMH:
|
|
case ARM::VMINNMS:
|
|
case ARM::VSELEQH:
|
|
case ARM::VSELEQS:
|
|
case ARM::VSELGEH:
|
|
case ARM::VSELGES:
|
|
case ARM::VSELGTH:
|
|
case ARM::VSELGTS:
|
|
case ARM::VSELVSH:
|
|
case ARM::VSELVSS: {
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: Sn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(30)) << 15;
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
// op: Sm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
break;
|
|
}
|
|
case ARM::VDUP16d:
|
|
case ARM::VDUP16q:
|
|
case ARM::VDUP32d:
|
|
case ARM::VDUP32q:
|
|
case ARM::VDUP8d:
|
|
case ARM::VDUP8q: {
|
|
// op: V
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: R
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
Value = NEONThumb2DupPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSETLNi32: {
|
|
// op: V
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: R
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 21;
|
|
Value = NEONThumb2DupPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSETLNi16: {
|
|
// op: V
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: R
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(2)) << 20;
|
|
Value |= (op & UINT64_C(1)) << 6;
|
|
Value = NEONThumb2DupPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSETLNi8: {
|
|
// op: V
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: R
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(4)) << 19;
|
|
Value |= (op & UINT64_C(3)) << 5;
|
|
Value = NEONThumb2DupPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VGETLNi32: {
|
|
// op: V
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: R
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 21;
|
|
Value = NEONThumb2DupPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VGETLNs16:
|
|
case ARM::VGETLNu16: {
|
|
// op: V
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: R
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(2)) << 20;
|
|
Value |= (op & UINT64_C(1)) << 6;
|
|
Value = NEONThumb2DupPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VGETLNs8:
|
|
case ARM::VGETLNu8: {
|
|
// op: V
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: R
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(4)) << 19;
|
|
Value |= (op & UINT64_C(3)) << 5;
|
|
Value = NEONThumb2DupPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1d16:
|
|
case ARM::VLD1d16T:
|
|
case ARM::VLD1d32:
|
|
case ARM::VLD1d32T:
|
|
case ARM::VLD1d64:
|
|
case ARM::VLD1d64T:
|
|
case ARM::VLD1d8:
|
|
case ARM::VLD1d8T: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1LNd16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1d16Q:
|
|
case ARM::VLD1d32Q:
|
|
case ARM::VLD1d64Q:
|
|
case ARM::VLD1d8Q:
|
|
case ARM::VLD1q16:
|
|
case ARM::VLD1q32:
|
|
case ARM::VLD1q64:
|
|
case ARM::VLD1q8:
|
|
case ARM::VLD2b16:
|
|
case ARM::VLD2b32:
|
|
case ARM::VLD2b8:
|
|
case ARM::VLD2d16:
|
|
case ARM::VLD2d32:
|
|
case ARM::VLD2d8:
|
|
case ARM::VLD2q16:
|
|
case ARM::VLD2q32:
|
|
case ARM::VLD2q8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1LNd32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1LNd16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1d16Twb_register:
|
|
case ARM::VLD1d16wb_register:
|
|
case ARM::VLD1d32Twb_register:
|
|
case ARM::VLD1d32wb_register:
|
|
case ARM::VLD1d64Twb_register:
|
|
case ARM::VLD1d64wb_register:
|
|
case ARM::VLD1d8Twb_register:
|
|
case ARM::VLD1d8wb_register: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD2LNd32:
|
|
case ARM::VLD2LNq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD2LNd16:
|
|
case ARM::VLD2LNq16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD2LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1d16Twb_fixed:
|
|
case ARM::VLD1d16wb_fixed:
|
|
case ARM::VLD1d32Twb_fixed:
|
|
case ARM::VLD1d32wb_fixed:
|
|
case ARM::VLD1d64Twb_fixed:
|
|
case ARM::VLD1d64wb_fixed:
|
|
case ARM::VLD1d8Twb_fixed:
|
|
case ARM::VLD1d8wb_fixed: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1d16Qwb_register:
|
|
case ARM::VLD1d32Qwb_register:
|
|
case ARM::VLD1d64Qwb_register:
|
|
case ARM::VLD1d8Qwb_register:
|
|
case ARM::VLD1q16wb_register:
|
|
case ARM::VLD1q32wb_register:
|
|
case ARM::VLD1q64wb_register:
|
|
case ARM::VLD1q8wb_register:
|
|
case ARM::VLD2b16wb_register:
|
|
case ARM::VLD2b32wb_register:
|
|
case ARM::VLD2b8wb_register:
|
|
case ARM::VLD2d16wb_register:
|
|
case ARM::VLD2d32wb_register:
|
|
case ARM::VLD2d8wb_register:
|
|
case ARM::VLD2q16wb_register:
|
|
case ARM::VLD2q32wb_register:
|
|
case ARM::VLD2q8wb_register: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1d16Qwb_fixed:
|
|
case ARM::VLD1d32Qwb_fixed:
|
|
case ARM::VLD1d64Qwb_fixed:
|
|
case ARM::VLD1d8Qwb_fixed:
|
|
case ARM::VLD1q16wb_fixed:
|
|
case ARM::VLD1q32wb_fixed:
|
|
case ARM::VLD1q64wb_fixed:
|
|
case ARM::VLD1q8wb_fixed:
|
|
case ARM::VLD2b16wb_fixed:
|
|
case ARM::VLD2b32wb_fixed:
|
|
case ARM::VLD2b8wb_fixed:
|
|
case ARM::VLD2d16wb_fixed:
|
|
case ARM::VLD2d32wb_fixed:
|
|
case ARM::VLD2d8wb_fixed:
|
|
case ARM::VLD2q16wb_fixed:
|
|
case ARM::VLD2q32wb_fixed:
|
|
case ARM::VLD2q8wb_fixed: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3LNd32:
|
|
case ARM::VLD3LNq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3LNd16:
|
|
case ARM::VLD3LNq16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD2LNd32_UPD:
|
|
case ARM::VLD2LNq32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD2LNd16_UPD:
|
|
case ARM::VLD2LNq16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD2LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3d16:
|
|
case ARM::VLD3d32:
|
|
case ARM::VLD3d8:
|
|
case ARM::VLD3q16:
|
|
case ARM::VLD3q32:
|
|
case ARM::VLD3q8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3LNd32_UPD:
|
|
case ARM::VLD3LNq32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3LNd16_UPD:
|
|
case ARM::VLD3LNq16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3d16_UPD:
|
|
case ARM::VLD3d32_UPD:
|
|
case ARM::VLD3d8_UPD:
|
|
case ARM::VLD3q16_UPD:
|
|
case ARM::VLD3q32_UPD:
|
|
case ARM::VLD3q8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4LNd16:
|
|
case ARM::VLD4LNq16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4LNd32:
|
|
case ARM::VLD4LNq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4d16:
|
|
case ARM::VLD4d32:
|
|
case ARM::VLD4d8:
|
|
case ARM::VLD4q16:
|
|
case ARM::VLD4q32:
|
|
case ARM::VLD4q8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4LNd16_UPD:
|
|
case ARM::VLD4LNq16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4LNd32_UPD:
|
|
case ARM::VLD4LNq32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4d16_UPD:
|
|
case ARM::VLD4d32_UPD:
|
|
case ARM::VLD4d8_UPD:
|
|
case ARM::VLD4q16_UPD:
|
|
case ARM::VLD4q32_UPD:
|
|
case ARM::VLD4q8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1DUPd16:
|
|
case ARM::VLD1DUPd32:
|
|
case ARM::VLD1DUPd8:
|
|
case ARM::VLD1DUPq16:
|
|
case ARM::VLD1DUPq32:
|
|
case ARM::VLD1DUPq8:
|
|
case ARM::VLD2DUPd16:
|
|
case ARM::VLD2DUPd16x2:
|
|
case ARM::VLD2DUPd32:
|
|
case ARM::VLD2DUPd32x2:
|
|
case ARM::VLD2DUPd8:
|
|
case ARM::VLD2DUPd8x2: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1DUPd16wb_register:
|
|
case ARM::VLD1DUPd32wb_register:
|
|
case ARM::VLD1DUPd8wb_register:
|
|
case ARM::VLD1DUPq16wb_register:
|
|
case ARM::VLD1DUPq32wb_register:
|
|
case ARM::VLD1DUPq8wb_register:
|
|
case ARM::VLD2DUPd16wb_register:
|
|
case ARM::VLD2DUPd16x2wb_register:
|
|
case ARM::VLD2DUPd32wb_register:
|
|
case ARM::VLD2DUPd32x2wb_register:
|
|
case ARM::VLD2DUPd8wb_register:
|
|
case ARM::VLD2DUPd8x2wb_register: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1DUPd16wb_fixed:
|
|
case ARM::VLD1DUPd32wb_fixed:
|
|
case ARM::VLD1DUPd8wb_fixed:
|
|
case ARM::VLD1DUPq16wb_fixed:
|
|
case ARM::VLD1DUPq32wb_fixed:
|
|
case ARM::VLD1DUPq8wb_fixed:
|
|
case ARM::VLD2DUPd16wb_fixed:
|
|
case ARM::VLD2DUPd16x2wb_fixed:
|
|
case ARM::VLD2DUPd32wb_fixed:
|
|
case ARM::VLD2DUPd32x2wb_fixed:
|
|
case ARM::VLD2DUPd8wb_fixed:
|
|
case ARM::VLD2DUPd8x2wb_fixed: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3DUPd16:
|
|
case ARM::VLD3DUPd32:
|
|
case ARM::VLD3DUPd8:
|
|
case ARM::VLD3DUPq16:
|
|
case ARM::VLD3DUPq32:
|
|
case ARM::VLD3DUPq8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD3DUPd16_UPD:
|
|
case ARM::VLD3DUPd32_UPD:
|
|
case ARM::VLD3DUPd8_UPD:
|
|
case ARM::VLD3DUPq16_UPD:
|
|
case ARM::VLD3DUPq32_UPD:
|
|
case ARM::VLD3DUPq8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4DUPd32:
|
|
case ARM::VLD4DUPq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(32)) << 1;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4DUPd16:
|
|
case ARM::VLD4DUPd8:
|
|
case ARM::VLD4DUPq16:
|
|
case ARM::VLD4DUPq8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4DUPd32_UPD:
|
|
case ARM::VLD4DUPq32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(32)) << 1;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD4DUPd16_UPD:
|
|
case ARM::VLD4DUPd8_UPD:
|
|
case ARM::VLD4DUPq16_UPD:
|
|
case ARM::VLD4DUPq8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLD1LNd32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMOVv16i8:
|
|
case ARM::VMOVv1i64:
|
|
case ARM::VMOVv2f32:
|
|
case ARM::VMOVv2i64:
|
|
case ARM::VMOVv4f32:
|
|
case ARM::VMOVv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(128)) << 17;
|
|
Value |= (op & UINT64_C(112)) << 12;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VBICiv2i32:
|
|
case ARM::VBICiv4i32:
|
|
case ARM::VORRiv2i32:
|
|
case ARM::VORRiv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(128)) << 17;
|
|
Value |= (op & UINT64_C(112)) << 12;
|
|
Value |= op & UINT64_C(1536);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMOVv2i32:
|
|
case ARM::VMOVv4i32:
|
|
case ARM::VMVNv2i32:
|
|
case ARM::VMVNv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(128)) << 17;
|
|
Value |= (op & UINT64_C(112)) << 12;
|
|
Value |= op & UINT64_C(3840);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VBICiv4i16:
|
|
case ARM::VBICiv8i16:
|
|
case ARM::VMOVv4i16:
|
|
case ARM::VMOVv8i16:
|
|
case ARM::VMVNv4i16:
|
|
case ARM::VMVNv8i16:
|
|
case ARM::VORRiv4i16:
|
|
case ARM::VORRiv8i16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(128)) << 17;
|
|
Value |= (op & UINT64_C(112)) << 12;
|
|
Value |= op & UINT64_C(512);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQSHLsiv4i16:
|
|
case ARM::VQSHLsiv8i16:
|
|
case ARM::VQSHLsuv4i16:
|
|
case ARM::VQSHLsuv8i16:
|
|
case ARM::VQSHLuiv4i16:
|
|
case ARM::VQSHLuiv8i16:
|
|
case ARM::VSHLLsv4i32:
|
|
case ARM::VSHLLuv4i32:
|
|
case ARM::VSHLiv4i16:
|
|
case ARM::VSHLiv8i16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQSHLsiv2i32:
|
|
case ARM::VQSHLsiv4i32:
|
|
case ARM::VQSHLsuv2i32:
|
|
case ARM::VQSHLsuv4i32:
|
|
case ARM::VQSHLuiv2i32:
|
|
case ARM::VQSHLuiv4i32:
|
|
case ARM::VSHLLsv2i64:
|
|
case ARM::VSHLLuv2i64:
|
|
case ARM::VSHLiv2i32:
|
|
case ARM::VSHLiv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQSHLsiv1i64:
|
|
case ARM::VQSHLsiv2i64:
|
|
case ARM::VQSHLsuv1i64:
|
|
case ARM::VQSHLsuv2i64:
|
|
case ARM::VQSHLuiv1i64:
|
|
case ARM::VQSHLuiv2i64:
|
|
case ARM::VSHLiv1i64:
|
|
case ARM::VSHLiv2i64: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(63)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQSHLsiv16i8:
|
|
case ARM::VQSHLsiv8i8:
|
|
case ARM::VQSHLsuv16i8:
|
|
case ARM::VQSHLsuv8i8:
|
|
case ARM::VQSHLuiv16i8:
|
|
case ARM::VQSHLuiv8i8:
|
|
case ARM::VSHLLsv8i16:
|
|
case ARM::VSHLLuv8i16:
|
|
case ARM::VSHLiv16i8:
|
|
case ARM::VSHLiv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VCVTf2xsd:
|
|
case ARM::VCVTf2xsq:
|
|
case ARM::VCVTf2xud:
|
|
case ARM::VCVTf2xuq:
|
|
case ARM::VCVTh2xsd:
|
|
case ARM::VCVTh2xsq:
|
|
case ARM::VCVTh2xud:
|
|
case ARM::VCVTh2xuq:
|
|
case ARM::VCVTxs2fd:
|
|
case ARM::VCVTxs2fq:
|
|
case ARM::VCVTxs2hd:
|
|
case ARM::VCVTxs2hq:
|
|
case ARM::VCVTxu2fd:
|
|
case ARM::VCVTxu2fq:
|
|
case ARM::VCVTxu2hd:
|
|
case ARM::VCVTxu2hq: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(63)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQRSHRNsv4i16:
|
|
case ARM::VQRSHRNuv4i16:
|
|
case ARM::VQRSHRUNv4i16:
|
|
case ARM::VQSHRNsv4i16:
|
|
case ARM::VQSHRNuv4i16:
|
|
case ARM::VQSHRUNv4i16:
|
|
case ARM::VRSHRNv4i16:
|
|
case ARM::VRSHRsv4i16:
|
|
case ARM::VRSHRsv8i16:
|
|
case ARM::VRSHRuv4i16:
|
|
case ARM::VRSHRuv8i16:
|
|
case ARM::VSHRNv4i16:
|
|
case ARM::VSHRsv4i16:
|
|
case ARM::VSHRsv8i16:
|
|
case ARM::VSHRuv4i16:
|
|
case ARM::VSHRuv8i16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight16Imm(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQRSHRNsv2i32:
|
|
case ARM::VQRSHRNuv2i32:
|
|
case ARM::VQRSHRUNv2i32:
|
|
case ARM::VQSHRNsv2i32:
|
|
case ARM::VQSHRNuv2i32:
|
|
case ARM::VQSHRUNv2i32:
|
|
case ARM::VRSHRNv2i32:
|
|
case ARM::VRSHRsv2i32:
|
|
case ARM::VRSHRsv4i32:
|
|
case ARM::VRSHRuv2i32:
|
|
case ARM::VRSHRuv4i32:
|
|
case ARM::VSHRNv2i32:
|
|
case ARM::VSHRsv2i32:
|
|
case ARM::VSHRsv4i32:
|
|
case ARM::VSHRuv2i32:
|
|
case ARM::VSHRuv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight32Imm(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VRSHRsv1i64:
|
|
case ARM::VRSHRsv2i64:
|
|
case ARM::VRSHRuv1i64:
|
|
case ARM::VRSHRuv2i64:
|
|
case ARM::VSHRsv1i64:
|
|
case ARM::VSHRsv2i64:
|
|
case ARM::VSHRuv1i64:
|
|
case ARM::VSHRuv2i64: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight64Imm(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(63)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQRSHRNsv8i8:
|
|
case ARM::VQRSHRNuv8i8:
|
|
case ARM::VQRSHRUNv8i8:
|
|
case ARM::VQSHRNsv8i8:
|
|
case ARM::VQSHRNuv8i8:
|
|
case ARM::VQSHRUNv8i8:
|
|
case ARM::VRSHRNv8i8:
|
|
case ARM::VRSHRsv16i8:
|
|
case ARM::VRSHRsv8i8:
|
|
case ARM::VRSHRuv16i8:
|
|
case ARM::VRSHRuv8i8:
|
|
case ARM::VSHRNv8i8:
|
|
case ARM::VSHRsv16i8:
|
|
case ARM::VSHRsv8i8:
|
|
case ARM::VSHRuv16i8:
|
|
case ARM::VSHRuv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight8Imm(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VDUPLN32d:
|
|
case ARM::VDUPLN32q: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 19;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VDUPLN16d:
|
|
case ARM::VDUPLN16q: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 18;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VDUPLN8d:
|
|
case ARM::VDUPLN8q: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 17;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::AESIMC:
|
|
case ARM::AESMC:
|
|
case ARM::SHA1H:
|
|
case ARM::VABSfd:
|
|
case ARM::VABSfq:
|
|
case ARM::VABShd:
|
|
case ARM::VABShq:
|
|
case ARM::VABSv16i8:
|
|
case ARM::VABSv2i32:
|
|
case ARM::VABSv4i16:
|
|
case ARM::VABSv4i32:
|
|
case ARM::VABSv8i16:
|
|
case ARM::VABSv8i8:
|
|
case ARM::VCEQzv16i8:
|
|
case ARM::VCEQzv2f32:
|
|
case ARM::VCEQzv2i32:
|
|
case ARM::VCEQzv4f16:
|
|
case ARM::VCEQzv4f32:
|
|
case ARM::VCEQzv4i16:
|
|
case ARM::VCEQzv4i32:
|
|
case ARM::VCEQzv8f16:
|
|
case ARM::VCEQzv8i16:
|
|
case ARM::VCEQzv8i8:
|
|
case ARM::VCGEzv16i8:
|
|
case ARM::VCGEzv2f32:
|
|
case ARM::VCGEzv2i32:
|
|
case ARM::VCGEzv4f16:
|
|
case ARM::VCGEzv4f32:
|
|
case ARM::VCGEzv4i16:
|
|
case ARM::VCGEzv4i32:
|
|
case ARM::VCGEzv8f16:
|
|
case ARM::VCGEzv8i16:
|
|
case ARM::VCGEzv8i8:
|
|
case ARM::VCGTzv16i8:
|
|
case ARM::VCGTzv2f32:
|
|
case ARM::VCGTzv2i32:
|
|
case ARM::VCGTzv4f16:
|
|
case ARM::VCGTzv4f32:
|
|
case ARM::VCGTzv4i16:
|
|
case ARM::VCGTzv4i32:
|
|
case ARM::VCGTzv8f16:
|
|
case ARM::VCGTzv8i16:
|
|
case ARM::VCGTzv8i8:
|
|
case ARM::VCLEzv16i8:
|
|
case ARM::VCLEzv2f32:
|
|
case ARM::VCLEzv2i32:
|
|
case ARM::VCLEzv4f16:
|
|
case ARM::VCLEzv4f32:
|
|
case ARM::VCLEzv4i16:
|
|
case ARM::VCLEzv4i32:
|
|
case ARM::VCLEzv8f16:
|
|
case ARM::VCLEzv8i16:
|
|
case ARM::VCLEzv8i8:
|
|
case ARM::VCLSv16i8:
|
|
case ARM::VCLSv2i32:
|
|
case ARM::VCLSv4i16:
|
|
case ARM::VCLSv4i32:
|
|
case ARM::VCLSv8i16:
|
|
case ARM::VCLSv8i8:
|
|
case ARM::VCLTzv16i8:
|
|
case ARM::VCLTzv2f32:
|
|
case ARM::VCLTzv2i32:
|
|
case ARM::VCLTzv4f16:
|
|
case ARM::VCLTzv4f32:
|
|
case ARM::VCLTzv4i16:
|
|
case ARM::VCLTzv4i32:
|
|
case ARM::VCLTzv8f16:
|
|
case ARM::VCLTzv8i16:
|
|
case ARM::VCLTzv8i8:
|
|
case ARM::VCLZv16i8:
|
|
case ARM::VCLZv2i32:
|
|
case ARM::VCLZv4i16:
|
|
case ARM::VCLZv4i32:
|
|
case ARM::VCLZv8i16:
|
|
case ARM::VCLZv8i8:
|
|
case ARM::VCNTd:
|
|
case ARM::VCNTq:
|
|
case ARM::VCVTf2h:
|
|
case ARM::VCVTf2sd:
|
|
case ARM::VCVTf2sq:
|
|
case ARM::VCVTf2ud:
|
|
case ARM::VCVTf2uq:
|
|
case ARM::VCVTh2f:
|
|
case ARM::VCVTh2sd:
|
|
case ARM::VCVTh2sq:
|
|
case ARM::VCVTh2ud:
|
|
case ARM::VCVTh2uq:
|
|
case ARM::VCVTs2fd:
|
|
case ARM::VCVTs2fq:
|
|
case ARM::VCVTs2hd:
|
|
case ARM::VCVTs2hq:
|
|
case ARM::VCVTu2fd:
|
|
case ARM::VCVTu2fq:
|
|
case ARM::VCVTu2hd:
|
|
case ARM::VCVTu2hq:
|
|
case ARM::VMOVLsv2i64:
|
|
case ARM::VMOVLsv4i32:
|
|
case ARM::VMOVLsv8i16:
|
|
case ARM::VMOVLuv2i64:
|
|
case ARM::VMOVLuv4i32:
|
|
case ARM::VMOVLuv8i16:
|
|
case ARM::VMOVNv2i32:
|
|
case ARM::VMOVNv4i16:
|
|
case ARM::VMOVNv8i8:
|
|
case ARM::VMVNd:
|
|
case ARM::VMVNq:
|
|
case ARM::VNEGf32q:
|
|
case ARM::VNEGfd:
|
|
case ARM::VNEGhd:
|
|
case ARM::VNEGhq:
|
|
case ARM::VNEGs16d:
|
|
case ARM::VNEGs16q:
|
|
case ARM::VNEGs32d:
|
|
case ARM::VNEGs32q:
|
|
case ARM::VNEGs8d:
|
|
case ARM::VNEGs8q:
|
|
case ARM::VPADDLsv16i8:
|
|
case ARM::VPADDLsv2i32:
|
|
case ARM::VPADDLsv4i16:
|
|
case ARM::VPADDLsv4i32:
|
|
case ARM::VPADDLsv8i16:
|
|
case ARM::VPADDLsv8i8:
|
|
case ARM::VPADDLuv16i8:
|
|
case ARM::VPADDLuv2i32:
|
|
case ARM::VPADDLuv4i16:
|
|
case ARM::VPADDLuv4i32:
|
|
case ARM::VPADDLuv8i16:
|
|
case ARM::VPADDLuv8i8:
|
|
case ARM::VQABSv16i8:
|
|
case ARM::VQABSv2i32:
|
|
case ARM::VQABSv4i16:
|
|
case ARM::VQABSv4i32:
|
|
case ARM::VQABSv8i16:
|
|
case ARM::VQABSv8i8:
|
|
case ARM::VQMOVNsuv2i32:
|
|
case ARM::VQMOVNsuv4i16:
|
|
case ARM::VQMOVNsuv8i8:
|
|
case ARM::VQMOVNsv2i32:
|
|
case ARM::VQMOVNsv4i16:
|
|
case ARM::VQMOVNsv8i8:
|
|
case ARM::VQMOVNuv2i32:
|
|
case ARM::VQMOVNuv4i16:
|
|
case ARM::VQMOVNuv8i8:
|
|
case ARM::VQNEGv16i8:
|
|
case ARM::VQNEGv2i32:
|
|
case ARM::VQNEGv4i16:
|
|
case ARM::VQNEGv4i32:
|
|
case ARM::VQNEGv8i16:
|
|
case ARM::VQNEGv8i8:
|
|
case ARM::VRECPEd:
|
|
case ARM::VRECPEfd:
|
|
case ARM::VRECPEfq:
|
|
case ARM::VRECPEhd:
|
|
case ARM::VRECPEhq:
|
|
case ARM::VRECPEq:
|
|
case ARM::VREV16d8:
|
|
case ARM::VREV16q8:
|
|
case ARM::VREV32d16:
|
|
case ARM::VREV32d8:
|
|
case ARM::VREV32q16:
|
|
case ARM::VREV32q8:
|
|
case ARM::VREV64d16:
|
|
case ARM::VREV64d32:
|
|
case ARM::VREV64d8:
|
|
case ARM::VREV64q16:
|
|
case ARM::VREV64q32:
|
|
case ARM::VREV64q8:
|
|
case ARM::VRSQRTEd:
|
|
case ARM::VRSQRTEfd:
|
|
case ARM::VRSQRTEfq:
|
|
case ARM::VRSQRTEhd:
|
|
case ARM::VRSQRTEhq:
|
|
case ARM::VRSQRTEq:
|
|
case ARM::VSHLLi16:
|
|
case ARM::VSHLLi32:
|
|
case ARM::VSHLLi8:
|
|
case ARM::VSWPd:
|
|
case ARM::VSWPq:
|
|
case ARM::VTRNd16:
|
|
case ARM::VTRNd32:
|
|
case ARM::VTRNd8:
|
|
case ARM::VTRNq16:
|
|
case ARM::VTRNq32:
|
|
case ARM::VTRNq8:
|
|
case ARM::VUZPd16:
|
|
case ARM::VUZPd8:
|
|
case ARM::VUZPq16:
|
|
case ARM::VUZPq32:
|
|
case ARM::VUZPq8:
|
|
case ARM::VZIPd16:
|
|
case ARM::VZIPd8:
|
|
case ARM::VZIPq16:
|
|
case ARM::VZIPq32:
|
|
case ARM::VZIPq8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VCVTANSDf:
|
|
case ARM::VCVTANSDh:
|
|
case ARM::VCVTANSQf:
|
|
case ARM::VCVTANSQh:
|
|
case ARM::VCVTANUDf:
|
|
case ARM::VCVTANUDh:
|
|
case ARM::VCVTANUQf:
|
|
case ARM::VCVTANUQh:
|
|
case ARM::VCVTMNSDf:
|
|
case ARM::VCVTMNSDh:
|
|
case ARM::VCVTMNSQf:
|
|
case ARM::VCVTMNSQh:
|
|
case ARM::VCVTMNUDf:
|
|
case ARM::VCVTMNUDh:
|
|
case ARM::VCVTMNUQf:
|
|
case ARM::VCVTMNUQh:
|
|
case ARM::VCVTNNSDf:
|
|
case ARM::VCVTNNSDh:
|
|
case ARM::VCVTNNSQf:
|
|
case ARM::VCVTNNSQh:
|
|
case ARM::VCVTNNUDf:
|
|
case ARM::VCVTNNUDh:
|
|
case ARM::VCVTNNUQf:
|
|
case ARM::VCVTNNUQh:
|
|
case ARM::VCVTPNSDf:
|
|
case ARM::VCVTPNSDh:
|
|
case ARM::VCVTPNSQf:
|
|
case ARM::VCVTPNSQh:
|
|
case ARM::VCVTPNUDf:
|
|
case ARM::VCVTPNUDh:
|
|
case ARM::VCVTPNUQf:
|
|
case ARM::VCVTPNUQh:
|
|
case ARM::VRINTANDf:
|
|
case ARM::VRINTANDh:
|
|
case ARM::VRINTANQf:
|
|
case ARM::VRINTANQh:
|
|
case ARM::VRINTMNDf:
|
|
case ARM::VRINTMNDh:
|
|
case ARM::VRINTMNQf:
|
|
case ARM::VRINTMNQh:
|
|
case ARM::VRINTNNDf:
|
|
case ARM::VRINTNNDh:
|
|
case ARM::VRINTNNQf:
|
|
case ARM::VRINTNNQh:
|
|
case ARM::VRINTPNDf:
|
|
case ARM::VRINTPNDh:
|
|
case ARM::VRINTPNQf:
|
|
case ARM::VRINTPNQh:
|
|
case ARM::VRINTXNDf:
|
|
case ARM::VRINTXNDh:
|
|
case ARM::VRINTXNQf:
|
|
case ARM::VRINTXNQh:
|
|
case ARM::VRINTZNDf:
|
|
case ARM::VRINTZNDh:
|
|
case ARM::VRINTZNQf:
|
|
case ARM::VRINTZNQh: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2V8PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSLIv4i16:
|
|
case ARM::VSLIv8i16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSLIv2i32:
|
|
case ARM::VSLIv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSLIv1i64:
|
|
case ARM::VSLIv2i64: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(63)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSLIv16i8:
|
|
case ARM::VSLIv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VRSRAsv4i16:
|
|
case ARM::VRSRAsv8i16:
|
|
case ARM::VRSRAuv4i16:
|
|
case ARM::VRSRAuv8i16:
|
|
case ARM::VSRAsv4i16:
|
|
case ARM::VSRAsv8i16:
|
|
case ARM::VSRAuv4i16:
|
|
case ARM::VSRAuv8i16:
|
|
case ARM::VSRIv4i16:
|
|
case ARM::VSRIv8i16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight16Imm(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VRSRAsv2i32:
|
|
case ARM::VRSRAsv4i32:
|
|
case ARM::VRSRAuv2i32:
|
|
case ARM::VRSRAuv4i32:
|
|
case ARM::VSRAsv2i32:
|
|
case ARM::VSRAsv4i32:
|
|
case ARM::VSRAuv2i32:
|
|
case ARM::VSRAuv4i32:
|
|
case ARM::VSRIv2i32:
|
|
case ARM::VSRIv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight32Imm(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VRSRAsv1i64:
|
|
case ARM::VRSRAsv2i64:
|
|
case ARM::VRSRAuv1i64:
|
|
case ARM::VRSRAuv2i64:
|
|
case ARM::VSRAsv1i64:
|
|
case ARM::VSRAsv2i64:
|
|
case ARM::VSRAuv1i64:
|
|
case ARM::VSRAuv2i64:
|
|
case ARM::VSRIv1i64:
|
|
case ARM::VSRIv2i64: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight64Imm(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(63)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VRSRAsv16i8:
|
|
case ARM::VRSRAsv8i8:
|
|
case ARM::VRSRAuv16i8:
|
|
case ARM::VRSRAuv8i8:
|
|
case ARM::VSRAsv16i8:
|
|
case ARM::VSRAsv8i8:
|
|
case ARM::VSRAuv16i8:
|
|
case ARM::VSRAuv8i8:
|
|
case ARM::VSRIv16i8:
|
|
case ARM::VSRIv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: SIMM
|
|
op = getShiftRight8Imm(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 16;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::AESD:
|
|
case ARM::AESE:
|
|
case ARM::SHA1SU1:
|
|
case ARM::SHA256SU0:
|
|
case ARM::VPADALsv16i8:
|
|
case ARM::VPADALsv2i32:
|
|
case ARM::VPADALsv4i16:
|
|
case ARM::VPADALsv4i32:
|
|
case ARM::VPADALsv8i16:
|
|
case ARM::VPADALsv8i8:
|
|
case ARM::VPADALuv16i8:
|
|
case ARM::VPADALuv2i32:
|
|
case ARM::VPADALuv4i16:
|
|
case ARM::VPADALuv4i32:
|
|
case ARM::VPADALuv8i16:
|
|
case ARM::VPADALuv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VEXTd32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: index
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 10;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VEXTq64: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: index
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 11;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VEXTq8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: index
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VEXTq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: index
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 10;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VEXTd16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: index
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 9;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VEXTd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: index
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VEXTq16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: index
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 9;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VABDLsv2i64:
|
|
case ARM::VABDLsv4i32:
|
|
case ARM::VABDLsv8i16:
|
|
case ARM::VABDLuv2i64:
|
|
case ARM::VABDLuv4i32:
|
|
case ARM::VABDLuv8i16:
|
|
case ARM::VABDfd:
|
|
case ARM::VABDfq:
|
|
case ARM::VABDhd:
|
|
case ARM::VABDhq:
|
|
case ARM::VABDsv16i8:
|
|
case ARM::VABDsv2i32:
|
|
case ARM::VABDsv4i16:
|
|
case ARM::VABDsv4i32:
|
|
case ARM::VABDsv8i16:
|
|
case ARM::VABDsv8i8:
|
|
case ARM::VABDuv16i8:
|
|
case ARM::VABDuv2i32:
|
|
case ARM::VABDuv4i16:
|
|
case ARM::VABDuv4i32:
|
|
case ARM::VABDuv8i16:
|
|
case ARM::VABDuv8i8:
|
|
case ARM::VACGEfd:
|
|
case ARM::VACGEfq:
|
|
case ARM::VACGEhd:
|
|
case ARM::VACGEhq:
|
|
case ARM::VACGTfd:
|
|
case ARM::VACGTfq:
|
|
case ARM::VACGThd:
|
|
case ARM::VACGThq:
|
|
case ARM::VADDHNv2i32:
|
|
case ARM::VADDHNv4i16:
|
|
case ARM::VADDHNv8i8:
|
|
case ARM::VADDLsv2i64:
|
|
case ARM::VADDLsv4i32:
|
|
case ARM::VADDLsv8i16:
|
|
case ARM::VADDLuv2i64:
|
|
case ARM::VADDLuv4i32:
|
|
case ARM::VADDLuv8i16:
|
|
case ARM::VADDWsv2i64:
|
|
case ARM::VADDWsv4i32:
|
|
case ARM::VADDWsv8i16:
|
|
case ARM::VADDWuv2i64:
|
|
case ARM::VADDWuv4i32:
|
|
case ARM::VADDWuv8i16:
|
|
case ARM::VADDfd:
|
|
case ARM::VADDfq:
|
|
case ARM::VADDhd:
|
|
case ARM::VADDhq:
|
|
case ARM::VADDv16i8:
|
|
case ARM::VADDv1i64:
|
|
case ARM::VADDv2i32:
|
|
case ARM::VADDv2i64:
|
|
case ARM::VADDv4i16:
|
|
case ARM::VADDv4i32:
|
|
case ARM::VADDv8i16:
|
|
case ARM::VADDv8i8:
|
|
case ARM::VANDd:
|
|
case ARM::VANDq:
|
|
case ARM::VBICd:
|
|
case ARM::VBICq:
|
|
case ARM::VCEQfd:
|
|
case ARM::VCEQfq:
|
|
case ARM::VCEQhd:
|
|
case ARM::VCEQhq:
|
|
case ARM::VCEQv16i8:
|
|
case ARM::VCEQv2i32:
|
|
case ARM::VCEQv4i16:
|
|
case ARM::VCEQv4i32:
|
|
case ARM::VCEQv8i16:
|
|
case ARM::VCEQv8i8:
|
|
case ARM::VCGEfd:
|
|
case ARM::VCGEfq:
|
|
case ARM::VCGEhd:
|
|
case ARM::VCGEhq:
|
|
case ARM::VCGEsv16i8:
|
|
case ARM::VCGEsv2i32:
|
|
case ARM::VCGEsv4i16:
|
|
case ARM::VCGEsv4i32:
|
|
case ARM::VCGEsv8i16:
|
|
case ARM::VCGEsv8i8:
|
|
case ARM::VCGEuv16i8:
|
|
case ARM::VCGEuv2i32:
|
|
case ARM::VCGEuv4i16:
|
|
case ARM::VCGEuv4i32:
|
|
case ARM::VCGEuv8i16:
|
|
case ARM::VCGEuv8i8:
|
|
case ARM::VCGTfd:
|
|
case ARM::VCGTfq:
|
|
case ARM::VCGThd:
|
|
case ARM::VCGThq:
|
|
case ARM::VCGTsv16i8:
|
|
case ARM::VCGTsv2i32:
|
|
case ARM::VCGTsv4i16:
|
|
case ARM::VCGTsv4i32:
|
|
case ARM::VCGTsv8i16:
|
|
case ARM::VCGTsv8i8:
|
|
case ARM::VCGTuv16i8:
|
|
case ARM::VCGTuv2i32:
|
|
case ARM::VCGTuv4i16:
|
|
case ARM::VCGTuv4i32:
|
|
case ARM::VCGTuv8i16:
|
|
case ARM::VCGTuv8i8:
|
|
case ARM::VEORd:
|
|
case ARM::VEORq:
|
|
case ARM::VHADDsv16i8:
|
|
case ARM::VHADDsv2i32:
|
|
case ARM::VHADDsv4i16:
|
|
case ARM::VHADDsv4i32:
|
|
case ARM::VHADDsv8i16:
|
|
case ARM::VHADDsv8i8:
|
|
case ARM::VHADDuv16i8:
|
|
case ARM::VHADDuv2i32:
|
|
case ARM::VHADDuv4i16:
|
|
case ARM::VHADDuv4i32:
|
|
case ARM::VHADDuv8i16:
|
|
case ARM::VHADDuv8i8:
|
|
case ARM::VHSUBsv16i8:
|
|
case ARM::VHSUBsv2i32:
|
|
case ARM::VHSUBsv4i16:
|
|
case ARM::VHSUBsv4i32:
|
|
case ARM::VHSUBsv8i16:
|
|
case ARM::VHSUBsv8i8:
|
|
case ARM::VHSUBuv16i8:
|
|
case ARM::VHSUBuv2i32:
|
|
case ARM::VHSUBuv4i16:
|
|
case ARM::VHSUBuv4i32:
|
|
case ARM::VHSUBuv8i16:
|
|
case ARM::VHSUBuv8i8:
|
|
case ARM::VMAXfd:
|
|
case ARM::VMAXfq:
|
|
case ARM::VMAXhd:
|
|
case ARM::VMAXhq:
|
|
case ARM::VMAXsv16i8:
|
|
case ARM::VMAXsv2i32:
|
|
case ARM::VMAXsv4i16:
|
|
case ARM::VMAXsv4i32:
|
|
case ARM::VMAXsv8i16:
|
|
case ARM::VMAXsv8i8:
|
|
case ARM::VMAXuv16i8:
|
|
case ARM::VMAXuv2i32:
|
|
case ARM::VMAXuv4i16:
|
|
case ARM::VMAXuv4i32:
|
|
case ARM::VMAXuv8i16:
|
|
case ARM::VMAXuv8i8:
|
|
case ARM::VMINfd:
|
|
case ARM::VMINfq:
|
|
case ARM::VMINhd:
|
|
case ARM::VMINhq:
|
|
case ARM::VMINsv16i8:
|
|
case ARM::VMINsv2i32:
|
|
case ARM::VMINsv4i16:
|
|
case ARM::VMINsv4i32:
|
|
case ARM::VMINsv8i16:
|
|
case ARM::VMINsv8i8:
|
|
case ARM::VMINuv16i8:
|
|
case ARM::VMINuv2i32:
|
|
case ARM::VMINuv4i16:
|
|
case ARM::VMINuv4i32:
|
|
case ARM::VMINuv8i16:
|
|
case ARM::VMINuv8i8:
|
|
case ARM::VMULLp64:
|
|
case ARM::VMULLp8:
|
|
case ARM::VMULLsv2i64:
|
|
case ARM::VMULLsv4i32:
|
|
case ARM::VMULLsv8i16:
|
|
case ARM::VMULLuv2i64:
|
|
case ARM::VMULLuv4i32:
|
|
case ARM::VMULLuv8i16:
|
|
case ARM::VMULfd:
|
|
case ARM::VMULfq:
|
|
case ARM::VMULhd:
|
|
case ARM::VMULhq:
|
|
case ARM::VMULpd:
|
|
case ARM::VMULpq:
|
|
case ARM::VMULv16i8:
|
|
case ARM::VMULv2i32:
|
|
case ARM::VMULv4i16:
|
|
case ARM::VMULv4i32:
|
|
case ARM::VMULv8i16:
|
|
case ARM::VMULv8i8:
|
|
case ARM::VORNd:
|
|
case ARM::VORNq:
|
|
case ARM::VORRd:
|
|
case ARM::VORRq:
|
|
case ARM::VPADDf:
|
|
case ARM::VPADDh:
|
|
case ARM::VPADDi16:
|
|
case ARM::VPADDi32:
|
|
case ARM::VPADDi8:
|
|
case ARM::VPMAXf:
|
|
case ARM::VPMAXh:
|
|
case ARM::VPMAXs16:
|
|
case ARM::VPMAXs32:
|
|
case ARM::VPMAXs8:
|
|
case ARM::VPMAXu16:
|
|
case ARM::VPMAXu32:
|
|
case ARM::VPMAXu8:
|
|
case ARM::VPMINf:
|
|
case ARM::VPMINh:
|
|
case ARM::VPMINs16:
|
|
case ARM::VPMINs32:
|
|
case ARM::VPMINs8:
|
|
case ARM::VPMINu16:
|
|
case ARM::VPMINu32:
|
|
case ARM::VPMINu8:
|
|
case ARM::VQADDsv16i8:
|
|
case ARM::VQADDsv1i64:
|
|
case ARM::VQADDsv2i32:
|
|
case ARM::VQADDsv2i64:
|
|
case ARM::VQADDsv4i16:
|
|
case ARM::VQADDsv4i32:
|
|
case ARM::VQADDsv8i16:
|
|
case ARM::VQADDsv8i8:
|
|
case ARM::VQADDuv16i8:
|
|
case ARM::VQADDuv1i64:
|
|
case ARM::VQADDuv2i32:
|
|
case ARM::VQADDuv2i64:
|
|
case ARM::VQADDuv4i16:
|
|
case ARM::VQADDuv4i32:
|
|
case ARM::VQADDuv8i16:
|
|
case ARM::VQADDuv8i8:
|
|
case ARM::VQDMULHv2i32:
|
|
case ARM::VQDMULHv4i16:
|
|
case ARM::VQDMULHv4i32:
|
|
case ARM::VQDMULHv8i16:
|
|
case ARM::VQDMULLv2i64:
|
|
case ARM::VQDMULLv4i32:
|
|
case ARM::VQRDMULHv2i32:
|
|
case ARM::VQRDMULHv4i16:
|
|
case ARM::VQRDMULHv4i32:
|
|
case ARM::VQRDMULHv8i16:
|
|
case ARM::VQSUBsv16i8:
|
|
case ARM::VQSUBsv1i64:
|
|
case ARM::VQSUBsv2i32:
|
|
case ARM::VQSUBsv2i64:
|
|
case ARM::VQSUBsv4i16:
|
|
case ARM::VQSUBsv4i32:
|
|
case ARM::VQSUBsv8i16:
|
|
case ARM::VQSUBsv8i8:
|
|
case ARM::VQSUBuv16i8:
|
|
case ARM::VQSUBuv1i64:
|
|
case ARM::VQSUBuv2i32:
|
|
case ARM::VQSUBuv2i64:
|
|
case ARM::VQSUBuv4i16:
|
|
case ARM::VQSUBuv4i32:
|
|
case ARM::VQSUBuv8i16:
|
|
case ARM::VQSUBuv8i8:
|
|
case ARM::VRADDHNv2i32:
|
|
case ARM::VRADDHNv4i16:
|
|
case ARM::VRADDHNv8i8:
|
|
case ARM::VRECPSfd:
|
|
case ARM::VRECPSfq:
|
|
case ARM::VRECPShd:
|
|
case ARM::VRECPShq:
|
|
case ARM::VRHADDsv16i8:
|
|
case ARM::VRHADDsv2i32:
|
|
case ARM::VRHADDsv4i16:
|
|
case ARM::VRHADDsv4i32:
|
|
case ARM::VRHADDsv8i16:
|
|
case ARM::VRHADDsv8i8:
|
|
case ARM::VRHADDuv16i8:
|
|
case ARM::VRHADDuv2i32:
|
|
case ARM::VRHADDuv4i16:
|
|
case ARM::VRHADDuv4i32:
|
|
case ARM::VRHADDuv8i16:
|
|
case ARM::VRHADDuv8i8:
|
|
case ARM::VRSQRTSfd:
|
|
case ARM::VRSQRTSfq:
|
|
case ARM::VRSQRTShd:
|
|
case ARM::VRSQRTShq:
|
|
case ARM::VRSUBHNv2i32:
|
|
case ARM::VRSUBHNv4i16:
|
|
case ARM::VRSUBHNv8i8:
|
|
case ARM::VSUBHNv2i32:
|
|
case ARM::VSUBHNv4i16:
|
|
case ARM::VSUBHNv8i8:
|
|
case ARM::VSUBLsv2i64:
|
|
case ARM::VSUBLsv4i32:
|
|
case ARM::VSUBLsv8i16:
|
|
case ARM::VSUBLuv2i64:
|
|
case ARM::VSUBLuv4i32:
|
|
case ARM::VSUBLuv8i16:
|
|
case ARM::VSUBWsv2i64:
|
|
case ARM::VSUBWsv4i32:
|
|
case ARM::VSUBWsv8i16:
|
|
case ARM::VSUBWuv2i64:
|
|
case ARM::VSUBWuv4i32:
|
|
case ARM::VSUBWuv8i16:
|
|
case ARM::VSUBfd:
|
|
case ARM::VSUBfq:
|
|
case ARM::VSUBhd:
|
|
case ARM::VSUBhq:
|
|
case ARM::VSUBv16i8:
|
|
case ARM::VSUBv1i64:
|
|
case ARM::VSUBv2i32:
|
|
case ARM::VSUBv2i64:
|
|
case ARM::VSUBv4i16:
|
|
case ARM::VSUBv4i32:
|
|
case ARM::VSUBv8i16:
|
|
case ARM::VSUBv8i8:
|
|
case ARM::VTBL1:
|
|
case ARM::VTBL2:
|
|
case ARM::VTBL3:
|
|
case ARM::VTBL4:
|
|
case ARM::VTSTv16i8:
|
|
case ARM::VTSTv2i32:
|
|
case ARM::VTSTv4i16:
|
|
case ARM::VTSTv4i32:
|
|
case ARM::VTSTv8i16:
|
|
case ARM::VTSTv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMAXNMNDf:
|
|
case ARM::VMAXNMNDh:
|
|
case ARM::VMAXNMNQf:
|
|
case ARM::VMAXNMNQh:
|
|
case ARM::VMINNMNDf:
|
|
case ARM::VMINNMNDh:
|
|
case ARM::VMINNMNQf:
|
|
case ARM::VMINNMNQh: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2V8PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMULLslsv2i32:
|
|
case ARM::VMULLsluv2i32:
|
|
case ARM::VMULslfd:
|
|
case ARM::VMULslfq:
|
|
case ARM::VMULslv2i32:
|
|
case ARM::VMULslv4i32:
|
|
case ARM::VQDMULHslv2i32:
|
|
case ARM::VQDMULHslv4i32:
|
|
case ARM::VQDMULLslv2i32:
|
|
case ARM::VQRDMULHslv2i32:
|
|
case ARM::VQRDMULHslv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMULLslsv4i16:
|
|
case ARM::VMULLsluv4i16:
|
|
case ARM::VMULslhd:
|
|
case ARM::VMULslhq:
|
|
case ARM::VMULslv4i16:
|
|
case ARM::VMULslv8i16:
|
|
case ARM::VQDMULHslv4i16:
|
|
case ARM::VQDMULHslv8i16:
|
|
case ARM::VQDMULLslv4i16:
|
|
case ARM::VQRDMULHslv4i16:
|
|
case ARM::VQRDMULHslv8i16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(2)) << 4;
|
|
Value |= (op & UINT64_C(1)) << 3;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VQRSHLsv16i8:
|
|
case ARM::VQRSHLsv1i64:
|
|
case ARM::VQRSHLsv2i32:
|
|
case ARM::VQRSHLsv2i64:
|
|
case ARM::VQRSHLsv4i16:
|
|
case ARM::VQRSHLsv4i32:
|
|
case ARM::VQRSHLsv8i16:
|
|
case ARM::VQRSHLsv8i8:
|
|
case ARM::VQRSHLuv16i8:
|
|
case ARM::VQRSHLuv1i64:
|
|
case ARM::VQRSHLuv2i32:
|
|
case ARM::VQRSHLuv2i64:
|
|
case ARM::VQRSHLuv4i16:
|
|
case ARM::VQRSHLuv4i32:
|
|
case ARM::VQRSHLuv8i16:
|
|
case ARM::VQRSHLuv8i8:
|
|
case ARM::VQSHLsv16i8:
|
|
case ARM::VQSHLsv1i64:
|
|
case ARM::VQSHLsv2i32:
|
|
case ARM::VQSHLsv2i64:
|
|
case ARM::VQSHLsv4i16:
|
|
case ARM::VQSHLsv4i32:
|
|
case ARM::VQSHLsv8i16:
|
|
case ARM::VQSHLsv8i8:
|
|
case ARM::VQSHLuv16i8:
|
|
case ARM::VQSHLuv1i64:
|
|
case ARM::VQSHLuv2i32:
|
|
case ARM::VQSHLuv2i64:
|
|
case ARM::VQSHLuv4i16:
|
|
case ARM::VQSHLuv4i32:
|
|
case ARM::VQSHLuv8i16:
|
|
case ARM::VQSHLuv8i8:
|
|
case ARM::VRSHLsv16i8:
|
|
case ARM::VRSHLsv1i64:
|
|
case ARM::VRSHLsv2i32:
|
|
case ARM::VRSHLsv2i64:
|
|
case ARM::VRSHLsv4i16:
|
|
case ARM::VRSHLsv4i32:
|
|
case ARM::VRSHLsv8i16:
|
|
case ARM::VRSHLsv8i8:
|
|
case ARM::VRSHLuv16i8:
|
|
case ARM::VRSHLuv1i64:
|
|
case ARM::VRSHLuv2i32:
|
|
case ARM::VRSHLuv2i64:
|
|
case ARM::VRSHLuv4i16:
|
|
case ARM::VRSHLuv4i32:
|
|
case ARM::VRSHLuv8i16:
|
|
case ARM::VRSHLuv8i8:
|
|
case ARM::VSHLsv16i8:
|
|
case ARM::VSHLsv1i64:
|
|
case ARM::VSHLsv2i32:
|
|
case ARM::VSHLsv2i64:
|
|
case ARM::VSHLsv4i16:
|
|
case ARM::VSHLsv4i32:
|
|
case ARM::VSHLsv8i16:
|
|
case ARM::VSHLsv8i8:
|
|
case ARM::VSHLuv16i8:
|
|
case ARM::VSHLuv1i64:
|
|
case ARM::VSHLuv2i32:
|
|
case ARM::VSHLuv2i64:
|
|
case ARM::VSHLuv4i16:
|
|
case ARM::VSHLuv4i32:
|
|
case ARM::VSHLuv8i16:
|
|
case ARM::VSHLuv8i8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::SHA1C:
|
|
case ARM::SHA1M:
|
|
case ARM::SHA1P:
|
|
case ARM::SHA1SU0:
|
|
case ARM::SHA256H:
|
|
case ARM::SHA256H2:
|
|
case ARM::SHA256SU1:
|
|
case ARM::VABALsv2i64:
|
|
case ARM::VABALsv4i32:
|
|
case ARM::VABALsv8i16:
|
|
case ARM::VABALuv2i64:
|
|
case ARM::VABALuv4i32:
|
|
case ARM::VABALuv8i16:
|
|
case ARM::VABAsv16i8:
|
|
case ARM::VABAsv2i32:
|
|
case ARM::VABAsv4i16:
|
|
case ARM::VABAsv4i32:
|
|
case ARM::VABAsv8i16:
|
|
case ARM::VABAsv8i8:
|
|
case ARM::VABAuv16i8:
|
|
case ARM::VABAuv2i32:
|
|
case ARM::VABAuv4i16:
|
|
case ARM::VABAuv4i32:
|
|
case ARM::VABAuv8i16:
|
|
case ARM::VABAuv8i8:
|
|
case ARM::VBIFd:
|
|
case ARM::VBIFq:
|
|
case ARM::VBITd:
|
|
case ARM::VBITq:
|
|
case ARM::VBSLd:
|
|
case ARM::VBSLq:
|
|
case ARM::VFMAfd:
|
|
case ARM::VFMAfq:
|
|
case ARM::VFMAhd:
|
|
case ARM::VFMAhq:
|
|
case ARM::VFMSfd:
|
|
case ARM::VFMSfq:
|
|
case ARM::VFMShd:
|
|
case ARM::VFMShq:
|
|
case ARM::VMLALsv2i64:
|
|
case ARM::VMLALsv4i32:
|
|
case ARM::VMLALsv8i16:
|
|
case ARM::VMLALuv2i64:
|
|
case ARM::VMLALuv4i32:
|
|
case ARM::VMLALuv8i16:
|
|
case ARM::VMLAfd:
|
|
case ARM::VMLAfq:
|
|
case ARM::VMLAhd:
|
|
case ARM::VMLAhq:
|
|
case ARM::VMLAv16i8:
|
|
case ARM::VMLAv2i32:
|
|
case ARM::VMLAv4i16:
|
|
case ARM::VMLAv4i32:
|
|
case ARM::VMLAv8i16:
|
|
case ARM::VMLAv8i8:
|
|
case ARM::VMLSLsv2i64:
|
|
case ARM::VMLSLsv4i32:
|
|
case ARM::VMLSLsv8i16:
|
|
case ARM::VMLSLuv2i64:
|
|
case ARM::VMLSLuv4i32:
|
|
case ARM::VMLSLuv8i16:
|
|
case ARM::VMLSfd:
|
|
case ARM::VMLSfq:
|
|
case ARM::VMLShd:
|
|
case ARM::VMLShq:
|
|
case ARM::VMLSv16i8:
|
|
case ARM::VMLSv2i32:
|
|
case ARM::VMLSv4i16:
|
|
case ARM::VMLSv4i32:
|
|
case ARM::VMLSv8i16:
|
|
case ARM::VMLSv8i8:
|
|
case ARM::VQDMLALv2i64:
|
|
case ARM::VQDMLALv4i32:
|
|
case ARM::VQDMLSLv2i64:
|
|
case ARM::VQDMLSLv4i32:
|
|
case ARM::VQRDMLAHv2i32:
|
|
case ARM::VQRDMLAHv4i16:
|
|
case ARM::VQRDMLAHv4i32:
|
|
case ARM::VQRDMLAHv8i16:
|
|
case ARM::VQRDMLSHv2i32:
|
|
case ARM::VQRDMLSHv4i16:
|
|
case ARM::VQRDMLSHv4i32:
|
|
case ARM::VQRDMLSHv8i16:
|
|
case ARM::VTBX1:
|
|
case ARM::VTBX2:
|
|
case ARM::VTBX3:
|
|
case ARM::VTBX4: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMLALslsv2i32:
|
|
case ARM::VMLALsluv2i32:
|
|
case ARM::VMLAslfd:
|
|
case ARM::VMLAslfq:
|
|
case ARM::VMLAslv2i32:
|
|
case ARM::VMLAslv4i32:
|
|
case ARM::VMLSLslsv2i32:
|
|
case ARM::VMLSLsluv2i32:
|
|
case ARM::VMLSslfd:
|
|
case ARM::VMLSslfq:
|
|
case ARM::VMLSslv2i32:
|
|
case ARM::VMLSslv4i32:
|
|
case ARM::VQDMLALslv2i32:
|
|
case ARM::VQDMLSLslv2i32:
|
|
case ARM::VQRDMLAHslv2i32:
|
|
case ARM::VQRDMLAHslv4i32:
|
|
case ARM::VQRDMLSHslv2i32:
|
|
case ARM::VQRDMLSHslv4i32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMLALslsv4i16:
|
|
case ARM::VMLALsluv4i16:
|
|
case ARM::VMLAslhd:
|
|
case ARM::VMLAslhq:
|
|
case ARM::VMLAslv4i16:
|
|
case ARM::VMLAslv8i16:
|
|
case ARM::VMLSLslsv4i16:
|
|
case ARM::VMLSLsluv4i16:
|
|
case ARM::VMLSslhd:
|
|
case ARM::VMLSslhq:
|
|
case ARM::VMLSslv4i16:
|
|
case ARM::VMLSslv8i16:
|
|
case ARM::VQDMLALslv4i16:
|
|
case ARM::VQDMLSLslv4i16:
|
|
case ARM::VQRDMLAHslv4i16:
|
|
case ARM::VQRDMLAHslv8i16:
|
|
case ARM::VQRDMLSHslv4i16:
|
|
case ARM::VQRDMLSHslv8i16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Vn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Vm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(2)) << 4;
|
|
Value |= (op & UINT64_C(1)) << 3;
|
|
Value = NEONThumb2DataIPostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST3LNd32:
|
|
case ARM::VST3LNq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST3LNd16:
|
|
case ARM::VST3LNq16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST3LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1LNd16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST2LNd32:
|
|
case ARM::VST2LNq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST2LNd16:
|
|
case ARM::VST2LNq16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST2LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST4LNd16:
|
|
case ARM::VST4LNq16: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST4LNd8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1d16:
|
|
case ARM::VST1d16T:
|
|
case ARM::VST1d32:
|
|
case ARM::VST1d32T:
|
|
case ARM::VST1d64:
|
|
case ARM::VST1d64T:
|
|
case ARM::VST1d8:
|
|
case ARM::VST1d8T:
|
|
case ARM::VST3d16:
|
|
case ARM::VST3d32:
|
|
case ARM::VST3d8:
|
|
case ARM::VST3q16:
|
|
case ARM::VST3q32:
|
|
case ARM::VST3q8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST4LNd32:
|
|
case ARM::VST4LNq32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1d16Q:
|
|
case ARM::VST1d32Q:
|
|
case ARM::VST1d64Q:
|
|
case ARM::VST1d8Q:
|
|
case ARM::VST1q16:
|
|
case ARM::VST1q32:
|
|
case ARM::VST1q64:
|
|
case ARM::VST1q8:
|
|
case ARM::VST2b16:
|
|
case ARM::VST2b32:
|
|
case ARM::VST2b8:
|
|
case ARM::VST2d16:
|
|
case ARM::VST2d32:
|
|
case ARM::VST2d8:
|
|
case ARM::VST2q16:
|
|
case ARM::VST2q32:
|
|
case ARM::VST2q8:
|
|
case ARM::VST4d16:
|
|
case ARM::VST4d32:
|
|
case ARM::VST4d8:
|
|
case ARM::VST4q16:
|
|
case ARM::VST4q32:
|
|
case ARM::VST4q8: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1LNd32: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1d16wb_fixed:
|
|
case ARM::VST1d32wb_fixed:
|
|
case ARM::VST1d64wb_fixed:
|
|
case ARM::VST1d8wb_fixed: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1d16Qwb_fixed:
|
|
case ARM::VST1d16Twb_fixed:
|
|
case ARM::VST1d32Qwb_fixed:
|
|
case ARM::VST1d32Twb_fixed:
|
|
case ARM::VST1d64Qwb_fixed:
|
|
case ARM::VST1d64Twb_fixed:
|
|
case ARM::VST1d8Qwb_fixed:
|
|
case ARM::VST1d8Twb_fixed:
|
|
case ARM::VST1q16wb_fixed:
|
|
case ARM::VST1q32wb_fixed:
|
|
case ARM::VST1q64wb_fixed:
|
|
case ARM::VST1q8wb_fixed:
|
|
case ARM::VST2b16wb_fixed:
|
|
case ARM::VST2b32wb_fixed:
|
|
case ARM::VST2b8wb_fixed:
|
|
case ARM::VST2d16wb_fixed:
|
|
case ARM::VST2d32wb_fixed:
|
|
case ARM::VST2d8wb_fixed:
|
|
case ARM::VST2q16wb_fixed:
|
|
case ARM::VST2q32wb_fixed:
|
|
case ARM::VST2q8wb_fixed: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST3LNd32_UPD:
|
|
case ARM::VST3LNq32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST3LNd16_UPD:
|
|
case ARM::VST3LNq16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST3LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1LNd16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST2LNd32_UPD:
|
|
case ARM::VST2LNq32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST2LNd16_UPD:
|
|
case ARM::VST2LNq16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST2LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST4LNd16_UPD:
|
|
case ARM::VST4LNq16_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST4LNd8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST3d16_UPD:
|
|
case ARM::VST3d32_UPD:
|
|
case ARM::VST3d8_UPD:
|
|
case ARM::VST3q16_UPD:
|
|
case ARM::VST3q32_UPD:
|
|
case ARM::VST3q8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1d16wb_register:
|
|
case ARM::VST1d32wb_register:
|
|
case ARM::VST1d64wb_register:
|
|
case ARM::VST1d8wb_register: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST4LNd32_UPD:
|
|
case ARM::VST4LNq32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST4d16_UPD:
|
|
case ARM::VST4d32_UPD:
|
|
case ARM::VST4d8_UPD:
|
|
case ARM::VST4q16_UPD:
|
|
case ARM::VST4q32_UPD:
|
|
case ARM::VST4q8_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1d16Qwb_register:
|
|
case ARM::VST1d16Twb_register:
|
|
case ARM::VST1d32Qwb_register:
|
|
case ARM::VST1d32Twb_register:
|
|
case ARM::VST1d64Qwb_register:
|
|
case ARM::VST1d64Twb_register:
|
|
case ARM::VST1d8Qwb_register:
|
|
case ARM::VST1d8Twb_register:
|
|
case ARM::VST1q16wb_register:
|
|
case ARM::VST1q32wb_register:
|
|
case ARM::VST1q64wb_register:
|
|
case ARM::VST1q8wb_register:
|
|
case ARM::VST2b16wb_register:
|
|
case ARM::VST2b32wb_register:
|
|
case ARM::VST2b8wb_register:
|
|
case ARM::VST2d16wb_register:
|
|
case ARM::VST2d32wb_register:
|
|
case ARM::VST2d8wb_register:
|
|
case ARM::VST2q16wb_register:
|
|
case ARM::VST2q32wb_register:
|
|
case ARM::VST2q8wb_register: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VST1LNd32_UPD: {
|
|
// op: Vd
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(48);
|
|
// op: Rm
|
|
op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lane
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::LDC2L_OFFSET:
|
|
case ARM::LDC2L_PRE:
|
|
case ARM::LDC2_OFFSET:
|
|
case ARM::LDC2_PRE:
|
|
case ARM::STC2L_OFFSET:
|
|
case ARM::STC2L_PRE:
|
|
case ARM::STC2_OFFSET:
|
|
case ARM::STC2_PRE:
|
|
case ARM::t2LDC2L_OFFSET:
|
|
case ARM::t2LDC2L_PRE:
|
|
case ARM::t2LDC2_OFFSET:
|
|
case ARM::t2LDC2_PRE:
|
|
case ARM::t2LDCL_OFFSET:
|
|
case ARM::t2LDCL_PRE:
|
|
case ARM::t2LDC_OFFSET:
|
|
case ARM::t2LDC_PRE:
|
|
case ARM::t2STC2L_OFFSET:
|
|
case ARM::t2STC2L_PRE:
|
|
case ARM::t2STC2_OFFSET:
|
|
case ARM::t2STC2_PRE:
|
|
case ARM::t2STCL_OFFSET:
|
|
case ARM::t2STCL_PRE:
|
|
case ARM::t2STC_OFFSET:
|
|
case ARM::t2STC_PRE: {
|
|
// op: addr
|
|
op = getAddrMode5OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::t2PLDWi12:
|
|
case ARM::t2PLDi12:
|
|
case ARM::t2PLIi12: {
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::PLDWi12:
|
|
case ARM::PLDi12:
|
|
case ARM::PLIi12: {
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::t2PLDpci:
|
|
case ARM::t2PLIpci: {
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::t2LDAEXB:
|
|
case ARM::t2LDAEXH:
|
|
case ARM::t2LDREXB:
|
|
case ARM::t2LDREXH: {
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::t2LDAEXD:
|
|
case ARM::t2LDREXD: {
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
break;
|
|
}
|
|
case ARM::t2PLDWi8:
|
|
case ARM::t2PLDi8:
|
|
case ARM::t2PLIi8: {
|
|
// op: addr
|
|
op = getT2AddrModeImm8OpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2PLDWs:
|
|
case ARM::t2PLDs:
|
|
case ARM::t2PLIs: {
|
|
// op: addr
|
|
op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(960)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 4;
|
|
Value |= (op & UINT64_C(60)) >> 2;
|
|
break;
|
|
}
|
|
case ARM::t2MSRbanked: {
|
|
// op: banked
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(32)) << 15;
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::t2MRSbanked: {
|
|
// op: banked
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(32)) << 15;
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= op & UINT64_C(16);
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
break;
|
|
}
|
|
case ARM::t2IT: {
|
|
// op: cc
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 4;
|
|
// op: mask
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::tADDrSPi: {
|
|
// op: dst
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 8;
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::BX: {
|
|
// op: dst
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::tPICADD: {
|
|
// op: dst
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::tSETEND: {
|
|
// op: end
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 3;
|
|
break;
|
|
}
|
|
case ARM::SETEND: {
|
|
// op: end
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 9;
|
|
break;
|
|
}
|
|
case ARM::BL: {
|
|
// op: func
|
|
op = getARMBLTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= op & UINT64_C(16777215);
|
|
break;
|
|
}
|
|
case ARM::t2BXJ: {
|
|
// op: func
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::BLX: {
|
|
// op: func
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::tBLXNSr:
|
|
case ARM::tBLXr: {
|
|
// op: func
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 3;
|
|
break;
|
|
}
|
|
case ARM::tBL: {
|
|
// op: func
|
|
op = getThumbBLTargetOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(8388608)) << 3;
|
|
Value |= (op & UINT64_C(2095104)) << 5;
|
|
Value |= (op & UINT64_C(4194304)) >> 9;
|
|
Value |= (op & UINT64_C(2097152)) >> 10;
|
|
Value |= op & UINT64_C(2047);
|
|
break;
|
|
}
|
|
case ARM::tBLXi: {
|
|
// op: func
|
|
op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(8388608)) << 3;
|
|
Value |= (op & UINT64_C(2095104)) << 5;
|
|
Value |= (op & UINT64_C(4194304)) >> 9;
|
|
Value |= (op & UINT64_C(2097152)) >> 10;
|
|
Value |= op & UINT64_C(2046);
|
|
break;
|
|
}
|
|
case ARM::t2SETPAN: {
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 3;
|
|
break;
|
|
}
|
|
case ARM::SETPAN: {
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 9;
|
|
break;
|
|
}
|
|
case ARM::tHINT: {
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 4;
|
|
break;
|
|
}
|
|
case ARM::HVC: {
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(65520)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2HINT:
|
|
case ARM::t2SUBS_PC_LR:
|
|
case ARM::tSVC: {
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tADDspi:
|
|
case ARM::tSUBspi: {
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(127);
|
|
break;
|
|
}
|
|
case ARM::t2HVC:
|
|
case ARM::t2UDF: {
|
|
// op: imm16
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(61440)) << 4;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::UDF: {
|
|
// op: imm16
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(65520)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::tUDF: {
|
|
// op: imm8
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tCPS: {
|
|
// op: imod
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 4;
|
|
// op: iflags
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::CPS2p: {
|
|
// op: imod
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 18;
|
|
// op: iflags
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 6;
|
|
break;
|
|
}
|
|
case ARM::CPS3p: {
|
|
// op: imod
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 18;
|
|
// op: iflags
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 6;
|
|
// op: mode
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(31);
|
|
break;
|
|
}
|
|
case ARM::t2CPS2p: {
|
|
// op: imod
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 9;
|
|
// op: iflags
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
break;
|
|
}
|
|
case ARM::t2CPS3p: {
|
|
// op: imod
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 9;
|
|
// op: iflags
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
// op: mode
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(31);
|
|
break;
|
|
}
|
|
case ARM::t2MSR_AR: {
|
|
// op: mask
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 16;
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::CPS1p:
|
|
case ARM::SRSDA:
|
|
case ARM::SRSDA_UPD:
|
|
case ARM::SRSDB:
|
|
case ARM::SRSDB_UPD:
|
|
case ARM::SRSIA:
|
|
case ARM::SRSIA_UPD:
|
|
case ARM::SRSIB:
|
|
case ARM::SRSIB_UPD:
|
|
case ARM::t2CPS1p:
|
|
case ARM::t2SRSDB:
|
|
case ARM::t2SRSDB_UPD:
|
|
case ARM::t2SRSIA:
|
|
case ARM::t2SRSIA_UPD: {
|
|
// op: mode
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(31);
|
|
break;
|
|
}
|
|
case ARM::LDC2L_POST:
|
|
case ARM::LDC2_POST:
|
|
case ARM::STC2L_POST:
|
|
case ARM::STC2_POST:
|
|
case ARM::t2LDC2L_POST:
|
|
case ARM::t2LDC2_POST:
|
|
case ARM::t2LDCL_POST:
|
|
case ARM::t2LDC_POST:
|
|
case ARM::t2STC2L_POST:
|
|
case ARM::t2STC2_POST:
|
|
case ARM::t2STCL_POST:
|
|
case ARM::t2STC_POST: {
|
|
// op: offset
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= op & UINT64_C(255);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::CDP2:
|
|
case ARM::t2CDP:
|
|
case ARM::t2CDP2: {
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 20;
|
|
// op: CRn
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc2
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2SMC: {
|
|
// op: opt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::DMB:
|
|
case ARM::DSB:
|
|
case ARM::ISB:
|
|
case ARM::t2DBG:
|
|
case ARM::t2DMB:
|
|
case ARM::t2DSB:
|
|
case ARM::t2ISB: {
|
|
// op: opt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::LDC2L_OPTION:
|
|
case ARM::LDC2_OPTION:
|
|
case ARM::STC2L_OPTION:
|
|
case ARM::STC2_OPTION:
|
|
case ARM::t2LDC2L_OPTION:
|
|
case ARM::t2LDC2_OPTION:
|
|
case ARM::t2LDCL_OPTION:
|
|
case ARM::t2LDC_OPTION:
|
|
case ARM::t2STC2L_OPTION:
|
|
case ARM::t2STC2_OPTION:
|
|
case ARM::t2STCL_OPTION:
|
|
case ARM::t2STC_OPTION: {
|
|
// op: option
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::BX_RET:
|
|
case ARM::ERET:
|
|
case ARM::MOVPCLR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
break;
|
|
}
|
|
case ARM::FMSTAT: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::t2Bcc: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 22;
|
|
// op: target
|
|
op = getBranchTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(1048576)) << 6;
|
|
Value |= (op & UINT64_C(258048)) << 4;
|
|
Value |= (op & UINT64_C(262144)) >> 5;
|
|
Value |= (op & UINT64_C(524288)) >> 8;
|
|
Value |= (op & UINT64_C(4094)) >> 1;
|
|
break;
|
|
}
|
|
case ARM::VCMPEZD:
|
|
case ARM::VCMPZD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::MRS:
|
|
case ARM::MRSsys: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::VLDMSIA:
|
|
case ARM::VSTMSIA: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 14;
|
|
Value |= (op & UINT64_C(7680)) << 3;
|
|
Value |= op & UINT64_C(255);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::FLDMXIA:
|
|
case ARM::FSTMXIA: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(3840)) << 4;
|
|
Value |= op & UINT64_C(254);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLDMDIA:
|
|
case ARM::VSTMDIA: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 10;
|
|
Value |= (op & UINT64_C(3840)) << 4;
|
|
Value |= op & UINT64_C(254);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLLDM:
|
|
case ARM::VLSTM: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMRS:
|
|
case ARM::VMRS_FPEXC:
|
|
case ARM::VMRS_FPINST:
|
|
case ARM::VMRS_FPINST2:
|
|
case ARM::VMRS_FPSID:
|
|
case ARM::VMRS_MVFR0:
|
|
case ARM::VMRS_MVFR1:
|
|
case ARM::VMRS_MVFR2: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VCMPEZH:
|
|
case ARM::VCMPEZS:
|
|
case ARM::VCMPZH:
|
|
case ARM::VCMPZS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::BX_pred: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: dst
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::BL_pred: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: func
|
|
op = getARMBLTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= op & UINT64_C(16777215);
|
|
break;
|
|
}
|
|
case ARM::BLX_pred:
|
|
case ARM::BXJ: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: func
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::HINT: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::DBG:
|
|
case ARM::SMC: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: opt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::LDMDA:
|
|
case ARM::LDMDB:
|
|
case ARM::LDMIA:
|
|
case ARM::LDMIB:
|
|
case ARM::STMDA:
|
|
case ARM::STMDB:
|
|
case ARM::STMIA:
|
|
case ARM::STMIB:
|
|
case ARM::sysLDMDA:
|
|
case ARM::sysLDMDB:
|
|
case ARM::sysLDMIA:
|
|
case ARM::sysLDMIB:
|
|
case ARM::sysSTMDA:
|
|
case ARM::sysSTMDB:
|
|
case ARM::sysSTMIA:
|
|
case ARM::sysSTMIB: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 3, Fixups, STI);
|
|
Value |= op & UINT64_C(65535);
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::VMSR:
|
|
case ARM::VMSR_FPEXC:
|
|
case ARM::VMSR_FPINST:
|
|
case ARM::VMSR_FPINST2:
|
|
case ARM::VMSR_FPSID: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: src
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::SVC: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: svc
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(16777215);
|
|
break;
|
|
}
|
|
case ARM::Bcc: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: target
|
|
op = getARMBranchTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= op & UINT64_C(16777215);
|
|
break;
|
|
}
|
|
case ARM::tBcc: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: target
|
|
op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::VABSD:
|
|
case ARM::VCMPD:
|
|
case ARM::VCMPED:
|
|
case ARM::VMOVD:
|
|
case ARM::VNEGD:
|
|
case ARM::VRINTRD:
|
|
case ARM::VRINTXD:
|
|
case ARM::VRINTZD:
|
|
case ARM::VSQRTD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VCVTBHD:
|
|
case ARM::VCVTTHD:
|
|
case ARM::VSITOD:
|
|
case ARM::VUITOD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Sm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::FCONSTD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(240)) << 12;
|
|
Value |= op & UINT64_C(15);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VCVTBDH:
|
|
case ARM::VCVTTDH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::CLZ:
|
|
case ARM::RBIT:
|
|
case ARM::REV:
|
|
case ARM::REV16:
|
|
case ARM::REVSH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MOVi16: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: imm
|
|
op = getHiLo16ImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(61440)) << 4;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::ADR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: label
|
|
op = getAdrLabelOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(12288)) << 10;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::CMNzrr:
|
|
case ARM::CMPrr:
|
|
case ARM::TEQrr:
|
|
case ARM::TSTrr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::CMNri:
|
|
case ARM::CMPri:
|
|
case ARM::TEQri:
|
|
case ARM::TSTri: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getModImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::VLDMSDB_UPD:
|
|
case ARM::VLDMSIA_UPD:
|
|
case ARM::VSTMSDB_UPD:
|
|
case ARM::VSTMSIA_UPD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 14;
|
|
Value |= (op & UINT64_C(7680)) << 3;
|
|
Value |= op & UINT64_C(255);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::FLDMXDB_UPD:
|
|
case ARM::FLDMXIA_UPD:
|
|
case ARM::FSTMXDB_UPD:
|
|
case ARM::FSTMXIA_UPD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(3840)) << 4;
|
|
Value |= op & UINT64_C(254);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLDMDDB_UPD:
|
|
case ARM::VLDMDIA_UPD:
|
|
case ARM::VSTMDDB_UPD:
|
|
case ARM::VSTMDIA_UPD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 10;
|
|
Value |= (op & UINT64_C(3840)) << 4;
|
|
Value |= op & UINT64_C(254);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMOVRH:
|
|
case ARM::VMOVRS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Sn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(30)) << 15;
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::LDA:
|
|
case ARM::LDAB:
|
|
case ARM::LDAEX:
|
|
case ARM::LDAEXB:
|
|
case ARM::LDAEXD:
|
|
case ARM::LDAEXH:
|
|
case ARM::LDAH:
|
|
case ARM::LDREX:
|
|
case ARM::LDREXB:
|
|
case ARM::LDREXD:
|
|
case ARM::LDREXH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::STL:
|
|
case ARM::STLB:
|
|
case ARM::STLH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::VCVTSD:
|
|
case ARM::VTOSIRD:
|
|
case ARM::VTOSIZD:
|
|
case ARM::VTOUIRD:
|
|
case ARM::VTOUIZD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VABSH:
|
|
case ARM::VABSS:
|
|
case ARM::VCMPEH:
|
|
case ARM::VCMPES:
|
|
case ARM::VCMPH:
|
|
case ARM::VCMPS:
|
|
case ARM::VCVTBHS:
|
|
case ARM::VCVTBSH:
|
|
case ARM::VCVTTHS:
|
|
case ARM::VCVTTSH:
|
|
case ARM::VMOVS:
|
|
case ARM::VNEGH:
|
|
case ARM::VNEGS:
|
|
case ARM::VRINTRH:
|
|
case ARM::VRINTRS:
|
|
case ARM::VRINTXH:
|
|
case ARM::VRINTXS:
|
|
case ARM::VRINTZH:
|
|
case ARM::VRINTZS:
|
|
case ARM::VSITOH:
|
|
case ARM::VSITOS:
|
|
case ARM::VSQRTH:
|
|
case ARM::VSQRTS:
|
|
case ARM::VTOSIRH:
|
|
case ARM::VTOSIRS:
|
|
case ARM::VTOSIZH:
|
|
case ARM::VTOSIZS:
|
|
case ARM::VTOUIRH:
|
|
case ARM::VTOUIRS:
|
|
case ARM::VTOUIZH:
|
|
case ARM::VTOUIZS:
|
|
case ARM::VUITOH:
|
|
case ARM::VUITOS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: Sm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::FCONSTH:
|
|
case ARM::FCONSTS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(240)) << 12;
|
|
Value |= op & UINT64_C(15);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VCVTDS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMOVHR:
|
|
case ARM::VMOVSR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(30)) << 15;
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::MSRbanked: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: banked
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(32)) << 17;
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 4;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MRSbanked: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: banked
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(32)) << 17;
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 4;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::MSR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: mask
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MSRi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: mask
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getModImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::LDMDA_UPD:
|
|
case ARM::LDMDB_UPD:
|
|
case ARM::LDMIA_UPD:
|
|
case ARM::LDMIB_UPD:
|
|
case ARM::STMDA_UPD:
|
|
case ARM::STMDB_UPD:
|
|
case ARM::STMIA_UPD:
|
|
case ARM::STMIB_UPD:
|
|
case ARM::sysLDMDA_UPD:
|
|
case ARM::sysLDMDB_UPD:
|
|
case ARM::sysLDMIA_UPD:
|
|
case ARM::sysLDMIB_UPD:
|
|
case ARM::sysSTMDA_UPD:
|
|
case ARM::sysSTMDB_UPD:
|
|
case ARM::sysSTMIA_UPD:
|
|
case ARM::sysSTMIB_UPD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 4, Fixups, STI);
|
|
Value |= op & UINT64_C(65535);
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::MOVr:
|
|
case ARM::MOVr_TC:
|
|
case ARM::MVNr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MOVi:
|
|
case ARM::MVNi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: imm
|
|
op = getModImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::VADDD:
|
|
case ARM::VDIVD:
|
|
case ARM::VMULD:
|
|
case ARM::VNMULD:
|
|
case ARM::VSUBD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Dn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLDRD:
|
|
case ARM::VSTRD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrMode5OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMOVDRR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VMOVRRD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::SXTB:
|
|
case ARM::SXTB16:
|
|
case ARM::SXTH:
|
|
case ARM::UXTB:
|
|
case ARM::UXTB16:
|
|
case ARM::UXTH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: rot
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 10;
|
|
break;
|
|
}
|
|
case ARM::SEL: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::BFC: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: imm
|
|
op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(992)) << 11;
|
|
Value |= (op & UINT64_C(31)) << 7;
|
|
break;
|
|
}
|
|
case ARM::MOVTi16: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: imm
|
|
op = getHiLo16ImmOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(61440)) << 4;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::SSAT16:
|
|
case ARM::USAT16: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: sat_imm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::SDIV:
|
|
case ARM::SMMUL:
|
|
case ARM::SMMULR:
|
|
case ARM::UDIV:
|
|
case ARM::USAD8: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
break;
|
|
}
|
|
case ARM::CMNzrsi:
|
|
case ARM::CMPrsi:
|
|
case ARM::TEQrsi:
|
|
case ARM::TSTrsi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: shift
|
|
op = getSORegImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::QADD16:
|
|
case ARM::QADD8:
|
|
case ARM::QASX:
|
|
case ARM::QSAX:
|
|
case ARM::QSUB16:
|
|
case ARM::QSUB8:
|
|
case ARM::SADD16:
|
|
case ARM::SADD8:
|
|
case ARM::SASX:
|
|
case ARM::SHADD16:
|
|
case ARM::SHADD8:
|
|
case ARM::SHASX:
|
|
case ARM::SHSAX:
|
|
case ARM::SHSUB16:
|
|
case ARM::SHSUB8:
|
|
case ARM::SSAX:
|
|
case ARM::SSUB16:
|
|
case ARM::SSUB8:
|
|
case ARM::UADD16:
|
|
case ARM::UADD8:
|
|
case ARM::UASX:
|
|
case ARM::UHADD16:
|
|
case ARM::UHADD8:
|
|
case ARM::UHASX:
|
|
case ARM::UHSAX:
|
|
case ARM::UHSUB16:
|
|
case ARM::UHSUB8:
|
|
case ARM::UQADD16:
|
|
case ARM::UQADD8:
|
|
case ARM::UQASX:
|
|
case ARM::UQSAX:
|
|
case ARM::UQSUB16:
|
|
case ARM::UQSUB8:
|
|
case ARM::USAX:
|
|
case ARM::USUB16:
|
|
case ARM::USUB8: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::SMUAD:
|
|
case ARM::SMUADX:
|
|
case ARM::SMULBB:
|
|
case ARM::SMULBT:
|
|
case ARM::SMULTB:
|
|
case ARM::SMULTT:
|
|
case ARM::SMULWB:
|
|
case ARM::SMULWT:
|
|
case ARM::SMUSD:
|
|
case ARM::SMUSDX: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::QADD:
|
|
case ARM::QDADD:
|
|
case ARM::QDSUB:
|
|
case ARM::QSUB: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::SWP:
|
|
case ARM::SWPB: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::LDRBi12:
|
|
case ARM::LDRi12:
|
|
case ARM::STRBi12:
|
|
case ARM::STRi12: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::LDRcp: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::STLEX:
|
|
case ARM::STLEXB:
|
|
case ARM::STLEXD:
|
|
case ARM::STLEXH:
|
|
case ARM::STREX:
|
|
case ARM::STREXB:
|
|
case ARM::STREXD:
|
|
case ARM::STREXH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::VADDH:
|
|
case ARM::VADDS:
|
|
case ARM::VDIVH:
|
|
case ARM::VDIVS:
|
|
case ARM::VMULH:
|
|
case ARM::VMULS:
|
|
case ARM::VNMULH:
|
|
case ARM::VNMULS:
|
|
case ARM::VSUBH:
|
|
case ARM::VSUBS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: Sn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(30)) << 15;
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
// op: Sm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLDRH:
|
|
case ARM::VSTRH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: addr
|
|
op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VLDRS:
|
|
case ARM::VSTRS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: addr
|
|
op = getAddrMode5OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSHTOH:
|
|
case ARM::VSHTOS:
|
|
case ARM::VSLTOH:
|
|
case ARM::VSLTOS:
|
|
case ARM::VTOSHH:
|
|
case ARM::VTOSHS:
|
|
case ARM::VTOSLH:
|
|
case ARM::VTOSLS:
|
|
case ARM::VTOUHH:
|
|
case ARM::VTOUHS:
|
|
case ARM::VTOULH:
|
|
case ARM::VTOULS:
|
|
case ARM::VUHTOH:
|
|
case ARM::VUHTOS:
|
|
case ARM::VULTOH:
|
|
case ARM::VULTOS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: fbits
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
// op: dst
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::VSHTOD:
|
|
case ARM::VSLTOD:
|
|
case ARM::VTOSHD:
|
|
case ARM::VTOSLD:
|
|
case ARM::VTOUHD:
|
|
case ARM::VTOULD:
|
|
case ARM::VUHTOD:
|
|
case ARM::VULTOD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: fbits
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
// op: dst
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::ADCrr:
|
|
case ARM::ADDrr:
|
|
case ARM::ANDrr:
|
|
case ARM::BICrr:
|
|
case ARM::EORrr:
|
|
case ARM::ORRrr:
|
|
case ARM::RSBrr:
|
|
case ARM::RSCrr:
|
|
case ARM::SBCrr:
|
|
case ARM::SUBrr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::ADCri:
|
|
case ARM::ADDri:
|
|
case ARM::ANDri:
|
|
case ARM::BICri:
|
|
case ARM::EORri:
|
|
case ARM::ORRri:
|
|
case ARM::RSBri:
|
|
case ARM::RSCri:
|
|
case ARM::SBCri:
|
|
case ARM::SUBri: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getModImmOpValue(MI, 2, Fixups, STI);
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::MVNsi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: shift
|
|
op = getSORegImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MOVsi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: src
|
|
op = getSORegImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MUL: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::VFMAD:
|
|
case ARM::VFMSD:
|
|
case ARM::VFNMAD:
|
|
case ARM::VFNMSD:
|
|
case ARM::VMLAD:
|
|
case ARM::VMLSD:
|
|
case ARM::VNMLAD:
|
|
case ARM::VNMLSD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Dd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 18;
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Dn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value |= (op & UINT64_C(16)) << 3;
|
|
// op: Dm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 1;
|
|
Value |= op & UINT64_C(15);
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::SXTAB:
|
|
case ARM::SXTAB16:
|
|
case ARM::SXTAH:
|
|
case ARM::UXTAB:
|
|
case ARM::UXTAB16:
|
|
case ARM::UXTAH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: rot
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(3)) << 10;
|
|
break;
|
|
}
|
|
case ARM::PKHBT:
|
|
case ARM::PKHTB: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: sh
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 7;
|
|
break;
|
|
}
|
|
case ARM::SBFX:
|
|
case ARM::UBFX: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: lsb
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 7;
|
|
// op: width
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 16;
|
|
break;
|
|
}
|
|
case ARM::BFI: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: imm
|
|
op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(992)) << 11;
|
|
Value |= (op & UINT64_C(31)) << 7;
|
|
break;
|
|
}
|
|
case ARM::SSAT:
|
|
case ARM::USAT: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: sat_imm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 16;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: sh
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(31)) << 7;
|
|
Value |= (op & UINT64_C(32)) << 1;
|
|
break;
|
|
}
|
|
case ARM::MLS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::SMMLA:
|
|
case ARM::SMMLAR:
|
|
case ARM::SMMLS:
|
|
case ARM::SMMLSR:
|
|
case ARM::USADA8: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::UMAAL: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: RdLo
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: RdHi
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::CMNzrsr:
|
|
case ARM::CMPrsr:
|
|
case ARM::TEQrsr:
|
|
case ARM::TSTrsr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: shift
|
|
op = getSORegRegOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(3840);
|
|
Value |= op & UINT64_C(96);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::SMLAD:
|
|
case ARM::SMLADX:
|
|
case ARM::SMLSD:
|
|
case ARM::SMLSDX: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::SMLABB:
|
|
case ARM::SMLABT:
|
|
case ARM::SMLATB:
|
|
case ARM::SMLATT:
|
|
case ARM::SMLAWB:
|
|
case ARM::SMLAWT: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::SMLALBB:
|
|
case ARM::SMLALBT:
|
|
case ARM::SMLALD:
|
|
case ARM::SMLALDX:
|
|
case ARM::SMLALTB:
|
|
case ARM::SMLALTT:
|
|
case ARM::SMLSLD:
|
|
case ARM::SMLSLDX: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: RdLo
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: RdHi
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::LDRB_PRE_IMM:
|
|
case ARM::LDR_PRE_IMM: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::LDRBrs:
|
|
case ARM::LDRrs:
|
|
case ARM::STRBrs:
|
|
case ARM::STRrs: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: shift
|
|
op = getLdStSORegOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::STRB_PRE_IMM:
|
|
case ARM::STR_PRE_IMM: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrModeImm12OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4095);
|
|
break;
|
|
}
|
|
case ARM::VFMAH:
|
|
case ARM::VFMAS:
|
|
case ARM::VFMSH:
|
|
case ARM::VFMSS:
|
|
case ARM::VFNMAH:
|
|
case ARM::VFNMAS:
|
|
case ARM::VFNMSH:
|
|
case ARM::VFNMSS:
|
|
case ARM::VMLAH:
|
|
case ARM::VMLAS:
|
|
case ARM::VMLSH:
|
|
case ARM::VMLSS:
|
|
case ARM::VNMLAH:
|
|
case ARM::VNMLAS:
|
|
case ARM::VNMLSH:
|
|
case ARM::VNMLSS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Sd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 22;
|
|
Value |= (op & UINT64_C(30)) << 11;
|
|
// op: Sn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(30)) << 15;
|
|
Value |= (op & UINT64_C(1)) << 7;
|
|
// op: Sm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::LDRH:
|
|
case ARM::LDRSB:
|
|
case ARM::LDRSH:
|
|
case ARM::STRH: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: addr
|
|
op = getAddrMode3OpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(8192)) << 9;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::LDCL_OFFSET:
|
|
case ARM::LDCL_PRE:
|
|
case ARM::LDC_OFFSET:
|
|
case ARM::LDC_PRE:
|
|
case ARM::STCL_OFFSET:
|
|
case ARM::STCL_PRE:
|
|
case ARM::STC_OFFSET:
|
|
case ARM::STC_PRE: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: addr
|
|
op = getAddrMode5OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= op & UINT64_C(255);
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::LDRHTi:
|
|
case ARM::LDRSBTi:
|
|
case ARM::LDRSHTi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::STRHTi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::VMOVSRR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: dst1
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
// op: src1
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: src2
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::LDCL_POST:
|
|
case ARM::LDC_POST:
|
|
case ARM::STCL_POST:
|
|
case ARM::STC_POST: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: offset
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= op & UINT64_C(255);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::LDCL_OPTION:
|
|
case ARM::LDC_OPTION:
|
|
case ARM::STCL_OPTION:
|
|
case ARM::STC_OPTION: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: option
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::ADCrsi:
|
|
case ARM::ADDrsi:
|
|
case ARM::ANDrsi:
|
|
case ARM::BICrsi:
|
|
case ARM::EORrsi:
|
|
case ARM::ORRrsi:
|
|
case ARM::RSBrsi:
|
|
case ARM::RSCrsi:
|
|
case ARM::SBCrsi:
|
|
case ARM::SUBrsi: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 6, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: shift
|
|
op = getSORegImmOpValue(MI, 2, Fixups, STI);
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MVNsr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 6, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: shift
|
|
op = getSORegRegOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(3840);
|
|
Value |= op & UINT64_C(96);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MOVsr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 6, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: src
|
|
op = getSORegRegOpValue(MI, 1, Fixups, STI);
|
|
Value |= op & UINT64_C(3840);
|
|
Value |= op & UINT64_C(96);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MLA: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 6, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: Ra
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::SMULL:
|
|
case ARM::UMULL: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 6, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: RdLo
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: RdHi
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::VMOVRRS: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: src1
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 5;
|
|
Value |= (op & UINT64_C(30)) >> 1;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
Value = VFPThumb2PostEncoder(MI, Value, STI);
|
|
break;
|
|
}
|
|
case ARM::MRRC: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 4;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::LDRH_PRE:
|
|
case ARM::LDRSB_PRE:
|
|
case ARM::LDRSH_PRE: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrMode3OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(8192)) << 9;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::LDRB_PRE_REG:
|
|
case ARM::LDR_PRE_REG: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getLdStSORegOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::LDRBT_POST_REG:
|
|
case ARM::LDRB_POST_REG:
|
|
case ARM::LDRT_POST_REG:
|
|
case ARM::LDR_POST_REG: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::LDRBT_POST_IMM:
|
|
case ARM::LDRB_POST_IMM:
|
|
case ARM::LDRT_POST_IMM:
|
|
case ARM::LDR_POST_IMM: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= op & UINT64_C(4095);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::LDRH_POST:
|
|
case ARM::LDRSB_POST:
|
|
case ARM::LDRSH_POST: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(512)) << 13;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::STRH_PRE: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrMode3OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(8192)) << 9;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::STRB_PRE_REG:
|
|
case ARM::STR_PRE_REG: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getLdStSORegOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::STRBT_POST_REG:
|
|
case ARM::STRB_POST_REG:
|
|
case ARM::STRT_POST_REG:
|
|
case ARM::STR_POST_REG: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::STRBT_POST_IMM:
|
|
case ARM::STRB_POST_IMM:
|
|
case ARM::STRT_POST_IMM:
|
|
case ARM::STR_POST_IMM: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= op & UINT64_C(4095);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::STRH_POST: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(512)) << 13;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::MCRR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rt2
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 4;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::LDRD:
|
|
case ARM::STRD: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: addr
|
|
op = getAddrMode3OpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(8192)) << 9;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
break;
|
|
}
|
|
case ARM::LDRHTr:
|
|
case ARM::LDRSBTr:
|
|
case ARM::LDRSHTr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getPostIdxRegOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 19;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::STRHTr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rm
|
|
op = getPostIdxRegOpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(16)) << 19;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::ADCrsr:
|
|
case ARM::ADDrsr:
|
|
case ARM::ANDrsr:
|
|
case ARM::BICrsr:
|
|
case ARM::EORrsr:
|
|
case ARM::ORRrsr:
|
|
case ARM::RSBrsr:
|
|
case ARM::RSCrsr:
|
|
case ARM::SBCrsr:
|
|
case ARM::SUBrsr: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 7, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: shift
|
|
op = getSORegRegOpValue(MI, 2, Fixups, STI);
|
|
Value |= op & UINT64_C(3840);
|
|
Value |= op & UINT64_C(96);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::LDRD_PRE: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrMode3OpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(8192)) << 9;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::MRC: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 21;
|
|
// op: opc2
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: CRn
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::LDRD_POST: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(512)) << 13;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::STRD_PRE: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: addr
|
|
op = getAddrMode3OpValue(MI, 3, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(8192)) << 9;
|
|
Value |= (op & UINT64_C(7680)) << 7;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::STRD_POST: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: offset
|
|
op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(256)) << 15;
|
|
Value |= (op & UINT64_C(512)) << 13;
|
|
Value |= (op & UINT64_C(240)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
// op: addr
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::MCR: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: Rt
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 21;
|
|
// op: opc2
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: CRn
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
break;
|
|
}
|
|
case ARM::CDP: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: opc1
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 20;
|
|
// op: CRn
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: CRd
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: cop
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: opc2
|
|
op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
|
|
Value |= (op & UINT64_C(7)) << 5;
|
|
// op: CRm
|
|
op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::SMLAL:
|
|
case ARM::UMLAL: {
|
|
// op: p
|
|
op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 28;
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 8, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: RdLo
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 12;
|
|
// op: RdHi
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::tPUSH: {
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(16384)) >> 6;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tPOP: {
|
|
// op: regs
|
|
op = getRegisterListOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(32768)) >> 7;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2MOVr:
|
|
case ARM::t2MVNr:
|
|
case ARM::t2RRX: {
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2MOVi:
|
|
case ARM::t2MVNi: {
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 4, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: imm
|
|
op = getT2SOImmOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(2048)) << 15;
|
|
Value |= (op & UINT64_C(1792)) << 4;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2ASRri:
|
|
case ARM::t2LSLri:
|
|
case ARM::t2LSRri:
|
|
case ARM::t2RORri: {
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
// op: imm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= (op & UINT64_C(28)) << 10;
|
|
Value |= (op & UINT64_C(3)) << 6;
|
|
break;
|
|
}
|
|
case ARM::t2ADCrr:
|
|
case ARM::t2ADDrr:
|
|
case ARM::t2ANDrr:
|
|
case ARM::t2ASRrr:
|
|
case ARM::t2BICrr:
|
|
case ARM::t2EORrr:
|
|
case ARM::t2LSLrr:
|
|
case ARM::t2LSRrr:
|
|
case ARM::t2ORNrr:
|
|
case ARM::t2ORRrr:
|
|
case ARM::t2RORrr:
|
|
case ARM::t2RSBrr:
|
|
case ARM::t2SBCrr:
|
|
case ARM::t2SUBrr: {
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: Rm
|
|
op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2ADCri:
|
|
case ARM::t2ADDri:
|
|
case ARM::t2ANDri:
|
|
case ARM::t2BICri:
|
|
case ARM::t2EORri:
|
|
case ARM::t2ORNri:
|
|
case ARM::t2ORRri:
|
|
case ARM::t2RSBri:
|
|
case ARM::t2SBCri:
|
|
case ARM::t2SUBri: {
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: imm
|
|
op = getT2SOImmOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(2048)) << 15;
|
|
Value |= (op & UINT64_C(1792)) << 4;
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::t2MVNs: {
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 5, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: ShiftedRm
|
|
op = getT2SORegOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(3584)) << 3;
|
|
Value |= (op & UINT64_C(480)) >> 1;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::t2ADCrs:
|
|
case ARM::t2ADDrs:
|
|
case ARM::t2ANDrs:
|
|
case ARM::t2BICrs:
|
|
case ARM::t2EORrs:
|
|
case ARM::t2ORNrs:
|
|
case ARM::t2ORRrs:
|
|
case ARM::t2RSBrs:
|
|
case ARM::t2SBCrs:
|
|
case ARM::t2SUBrs: {
|
|
// op: s
|
|
op = getCCOutOpValue(MI, 6, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 20;
|
|
// op: Rd
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 8;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
|
|
Value |= (op & UINT64_C(15)) << 16;
|
|
// op: ShiftedRm
|
|
op = getT2SORegOpValue(MI, 2, Fixups, STI);
|
|
Value |= (op & UINT64_C(3584)) << 3;
|
|
Value |= (op & UINT64_C(480)) >> 1;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::PLDWrs:
|
|
case ARM::PLDrs:
|
|
case ARM::PLIrs: {
|
|
// op: shift
|
|
op = getLdStSORegOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(4096)) << 11;
|
|
Value |= (op & UINT64_C(122880)) << 3;
|
|
Value |= op & UINT64_C(4064);
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::BLXi: {
|
|
// op: target
|
|
op = getARMBLXTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(1)) << 24;
|
|
Value |= (op & UINT64_C(33554430)) >> 1;
|
|
break;
|
|
}
|
|
case ARM::tB: {
|
|
// op: target
|
|
op = getThumbBRTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= op & UINT64_C(2047);
|
|
break;
|
|
}
|
|
case ARM::tCBNZ:
|
|
case ARM::tCBZ: {
|
|
// op: target
|
|
op = getThumbCBTargetOpValue(MI, 1, Fixups, STI);
|
|
Value |= (op & UINT64_C(32)) << 4;
|
|
Value |= (op & UINT64_C(31)) << 3;
|
|
// op: Rn
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(7);
|
|
break;
|
|
}
|
|
case ARM::t2B: {
|
|
// op: target
|
|
op = getUnconditionalBranchTargetOpValue(MI, 0, Fixups, STI);
|
|
Value |= (op & UINT64_C(8388608)) << 3;
|
|
Value |= (op & UINT64_C(2095104)) << 5;
|
|
Value |= (op & UINT64_C(4194304)) >> 9;
|
|
Value |= (op & UINT64_C(2097152)) >> 10;
|
|
Value |= op & UINT64_C(2047);
|
|
break;
|
|
}
|
|
case ARM::BKPT:
|
|
case ARM::HLT: {
|
|
// op: val
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= (op & UINT64_C(65520)) << 4;
|
|
Value |= op & UINT64_C(15);
|
|
break;
|
|
}
|
|
case ARM::tBKPT: {
|
|
// op: val
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(255);
|
|
break;
|
|
}
|
|
case ARM::tHLT: {
|
|
// op: val
|
|
op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
|
|
Value |= op & UINT64_C(63);
|
|
break;
|
|
}
|
|
default:
|
|
std::string msg;
|
|
raw_string_ostream Msg(msg);
|
|
Msg << "Not supported instr: " << MI;
|
|
report_fatal_error(Msg.str());
|
|
}
|
|
return Value;
|
|
}
|
|
|