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362 lines
14 KiB
362 lines
14 KiB
//===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonFixupKinds.h"
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#include "HexagonMCTargetDesc.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAsmLayout.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm_ks;
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using namespace Hexagon;
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#define DEBUG_TYPE "hexagon-asm-backend"
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namespace {
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class HexagonAsmBackend : public MCAsmBackend {
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uint8_t OSABI;
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StringRef CPU;
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mutable uint64_t relaxedCnt;
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std::unique_ptr <MCInstrInfo> MCII;
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std::unique_ptr <MCInst *> RelaxTarget;
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MCInst * Extender;
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public:
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HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) :
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OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *),
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Extender(nullptr) {}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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return createHexagonELFObjectWriter(OS, OSABI, CPU);
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}
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void setExtender(MCContext &Context) const {
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if (Extender == nullptr)
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const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst;
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}
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MCInst *takeExtender() const {
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assert(Extender != nullptr);
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MCInst * Result = Extender;
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const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
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return Result;
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}
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unsigned getNumFixupKinds() const override {
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return Hexagon::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// HexagonFixupKinds.h.
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//
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// namei offset bits flags
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{"fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_LO16", 0, 32, 0},
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{"fixup_Hexagon_HI16", 0, 32, 0},
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{"fixup_Hexagon_32", 0, 32, 0},
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{"fixup_Hexagon_16", 0, 32, 0},
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{"fixup_Hexagon_8", 0, 32, 0},
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{"fixup_Hexagon_GPREL16_0", 0, 32, 0},
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{"fixup_Hexagon_GPREL16_1", 0, 32, 0},
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{"fixup_Hexagon_GPREL16_2", 0, 32, 0},
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{"fixup_Hexagon_GPREL16_3", 0, 32, 0},
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{"fixup_Hexagon_HL16", 0, 32, 0},
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{"fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_16_X", 0, 32, 0},
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{"fixup_Hexagon_12_X", 0, 32, 0},
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{"fixup_Hexagon_11_X", 0, 32, 0},
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{"fixup_Hexagon_10_X", 0, 32, 0},
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{"fixup_Hexagon_9_X", 0, 32, 0},
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{"fixup_Hexagon_8_X", 0, 32, 0},
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{"fixup_Hexagon_7_X", 0, 32, 0},
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{"fixup_Hexagon_6_X", 0, 32, 0},
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{"fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_COPY", 0, 32, 0},
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{"fixup_Hexagon_GLOB_DAT", 0, 32, 0},
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{"fixup_Hexagon_JMP_SLOT", 0, 32, 0},
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{"fixup_Hexagon_RELATIVE", 0, 32, 0},
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{"fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_GOTREL_LO16", 0, 32, 0},
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{"fixup_Hexagon_GOTREL_HI16", 0, 32, 0},
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{"fixup_Hexagon_GOTREL_32", 0, 32, 0},
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{"fixup_Hexagon_GOT_LO16", 0, 32, 0},
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{"fixup_Hexagon_GOT_HI16", 0, 32, 0},
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{"fixup_Hexagon_GOT_32", 0, 32, 0},
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{"fixup_Hexagon_GOT_16", 0, 32, 0},
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{"fixup_Hexagon_DTPMOD_32", 0, 32, 0},
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{"fixup_Hexagon_DTPREL_LO16", 0, 32, 0},
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{"fixup_Hexagon_DTPREL_HI16", 0, 32, 0},
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{"fixup_Hexagon_DTPREL_32", 0, 32, 0},
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{"fixup_Hexagon_DTPREL_16", 0, 32, 0},
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{"fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0},
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{"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0},
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{"fixup_Hexagon_GD_GOT_32", 0, 32, 0},
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{"fixup_Hexagon_GD_GOT_16", 0, 32, 0},
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{"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0},
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{"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0},
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{"fixup_Hexagon_LD_GOT_32", 0, 32, 0},
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{"fixup_Hexagon_LD_GOT_16", 0, 32, 0},
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{"fixup_Hexagon_IE_LO16", 0, 32, 0},
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{"fixup_Hexagon_IE_HI16", 0, 32, 0},
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{"fixup_Hexagon_IE_32", 0, 32, 0},
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{"fixup_Hexagon_IE_16", 0, 32, 0},
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{"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0},
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{"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0},
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{"fixup_Hexagon_IE_GOT_32", 0, 32, 0},
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{"fixup_Hexagon_IE_GOT_16", 0, 32, 0},
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{"fixup_Hexagon_TPREL_LO16", 0, 32, 0},
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{"fixup_Hexagon_TPREL_HI16", 0, 32, 0},
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{"fixup_Hexagon_TPREL_32", 0, 32, 0},
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{"fixup_Hexagon_TPREL_16", 0, 32, 0},
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{"fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_GOTREL_16_X", 0, 32, 0},
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{"fixup_Hexagon_GOTREL_11_X", 0, 32, 0},
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{"fixup_Hexagon_GOT_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_GOT_16_X", 0, 32, 0},
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{"fixup_Hexagon_GOT_11_X", 0, 32, 0},
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{"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_DTPREL_16_X", 0, 32, 0},
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{"fixup_Hexagon_DTPREL_11_X", 0, 32, 0},
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{"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0},
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{"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0},
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{"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0},
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{"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0},
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{"fixup_Hexagon_IE_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_IE_16_X", 0, 32, 0},
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{"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0},
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{"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0},
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{"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0},
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{"fixup_Hexagon_TPREL_16_X", 0, 32, 0},
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{"fixup_Hexagon_TPREL_11_X", 0, 32, 0}};
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if (Kind < FirstTargetFixupKind) {
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return MCAsmBackend::getFixupKindInfo(Kind);
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}
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
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unsigned /*DataSize*/, uint64_t /*Value*/,
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bool /*IsPCRel*/, unsigned int &KsError) const override {
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return;
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}
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bool isInstRelaxable(MCInst const &HMI) const {
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const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
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bool Relaxable = false;
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// Branches and loop-setup insns are handled as necessary by relaxation.
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if (llvm_ks::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
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(llvm_ks::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
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MCID.isBranch()) ||
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(llvm_ks::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
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HMI.getOpcode() != Hexagon::C4_addipc))
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if (HexagonMCInstrInfo::isExtendable(*MCII, HMI))
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Relaxable = true;
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return Relaxable;
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}
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/// MayNeedRelaxation - Check whether the given instruction may need
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/// relaxation.
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///
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/// \param Inst - The instruction to test.
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bool mayNeedRelaxation(MCInst const &Inst) const override {
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assert(HexagonMCInstrInfo::isBundle(Inst));
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bool PreviousIsExtender = false;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
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auto const &Inst = *I.getInst();
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if (!PreviousIsExtender) {
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if (isInstRelaxable(Inst))
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return true;
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}
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PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst);
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}
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return false;
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}
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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/// fixup requires the associated instruction to be relaxed.
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bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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MCInst const &MCB = DF->getInst();
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assert(HexagonMCInstrInfo::isBundle(MCB));
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*RelaxTarget = nullptr;
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MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
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MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
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// If we cannot resolve the fixup value, it requires relaxation.
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if (!Resolved) {
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switch ((unsigned)Fixup.getKind()) {
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case fixup_Hexagon_B22_PCREL:
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// GetFixupCount assumes B22 won't relax
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// Fallthrough
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default:
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return false;
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break;
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case fixup_Hexagon_B13_PCREL:
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case fixup_Hexagon_B15_PCREL:
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case fixup_Hexagon_B9_PCREL:
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case fixup_Hexagon_B7_PCREL: {
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if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
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++relaxedCnt;
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*RelaxTarget = &MCI;
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setExtender(Layout.getAssembler().getContext());
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return true;
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} else {
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return false;
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}
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break;
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}
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}
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}
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bool Relaxable = isInstRelaxable(MCI);
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if (Relaxable == false)
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return false;
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MCFixupKind Kind = Fixup.getKind();
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int64_t sValue = Value;
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int64_t maxValue;
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switch ((unsigned)Kind) {
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case fixup_Hexagon_B7_PCREL:
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maxValue = 1 << 8;
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break;
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case fixup_Hexagon_B9_PCREL:
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maxValue = 1 << 10;
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break;
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case fixup_Hexagon_B15_PCREL:
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maxValue = 1 << 16;
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break;
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case fixup_Hexagon_B22_PCREL:
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maxValue = 1 << 23;
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break;
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default:
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maxValue = INT64_MAX;
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break;
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}
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bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
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if (isFarAway) {
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if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
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++relaxedCnt;
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*RelaxTarget = &MCI;
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setExtender(Layout.getAssembler().getContext());
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return true;
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}
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}
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return false;
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}
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/// Simple predicate for targets where !Resolved implies requiring relaxation
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout, unsigned &KsError) const override {
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llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
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}
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void relaxInstruction(MCInst const & Inst,
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MCInst & Res) const override {
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assert(HexagonMCInstrInfo::isBundle(Inst) &&
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"Hexagon relaxInstruction only works on bundles");
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Res = HexagonMCInstrInfo::createBundle();
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// Copy the results into the bundle.
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bool Update = false;
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for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
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MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
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// if immediate extender needed, add it in
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if (*RelaxTarget == &CrntHMI) {
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Update = true;
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assert((HexagonMCInstrInfo::bundleSize(Res) < HEXAGON_PACKET_SIZE) &&
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"No room to insert extender for relaxation");
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MCInst *HMIx = takeExtender();
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*HMIx = HexagonMCInstrInfo::deriveExtender(
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*MCII, CrntHMI,
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HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI));
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Res.addOperand(MCOperand::createInst(HMIx));
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*RelaxTarget = nullptr;
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}
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// now copy over the original instruction(the one we may have extended)
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Res.addOperand(MCOperand::createInst(I.getInst()));
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}
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(void)Update;
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assert(Update && "Didn't find relaxation target");
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}
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bool writeNopData(uint64_t Count,
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MCObjectWriter * OW) const override {
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static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
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ParseIn = 0x00004000, // In packet parse-bits.
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ParseEnd = 0x0000c000; // End of packet parse-bits.
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while(Count % HEXAGON_INSTR_SIZE) {
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DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" <<
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Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n");
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--Count;
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OW->write8(0);
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}
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while(Count) {
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Count -= HEXAGON_INSTR_SIZE;
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// Close the packet whenever a multiple of the maximum packet size remains
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uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))?
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ParseIn: ParseEnd;
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OW->write32(Nopcode | ParseBits);
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}
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return true;
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}
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};
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} // end anonymous namespace
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namespace llvm_ks {
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MCAsmBackend *createHexagonAsmBackend(Target const &T,
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MCRegisterInfo const & /*MRI*/,
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const Triple &TT, StringRef CPU) {
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
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return new HexagonAsmBackend(T, OSABI, CPU);
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}
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}
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