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286 lines
8.0 KiB
286 lines
8.0 KiB
//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the Hexagon target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
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#include "HexagonMCTargetDesc.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <stdint.h>
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namespace llvm_ks {
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/// HexagonII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace HexagonII {
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// *** The code below must match HexagonInstrFormat*.td *** //
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// Insn types.
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// *** Must match HexagonInstrFormat*.td ***
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enum Type {
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TypePSEUDO = 0,
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TypeALU32 = 1,
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TypeCR = 2,
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TypeJR = 3,
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TypeJ = 4,
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TypeLD = 5,
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TypeST = 6,
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TypeSYSTEM = 7,
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TypeXTYPE = 8,
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TypeMEMOP = 9,
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TypeNV = 10,
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TypeDUPLEX = 11,
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TypeCOMPOUND = 12,
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TypeCVI_FIRST = 13,
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TypeCVI_VA = TypeCVI_FIRST,
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TypeCVI_VA_DV = 14,
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TypeCVI_VX = 15,
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TypeCVI_VX_DV = 16,
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TypeCVI_VP = 17,
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TypeCVI_VP_VS = 18,
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TypeCVI_VS = 19,
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TypeCVI_VINLANESAT= 20,
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TypeCVI_VM_LD = 21,
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TypeCVI_VM_TMP_LD = 22,
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TypeCVI_VM_CUR_LD = 23,
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TypeCVI_VM_VP_LDU = 24,
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TypeCVI_VM_ST = 25,
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TypeCVI_VM_NEW_ST = 26,
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TypeCVI_VM_STU = 27,
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TypeCVI_HIST = 28,
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TypeCVI_LAST = TypeCVI_HIST,
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TypePREFIX = 30, // Such as extenders.
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TypeENDLOOP = 31 // Such as end of a HW loop.
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};
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enum SubTarget {
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HasV2SubT = 0xf,
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HasV2SubTOnly = 0x1,
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NoV2SubT = 0x0,
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HasV3SubT = 0xe,
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HasV3SubTOnly = 0x2,
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NoV3SubT = 0x1,
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HasV4SubT = 0xc,
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NoV4SubT = 0x3,
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HasV5SubT = 0x8,
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NoV5SubT = 0x7
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};
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enum AddrMode {
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NoAddrMode = 0, // No addressing mode
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Absolute = 1, // Absolute addressing mode
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AbsoluteSet = 2, // Absolute set addressing mode
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BaseImmOffset = 3, // Indirect with offset
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BaseLongOffset = 4, // Indirect with long offset
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BaseRegOffset = 5, // Indirect with register offset
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PostInc = 6 // Post increment addressing mode
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};
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// MemAccessSize is represented as 1+log2(N) where N is size in bits.
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enum class MemAccessSize {
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NoMemAccess = 0, // Not a memory acces instruction.
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ByteAccess = 1, // Byte access instruction (memb).
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HalfWordAccess = 2, // Half word access instruction (memh).
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WordAccess = 3, // Word access instruction (memw).
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DoubleWordAccess = 4, // Double word access instruction (memd)
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// 5, // We do not have a 16 byte vector access.
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Vector64Access = 7, // 64 Byte vector access instruction (vmem).
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Vector128Access = 8 // 128 Byte vector access instruction (vmem).
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};
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// MCInstrDesc TSFlags
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// *** Must match HexagonInstrFormat*.td ***
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enum {
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// This 5-bit field describes the insn type.
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TypePos = 0,
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TypeMask = 0x1f,
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// Solo instructions.
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SoloPos = 5,
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SoloMask = 0x1,
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// Packed only with A or X-type instructions.
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SoloAXPos = 6,
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SoloAXMask = 0x1,
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// Only A-type instruction in first slot or nothing.
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SoloAin1Pos = 7,
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SoloAin1Mask = 0x1,
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// Predicated instructions.
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PredicatedPos = 8,
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PredicatedMask = 0x1,
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PredicatedFalsePos = 9,
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PredicatedFalseMask = 0x1,
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PredicatedNewPos = 10,
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PredicatedNewMask = 0x1,
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PredicateLatePos = 11,
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PredicateLateMask = 0x1,
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// New-Value consumer instructions.
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NewValuePos = 12,
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NewValueMask = 0x1,
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// New-Value producer instructions.
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hasNewValuePos = 13,
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hasNewValueMask = 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos = 14,
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NewValueOpMask = 0x7,
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// Stores that can become new-value stores.
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mayNVStorePos = 17,
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mayNVStoreMask = 0x1,
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// New-value store instructions.
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NVStorePos = 18,
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NVStoreMask = 0x1,
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// Loads that can become current-value loads.
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mayCVLoadPos = 19,
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mayCVLoadMask = 0x1,
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// Current-value load instructions.
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CVLoadPos = 20,
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CVLoadMask = 0x1,
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// Extendable insns.
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ExtendablePos = 21,
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ExtendableMask = 0x1,
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// Insns must be extended.
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ExtendedPos = 22,
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ExtendedMask = 0x1,
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// Which operand may be extended.
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ExtendableOpPos = 23,
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ExtendableOpMask = 0x7,
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// Signed or unsigned range.
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ExtentSignedPos = 26,
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ExtentSignedMask = 0x1,
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// Number of bits of range before extending operand.
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ExtentBitsPos = 27,
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ExtentBitsMask = 0x1f,
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// Alignment power-of-two before extending operand.
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ExtentAlignPos = 32,
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ExtentAlignMask = 0x3,
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// Valid subtargets
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validSubTargetPos = 34,
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validSubTargetMask = 0xf,
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// Addressing mode for load/store instructions.
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AddrModePos = 40,
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AddrModeMask = 0x7,
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// Access size for load/store instructions.
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MemAccessSizePos = 43,
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MemAccesSizeMask = 0xf,
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// Branch predicted taken.
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TakenPos = 47,
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TakenMask = 0x1,
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// Floating-point instructions.
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FPPos = 48,
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FPMask = 0x1,
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// New-Value producer-2 instructions.
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hasNewValuePos2 = 50,
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hasNewValueMask2 = 0x1,
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// Which operand consumes or produces a new value.
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NewValueOpPos2 = 51,
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NewValueOpMask2 = 0x7,
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// Accumulator instructions.
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AccumulatorPos = 54,
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AccumulatorMask = 0x1,
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// Complex XU, prevent xu competition by prefering slot3
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PrefersSlot3Pos = 55,
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PrefersSlot3Mask = 0x1,
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};
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// *** The code above must match HexagonInstrFormat*.td *** //
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// Hexagon specific MO operand flag mask.
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enum HexagonMOTargetFlagVal {
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//===------------------------------------------------------------------===//
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// Hexagon Specific MachineOperand flags.
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MO_NO_FLAG,
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HMOTF_ConstExtended = 1,
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/// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
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/// Used for computing a global address for PIC compilations
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MO_PCREL,
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/// MO_GOT - Indicates a GOT-relative relocation
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MO_GOT,
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// Low or high part of a symbol.
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MO_LO16, MO_HI16,
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// Offset from the base of the SDA.
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MO_GPREL
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};
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// Hexagon Sub-instruction classes.
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enum SubInstructionGroup {
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HSIG_None = 0,
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HSIG_L1,
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HSIG_L2,
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HSIG_S1,
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HSIG_S2,
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HSIG_A,
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HSIG_Compound
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};
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// Hexagon Compound classes.
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enum CompoundGroup {
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HCG_None = 0,
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HCG_A,
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HCG_B,
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HCG_C
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};
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enum InstParseBits {
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INST_PARSE_MASK = 0x0000c000,
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INST_PARSE_PACKET_END = 0x0000c000,
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INST_PARSE_LOOP_END = 0x00008000,
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INST_PARSE_NOT_END = 0x00004000,
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INST_PARSE_DUPLEX = 0x00000000,
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INST_PARSE_EXTENDER = 0x00000000
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};
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enum InstIClassBits : unsigned {
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INST_ICLASS_MASK = 0xf0000000,
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INST_ICLASS_EXTENDER = 0x00000000,
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INST_ICLASS_J_1 = 0x10000000,
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INST_ICLASS_J_2 = 0x20000000,
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INST_ICLASS_LD_ST_1 = 0x30000000,
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INST_ICLASS_LD_ST_2 = 0x40000000,
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INST_ICLASS_J_3 = 0x50000000,
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INST_ICLASS_CR = 0x60000000,
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INST_ICLASS_ALU32_1 = 0x70000000,
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INST_ICLASS_XTYPE_1 = 0x80000000,
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INST_ICLASS_LD = 0x90000000,
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INST_ICLASS_ST = 0xa0000000,
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INST_ICLASS_ALU32_2 = 0xb0000000,
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INST_ICLASS_XTYPE_2 = 0xc0000000,
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INST_ICLASS_XTYPE_3 = 0xd0000000,
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INST_ICLASS_XTYPE_4 = 0xe0000000,
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INST_ICLASS_ALU32_3 = 0xf0000000
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};
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} // End namespace HexagonII.
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} // End namespace llvm_ks.
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#endif
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