You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
1336 lines
115 KiB
1336 lines
115 KiB
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|
|
|* *|
|
|
|* Target Instruction Enum Values *|
|
|
|* *|
|
|
|* Automatically generated file, do not edit! *|
|
|
|* *|
|
|
\*===----------------------------------------------------------------------===*/
|
|
|
|
|
|
#ifdef GET_INSTRINFO_ENUM
|
|
#undef GET_INSTRINFO_ENUM
|
|
namespace llvm_ks {
|
|
|
|
namespace SP {
|
|
enum {
|
|
PHI = 0,
|
|
INLINEASM = 1,
|
|
CFI_INSTRUCTION = 2,
|
|
EH_LABEL = 3,
|
|
GC_LABEL = 4,
|
|
KILL = 5,
|
|
EXTRACT_SUBREG = 6,
|
|
INSERT_SUBREG = 7,
|
|
IMPLICIT_DEF = 8,
|
|
SUBREG_TO_REG = 9,
|
|
COPY_TO_REGCLASS = 10,
|
|
DBG_VALUE = 11,
|
|
REG_SEQUENCE = 12,
|
|
COPY = 13,
|
|
BUNDLE = 14,
|
|
LIFETIME_START = 15,
|
|
LIFETIME_END = 16,
|
|
STACKMAP = 17,
|
|
PATCHPOINT = 18,
|
|
LOAD_STACK_GUARD = 19,
|
|
STATEPOINT = 20,
|
|
LOCAL_ESCAPE = 21,
|
|
FAULTING_LOAD_OP = 22,
|
|
G_ADD = 23,
|
|
ADDCCri = 24,
|
|
ADDCCrr = 25,
|
|
ADDCri = 26,
|
|
ADDCrr = 27,
|
|
ADDEri = 28,
|
|
ADDErr = 29,
|
|
ADDXC = 30,
|
|
ADDXCCC = 31,
|
|
ADDXri = 32,
|
|
ADDXrr = 33,
|
|
ADDri = 34,
|
|
ADDrr = 35,
|
|
ADJCALLSTACKDOWN = 36,
|
|
ADJCALLSTACKUP = 37,
|
|
ALIGNADDR = 38,
|
|
ALIGNADDRL = 39,
|
|
ANDCCri = 40,
|
|
ANDCCrr = 41,
|
|
ANDNCCri = 42,
|
|
ANDNCCrr = 43,
|
|
ANDNri = 44,
|
|
ANDNrr = 45,
|
|
ANDXNrr = 46,
|
|
ANDXri = 47,
|
|
ANDXrr = 48,
|
|
ANDri = 49,
|
|
ANDrr = 50,
|
|
ARRAY16 = 51,
|
|
ARRAY32 = 52,
|
|
ARRAY8 = 53,
|
|
ATOMIC_LOAD_ADD_32 = 54,
|
|
ATOMIC_LOAD_ADD_64 = 55,
|
|
ATOMIC_LOAD_AND_32 = 56,
|
|
ATOMIC_LOAD_AND_64 = 57,
|
|
ATOMIC_LOAD_MAX_32 = 58,
|
|
ATOMIC_LOAD_MAX_64 = 59,
|
|
ATOMIC_LOAD_MIN_32 = 60,
|
|
ATOMIC_LOAD_MIN_64 = 61,
|
|
ATOMIC_LOAD_NAND_32 = 62,
|
|
ATOMIC_LOAD_NAND_64 = 63,
|
|
ATOMIC_LOAD_OR_32 = 64,
|
|
ATOMIC_LOAD_OR_64 = 65,
|
|
ATOMIC_LOAD_SUB_32 = 66,
|
|
ATOMIC_LOAD_SUB_64 = 67,
|
|
ATOMIC_LOAD_UMAX_32 = 68,
|
|
ATOMIC_LOAD_UMAX_64 = 69,
|
|
ATOMIC_LOAD_UMIN_32 = 70,
|
|
ATOMIC_LOAD_UMIN_64 = 71,
|
|
ATOMIC_LOAD_XOR_32 = 72,
|
|
ATOMIC_LOAD_XOR_64 = 73,
|
|
ATOMIC_SWAP_64 = 74,
|
|
BA = 75,
|
|
BCOND = 76,
|
|
BCONDA = 77,
|
|
BINDri = 78,
|
|
BINDrr = 79,
|
|
BMASK = 80,
|
|
BPFCC = 81,
|
|
BPFCCA = 82,
|
|
BPFCCANT = 83,
|
|
BPFCCNT = 84,
|
|
BPGEZapn = 85,
|
|
BPGEZapt = 86,
|
|
BPGEZnapn = 87,
|
|
BPGEZnapt = 88,
|
|
BPGZapn = 89,
|
|
BPGZapt = 90,
|
|
BPGZnapn = 91,
|
|
BPGZnapt = 92,
|
|
BPICC = 93,
|
|
BPICCA = 94,
|
|
BPICCANT = 95,
|
|
BPICCNT = 96,
|
|
BPLEZapn = 97,
|
|
BPLEZapt = 98,
|
|
BPLEZnapn = 99,
|
|
BPLEZnapt = 100,
|
|
BPLZapn = 101,
|
|
BPLZapt = 102,
|
|
BPLZnapn = 103,
|
|
BPLZnapt = 104,
|
|
BPNZapn = 105,
|
|
BPNZapt = 106,
|
|
BPNZnapn = 107,
|
|
BPNZnapt = 108,
|
|
BPXCC = 109,
|
|
BPXCCA = 110,
|
|
BPXCCANT = 111,
|
|
BPXCCNT = 112,
|
|
BPZapn = 113,
|
|
BPZapt = 114,
|
|
BPZnapn = 115,
|
|
BPZnapt = 116,
|
|
BSHUFFLE = 117,
|
|
CALL = 118,
|
|
CALLri = 119,
|
|
CALLrr = 120,
|
|
CASXrr = 121,
|
|
CASrr = 122,
|
|
CMASK16 = 123,
|
|
CMASK32 = 124,
|
|
CMASK8 = 125,
|
|
CMPri = 126,
|
|
CMPrr = 127,
|
|
EDGE16 = 128,
|
|
EDGE16L = 129,
|
|
EDGE16LN = 130,
|
|
EDGE16N = 131,
|
|
EDGE32 = 132,
|
|
EDGE32L = 133,
|
|
EDGE32LN = 134,
|
|
EDGE32N = 135,
|
|
EDGE8 = 136,
|
|
EDGE8L = 137,
|
|
EDGE8LN = 138,
|
|
EDGE8N = 139,
|
|
FABSD = 140,
|
|
FABSQ = 141,
|
|
FABSS = 142,
|
|
FADDD = 143,
|
|
FADDQ = 144,
|
|
FADDS = 145,
|
|
FALIGNADATA = 146,
|
|
FAND = 147,
|
|
FANDNOT1 = 148,
|
|
FANDNOT1S = 149,
|
|
FANDNOT2 = 150,
|
|
FANDNOT2S = 151,
|
|
FANDS = 152,
|
|
FBCOND = 153,
|
|
FBCONDA = 154,
|
|
FCHKSM16 = 155,
|
|
FCMPD = 156,
|
|
FCMPEQ16 = 157,
|
|
FCMPEQ32 = 158,
|
|
FCMPGT16 = 159,
|
|
FCMPGT32 = 160,
|
|
FCMPLE16 = 161,
|
|
FCMPLE32 = 162,
|
|
FCMPNE16 = 163,
|
|
FCMPNE32 = 164,
|
|
FCMPQ = 165,
|
|
FCMPS = 166,
|
|
FDIVD = 167,
|
|
FDIVQ = 168,
|
|
FDIVS = 169,
|
|
FDMULQ = 170,
|
|
FDTOI = 171,
|
|
FDTOQ = 172,
|
|
FDTOS = 173,
|
|
FDTOX = 174,
|
|
FEXPAND = 175,
|
|
FHADDD = 176,
|
|
FHADDS = 177,
|
|
FHSUBD = 178,
|
|
FHSUBS = 179,
|
|
FITOD = 180,
|
|
FITOQ = 181,
|
|
FITOS = 182,
|
|
FLCMPD = 183,
|
|
FLCMPS = 184,
|
|
FLUSH = 185,
|
|
FLUSHW = 186,
|
|
FLUSHri = 187,
|
|
FLUSHrr = 188,
|
|
FMEAN16 = 189,
|
|
FMOVD = 190,
|
|
FMOVD_FCC = 191,
|
|
FMOVD_ICC = 192,
|
|
FMOVD_XCC = 193,
|
|
FMOVQ = 194,
|
|
FMOVQ_FCC = 195,
|
|
FMOVQ_ICC = 196,
|
|
FMOVQ_XCC = 197,
|
|
FMOVRGEZD = 198,
|
|
FMOVRGEZQ = 199,
|
|
FMOVRGEZS = 200,
|
|
FMOVRGZD = 201,
|
|
FMOVRGZQ = 202,
|
|
FMOVRGZS = 203,
|
|
FMOVRLEZD = 204,
|
|
FMOVRLEZQ = 205,
|
|
FMOVRLEZS = 206,
|
|
FMOVRLZD = 207,
|
|
FMOVRLZQ = 208,
|
|
FMOVRLZS = 209,
|
|
FMOVRNZD = 210,
|
|
FMOVRNZQ = 211,
|
|
FMOVRNZS = 212,
|
|
FMOVRZD = 213,
|
|
FMOVRZQ = 214,
|
|
FMOVRZS = 215,
|
|
FMOVS = 216,
|
|
FMOVS_FCC = 217,
|
|
FMOVS_ICC = 218,
|
|
FMOVS_XCC = 219,
|
|
FMUL8SUX16 = 220,
|
|
FMUL8ULX16 = 221,
|
|
FMUL8X16 = 222,
|
|
FMUL8X16AL = 223,
|
|
FMUL8X16AU = 224,
|
|
FMULD = 225,
|
|
FMULD8SUX16 = 226,
|
|
FMULD8ULX16 = 227,
|
|
FMULQ = 228,
|
|
FMULS = 229,
|
|
FNADDD = 230,
|
|
FNADDS = 231,
|
|
FNAND = 232,
|
|
FNANDS = 233,
|
|
FNEGD = 234,
|
|
FNEGQ = 235,
|
|
FNEGS = 236,
|
|
FNHADDD = 237,
|
|
FNHADDS = 238,
|
|
FNMULD = 239,
|
|
FNMULS = 240,
|
|
FNOR = 241,
|
|
FNORS = 242,
|
|
FNOT1 = 243,
|
|
FNOT1S = 244,
|
|
FNOT2 = 245,
|
|
FNOT2S = 246,
|
|
FNSMULD = 247,
|
|
FONE = 248,
|
|
FONES = 249,
|
|
FOR = 250,
|
|
FORNOT1 = 251,
|
|
FORNOT1S = 252,
|
|
FORNOT2 = 253,
|
|
FORNOT2S = 254,
|
|
FORS = 255,
|
|
FPACK16 = 256,
|
|
FPACK32 = 257,
|
|
FPACKFIX = 258,
|
|
FPADD16 = 259,
|
|
FPADD16S = 260,
|
|
FPADD32 = 261,
|
|
FPADD32S = 262,
|
|
FPADD64 = 263,
|
|
FPMERGE = 264,
|
|
FPSUB16 = 265,
|
|
FPSUB16S = 266,
|
|
FPSUB32 = 267,
|
|
FPSUB32S = 268,
|
|
FQTOD = 269,
|
|
FQTOI = 270,
|
|
FQTOS = 271,
|
|
FQTOX = 272,
|
|
FSLAS16 = 273,
|
|
FSLAS32 = 274,
|
|
FSLL16 = 275,
|
|
FSLL32 = 276,
|
|
FSMULD = 277,
|
|
FSQRTD = 278,
|
|
FSQRTQ = 279,
|
|
FSQRTS = 280,
|
|
FSRA16 = 281,
|
|
FSRA32 = 282,
|
|
FSRC1 = 283,
|
|
FSRC1S = 284,
|
|
FSRC2 = 285,
|
|
FSRC2S = 286,
|
|
FSRL16 = 287,
|
|
FSRL32 = 288,
|
|
FSTOD = 289,
|
|
FSTOI = 290,
|
|
FSTOQ = 291,
|
|
FSTOX = 292,
|
|
FSUBD = 293,
|
|
FSUBQ = 294,
|
|
FSUBS = 295,
|
|
FXNOR = 296,
|
|
FXNORS = 297,
|
|
FXOR = 298,
|
|
FXORS = 299,
|
|
FXTOD = 300,
|
|
FXTOQ = 301,
|
|
FXTOS = 302,
|
|
FZERO = 303,
|
|
FZEROS = 304,
|
|
GETPCX = 305,
|
|
JMPLri = 306,
|
|
JMPLrr = 307,
|
|
LDArr = 308,
|
|
LDDArr = 309,
|
|
LDDFArr = 310,
|
|
LDDFri = 311,
|
|
LDDFrr = 312,
|
|
LDDri = 313,
|
|
LDDrr = 314,
|
|
LDFArr = 315,
|
|
LDFSRri = 316,
|
|
LDFSRrr = 317,
|
|
LDFri = 318,
|
|
LDFrr = 319,
|
|
LDQFArr = 320,
|
|
LDQFri = 321,
|
|
LDQFrr = 322,
|
|
LDSBArr = 323,
|
|
LDSBri = 324,
|
|
LDSBrr = 325,
|
|
LDSHArr = 326,
|
|
LDSHri = 327,
|
|
LDSHrr = 328,
|
|
LDSTUBArr = 329,
|
|
LDSTUBri = 330,
|
|
LDSTUBrr = 331,
|
|
LDSWri = 332,
|
|
LDSWrr = 333,
|
|
LDUBArr = 334,
|
|
LDUBri = 335,
|
|
LDUBrr = 336,
|
|
LDUHArr = 337,
|
|
LDUHri = 338,
|
|
LDUHrr = 339,
|
|
LDXFSRri = 340,
|
|
LDXFSRrr = 341,
|
|
LDXri = 342,
|
|
LDXrr = 343,
|
|
LDri = 344,
|
|
LDrr = 345,
|
|
LEAX_ADDri = 346,
|
|
LEA_ADDri = 347,
|
|
LZCNT = 348,
|
|
MEMBARi = 349,
|
|
MOVDTOX = 350,
|
|
MOVFCCri = 351,
|
|
MOVFCCrr = 352,
|
|
MOVICCri = 353,
|
|
MOVICCrr = 354,
|
|
MOVRGEZri = 355,
|
|
MOVRGEZrr = 356,
|
|
MOVRGZri = 357,
|
|
MOVRGZrr = 358,
|
|
MOVRLEZri = 359,
|
|
MOVRLEZrr = 360,
|
|
MOVRLZri = 361,
|
|
MOVRLZrr = 362,
|
|
MOVRNZri = 363,
|
|
MOVRNZrr = 364,
|
|
MOVRRZri = 365,
|
|
MOVRRZrr = 366,
|
|
MOVSTOSW = 367,
|
|
MOVSTOUW = 368,
|
|
MOVWTOS = 369,
|
|
MOVXCCri = 370,
|
|
MOVXCCrr = 371,
|
|
MOVXTOD = 372,
|
|
MULSCCri = 373,
|
|
MULSCCrr = 374,
|
|
MULXri = 375,
|
|
MULXrr = 376,
|
|
NOP = 377,
|
|
ORCCri = 378,
|
|
ORCCrr = 379,
|
|
ORNCCri = 380,
|
|
ORNCCrr = 381,
|
|
ORNri = 382,
|
|
ORNrr = 383,
|
|
ORXNrr = 384,
|
|
ORXri = 385,
|
|
ORXrr = 386,
|
|
ORri = 387,
|
|
ORrr = 388,
|
|
PDIST = 389,
|
|
PDISTN = 390,
|
|
POPCrr = 391,
|
|
RDASR = 392,
|
|
RDPR = 393,
|
|
RDPSR = 394,
|
|
RDTBR = 395,
|
|
RDWIM = 396,
|
|
RESTOREri = 397,
|
|
RESTORErr = 398,
|
|
RET = 399,
|
|
RETL = 400,
|
|
RETTri = 401,
|
|
RETTrr = 402,
|
|
SAVEri = 403,
|
|
SAVErr = 404,
|
|
SDIVCCri = 405,
|
|
SDIVCCrr = 406,
|
|
SDIVXri = 407,
|
|
SDIVXrr = 408,
|
|
SDIVri = 409,
|
|
SDIVrr = 410,
|
|
SELECT_CC_DFP_FCC = 411,
|
|
SELECT_CC_DFP_ICC = 412,
|
|
SELECT_CC_FP_FCC = 413,
|
|
SELECT_CC_FP_ICC = 414,
|
|
SELECT_CC_Int_FCC = 415,
|
|
SELECT_CC_Int_ICC = 416,
|
|
SELECT_CC_QFP_FCC = 417,
|
|
SELECT_CC_QFP_ICC = 418,
|
|
SET = 419,
|
|
SETHIXi = 420,
|
|
SETHIi = 421,
|
|
SHUTDOWN = 422,
|
|
SIAM = 423,
|
|
SLLXri = 424,
|
|
SLLXrr = 425,
|
|
SLLri = 426,
|
|
SLLrr = 427,
|
|
SMULCCri = 428,
|
|
SMULCCrr = 429,
|
|
SMULri = 430,
|
|
SMULrr = 431,
|
|
SRAXri = 432,
|
|
SRAXrr = 433,
|
|
SRAri = 434,
|
|
SRArr = 435,
|
|
SRLXri = 436,
|
|
SRLXrr = 437,
|
|
SRLri = 438,
|
|
SRLrr = 439,
|
|
STArr = 440,
|
|
STBAR = 441,
|
|
STBArr = 442,
|
|
STBri = 443,
|
|
STBrr = 444,
|
|
STDArr = 445,
|
|
STDFArr = 446,
|
|
STDFri = 447,
|
|
STDFrr = 448,
|
|
STDri = 449,
|
|
STDrr = 450,
|
|
STFArr = 451,
|
|
STFSRri = 452,
|
|
STFSRrr = 453,
|
|
STFri = 454,
|
|
STFrr = 455,
|
|
STHArr = 456,
|
|
STHri = 457,
|
|
STHrr = 458,
|
|
STQFArr = 459,
|
|
STQFri = 460,
|
|
STQFrr = 461,
|
|
STXFSRri = 462,
|
|
STXFSRrr = 463,
|
|
STXri = 464,
|
|
STXrr = 465,
|
|
STri = 466,
|
|
STrr = 467,
|
|
SUBCCri = 468,
|
|
SUBCCrr = 469,
|
|
SUBCri = 470,
|
|
SUBCrr = 471,
|
|
SUBEri = 472,
|
|
SUBErr = 473,
|
|
SUBXri = 474,
|
|
SUBXrr = 475,
|
|
SUBri = 476,
|
|
SUBrr = 477,
|
|
SWAPArr = 478,
|
|
SWAPri = 479,
|
|
SWAPrr = 480,
|
|
TA3 = 481,
|
|
TA5 = 482,
|
|
TADDCCTVri = 483,
|
|
TADDCCTVrr = 484,
|
|
TADDCCri = 485,
|
|
TADDCCrr = 486,
|
|
TICCri = 487,
|
|
TICCrr = 488,
|
|
TLS_ADDXrr = 489,
|
|
TLS_ADDrr = 490,
|
|
TLS_CALL = 491,
|
|
TLS_LDXrr = 492,
|
|
TLS_LDrr = 493,
|
|
TSUBCCTVri = 494,
|
|
TSUBCCTVrr = 495,
|
|
TSUBCCri = 496,
|
|
TSUBCCrr = 497,
|
|
TXCCri = 498,
|
|
TXCCrr = 499,
|
|
UDIVCCri = 500,
|
|
UDIVCCrr = 501,
|
|
UDIVXri = 502,
|
|
UDIVXrr = 503,
|
|
UDIVri = 504,
|
|
UDIVrr = 505,
|
|
UMULCCri = 506,
|
|
UMULCCrr = 507,
|
|
UMULXHI = 508,
|
|
UMULri = 509,
|
|
UMULrr = 510,
|
|
UNIMP = 511,
|
|
V9FCMPD = 512,
|
|
V9FCMPED = 513,
|
|
V9FCMPEQ = 514,
|
|
V9FCMPES = 515,
|
|
V9FCMPQ = 516,
|
|
V9FCMPS = 517,
|
|
V9FMOVD_FCC = 518,
|
|
V9FMOVQ_FCC = 519,
|
|
V9FMOVS_FCC = 520,
|
|
V9MOVFCCri = 521,
|
|
V9MOVFCCrr = 522,
|
|
WRASRri = 523,
|
|
WRASRrr = 524,
|
|
WRPRri = 525,
|
|
WRPRrr = 526,
|
|
WRPSRri = 527,
|
|
WRPSRrr = 528,
|
|
WRTBRri = 529,
|
|
WRTBRrr = 530,
|
|
WRWIMri = 531,
|
|
WRWIMrr = 532,
|
|
XMULX = 533,
|
|
XMULXHI = 534,
|
|
XNORCCri = 535,
|
|
XNORCCrr = 536,
|
|
XNORXrr = 537,
|
|
XNORri = 538,
|
|
XNORrr = 539,
|
|
XORCCri = 540,
|
|
XORCCrr = 541,
|
|
XORXri = 542,
|
|
XORXrr = 543,
|
|
XORri = 544,
|
|
XORrr = 545,
|
|
INSTRUCTION_LIST_END = 546
|
|
};
|
|
|
|
namespace Sched {
|
|
enum {
|
|
NoInstrModel = 0,
|
|
SCHED_LIST_END = 1
|
|
};
|
|
} // end Sched namespace
|
|
} // end SP namespace
|
|
} // end llvm namespace
|
|
#endif // GET_INSTRINFO_ENUM
|
|
|
|
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|
|
|* *|
|
|
|* Target Instruction Descriptors *|
|
|
|* *|
|
|
|* Automatically generated file, do not edit! *|
|
|
|* *|
|
|
\*===----------------------------------------------------------------------===*/
|
|
|
|
|
|
#ifdef GET_INSTRINFO_MC_DESC
|
|
#undef GET_INSTRINFO_MC_DESC
|
|
namespace llvm_ks {
|
|
|
|
static const MCPhysReg ImplicitList1[] = { SP::ICC, 0 };
|
|
static const MCPhysReg ImplicitList2[] = { SP::O6, 0 };
|
|
static const MCPhysReg ImplicitList3[] = { SP::FCC0, 0 };
|
|
static const MCPhysReg ImplicitList4[] = { SP::O7, 0 };
|
|
static const MCPhysReg ImplicitList5[] = { SP::FSR, 0 };
|
|
static const MCPhysReg ImplicitList6[] = { SP::Y, SP::ICC, 0 };
|
|
static const MCPhysReg ImplicitList7[] = { SP::PSR, 0 };
|
|
static const MCPhysReg ImplicitList8[] = { SP::TBR, 0 };
|
|
static const MCPhysReg ImplicitList9[] = { SP::WIM, 0 };
|
|
static const MCPhysReg ImplicitList10[] = { SP::Y, 0 };
|
|
|
|
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo13[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo14[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo15[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo16[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo17[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo18[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo19[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo20[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo22[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo23[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo24[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
|
|
static const MCOperandInfo OperandInfo25[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
|
|
static const MCOperandInfo OperandInfo26[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo27[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo28[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo29[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo30[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo31[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo32[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo33[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo34[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo35[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo36[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo37[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo38[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo39[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo40[] = { { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo41[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo42[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo43[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo44[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo45[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
|
|
static const MCOperandInfo OperandInfo46[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
|
|
static const MCOperandInfo OperandInfo47[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo48[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo49[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo50[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo51[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo52[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo53[] = { { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo54[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo55[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo56[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo57[] = { { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo58[] = { { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo59[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo60[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo61[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo62[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo63[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo64[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo65[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo66[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo67[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo68[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo69[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo70[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo71[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo72[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo73[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo74[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo75[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo76[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo77[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo78[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo79[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo80[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo81[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo82[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo83[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo84[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo85[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo86[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo87[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo88[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo89[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo90[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo91[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo92[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo93[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo94[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
|
|
static const MCOperandInfo OperandInfo95[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo96[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo97[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo98[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo99[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
|
|
static const MCOperandInfo OperandInfo100[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
|
|
static const MCOperandInfo OperandInfo101[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
|
|
static const MCOperandInfo OperandInfo102[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo103[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo104[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo105[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo106[] = { { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo107[] = { { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo108[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo109[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo110[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo111[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo112[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo113[] = { { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo114[] = { { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
static const MCOperandInfo OperandInfo115[] = { { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
|
|
static const MCOperandInfo OperandInfo116[] = { { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
|
|
|
|
extern const MCInstrDesc SparcInsts[] = {
|
|
{ 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #0 = PHI
|
|
{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
|
|
{ 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2 = CFI_INSTRUCTION
|
|
{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #3 = EH_LABEL
|
|
{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #4 = GC_LABEL
|
|
{ 5, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #5 = KILL
|
|
{ 6, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = EXTRACT_SUBREG
|
|
{ 7, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #7 = INSERT_SUBREG
|
|
{ 8, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #8 = IMPLICIT_DEF
|
|
{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #9 = SUBREG_TO_REG
|
|
{ 10, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #10 = COPY_TO_REGCLASS
|
|
{ 11, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11 = DBG_VALUE
|
|
{ 12, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #12 = REG_SEQUENCE
|
|
{ 13, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #13 = COPY
|
|
{ 14, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #14 = BUNDLE
|
|
{ 15, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #15 = LIFETIME_START
|
|
{ 16, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #16 = LIFETIME_END
|
|
{ 17, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #17 = STACKMAP
|
|
{ 18, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #18 = PATCHPOINT
|
|
{ 19, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #19 = LOAD_STACK_GUARD
|
|
{ 20, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #20 = STATEPOINT
|
|
{ 21, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #21 = LOCAL_ESCAPE
|
|
{ 22, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #22 = FAULTING_LOAD_OP
|
|
{ 23, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #23 = G_ADD
|
|
{ 24, 3, 1, 4, 0, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #24 = ADDCCri
|
|
{ 25, 3, 1, 4, 0, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #25 = ADDCCrr
|
|
{ 26, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #26 = ADDCri
|
|
{ 27, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #27 = ADDCrr
|
|
{ 28, 3, 1, 4, 0, 0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #28 = ADDEri
|
|
{ 29, 3, 1, 4, 0, 0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #29 = ADDErr
|
|
{ 30, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #30 = ADDXC
|
|
{ 31, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr }, // Inst #31 = ADDXCCC
|
|
{ 32, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #32 = ADDXri
|
|
{ 33, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #33 = ADDXrr
|
|
{ 34, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #34 = ADDri
|
|
{ 35, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #35 = ADDrr
|
|
{ 36, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #36 = ADJCALLSTACKDOWN
|
|
{ 37, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #37 = ADJCALLSTACKUP
|
|
{ 38, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #38 = ALIGNADDR
|
|
{ 39, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #39 = ALIGNADDRL
|
|
{ 40, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #40 = ANDCCri
|
|
{ 41, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #41 = ANDCCrr
|
|
{ 42, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #42 = ANDNCCri
|
|
{ 43, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #43 = ANDNCCrr
|
|
{ 44, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #44 = ANDNri
|
|
{ 45, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = ANDNrr
|
|
{ 46, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = ANDXNrr
|
|
{ 47, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #47 = ANDXri
|
|
{ 48, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #48 = ANDXrr
|
|
{ 49, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #49 = ANDri
|
|
{ 50, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #50 = ANDrr
|
|
{ 51, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #51 = ARRAY16
|
|
{ 52, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #52 = ARRAY32
|
|
{ 53, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #53 = ARRAY8
|
|
{ 54, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #54 = ATOMIC_LOAD_ADD_32
|
|
{ 55, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #55 = ATOMIC_LOAD_ADD_64
|
|
{ 56, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #56 = ATOMIC_LOAD_AND_32
|
|
{ 57, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #57 = ATOMIC_LOAD_AND_64
|
|
{ 58, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #58 = ATOMIC_LOAD_MAX_32
|
|
{ 59, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #59 = ATOMIC_LOAD_MAX_64
|
|
{ 60, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #60 = ATOMIC_LOAD_MIN_32
|
|
{ 61, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #61 = ATOMIC_LOAD_MIN_64
|
|
{ 62, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #62 = ATOMIC_LOAD_NAND_32
|
|
{ 63, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #63 = ATOMIC_LOAD_NAND_64
|
|
{ 64, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #64 = ATOMIC_LOAD_OR_32
|
|
{ 65, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #65 = ATOMIC_LOAD_OR_64
|
|
{ 66, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #66 = ATOMIC_LOAD_SUB_32
|
|
{ 67, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #67 = ATOMIC_LOAD_SUB_64
|
|
{ 68, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #68 = ATOMIC_LOAD_UMAX_32
|
|
{ 69, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #69 = ATOMIC_LOAD_UMAX_64
|
|
{ 70, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #70 = ATOMIC_LOAD_UMIN_32
|
|
{ 71, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #71 = ATOMIC_LOAD_UMIN_64
|
|
{ 72, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #72 = ATOMIC_LOAD_XOR_32
|
|
{ 73, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #73 = ATOMIC_LOAD_XOR_64
|
|
{ 74, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #74 = ATOMIC_SWAP_64
|
|
{ 75, 1, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #75 = BA
|
|
{ 76, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #76 = BCOND
|
|
{ 77, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #77 = BCONDA
|
|
{ 78, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #78 = BINDri
|
|
{ 79, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #79 = BINDrr
|
|
{ 80, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #80 = BMASK
|
|
{ 81, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #81 = BPFCC
|
|
{ 82, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #82 = BPFCCA
|
|
{ 83, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #83 = BPFCCANT
|
|
{ 84, 3, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #84 = BPFCCNT
|
|
{ 85, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #85 = BPGEZapn
|
|
{ 86, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #86 = BPGEZapt
|
|
{ 87, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #87 = BPGEZnapn
|
|
{ 88, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #88 = BPGEZnapt
|
|
{ 89, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #89 = BPGZapn
|
|
{ 90, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #90 = BPGZapt
|
|
{ 91, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #91 = BPGZnapn
|
|
{ 92, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #92 = BPGZnapt
|
|
{ 93, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #93 = BPICC
|
|
{ 94, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #94 = BPICCA
|
|
{ 95, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #95 = BPICCANT
|
|
{ 96, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #96 = BPICCNT
|
|
{ 97, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #97 = BPLEZapn
|
|
{ 98, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #98 = BPLEZapt
|
|
{ 99, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #99 = BPLEZnapn
|
|
{ 100, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #100 = BPLEZnapt
|
|
{ 101, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #101 = BPLZapn
|
|
{ 102, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #102 = BPLZapt
|
|
{ 103, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #103 = BPLZnapn
|
|
{ 104, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #104 = BPLZnapt
|
|
{ 105, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #105 = BPNZapn
|
|
{ 106, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #106 = BPNZapt
|
|
{ 107, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #107 = BPNZnapn
|
|
{ 108, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #108 = BPNZnapt
|
|
{ 109, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #109 = BPXCC
|
|
{ 110, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #110 = BPXCCA
|
|
{ 111, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #111 = BPXCCANT
|
|
{ 112, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #112 = BPXCCNT
|
|
{ 113, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #113 = BPZapn
|
|
{ 114, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #114 = BPZapt
|
|
{ 115, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #115 = BPZnapn
|
|
{ 116, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #116 = BPZnapt
|
|
{ 117, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #117 = BSHUFFLE
|
|
{ 118, 1, 0, 4, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #118 = CALL
|
|
{ 119, 2, 0, 4, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #119 = CALLri
|
|
{ 120, 2, 0, 4, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #120 = CALLrr
|
|
{ 121, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #121 = CASXrr
|
|
{ 122, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #122 = CASrr
|
|
{ 123, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #123 = CMASK16
|
|
{ 124, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #124 = CMASK32
|
|
{ 125, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #125 = CMASK8
|
|
{ 126, 2, 0, 4, 0, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr }, // Inst #126 = CMPri
|
|
{ 127, 2, 0, 4, 0, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr }, // Inst #127 = CMPrr
|
|
{ 128, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #128 = EDGE16
|
|
{ 129, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #129 = EDGE16L
|
|
{ 130, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #130 = EDGE16LN
|
|
{ 131, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #131 = EDGE16N
|
|
{ 132, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #132 = EDGE32
|
|
{ 133, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #133 = EDGE32L
|
|
{ 134, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #134 = EDGE32LN
|
|
{ 135, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #135 = EDGE32N
|
|
{ 136, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #136 = EDGE8
|
|
{ 137, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #137 = EDGE8L
|
|
{ 138, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #138 = EDGE8LN
|
|
{ 139, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #139 = EDGE8N
|
|
{ 140, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #140 = FABSD
|
|
{ 141, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #141 = FABSQ
|
|
{ 142, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #142 = FABSS
|
|
{ 143, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #143 = FADDD
|
|
{ 144, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #144 = FADDQ
|
|
{ 145, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #145 = FADDS
|
|
{ 146, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #146 = FALIGNADATA
|
|
{ 147, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #147 = FAND
|
|
{ 148, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #148 = FANDNOT1
|
|
{ 149, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #149 = FANDNOT1S
|
|
{ 150, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #150 = FANDNOT2
|
|
{ 151, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #151 = FANDNOT2S
|
|
{ 152, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #152 = FANDS
|
|
{ 153, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #153 = FBCOND
|
|
{ 154, 2, 0, 4, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #154 = FBCONDA
|
|
{ 155, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #155 = FCHKSM16
|
|
{ 156, 2, 0, 4, 0, 0, 0x0ULL, nullptr, ImplicitList3, OperandInfo29, -1 ,nullptr }, // Inst #156 = FCMPD
|
|
{ 157, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #157 = FCMPEQ16
|
|
{ 158, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #158 = FCMPEQ32
|
|
{ 159, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #159 = FCMPGT16
|
|
{ 160, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #160 = FCMPGT32
|
|
{ 161, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #161 = FCMPLE16
|
|
{ 162, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #162 = FCMPLE32
|
|
{ 163, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #163 = FCMPNE16
|
|
{ 164, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #164 = FCMPNE32
|
|
{ 165, 2, 0, 4, 0, 0, 0x0ULL, nullptr, ImplicitList3, OperandInfo30, -1 ,nullptr }, // Inst #165 = FCMPQ
|
|
{ 166, 2, 0, 4, 0, 0, 0x0ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #166 = FCMPS
|
|
{ 167, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #167 = FDIVD
|
|
{ 168, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #168 = FDIVQ
|
|
{ 169, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #169 = FDIVS
|
|
{ 170, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #170 = FDMULQ
|
|
{ 171, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #171 = FDTOI
|
|
{ 172, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #172 = FDTOQ
|
|
{ 173, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #173 = FDTOS
|
|
{ 174, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #174 = FDTOX
|
|
{ 175, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #175 = FEXPAND
|
|
{ 176, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #176 = FHADDD
|
|
{ 177, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #177 = FHADDS
|
|
{ 178, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #178 = FHSUBD
|
|
{ 179, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #179 = FHSUBS
|
|
{ 180, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #180 = FITOD
|
|
{ 181, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #181 = FITOQ
|
|
{ 182, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #182 = FITOS
|
|
{ 183, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #183 = FLCMPD
|
|
{ 184, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #184 = FLCMPS
|
|
{ 185, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #185 = FLUSH
|
|
{ 186, 0, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #186 = FLUSHW
|
|
{ 187, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #187 = FLUSHri
|
|
{ 188, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #188 = FLUSHrr
|
|
{ 189, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #189 = FMEAN16
|
|
{ 190, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #190 = FMOVD
|
|
{ 191, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList3, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #191 = FMOVD_FCC
|
|
{ 192, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #192 = FMOVD_ICC
|
|
{ 193, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #193 = FMOVD_XCC
|
|
{ 194, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #194 = FMOVQ
|
|
{ 195, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList3, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #195 = FMOVQ_FCC
|
|
{ 196, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #196 = FMOVQ_ICC
|
|
{ 197, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #197 = FMOVQ_XCC
|
|
{ 198, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #198 = FMOVRGEZD
|
|
{ 199, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #199 = FMOVRGEZQ
|
|
{ 200, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #200 = FMOVRGEZS
|
|
{ 201, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #201 = FMOVRGZD
|
|
{ 202, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #202 = FMOVRGZQ
|
|
{ 203, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #203 = FMOVRGZS
|
|
{ 204, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #204 = FMOVRLEZD
|
|
{ 205, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #205 = FMOVRLEZQ
|
|
{ 206, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #206 = FMOVRLEZS
|
|
{ 207, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #207 = FMOVRLZD
|
|
{ 208, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #208 = FMOVRLZQ
|
|
{ 209, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #209 = FMOVRLZS
|
|
{ 210, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #210 = FMOVRNZD
|
|
{ 211, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #211 = FMOVRNZQ
|
|
{ 212, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #212 = FMOVRNZS
|
|
{ 213, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #213 = FMOVRZD
|
|
{ 214, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #214 = FMOVRZQ
|
|
{ 215, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #215 = FMOVRZS
|
|
{ 216, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #216 = FMOVS
|
|
{ 217, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList3, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #217 = FMOVS_FCC
|
|
{ 218, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #218 = FMOVS_ICC
|
|
{ 219, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #219 = FMOVS_XCC
|
|
{ 220, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #220 = FMUL8SUX16
|
|
{ 221, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #221 = FMUL8ULX16
|
|
{ 222, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #222 = FMUL8X16
|
|
{ 223, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #223 = FMUL8X16AL
|
|
{ 224, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #224 = FMUL8X16AU
|
|
{ 225, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #225 = FMULD
|
|
{ 226, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #226 = FMULD8SUX16
|
|
{ 227, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #227 = FMULD8ULX16
|
|
{ 228, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #228 = FMULQ
|
|
{ 229, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #229 = FMULS
|
|
{ 230, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #230 = FNADDD
|
|
{ 231, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #231 = FNADDS
|
|
{ 232, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #232 = FNAND
|
|
{ 233, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #233 = FNANDS
|
|
{ 234, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #234 = FNEGD
|
|
{ 235, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #235 = FNEGQ
|
|
{ 236, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #236 = FNEGS
|
|
{ 237, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #237 = FNHADDD
|
|
{ 238, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #238 = FNHADDS
|
|
{ 239, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #239 = FNMULD
|
|
{ 240, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #240 = FNMULS
|
|
{ 241, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #241 = FNOR
|
|
{ 242, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #242 = FNORS
|
|
{ 243, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #243 = FNOT1
|
|
{ 244, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #244 = FNOT1S
|
|
{ 245, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #245 = FNOT2
|
|
{ 246, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #246 = FNOT2S
|
|
{ 247, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #247 = FNSMULD
|
|
{ 248, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #248 = FONE
|
|
{ 249, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #249 = FONES
|
|
{ 250, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #250 = FOR
|
|
{ 251, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #251 = FORNOT1
|
|
{ 252, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #252 = FORNOT1S
|
|
{ 253, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #253 = FORNOT2
|
|
{ 254, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #254 = FORNOT2S
|
|
{ 255, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #255 = FORS
|
|
{ 256, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #256 = FPACK16
|
|
{ 257, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #257 = FPACK32
|
|
{ 258, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #258 = FPACKFIX
|
|
{ 259, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #259 = FPADD16
|
|
{ 260, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #260 = FPADD16S
|
|
{ 261, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #261 = FPADD32
|
|
{ 262, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #262 = FPADD32S
|
|
{ 263, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #263 = FPADD64
|
|
{ 264, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #264 = FPMERGE
|
|
{ 265, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #265 = FPSUB16
|
|
{ 266, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #266 = FPSUB16S
|
|
{ 267, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #267 = FPSUB32
|
|
{ 268, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #268 = FPSUB32S
|
|
{ 269, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #269 = FQTOD
|
|
{ 270, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #270 = FQTOI
|
|
{ 271, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #271 = FQTOS
|
|
{ 272, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #272 = FQTOX
|
|
{ 273, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #273 = FSLAS16
|
|
{ 274, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #274 = FSLAS32
|
|
{ 275, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #275 = FSLL16
|
|
{ 276, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #276 = FSLL32
|
|
{ 277, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #277 = FSMULD
|
|
{ 278, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #278 = FSQRTD
|
|
{ 279, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #279 = FSQRTQ
|
|
{ 280, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #280 = FSQRTS
|
|
{ 281, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #281 = FSRA16
|
|
{ 282, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #282 = FSRA32
|
|
{ 283, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #283 = FSRC1
|
|
{ 284, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #284 = FSRC1S
|
|
{ 285, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #285 = FSRC2
|
|
{ 286, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #286 = FSRC2S
|
|
{ 287, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #287 = FSRL16
|
|
{ 288, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #288 = FSRL32
|
|
{ 289, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #289 = FSTOD
|
|
{ 290, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #290 = FSTOI
|
|
{ 291, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #291 = FSTOQ
|
|
{ 292, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #292 = FSTOX
|
|
{ 293, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #293 = FSUBD
|
|
{ 294, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #294 = FSUBQ
|
|
{ 295, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #295 = FSUBS
|
|
{ 296, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #296 = FXNOR
|
|
{ 297, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #297 = FXNORS
|
|
{ 298, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #298 = FXOR
|
|
{ 299, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #299 = FXORS
|
|
{ 300, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #300 = FXTOD
|
|
{ 301, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #301 = FXTOQ
|
|
{ 302, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #302 = FXTOS
|
|
{ 303, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #303 = FZERO
|
|
{ 304, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #304 = FZEROS
|
|
{ 305, 1, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo5, -1 ,nullptr }, // Inst #305 = GETPCX
|
|
{ 306, 3, 1, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #306 = JMPLri
|
|
{ 307, 3, 1, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #307 = JMPLrr
|
|
{ 308, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #308 = LDArr
|
|
{ 309, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #309 = LDDArr
|
|
{ 310, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #310 = LDDFArr
|
|
{ 311, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #311 = LDDFri
|
|
{ 312, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #312 = LDDFrr
|
|
{ 313, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #313 = LDDri
|
|
{ 314, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #314 = LDDrr
|
|
{ 315, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #315 = LDFArr
|
|
{ 316, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr }, // Inst #316 = LDFSRri
|
|
{ 317, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr }, // Inst #317 = LDFSRrr
|
|
{ 318, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #318 = LDFri
|
|
{ 319, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #319 = LDFrr
|
|
{ 320, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #320 = LDQFArr
|
|
{ 321, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #321 = LDQFri
|
|
{ 322, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #322 = LDQFrr
|
|
{ 323, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #323 = LDSBArr
|
|
{ 324, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #324 = LDSBri
|
|
{ 325, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #325 = LDSBrr
|
|
{ 326, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #326 = LDSHArr
|
|
{ 327, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #327 = LDSHri
|
|
{ 328, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #328 = LDSHrr
|
|
{ 329, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #329 = LDSTUBArr
|
|
{ 330, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #330 = LDSTUBri
|
|
{ 331, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #331 = LDSTUBrr
|
|
{ 332, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #332 = LDSWri
|
|
{ 333, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #333 = LDSWrr
|
|
{ 334, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #334 = LDUBArr
|
|
{ 335, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #335 = LDUBri
|
|
{ 336, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #336 = LDUBrr
|
|
{ 337, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #337 = LDUHArr
|
|
{ 338, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #338 = LDUHri
|
|
{ 339, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #339 = LDUHrr
|
|
{ 340, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr }, // Inst #340 = LDXFSRri
|
|
{ 341, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr }, // Inst #341 = LDXFSRrr
|
|
{ 342, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #342 = LDXri
|
|
{ 343, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #343 = LDXrr
|
|
{ 344, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #344 = LDri
|
|
{ 345, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #345 = LDrr
|
|
{ 346, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #346 = LEAX_ADDri
|
|
{ 347, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #347 = LEA_ADDri
|
|
{ 348, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #348 = LZCNT
|
|
{ 349, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #349 = MEMBARi
|
|
{ 350, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #350 = MOVDTOX
|
|
{ 351, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #351 = MOVFCCri
|
|
{ 352, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList3, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #352 = MOVFCCrr
|
|
{ 353, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #353 = MOVICCri
|
|
{ 354, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #354 = MOVICCrr
|
|
{ 355, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #355 = MOVRGEZri
|
|
{ 356, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #356 = MOVRGEZrr
|
|
{ 357, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #357 = MOVRGZri
|
|
{ 358, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #358 = MOVRGZrr
|
|
{ 359, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #359 = MOVRLEZri
|
|
{ 360, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #360 = MOVRLEZrr
|
|
{ 361, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #361 = MOVRLZri
|
|
{ 362, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #362 = MOVRLZrr
|
|
{ 363, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #363 = MOVRNZri
|
|
{ 364, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #364 = MOVRNZrr
|
|
{ 365, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #365 = MOVRRZri
|
|
{ 366, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #366 = MOVRRZrr
|
|
{ 367, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #367 = MOVSTOSW
|
|
{ 368, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #368 = MOVSTOUW
|
|
{ 369, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #369 = MOVWTOS
|
|
{ 370, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #370 = MOVXCCri
|
|
{ 371, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList1, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #371 = MOVXCCrr
|
|
{ 372, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #372 = MOVXTOD
|
|
{ 373, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #373 = MULSCCri
|
|
{ 374, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList6, OperandInfo14, -1 ,nullptr }, // Inst #374 = MULSCCrr
|
|
{ 375, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #375 = MULXri
|
|
{ 376, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #376 = MULXrr
|
|
{ 377, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #377 = NOP
|
|
{ 378, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #378 = ORCCri
|
|
{ 379, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #379 = ORCCrr
|
|
{ 380, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #380 = ORNCCri
|
|
{ 381, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #381 = ORNCCrr
|
|
{ 382, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #382 = ORNri
|
|
{ 383, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #383 = ORNrr
|
|
{ 384, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #384 = ORXNrr
|
|
{ 385, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #385 = ORXri
|
|
{ 386, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #386 = ORXrr
|
|
{ 387, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #387 = ORri
|
|
{ 388, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #388 = ORrr
|
|
{ 389, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #389 = PDIST
|
|
{ 390, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #390 = PDISTN
|
|
{ 391, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #391 = POPCrr
|
|
{ 392, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #392 = RDASR
|
|
{ 393, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #393 = RDPR
|
|
{ 394, 1, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #394 = RDPSR
|
|
{ 395, 1, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList8, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #395 = RDTBR
|
|
{ 396, 1, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList9, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #396 = RDWIM
|
|
{ 397, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #397 = RESTOREri
|
|
{ 398, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #398 = RESTORErr
|
|
{ 399, 1, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #399 = RET
|
|
{ 400, 1, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #400 = RETL
|
|
{ 401, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #401 = RETTri
|
|
{ 402, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #402 = RETTrr
|
|
{ 403, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #403 = SAVEri
|
|
{ 404, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #404 = SAVErr
|
|
{ 405, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #405 = SDIVCCri
|
|
{ 406, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo14, -1 ,nullptr }, // Inst #406 = SDIVCCrr
|
|
{ 407, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #407 = SDIVXri
|
|
{ 408, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #408 = SDIVXrr
|
|
{ 409, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo13, -1 ,nullptr }, // Inst #409 = SDIVri
|
|
{ 410, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo14, -1 ,nullptr }, // Inst #410 = SDIVrr
|
|
{ 411, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #411 = SELECT_CC_DFP_FCC
|
|
{ 412, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #412 = SELECT_CC_DFP_ICC
|
|
{ 413, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #413 = SELECT_CC_FP_FCC
|
|
{ 414, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #414 = SELECT_CC_FP_ICC
|
|
{ 415, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #415 = SELECT_CC_Int_FCC
|
|
{ 416, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #416 = SELECT_CC_Int_ICC
|
|
{ 417, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #417 = SELECT_CC_QFP_FCC
|
|
{ 418, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #418 = SELECT_CC_QFP_ICC
|
|
{ 419, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #419 = SET
|
|
{ 420, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #420 = SETHIXi
|
|
{ 421, 2, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #421 = SETHIi
|
|
{ 422, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #422 = SHUTDOWN
|
|
{ 423, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #423 = SIAM
|
|
{ 424, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #424 = SLLXri
|
|
{ 425, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #425 = SLLXrr
|
|
{ 426, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #426 = SLLri
|
|
{ 427, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #427 = SLLrr
|
|
{ 428, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #428 = SMULCCri
|
|
{ 429, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo14, -1 ,nullptr }, // Inst #429 = SMULCCrr
|
|
{ 430, 3, 1, 4, 0, 0, 0x0ULL, nullptr, ImplicitList10, OperandInfo13, -1 ,nullptr }, // Inst #430 = SMULri
|
|
{ 431, 3, 1, 4, 0, 0, 0x0ULL, nullptr, ImplicitList10, OperandInfo14, -1 ,nullptr }, // Inst #431 = SMULrr
|
|
{ 432, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #432 = SRAXri
|
|
{ 433, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #433 = SRAXrr
|
|
{ 434, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #434 = SRAri
|
|
{ 435, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #435 = SRArr
|
|
{ 436, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #436 = SRLXri
|
|
{ 437, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #437 = SRLXrr
|
|
{ 438, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #438 = SRLri
|
|
{ 439, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #439 = SRLrr
|
|
{ 440, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #440 = STArr
|
|
{ 441, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #441 = STBAR
|
|
{ 442, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #442 = STBArr
|
|
{ 443, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #443 = STBri
|
|
{ 444, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #444 = STBrr
|
|
{ 445, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #445 = STDArr
|
|
{ 446, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #446 = STDFArr
|
|
{ 447, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #447 = STDFri
|
|
{ 448, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #448 = STDFrr
|
|
{ 449, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #449 = STDri
|
|
{ 450, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #450 = STDrr
|
|
{ 451, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #451 = STFArr
|
|
{ 452, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr }, // Inst #452 = STFSRri
|
|
{ 453, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr }, // Inst #453 = STFSRrr
|
|
{ 454, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #454 = STFri
|
|
{ 455, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #455 = STFrr
|
|
{ 456, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #456 = STHArr
|
|
{ 457, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #457 = STHri
|
|
{ 458, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #458 = STHrr
|
|
{ 459, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #459 = STQFArr
|
|
{ 460, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #460 = STQFri
|
|
{ 461, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #461 = STQFrr
|
|
{ 462, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr }, // Inst #462 = STXFSRri
|
|
{ 463, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr }, // Inst #463 = STXFSRrr
|
|
{ 464, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #464 = STXri
|
|
{ 465, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #465 = STXrr
|
|
{ 466, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #466 = STri
|
|
{ 467, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #467 = STrr
|
|
{ 468, 3, 1, 4, 0, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #468 = SUBCCri
|
|
{ 469, 3, 1, 4, 0, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #469 = SUBCCrr
|
|
{ 470, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #470 = SUBCri
|
|
{ 471, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #471 = SUBCrr
|
|
{ 472, 3, 1, 4, 0, 0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #472 = SUBEri
|
|
{ 473, 3, 1, 4, 0, 0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #473 = SUBErr
|
|
{ 474, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #474 = SUBXri
|
|
{ 475, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #475 = SUBXrr
|
|
{ 476, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #476 = SUBri
|
|
{ 477, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #477 = SUBrr
|
|
{ 478, 5, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #478 = SWAPArr
|
|
{ 479, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #479 = SWAPri
|
|
{ 480, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #480 = SWAPrr
|
|
{ 481, 0, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #481 = TA3
|
|
{ 482, 0, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #482 = TA5
|
|
{ 483, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #483 = TADDCCTVri
|
|
{ 484, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #484 = TADDCCTVrr
|
|
{ 485, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #485 = TADDCCri
|
|
{ 486, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #486 = TADDCCrr
|
|
{ 487, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #487 = TICCri
|
|
{ 488, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #488 = TICCrr
|
|
{ 489, 4, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #489 = TLS_ADDXrr
|
|
{ 490, 4, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #490 = TLS_ADDrr
|
|
{ 491, 2, 0, 4, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #491 = TLS_CALL
|
|
{ 492, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #492 = TLS_LDXrr
|
|
{ 493, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #493 = TLS_LDrr
|
|
{ 494, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #494 = TSUBCCTVri
|
|
{ 495, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #495 = TSUBCCTVrr
|
|
{ 496, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #496 = TSUBCCri
|
|
{ 497, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #497 = TSUBCCrr
|
|
{ 498, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #498 = TXCCri
|
|
{ 499, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #499 = TXCCrr
|
|
{ 500, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #500 = UDIVCCri
|
|
{ 501, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo14, -1 ,nullptr }, // Inst #501 = UDIVCCrr
|
|
{ 502, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #502 = UDIVXri
|
|
{ 503, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #503 = UDIVXrr
|
|
{ 504, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo13, -1 ,nullptr }, // Inst #504 = UDIVri
|
|
{ 505, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo14, -1 ,nullptr }, // Inst #505 = UDIVrr
|
|
{ 506, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #506 = UMULCCri
|
|
{ 507, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo14, -1 ,nullptr }, // Inst #507 = UMULCCrr
|
|
{ 508, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #508 = UMULXHI
|
|
{ 509, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList10, OperandInfo13, -1 ,nullptr }, // Inst #509 = UMULri
|
|
{ 510, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList10, OperandInfo14, -1 ,nullptr }, // Inst #510 = UMULrr
|
|
{ 511, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #511 = UNIMP
|
|
{ 512, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #512 = V9FCMPD
|
|
{ 513, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #513 = V9FCMPED
|
|
{ 514, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #514 = V9FCMPEQ
|
|
{ 515, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #515 = V9FCMPES
|
|
{ 516, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #516 = V9FCMPQ
|
|
{ 517, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #517 = V9FCMPS
|
|
{ 518, 5, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #518 = V9FMOVD_FCC
|
|
{ 519, 5, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #519 = V9FMOVQ_FCC
|
|
{ 520, 5, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #520 = V9FMOVS_FCC
|
|
{ 521, 5, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #521 = V9MOVFCCri
|
|
{ 522, 5, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #522 = V9MOVFCCrr
|
|
{ 523, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #523 = WRASRri
|
|
{ 524, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #524 = WRASRrr
|
|
{ 525, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #525 = WRPRri
|
|
{ 526, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #526 = WRPRrr
|
|
{ 527, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo27, -1 ,nullptr }, // Inst #527 = WRPSRri
|
|
{ 528, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo28, -1 ,nullptr }, // Inst #528 = WRPSRrr
|
|
{ 529, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo27, -1 ,nullptr }, // Inst #529 = WRTBRri
|
|
{ 530, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo28, -1 ,nullptr }, // Inst #530 = WRTBRrr
|
|
{ 531, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList9, OperandInfo27, -1 ,nullptr }, // Inst #531 = WRWIMri
|
|
{ 532, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList9, OperandInfo28, -1 ,nullptr }, // Inst #532 = WRWIMrr
|
|
{ 533, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #533 = XMULX
|
|
{ 534, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #534 = XMULXHI
|
|
{ 535, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #535 = XNORCCri
|
|
{ 536, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #536 = XNORCCrr
|
|
{ 537, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #537 = XNORXrr
|
|
{ 538, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #538 = XNORri
|
|
{ 539, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #539 = XNORrr
|
|
{ 540, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #540 = XORCCri
|
|
{ 541, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #541 = XORCCrr
|
|
{ 542, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #542 = XORXri
|
|
{ 543, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #543 = XORXrr
|
|
{ 544, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #544 = XORri
|
|
{ 545, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #545 = XORrr
|
|
};
|
|
|
|
static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
|
|
II->InitMCInstrInfo(SparcInsts, NULL, NULL, 546);
|
|
}
|
|
|
|
} // end llvm namespace
|
|
#endif // GET_INSTRINFO_MC_DESC
|
|
|
|
|
|
#ifdef GET_INSTRINFO_HEADER
|
|
#undef GET_INSTRINFO_HEADER
|
|
namespace llvm_ks {
|
|
struct SparcGenInstrInfo : public TargetInstrInfo {
|
|
explicit SparcGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1);
|
|
~SparcGenInstrInfo() override {}
|
|
};
|
|
} // end llvm namespace
|
|
#endif // GET_INSTRINFO_HEADER
|
|
|
|
|
|
#ifdef GET_INSTRINFO_OPERAND_ENUM
|
|
#undef GET_INSTRINFO_OPERAND_ENUM
|
|
namespace llvm_ks {
|
|
namespace SP {
|
|
namespace OpName {
|
|
enum {
|
|
OPERAND_LAST
|
|
};
|
|
} // end namespace OpName
|
|
} // end namespace SP
|
|
} // end namespace llvm_ks
|
|
#endif //GET_INSTRINFO_OPERAND_ENUM
|
|
#ifdef GET_INSTRINFO_NAMED_OPS
|
|
#undef GET_INSTRINFO_NAMED_OPS
|
|
namespace llvm_ks {
|
|
namespace SP {
|
|
LLVM_READONLY
|
|
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
|
|
return -1;
|
|
}
|
|
} // end namespace SP
|
|
} // end namespace llvm_ks
|
|
#endif //GET_INSTRINFO_NAMED_OPS
|
|
|
|
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
|
|
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
|
|
namespace llvm_ks {
|
|
namespace SP {
|
|
namespace OpTypes {
|
|
enum OperandType {
|
|
CCOp = 0,
|
|
MEMri = 1,
|
|
MEMrr = 2,
|
|
TLSSym = 3,
|
|
bprtarget = 4,
|
|
bprtarget16 = 5,
|
|
brtarget = 6,
|
|
calltarget = 7,
|
|
f32imm = 8,
|
|
f64imm = 9,
|
|
getPCX = 10,
|
|
i16imm = 11,
|
|
i1imm = 12,
|
|
i32imm = 13,
|
|
i64imm = 14,
|
|
i8imm = 15,
|
|
simm13Op = 16,
|
|
OPERAND_TYPE_LIST_END
|
|
};
|
|
} // end namespace OpTypes
|
|
} // end namespace SP
|
|
} // end namespace llvm_ks
|
|
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
|