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1388 lines
37 KiB
1388 lines
37 KiB
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Target Register Enum Values *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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namespace llvm_ks {
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class MCRegisterClass;
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extern const MCRegisterClass SystemZMCRegisterClasses[];
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namespace SystemZ {
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enum {
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NoRegister,
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CC = 1,
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V0 = 2,
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V1 = 3,
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V2 = 4,
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V3 = 5,
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V4 = 6,
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V5 = 7,
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V6 = 8,
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V7 = 9,
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V8 = 10,
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V9 = 11,
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V10 = 12,
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V11 = 13,
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V12 = 14,
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V13 = 15,
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V14 = 16,
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V15 = 17,
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V16 = 18,
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V17 = 19,
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V18 = 20,
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V19 = 21,
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V20 = 22,
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V21 = 23,
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V22 = 24,
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V23 = 25,
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V24 = 26,
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V25 = 27,
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V26 = 28,
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V27 = 29,
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V28 = 30,
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V29 = 31,
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V30 = 32,
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V31 = 33,
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F0D = 34,
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F1D = 35,
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F2D = 36,
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F3D = 37,
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F4D = 38,
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F5D = 39,
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F6D = 40,
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F7D = 41,
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F8D = 42,
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F9D = 43,
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F10D = 44,
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F11D = 45,
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F12D = 46,
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F13D = 47,
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F14D = 48,
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F15D = 49,
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F16D = 50,
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F17D = 51,
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F18D = 52,
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F19D = 53,
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F20D = 54,
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F21D = 55,
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F22D = 56,
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F23D = 57,
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F24D = 58,
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F25D = 59,
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F26D = 60,
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F27D = 61,
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F28D = 62,
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F29D = 63,
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F30D = 64,
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F31D = 65,
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F0Q = 66,
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F1Q = 67,
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F4Q = 68,
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F5Q = 69,
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F8Q = 70,
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F9Q = 71,
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F12Q = 72,
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F13Q = 73,
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F0S = 74,
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F1S = 75,
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F2S = 76,
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F3S = 77,
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F4S = 78,
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F5S = 79,
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F6S = 80,
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F7S = 81,
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F8S = 82,
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F9S = 83,
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F10S = 84,
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F11S = 85,
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F12S = 86,
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F13S = 87,
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F14S = 88,
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F15S = 89,
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F16S = 90,
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F17S = 91,
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F18S = 92,
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F19S = 93,
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F20S = 94,
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F21S = 95,
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F22S = 96,
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F23S = 97,
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F24S = 98,
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F25S = 99,
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F26S = 100,
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F27S = 101,
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F28S = 102,
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F29S = 103,
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F30S = 104,
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F31S = 105,
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R0D = 106,
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R1D = 107,
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R2D = 108,
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R3D = 109,
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R4D = 110,
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R5D = 111,
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R6D = 112,
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R7D = 113,
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R8D = 114,
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R9D = 115,
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R10D = 116,
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R11D = 117,
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R12D = 118,
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R13D = 119,
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R14D = 120,
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R15D = 121,
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R0H = 122,
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R1H = 123,
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R2H = 124,
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R3H = 125,
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R4H = 126,
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R5H = 127,
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R6H = 128,
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R7H = 129,
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R8H = 130,
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R9H = 131,
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R10H = 132,
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R11H = 133,
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R12H = 134,
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R13H = 135,
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R14H = 136,
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R15H = 137,
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R0L = 138,
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R1L = 139,
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R2L = 140,
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R3L = 141,
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R4L = 142,
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R5L = 143,
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R6L = 144,
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R7L = 145,
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R8L = 146,
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R9L = 147,
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R10L = 148,
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R11L = 149,
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R12L = 150,
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R13L = 151,
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R14L = 152,
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R15L = 153,
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R0Q = 154,
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R2Q = 155,
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R4Q = 156,
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R6Q = 157,
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R8Q = 158,
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R10Q = 159,
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R12Q = 160,
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R14Q = 161,
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NUM_TARGET_REGS // 162
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};
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}
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// Register classes
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namespace SystemZ {
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enum {
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GRX32BitRegClassID = 0,
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VR32BitRegClassID = 1,
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FP32BitRegClassID = 2,
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GR32BitRegClassID = 3,
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GRH32BitRegClassID = 4,
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ADDR32BitRegClassID = 5,
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CCRegsRegClassID = 6,
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VR64BitRegClassID = 7,
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FP64BitRegClassID = 8,
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GR64BitRegClassID = 9,
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ADDR64BitRegClassID = 10,
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VR128BitRegClassID = 11,
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VF128BitRegClassID = 12,
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FP128BitRegClassID = 13,
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GR128BitRegClassID = 14,
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ADDR128BitRegClassID = 15,
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};
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}
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// Subregister indices
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namespace SystemZ {
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enum {
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NoSubRegister,
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subreg_h32, // 1
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subreg_h64, // 2
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subreg_hh32, // 3
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subreg_hl32, // 4
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subreg_hr32, // 5
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subreg_l32, // 6
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subreg_l64, // 7
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subreg_r32, // 8
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subreg_r64, // 9
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NUM_TARGET_SUBREGS
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};
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}
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} // End llvm namespace
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#endif // GET_REGINFO_ENUM
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* MC Register Information *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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namespace llvm_ks {
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extern const MCPhysReg SystemZRegDiffLists[] = {
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/* 0 */ 64953, 1, 1, 1, 0,
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/* 5 */ 65357, 1, 0,
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/* 8 */ 65471, 2, 0,
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/* 11 */ 65473, 2, 0,
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/* 14 */ 65475, 2, 0,
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/* 17 */ 65477, 2, 0,
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/* 20 */ 32, 40, 0,
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/* 23 */ 65506, 40, 65494, 40, 0,
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/* 28 */ 65508, 40, 65494, 40, 0,
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/* 33 */ 65510, 40, 65494, 40, 0,
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/* 38 */ 65512, 40, 65494, 40, 0,
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/* 43 */ 65504, 40, 0,
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/* 46 */ 65520, 40, 0,
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/* 49 */ 65504, 41, 0,
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/* 52 */ 65520, 41, 0,
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/* 55 */ 65504, 42, 0,
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/* 58 */ 65520, 42, 0,
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/* 61 */ 65504, 43, 0,
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/* 64 */ 65520, 43, 0,
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/* 67 */ 65504, 44, 0,
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/* 70 */ 65520, 44, 0,
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/* 73 */ 65504, 45, 0,
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/* 76 */ 65520, 45, 0,
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/* 79 */ 65504, 46, 0,
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/* 82 */ 65520, 46, 0,
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/* 85 */ 65504, 47, 0,
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/* 88 */ 65520, 47, 0,
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/* 91 */ 65504, 48, 0,
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/* 94 */ 65520, 48, 0,
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/* 97 */ 65496, 65504, 56, 0,
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/* 101 */ 65496, 65504, 58, 0,
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/* 105 */ 65496, 65504, 60, 0,
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/* 109 */ 65496, 65504, 62, 0,
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/* 113 */ 65496, 65504, 64, 0,
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/* 117 */ 65293, 0,
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/* 119 */ 65326, 0,
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/* 121 */ 65463, 0,
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/* 123 */ 65503, 0,
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/* 125 */ 65496, 65504, 0,
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/* 128 */ 65489, 32, 65520, 65519, 32, 65520, 0,
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/* 135 */ 65490, 32, 65520, 65519, 32, 65520, 0,
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/* 142 */ 65491, 32, 65520, 65519, 32, 65520, 0,
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/* 149 */ 65492, 32, 65520, 65519, 32, 65520, 0,
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/* 156 */ 65493, 32, 65520, 65519, 32, 65520, 0,
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/* 163 */ 65494, 32, 65520, 65519, 32, 65520, 0,
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/* 170 */ 65495, 32, 65520, 65519, 32, 65520, 0,
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/* 177 */ 65496, 32, 65520, 65519, 32, 65520, 0,
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/* 184 */ 65535, 0,
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};
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extern const unsigned SystemZLaneMaskLists[] = {
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/* 0 */ 0x00000000, ~0u,
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/* 2 */ 0x00000004, 0x00000002, 0x00000010, 0x00000001, ~0u,
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/* 7 */ 0x00000008, 0x00000020, ~0u,
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};
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extern const uint16_t SystemZSubRegIdxLists[] = {
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/* 0 */ 6, 1, 0,
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/* 3 */ 7, 6, 1, 2, 4, 3, 0,
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/* 10 */ 7, 8, 2, 5, 0,
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/* 15 */ 9, 8, 0,
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};
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extern const MCRegisterInfo::SubRegCoveredBits SystemZSubRegIdxRanges[] = {
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{ 65535, 65535 },
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{ 32, 32 }, // subreg_h32
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{ 64, 64 }, // subreg_h64
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{ 96, 32 }, // subreg_hh32
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{ 64, 32 }, // subreg_hl32
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{ 96, 32 }, // subreg_hr32
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{ 0, 32 }, // subreg_l32
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{ 0, 64 }, // subreg_l64
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{ 32, 32 }, // subreg_r32
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{ 64, 64 }, // subreg_r64
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};
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extern const char SystemZRegStrings[] = {
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/* 0 */ 'V', '1', '0', 0,
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/* 4 */ 'V', '2', '0', 0,
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/* 8 */ 'V', '3', '0', 0,
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/* 12 */ 'V', '0', 0,
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/* 15 */ 'V', '1', '1', 0,
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/* 19 */ 'V', '2', '1', 0,
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/* 23 */ 'V', '3', '1', 0,
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/* 27 */ 'V', '1', 0,
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/* 30 */ 'V', '1', '2', 0,
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/* 34 */ 'V', '2', '2', 0,
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/* 38 */ 'V', '2', 0,
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/* 41 */ 'V', '1', '3', 0,
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/* 45 */ 'V', '2', '3', 0,
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/* 49 */ 'V', '3', 0,
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/* 52 */ 'V', '1', '4', 0,
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/* 56 */ 'V', '2', '4', 0,
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/* 60 */ 'V', '4', 0,
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/* 63 */ 'V', '1', '5', 0,
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/* 67 */ 'V', '2', '5', 0,
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/* 71 */ 'V', '5', 0,
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/* 74 */ 'V', '1', '6', 0,
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/* 78 */ 'V', '2', '6', 0,
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/* 82 */ 'V', '6', 0,
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/* 85 */ 'V', '1', '7', 0,
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/* 89 */ 'V', '2', '7', 0,
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/* 93 */ 'V', '7', 0,
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/* 96 */ 'V', '1', '8', 0,
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/* 100 */ 'V', '2', '8', 0,
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/* 104 */ 'V', '8', 0,
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/* 107 */ 'V', '1', '9', 0,
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/* 111 */ 'V', '2', '9', 0,
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/* 115 */ 'V', '9', 0,
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/* 118 */ 'C', 'C', 0,
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/* 121 */ 'F', '1', '0', 'D', 0,
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/* 126 */ 'R', '1', '0', 'D', 0,
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/* 131 */ 'F', '2', '0', 'D', 0,
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/* 136 */ 'F', '3', '0', 'D', 0,
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/* 141 */ 'F', '0', 'D', 0,
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/* 145 */ 'R', '0', 'D', 0,
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/* 149 */ 'F', '1', '1', 'D', 0,
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/* 154 */ 'R', '1', '1', 'D', 0,
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/* 159 */ 'F', '2', '1', 'D', 0,
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/* 164 */ 'F', '3', '1', 'D', 0,
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/* 169 */ 'F', '1', 'D', 0,
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/* 173 */ 'R', '1', 'D', 0,
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/* 177 */ 'F', '1', '2', 'D', 0,
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/* 182 */ 'R', '1', '2', 'D', 0,
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/* 187 */ 'F', '2', '2', 'D', 0,
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/* 192 */ 'F', '2', 'D', 0,
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/* 196 */ 'R', '2', 'D', 0,
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/* 200 */ 'F', '1', '3', 'D', 0,
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/* 205 */ 'R', '1', '3', 'D', 0,
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/* 210 */ 'F', '2', '3', 'D', 0,
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/* 215 */ 'F', '3', 'D', 0,
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/* 219 */ 'R', '3', 'D', 0,
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/* 223 */ 'F', '1', '4', 'D', 0,
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/* 228 */ 'R', '1', '4', 'D', 0,
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/* 233 */ 'F', '2', '4', 'D', 0,
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/* 238 */ 'F', '4', 'D', 0,
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/* 242 */ 'R', '4', 'D', 0,
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/* 246 */ 'F', '1', '5', 'D', 0,
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/* 251 */ 'R', '1', '5', 'D', 0,
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/* 256 */ 'F', '2', '5', 'D', 0,
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/* 261 */ 'F', '5', 'D', 0,
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/* 265 */ 'R', '5', 'D', 0,
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/* 269 */ 'F', '1', '6', 'D', 0,
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/* 274 */ 'F', '2', '6', 'D', 0,
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/* 279 */ 'F', '6', 'D', 0,
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/* 283 */ 'R', '6', 'D', 0,
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/* 287 */ 'F', '1', '7', 'D', 0,
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/* 292 */ 'F', '2', '7', 'D', 0,
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/* 297 */ 'F', '7', 'D', 0,
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/* 301 */ 'R', '7', 'D', 0,
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/* 305 */ 'F', '1', '8', 'D', 0,
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/* 310 */ 'F', '2', '8', 'D', 0,
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/* 315 */ 'F', '8', 'D', 0,
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/* 319 */ 'R', '8', 'D', 0,
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/* 323 */ 'F', '1', '9', 'D', 0,
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/* 328 */ 'F', '2', '9', 'D', 0,
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/* 333 */ 'F', '9', 'D', 0,
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/* 337 */ 'R', '9', 'D', 0,
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/* 341 */ 'R', '1', '0', 'H', 0,
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/* 346 */ 'R', '0', 'H', 0,
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/* 350 */ 'R', '1', '1', 'H', 0,
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/* 355 */ 'R', '1', 'H', 0,
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/* 359 */ 'R', '1', '2', 'H', 0,
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/* 364 */ 'R', '2', 'H', 0,
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/* 368 */ 'R', '1', '3', 'H', 0,
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/* 373 */ 'R', '3', 'H', 0,
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/* 377 */ 'R', '1', '4', 'H', 0,
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/* 382 */ 'R', '4', 'H', 0,
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/* 386 */ 'R', '1', '5', 'H', 0,
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/* 391 */ 'R', '5', 'H', 0,
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/* 395 */ 'R', '6', 'H', 0,
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/* 399 */ 'R', '7', 'H', 0,
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/* 403 */ 'R', '8', 'H', 0,
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/* 407 */ 'R', '9', 'H', 0,
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/* 411 */ 'R', '1', '0', 'L', 0,
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/* 416 */ 'R', '0', 'L', 0,
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/* 420 */ 'R', '1', '1', 'L', 0,
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/* 425 */ 'R', '1', 'L', 0,
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/* 429 */ 'R', '1', '2', 'L', 0,
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/* 434 */ 'R', '2', 'L', 0,
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/* 438 */ 'R', '1', '3', 'L', 0,
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/* 443 */ 'R', '3', 'L', 0,
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/* 447 */ 'R', '1', '4', 'L', 0,
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/* 452 */ 'R', '4', 'L', 0,
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/* 456 */ 'R', '1', '5', 'L', 0,
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/* 461 */ 'R', '5', 'L', 0,
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/* 465 */ 'R', '6', 'L', 0,
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/* 469 */ 'R', '7', 'L', 0,
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/* 473 */ 'R', '8', 'L', 0,
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/* 477 */ 'R', '9', 'L', 0,
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/* 481 */ 'R', '1', '0', 'Q', 0,
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/* 486 */ 'F', '0', 'Q', 0,
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/* 490 */ 'R', '0', 'Q', 0,
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/* 494 */ 'F', '1', 'Q', 0,
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/* 498 */ 'F', '1', '2', 'Q', 0,
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/* 503 */ 'R', '1', '2', 'Q', 0,
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/* 508 */ 'R', '2', 'Q', 0,
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/* 512 */ 'F', '1', '3', 'Q', 0,
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/* 517 */ 'R', '1', '4', 'Q', 0,
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/* 522 */ 'F', '4', 'Q', 0,
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/* 526 */ 'R', '4', 'Q', 0,
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/* 530 */ 'F', '5', 'Q', 0,
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/* 534 */ 'R', '6', 'Q', 0,
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/* 538 */ 'F', '8', 'Q', 0,
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/* 542 */ 'R', '8', 'Q', 0,
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/* 546 */ 'F', '9', 'Q', 0,
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/* 550 */ 'F', '1', '0', 'S', 0,
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/* 555 */ 'F', '2', '0', 'S', 0,
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/* 560 */ 'F', '3', '0', 'S', 0,
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/* 565 */ 'F', '0', 'S', 0,
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/* 569 */ 'F', '1', '1', 'S', 0,
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/* 574 */ 'F', '2', '1', 'S', 0,
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/* 579 */ 'F', '3', '1', 'S', 0,
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/* 584 */ 'F', '1', 'S', 0,
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/* 588 */ 'F', '1', '2', 'S', 0,
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/* 593 */ 'F', '2', '2', 'S', 0,
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/* 598 */ 'F', '2', 'S', 0,
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/* 602 */ 'F', '1', '3', 'S', 0,
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/* 607 */ 'F', '2', '3', 'S', 0,
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/* 612 */ 'F', '3', 'S', 0,
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/* 616 */ 'F', '1', '4', 'S', 0,
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/* 621 */ 'F', '2', '4', 'S', 0,
|
|
/* 626 */ 'F', '4', 'S', 0,
|
|
/* 630 */ 'F', '1', '5', 'S', 0,
|
|
/* 635 */ 'F', '2', '5', 'S', 0,
|
|
/* 640 */ 'F', '5', 'S', 0,
|
|
/* 644 */ 'F', '1', '6', 'S', 0,
|
|
/* 649 */ 'F', '2', '6', 'S', 0,
|
|
/* 654 */ 'F', '6', 'S', 0,
|
|
/* 658 */ 'F', '1', '7', 'S', 0,
|
|
/* 663 */ 'F', '2', '7', 'S', 0,
|
|
/* 668 */ 'F', '7', 'S', 0,
|
|
/* 672 */ 'F', '1', '8', 'S', 0,
|
|
/* 677 */ 'F', '2', '8', 'S', 0,
|
|
/* 682 */ 'F', '8', 'S', 0,
|
|
/* 686 */ 'F', '1', '9', 'S', 0,
|
|
/* 691 */ 'F', '2', '9', 'S', 0,
|
|
/* 696 */ 'F', '9', 'S', 0,
|
|
};
|
|
|
|
extern const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
|
|
{ 3, 0, 0, 0, 0, 0 },
|
|
{ 118, 4, 4, 2, 2945, 0 },
|
|
{ 12, 20, 4, 15, 2945, 8 },
|
|
{ 27, 20, 4, 15, 2945, 8 },
|
|
{ 38, 20, 4, 15, 2945, 8 },
|
|
{ 49, 20, 4, 15, 2945, 8 },
|
|
{ 60, 20, 4, 15, 2945, 8 },
|
|
{ 71, 20, 4, 15, 2945, 8 },
|
|
{ 82, 20, 4, 15, 2945, 8 },
|
|
{ 93, 20, 4, 15, 2945, 8 },
|
|
{ 104, 20, 4, 15, 2945, 8 },
|
|
{ 115, 20, 4, 15, 2945, 8 },
|
|
{ 0, 20, 4, 15, 2945, 8 },
|
|
{ 15, 20, 4, 15, 2945, 8 },
|
|
{ 30, 20, 4, 15, 2945, 8 },
|
|
{ 41, 20, 4, 15, 2945, 8 },
|
|
{ 52, 20, 4, 15, 2945, 8 },
|
|
{ 63, 20, 4, 15, 2945, 8 },
|
|
{ 74, 20, 4, 15, 2945, 8 },
|
|
{ 85, 20, 4, 15, 2945, 8 },
|
|
{ 96, 20, 4, 15, 2945, 8 },
|
|
{ 107, 20, 4, 15, 2945, 8 },
|
|
{ 4, 20, 4, 15, 2945, 8 },
|
|
{ 19, 20, 4, 15, 2945, 8 },
|
|
{ 34, 20, 4, 15, 2945, 8 },
|
|
{ 45, 20, 4, 15, 2945, 8 },
|
|
{ 56, 20, 4, 15, 2945, 8 },
|
|
{ 67, 20, 4, 15, 2945, 8 },
|
|
{ 78, 20, 4, 15, 2945, 8 },
|
|
{ 89, 20, 4, 15, 2945, 8 },
|
|
{ 100, 20, 4, 15, 2945, 8 },
|
|
{ 111, 20, 4, 15, 2945, 8 },
|
|
{ 8, 20, 4, 15, 2945, 8 },
|
|
{ 23, 20, 4, 15, 2945, 8 },
|
|
{ 141, 21, 114, 16, 1969, 8 },
|
|
{ 169, 21, 114, 16, 1969, 8 },
|
|
{ 192, 21, 110, 16, 1969, 8 },
|
|
{ 215, 21, 110, 16, 1969, 8 },
|
|
{ 238, 21, 110, 16, 1969, 8 },
|
|
{ 261, 21, 110, 16, 1969, 8 },
|
|
{ 279, 21, 106, 16, 1969, 8 },
|
|
{ 297, 21, 106, 16, 1969, 8 },
|
|
{ 315, 21, 106, 16, 1969, 8 },
|
|
{ 333, 21, 106, 16, 1969, 8 },
|
|
{ 121, 21, 102, 16, 1969, 8 },
|
|
{ 149, 21, 102, 16, 1969, 8 },
|
|
{ 177, 21, 102, 16, 1969, 8 },
|
|
{ 200, 21, 102, 16, 1969, 8 },
|
|
{ 223, 21, 98, 16, 1969, 8 },
|
|
{ 246, 21, 98, 16, 1969, 8 },
|
|
{ 269, 21, 126, 16, 1969, 8 },
|
|
{ 287, 21, 126, 16, 1969, 8 },
|
|
{ 305, 21, 126, 16, 1969, 8 },
|
|
{ 323, 21, 126, 16, 1969, 8 },
|
|
{ 131, 21, 126, 16, 1969, 8 },
|
|
{ 159, 21, 126, 16, 1969, 8 },
|
|
{ 187, 21, 126, 16, 1969, 8 },
|
|
{ 210, 21, 126, 16, 1969, 8 },
|
|
{ 233, 21, 126, 16, 1969, 8 },
|
|
{ 256, 21, 126, 16, 1969, 8 },
|
|
{ 274, 21, 126, 16, 1969, 8 },
|
|
{ 292, 21, 126, 16, 1969, 8 },
|
|
{ 310, 21, 126, 16, 1969, 8 },
|
|
{ 328, 21, 126, 16, 1969, 8 },
|
|
{ 136, 21, 126, 16, 1969, 8 },
|
|
{ 164, 21, 126, 16, 1969, 8 },
|
|
{ 486, 23, 4, 10, 129, 7 },
|
|
{ 494, 23, 4, 10, 129, 7 },
|
|
{ 522, 28, 4, 10, 177, 7 },
|
|
{ 530, 28, 4, 10, 177, 7 },
|
|
{ 538, 33, 4, 10, 225, 7 },
|
|
{ 546, 33, 4, 10, 225, 7 },
|
|
{ 498, 38, 4, 10, 273, 7 },
|
|
{ 512, 38, 4, 10, 273, 7 },
|
|
{ 565, 4, 113, 2, 1937, 0 },
|
|
{ 584, 4, 113, 2, 1937, 0 },
|
|
{ 598, 4, 109, 2, 1937, 0 },
|
|
{ 612, 4, 109, 2, 1937, 0 },
|
|
{ 626, 4, 109, 2, 1937, 0 },
|
|
{ 640, 4, 109, 2, 1937, 0 },
|
|
{ 654, 4, 105, 2, 1937, 0 },
|
|
{ 668, 4, 105, 2, 1937, 0 },
|
|
{ 682, 4, 105, 2, 1937, 0 },
|
|
{ 696, 4, 105, 2, 1937, 0 },
|
|
{ 550, 4, 101, 2, 1937, 0 },
|
|
{ 569, 4, 101, 2, 1937, 0 },
|
|
{ 588, 4, 101, 2, 1937, 0 },
|
|
{ 602, 4, 101, 2, 1937, 0 },
|
|
{ 616, 4, 97, 2, 1937, 0 },
|
|
{ 630, 4, 97, 2, 1937, 0 },
|
|
{ 644, 4, 125, 2, 1937, 0 },
|
|
{ 658, 4, 125, 2, 1937, 0 },
|
|
{ 672, 4, 125, 2, 1937, 0 },
|
|
{ 686, 4, 125, 2, 1937, 0 },
|
|
{ 555, 4, 125, 2, 1937, 0 },
|
|
{ 574, 4, 125, 2, 1937, 0 },
|
|
{ 593, 4, 125, 2, 1937, 0 },
|
|
{ 607, 4, 125, 2, 1937, 0 },
|
|
{ 621, 4, 125, 2, 1937, 0 },
|
|
{ 635, 4, 125, 2, 1937, 0 },
|
|
{ 649, 4, 125, 2, 1937, 0 },
|
|
{ 663, 4, 125, 2, 1937, 0 },
|
|
{ 677, 4, 125, 2, 1937, 0 },
|
|
{ 691, 4, 125, 2, 1937, 0 },
|
|
{ 560, 4, 125, 2, 1937, 0 },
|
|
{ 579, 4, 125, 2, 1937, 0 },
|
|
{ 145, 132, 92, 0, 82, 4 },
|
|
{ 173, 132, 86, 0, 82, 4 },
|
|
{ 196, 132, 86, 0, 82, 4 },
|
|
{ 219, 132, 80, 0, 82, 4 },
|
|
{ 242, 132, 80, 0, 82, 4 },
|
|
{ 265, 132, 74, 0, 82, 4 },
|
|
{ 283, 132, 74, 0, 82, 4 },
|
|
{ 301, 132, 68, 0, 82, 4 },
|
|
{ 319, 132, 68, 0, 82, 4 },
|
|
{ 337, 132, 62, 0, 82, 4 },
|
|
{ 126, 132, 62, 0, 82, 4 },
|
|
{ 154, 132, 56, 0, 82, 4 },
|
|
{ 182, 132, 56, 0, 82, 4 },
|
|
{ 205, 132, 50, 0, 82, 4 },
|
|
{ 228, 132, 50, 0, 82, 4 },
|
|
{ 251, 132, 21, 0, 82, 4 },
|
|
{ 346, 4, 94, 2, 1906, 0 },
|
|
{ 355, 4, 88, 2, 1906, 0 },
|
|
{ 364, 4, 88, 2, 1906, 0 },
|
|
{ 373, 4, 82, 2, 1906, 0 },
|
|
{ 382, 4, 82, 2, 1906, 0 },
|
|
{ 391, 4, 76, 2, 1906, 0 },
|
|
{ 395, 4, 76, 2, 1906, 0 },
|
|
{ 399, 4, 70, 2, 1906, 0 },
|
|
{ 403, 4, 70, 2, 1906, 0 },
|
|
{ 407, 4, 64, 2, 1906, 0 },
|
|
{ 341, 4, 64, 2, 1906, 0 },
|
|
{ 350, 4, 58, 2, 1906, 0 },
|
|
{ 359, 4, 58, 2, 1906, 0 },
|
|
{ 368, 4, 52, 2, 1906, 0 },
|
|
{ 377, 4, 52, 2, 1906, 0 },
|
|
{ 386, 4, 46, 2, 1906, 0 },
|
|
{ 416, 4, 91, 2, 1874, 0 },
|
|
{ 425, 4, 85, 2, 1874, 0 },
|
|
{ 434, 4, 85, 2, 1874, 0 },
|
|
{ 443, 4, 79, 2, 1874, 0 },
|
|
{ 452, 4, 79, 2, 1874, 0 },
|
|
{ 461, 4, 73, 2, 1874, 0 },
|
|
{ 465, 4, 73, 2, 1874, 0 },
|
|
{ 469, 4, 67, 2, 1874, 0 },
|
|
{ 473, 4, 67, 2, 1874, 0 },
|
|
{ 477, 4, 61, 2, 1874, 0 },
|
|
{ 411, 4, 61, 2, 1874, 0 },
|
|
{ 420, 4, 55, 2, 1874, 0 },
|
|
{ 429, 4, 55, 2, 1874, 0 },
|
|
{ 438, 4, 49, 2, 1874, 0 },
|
|
{ 447, 4, 49, 2, 1874, 0 },
|
|
{ 456, 4, 43, 2, 1874, 0 },
|
|
{ 490, 128, 4, 3, 4, 2 },
|
|
{ 508, 135, 4, 3, 4, 2 },
|
|
{ 526, 142, 4, 3, 4, 2 },
|
|
{ 534, 149, 4, 3, 4, 2 },
|
|
{ 542, 156, 4, 3, 4, 2 },
|
|
{ 481, 163, 4, 3, 4, 2 },
|
|
{ 503, 170, 4, 3, 4, 2 },
|
|
{ 517, 177, 4, 3, 4, 2 },
|
|
};
|
|
|
|
extern const MCPhysReg SystemZRegUnitRoots[][2] = {
|
|
{ SystemZ::CC },
|
|
{ SystemZ::F0S },
|
|
{ SystemZ::F1S },
|
|
{ SystemZ::F2S },
|
|
{ SystemZ::F3S },
|
|
{ SystemZ::F4S },
|
|
{ SystemZ::F5S },
|
|
{ SystemZ::F6S },
|
|
{ SystemZ::F7S },
|
|
{ SystemZ::F8S },
|
|
{ SystemZ::F9S },
|
|
{ SystemZ::F10S },
|
|
{ SystemZ::F11S },
|
|
{ SystemZ::F12S },
|
|
{ SystemZ::F13S },
|
|
{ SystemZ::F14S },
|
|
{ SystemZ::F15S },
|
|
{ SystemZ::F16S },
|
|
{ SystemZ::F17S },
|
|
{ SystemZ::F18S },
|
|
{ SystemZ::F19S },
|
|
{ SystemZ::F20S },
|
|
{ SystemZ::F21S },
|
|
{ SystemZ::F22S },
|
|
{ SystemZ::F23S },
|
|
{ SystemZ::F24S },
|
|
{ SystemZ::F25S },
|
|
{ SystemZ::F26S },
|
|
{ SystemZ::F27S },
|
|
{ SystemZ::F28S },
|
|
{ SystemZ::F29S },
|
|
{ SystemZ::F30S },
|
|
{ SystemZ::F31S },
|
|
{ SystemZ::R0L },
|
|
{ SystemZ::R0H },
|
|
{ SystemZ::R1L },
|
|
{ SystemZ::R1H },
|
|
{ SystemZ::R2L },
|
|
{ SystemZ::R2H },
|
|
{ SystemZ::R3L },
|
|
{ SystemZ::R3H },
|
|
{ SystemZ::R4L },
|
|
{ SystemZ::R4H },
|
|
{ SystemZ::R5L },
|
|
{ SystemZ::R5H },
|
|
{ SystemZ::R6L },
|
|
{ SystemZ::R6H },
|
|
{ SystemZ::R7L },
|
|
{ SystemZ::R7H },
|
|
{ SystemZ::R8L },
|
|
{ SystemZ::R8H },
|
|
{ SystemZ::R9L },
|
|
{ SystemZ::R9H },
|
|
{ SystemZ::R10L },
|
|
{ SystemZ::R10H },
|
|
{ SystemZ::R11L },
|
|
{ SystemZ::R11H },
|
|
{ SystemZ::R12L },
|
|
{ SystemZ::R12H },
|
|
{ SystemZ::R13L },
|
|
{ SystemZ::R13H },
|
|
{ SystemZ::R14L },
|
|
{ SystemZ::R14H },
|
|
{ SystemZ::R15L },
|
|
{ SystemZ::R15H },
|
|
};
|
|
|
|
namespace { // Register classes...
|
|
// GRX32Bit Register Class...
|
|
const MCPhysReg GRX32Bit[] = {
|
|
SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15L, SystemZ::R15H, SystemZ::R14L, SystemZ::R14H, SystemZ::R13L, SystemZ::R13H, SystemZ::R12L, SystemZ::R12H, SystemZ::R11L, SystemZ::R11H, SystemZ::R10L, SystemZ::R10H, SystemZ::R9L, SystemZ::R9H, SystemZ::R8L, SystemZ::R8H, SystemZ::R7L, SystemZ::R7H, SystemZ::R6L, SystemZ::R6H,
|
|
};
|
|
|
|
// GRX32Bit Bit set.
|
|
const uint8_t GRX32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// VR32Bit Register Class...
|
|
const MCPhysReg VR32Bit[] = {
|
|
SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
|
|
};
|
|
|
|
// VR32Bit Bit set.
|
|
const uint8_t VR32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// FP32Bit Register Class...
|
|
const MCPhysReg FP32Bit[] = {
|
|
SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
|
|
};
|
|
|
|
// FP32Bit Bit set.
|
|
const uint8_t FP32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
|
};
|
|
|
|
// GR32Bit Register Class...
|
|
const MCPhysReg GR32Bit[] = {
|
|
SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
|
|
};
|
|
|
|
// GR32Bit Bit set.
|
|
const uint8_t GR32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
|
};
|
|
|
|
// GRH32Bit Register Class...
|
|
const MCPhysReg GRH32Bit[] = {
|
|
SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, SystemZ::R4H, SystemZ::R5H, SystemZ::R15H, SystemZ::R14H, SystemZ::R13H, SystemZ::R12H, SystemZ::R11H, SystemZ::R10H, SystemZ::R9H, SystemZ::R8H, SystemZ::R7H, SystemZ::R6H,
|
|
};
|
|
|
|
// GRH32Bit Bit set.
|
|
const uint8_t GRH32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
|
};
|
|
|
|
// ADDR32Bit Register Class...
|
|
const MCPhysReg ADDR32Bit[] = {
|
|
SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R15L, SystemZ::R14L, SystemZ::R13L, SystemZ::R12L, SystemZ::R11L, SystemZ::R10L, SystemZ::R9L, SystemZ::R8L, SystemZ::R7L, SystemZ::R6L,
|
|
};
|
|
|
|
// ADDR32Bit Bit set.
|
|
const uint8_t ADDR32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
|
|
};
|
|
|
|
// CCRegs Register Class...
|
|
const MCPhysReg CCRegs[] = {
|
|
SystemZ::CC,
|
|
};
|
|
|
|
// CCRegs Bit set.
|
|
const uint8_t CCRegsBits[] = {
|
|
0x02,
|
|
};
|
|
|
|
// VR64Bit Register Class...
|
|
const MCPhysReg VR64Bit[] = {
|
|
SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
|
|
};
|
|
|
|
// VR64Bit Bit set.
|
|
const uint8_t VR64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// FP64Bit Register Class...
|
|
const MCPhysReg FP64Bit[] = {
|
|
SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
|
|
};
|
|
|
|
// FP64Bit Bit set.
|
|
const uint8_t FP64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
|
};
|
|
|
|
// GR64Bit Register Class...
|
|
const MCPhysReg GR64Bit[] = {
|
|
SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
|
|
};
|
|
|
|
// GR64Bit Bit set.
|
|
const uint8_t GR64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
|
};
|
|
|
|
// ADDR64Bit Register Class...
|
|
const MCPhysReg ADDR64Bit[] = {
|
|
SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R15D, SystemZ::R14D, SystemZ::R13D, SystemZ::R12D, SystemZ::R11D, SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D, SystemZ::R6D,
|
|
};
|
|
|
|
// ADDR64Bit Bit set.
|
|
const uint8_t ADDR64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
|
|
};
|
|
|
|
// VR128Bit Register Class...
|
|
const MCPhysReg VR128Bit[] = {
|
|
SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
|
|
};
|
|
|
|
// VR128Bit Bit set.
|
|
const uint8_t VR128BitBits[] = {
|
|
0xfc, 0xff, 0xff, 0xff, 0x03,
|
|
};
|
|
|
|
// VF128Bit Register Class...
|
|
const MCPhysReg VF128Bit[] = {
|
|
SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
|
|
};
|
|
|
|
// VF128Bit Bit set.
|
|
const uint8_t VF128BitBits[] = {
|
|
0xfc, 0xff, 0x03,
|
|
};
|
|
|
|
// FP128Bit Register Class...
|
|
const MCPhysReg FP128Bit[] = {
|
|
SystemZ::F0Q, SystemZ::F1Q, SystemZ::F4Q, SystemZ::F5Q, SystemZ::F8Q, SystemZ::F9Q, SystemZ::F12Q, SystemZ::F13Q,
|
|
};
|
|
|
|
// FP128Bit Bit set.
|
|
const uint8_t FP128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
|
};
|
|
|
|
// GR128Bit Register Class...
|
|
const MCPhysReg GR128Bit[] = {
|
|
SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
|
|
};
|
|
|
|
// GR128Bit Bit set.
|
|
const uint8_t GR128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
|
};
|
|
|
|
// ADDR128Bit Register Class...
|
|
const MCPhysReg ADDR128Bit[] = {
|
|
SystemZ::R2Q, SystemZ::R4Q, SystemZ::R12Q, SystemZ::R10Q, SystemZ::R8Q, SystemZ::R6Q, SystemZ::R14Q,
|
|
};
|
|
|
|
// ADDR128Bit Bit set.
|
|
const uint8_t ADDR128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
|
};
|
|
|
|
}
|
|
|
|
extern const char SystemZRegClassStrings[] = {
|
|
/* 0 */ 'C', 'C', 'R', 'e', 'g', 's', 0,
|
|
/* 7 */ 'G', 'R', 'H', '3', '2', 'B', 'i', 't', 0,
|
|
/* 16 */ 'F', 'P', '3', '2', 'B', 'i', 't', 0,
|
|
/* 24 */ 'A', 'D', 'D', 'R', '3', '2', 'B', 'i', 't', 0,
|
|
/* 34 */ 'G', 'R', '3', '2', 'B', 'i', 't', 0,
|
|
/* 42 */ 'V', 'R', '3', '2', 'B', 'i', 't', 0,
|
|
/* 50 */ 'G', 'R', 'X', '3', '2', 'B', 'i', 't', 0,
|
|
/* 59 */ 'F', 'P', '6', '4', 'B', 'i', 't', 0,
|
|
/* 67 */ 'A', 'D', 'D', 'R', '6', '4', 'B', 'i', 't', 0,
|
|
/* 77 */ 'G', 'R', '6', '4', 'B', 'i', 't', 0,
|
|
/* 85 */ 'V', 'R', '6', '4', 'B', 'i', 't', 0,
|
|
/* 93 */ 'V', 'F', '1', '2', '8', 'B', 'i', 't', 0,
|
|
/* 102 */ 'F', 'P', '1', '2', '8', 'B', 'i', 't', 0,
|
|
/* 111 */ 'A', 'D', 'D', 'R', '1', '2', '8', 'B', 'i', 't', 0,
|
|
/* 122 */ 'G', 'R', '1', '2', '8', 'B', 'i', 't', 0,
|
|
/* 131 */ 'V', 'R', '1', '2', '8', 'B', 'i', 't', 0,
|
|
};
|
|
|
|
extern const MCRegisterClass SystemZMCRegisterClasses[] = {
|
|
{ GRX32Bit, GRX32BitBits, 50, 32, sizeof(GRX32BitBits), SystemZ::GRX32BitRegClassID, 4, 4, 1, 1 },
|
|
{ VR32Bit, VR32BitBits, 42, 32, sizeof(VR32BitBits), SystemZ::VR32BitRegClassID, 4, 4, 1, 1 },
|
|
{ FP32Bit, FP32BitBits, 16, 16, sizeof(FP32BitBits), SystemZ::FP32BitRegClassID, 4, 4, 1, 1 },
|
|
{ GR32Bit, GR32BitBits, 34, 16, sizeof(GR32BitBits), SystemZ::GR32BitRegClassID, 4, 4, 1, 1 },
|
|
{ GRH32Bit, GRH32BitBits, 7, 16, sizeof(GRH32BitBits), SystemZ::GRH32BitRegClassID, 4, 4, 1, 1 },
|
|
{ ADDR32Bit, ADDR32BitBits, 24, 15, sizeof(ADDR32BitBits), SystemZ::ADDR32BitRegClassID, 4, 4, 1, 1 },
|
|
{ CCRegs, CCRegsBits, 0, 1, sizeof(CCRegsBits), SystemZ::CCRegsRegClassID, 4, 4, 1, 0 },
|
|
{ VR64Bit, VR64BitBits, 85, 32, sizeof(VR64BitBits), SystemZ::VR64BitRegClassID, 8, 8, 1, 1 },
|
|
{ FP64Bit, FP64BitBits, 59, 16, sizeof(FP64BitBits), SystemZ::FP64BitRegClassID, 8, 8, 1, 1 },
|
|
{ GR64Bit, GR64BitBits, 77, 16, sizeof(GR64BitBits), SystemZ::GR64BitRegClassID, 8, 8, 1, 1 },
|
|
{ ADDR64Bit, ADDR64BitBits, 67, 15, sizeof(ADDR64BitBits), SystemZ::ADDR64BitRegClassID, 8, 8, 1, 1 },
|
|
{ VR128Bit, VR128BitBits, 131, 32, sizeof(VR128BitBits), SystemZ::VR128BitRegClassID, 16, 16, 1, 1 },
|
|
{ VF128Bit, VF128BitBits, 93, 16, sizeof(VF128BitBits), SystemZ::VF128BitRegClassID, 16, 16, 1, 1 },
|
|
{ FP128Bit, FP128BitBits, 102, 8, sizeof(FP128BitBits), SystemZ::FP128BitRegClassID, 16, 16, 1, 1 },
|
|
{ GR128Bit, GR128BitBits, 122, 8, sizeof(GR128BitBits), SystemZ::GR128BitRegClassID, 16, 16, 1, 1 },
|
|
{ ADDR128Bit, ADDR128BitBits, 111, 7, sizeof(ADDR128BitBits), SystemZ::ADDR128BitRegClassID, 16, 16, 1, 1 },
|
|
};
|
|
|
|
// SystemZ Dwarf<->LLVM register mappings.
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0Dwarf2L[] = {
|
|
{ 0U, SystemZ::R0D },
|
|
{ 1U, SystemZ::R1D },
|
|
{ 2U, SystemZ::R2D },
|
|
{ 3U, SystemZ::R3D },
|
|
{ 4U, SystemZ::R4D },
|
|
{ 5U, SystemZ::R5D },
|
|
{ 6U, SystemZ::R6D },
|
|
{ 7U, SystemZ::R7D },
|
|
{ 8U, SystemZ::R8D },
|
|
{ 9U, SystemZ::R9D },
|
|
{ 10U, SystemZ::R10D },
|
|
{ 11U, SystemZ::R11D },
|
|
{ 12U, SystemZ::R12D },
|
|
{ 13U, SystemZ::R13D },
|
|
{ 14U, SystemZ::R14D },
|
|
{ 15U, SystemZ::R15D },
|
|
{ 16U, SystemZ::F0D },
|
|
{ 17U, SystemZ::F2D },
|
|
{ 18U, SystemZ::F4D },
|
|
{ 19U, SystemZ::F6D },
|
|
{ 20U, SystemZ::F1D },
|
|
{ 21U, SystemZ::F3D },
|
|
{ 22U, SystemZ::F5D },
|
|
{ 23U, SystemZ::F7D },
|
|
{ 24U, SystemZ::F8D },
|
|
{ 25U, SystemZ::F10D },
|
|
{ 26U, SystemZ::F12D },
|
|
{ 27U, SystemZ::F14D },
|
|
{ 28U, SystemZ::F9D },
|
|
{ 29U, SystemZ::F11D },
|
|
{ 30U, SystemZ::F13D },
|
|
{ 31U, SystemZ::F15D },
|
|
{ 68U, SystemZ::F16D },
|
|
{ 69U, SystemZ::F18D },
|
|
{ 70U, SystemZ::F20D },
|
|
{ 71U, SystemZ::F22D },
|
|
{ 72U, SystemZ::F17D },
|
|
{ 73U, SystemZ::F19D },
|
|
{ 74U, SystemZ::F21D },
|
|
{ 75U, SystemZ::F23D },
|
|
{ 76U, SystemZ::F24D },
|
|
{ 77U, SystemZ::F26D },
|
|
{ 78U, SystemZ::F28D },
|
|
{ 79U, SystemZ::F30D },
|
|
{ 80U, SystemZ::F25D },
|
|
{ 81U, SystemZ::F27D },
|
|
{ 82U, SystemZ::F29D },
|
|
{ 83U, SystemZ::F31D },
|
|
};
|
|
extern const unsigned SystemZDwarfFlavour0Dwarf2LSize = array_lengthof(SystemZDwarfFlavour0Dwarf2L);
|
|
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0Dwarf2L[] = {
|
|
{ 0U, SystemZ::R0D },
|
|
{ 1U, SystemZ::R1D },
|
|
{ 2U, SystemZ::R2D },
|
|
{ 3U, SystemZ::R3D },
|
|
{ 4U, SystemZ::R4D },
|
|
{ 5U, SystemZ::R5D },
|
|
{ 6U, SystemZ::R6D },
|
|
{ 7U, SystemZ::R7D },
|
|
{ 8U, SystemZ::R8D },
|
|
{ 9U, SystemZ::R9D },
|
|
{ 10U, SystemZ::R10D },
|
|
{ 11U, SystemZ::R11D },
|
|
{ 12U, SystemZ::R12D },
|
|
{ 13U, SystemZ::R13D },
|
|
{ 14U, SystemZ::R14D },
|
|
{ 15U, SystemZ::R15D },
|
|
{ 16U, SystemZ::F0D },
|
|
{ 17U, SystemZ::F2D },
|
|
{ 18U, SystemZ::F4D },
|
|
{ 19U, SystemZ::F6D },
|
|
{ 20U, SystemZ::F1D },
|
|
{ 21U, SystemZ::F3D },
|
|
{ 22U, SystemZ::F5D },
|
|
{ 23U, SystemZ::F7D },
|
|
{ 24U, SystemZ::F8D },
|
|
{ 25U, SystemZ::F10D },
|
|
{ 26U, SystemZ::F12D },
|
|
{ 27U, SystemZ::F14D },
|
|
{ 28U, SystemZ::F9D },
|
|
{ 29U, SystemZ::F11D },
|
|
{ 30U, SystemZ::F13D },
|
|
{ 31U, SystemZ::F15D },
|
|
{ 68U, SystemZ::F16D },
|
|
{ 69U, SystemZ::F18D },
|
|
{ 70U, SystemZ::F20D },
|
|
{ 71U, SystemZ::F22D },
|
|
{ 72U, SystemZ::F17D },
|
|
{ 73U, SystemZ::F19D },
|
|
{ 74U, SystemZ::F21D },
|
|
{ 75U, SystemZ::F23D },
|
|
{ 76U, SystemZ::F24D },
|
|
{ 77U, SystemZ::F26D },
|
|
{ 78U, SystemZ::F28D },
|
|
{ 79U, SystemZ::F30D },
|
|
{ 80U, SystemZ::F25D },
|
|
{ 81U, SystemZ::F27D },
|
|
{ 82U, SystemZ::F29D },
|
|
{ 83U, SystemZ::F31D },
|
|
};
|
|
extern const unsigned SystemZEHFlavour0Dwarf2LSize = array_lengthof(SystemZEHFlavour0Dwarf2L);
|
|
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZDwarfFlavour0L2Dwarf[] = {
|
|
{ SystemZ::V0, 16U },
|
|
{ SystemZ::V1, 20U },
|
|
{ SystemZ::V2, 17U },
|
|
{ SystemZ::V3, 21U },
|
|
{ SystemZ::V4, 18U },
|
|
{ SystemZ::V5, 22U },
|
|
{ SystemZ::V6, 19U },
|
|
{ SystemZ::V7, 23U },
|
|
{ SystemZ::V8, 24U },
|
|
{ SystemZ::V9, 28U },
|
|
{ SystemZ::V10, 25U },
|
|
{ SystemZ::V11, 29U },
|
|
{ SystemZ::V12, 26U },
|
|
{ SystemZ::V13, 30U },
|
|
{ SystemZ::V14, 27U },
|
|
{ SystemZ::V15, 31U },
|
|
{ SystemZ::V16, 68U },
|
|
{ SystemZ::V17, 72U },
|
|
{ SystemZ::V18, 69U },
|
|
{ SystemZ::V19, 73U },
|
|
{ SystemZ::V20, 70U },
|
|
{ SystemZ::V21, 74U },
|
|
{ SystemZ::V22, 71U },
|
|
{ SystemZ::V23, 75U },
|
|
{ SystemZ::V24, 76U },
|
|
{ SystemZ::V25, 80U },
|
|
{ SystemZ::V26, 77U },
|
|
{ SystemZ::V27, 81U },
|
|
{ SystemZ::V28, 78U },
|
|
{ SystemZ::V29, 82U },
|
|
{ SystemZ::V30, 79U },
|
|
{ SystemZ::V31, 83U },
|
|
{ SystemZ::F0D, 16U },
|
|
{ SystemZ::F1D, 20U },
|
|
{ SystemZ::F2D, 17U },
|
|
{ SystemZ::F3D, 21U },
|
|
{ SystemZ::F4D, 18U },
|
|
{ SystemZ::F5D, 22U },
|
|
{ SystemZ::F6D, 19U },
|
|
{ SystemZ::F7D, 23U },
|
|
{ SystemZ::F8D, 24U },
|
|
{ SystemZ::F9D, 28U },
|
|
{ SystemZ::F10D, 25U },
|
|
{ SystemZ::F11D, 29U },
|
|
{ SystemZ::F12D, 26U },
|
|
{ SystemZ::F13D, 30U },
|
|
{ SystemZ::F14D, 27U },
|
|
{ SystemZ::F15D, 31U },
|
|
{ SystemZ::F16D, 68U },
|
|
{ SystemZ::F17D, 72U },
|
|
{ SystemZ::F18D, 69U },
|
|
{ SystemZ::F19D, 73U },
|
|
{ SystemZ::F20D, 70U },
|
|
{ SystemZ::F21D, 74U },
|
|
{ SystemZ::F22D, 71U },
|
|
{ SystemZ::F23D, 75U },
|
|
{ SystemZ::F24D, 76U },
|
|
{ SystemZ::F25D, 80U },
|
|
{ SystemZ::F26D, 77U },
|
|
{ SystemZ::F27D, 81U },
|
|
{ SystemZ::F28D, 78U },
|
|
{ SystemZ::F29D, 82U },
|
|
{ SystemZ::F30D, 79U },
|
|
{ SystemZ::F31D, 83U },
|
|
{ SystemZ::R0D, 0U },
|
|
{ SystemZ::R1D, 1U },
|
|
{ SystemZ::R2D, 2U },
|
|
{ SystemZ::R3D, 3U },
|
|
{ SystemZ::R4D, 4U },
|
|
{ SystemZ::R5D, 5U },
|
|
{ SystemZ::R6D, 6U },
|
|
{ SystemZ::R7D, 7U },
|
|
{ SystemZ::R8D, 8U },
|
|
{ SystemZ::R9D, 9U },
|
|
{ SystemZ::R10D, 10U },
|
|
{ SystemZ::R11D, 11U },
|
|
{ SystemZ::R12D, 12U },
|
|
{ SystemZ::R13D, 13U },
|
|
{ SystemZ::R14D, 14U },
|
|
{ SystemZ::R15D, 15U },
|
|
};
|
|
extern const unsigned SystemZDwarfFlavour0L2DwarfSize = array_lengthof(SystemZDwarfFlavour0L2Dwarf);
|
|
|
|
extern const MCRegisterInfo::DwarfLLVMRegPair SystemZEHFlavour0L2Dwarf[] = {
|
|
{ SystemZ::V0, 16U },
|
|
{ SystemZ::V1, 20U },
|
|
{ SystemZ::V2, 17U },
|
|
{ SystemZ::V3, 21U },
|
|
{ SystemZ::V4, 18U },
|
|
{ SystemZ::V5, 22U },
|
|
{ SystemZ::V6, 19U },
|
|
{ SystemZ::V7, 23U },
|
|
{ SystemZ::V8, 24U },
|
|
{ SystemZ::V9, 28U },
|
|
{ SystemZ::V10, 25U },
|
|
{ SystemZ::V11, 29U },
|
|
{ SystemZ::V12, 26U },
|
|
{ SystemZ::V13, 30U },
|
|
{ SystemZ::V14, 27U },
|
|
{ SystemZ::V15, 31U },
|
|
{ SystemZ::V16, 68U },
|
|
{ SystemZ::V17, 72U },
|
|
{ SystemZ::V18, 69U },
|
|
{ SystemZ::V19, 73U },
|
|
{ SystemZ::V20, 70U },
|
|
{ SystemZ::V21, 74U },
|
|
{ SystemZ::V22, 71U },
|
|
{ SystemZ::V23, 75U },
|
|
{ SystemZ::V24, 76U },
|
|
{ SystemZ::V25, 80U },
|
|
{ SystemZ::V26, 77U },
|
|
{ SystemZ::V27, 81U },
|
|
{ SystemZ::V28, 78U },
|
|
{ SystemZ::V29, 82U },
|
|
{ SystemZ::V30, 79U },
|
|
{ SystemZ::V31, 83U },
|
|
{ SystemZ::F0D, 16U },
|
|
{ SystemZ::F1D, 20U },
|
|
{ SystemZ::F2D, 17U },
|
|
{ SystemZ::F3D, 21U },
|
|
{ SystemZ::F4D, 18U },
|
|
{ SystemZ::F5D, 22U },
|
|
{ SystemZ::F6D, 19U },
|
|
{ SystemZ::F7D, 23U },
|
|
{ SystemZ::F8D, 24U },
|
|
{ SystemZ::F9D, 28U },
|
|
{ SystemZ::F10D, 25U },
|
|
{ SystemZ::F11D, 29U },
|
|
{ SystemZ::F12D, 26U },
|
|
{ SystemZ::F13D, 30U },
|
|
{ SystemZ::F14D, 27U },
|
|
{ SystemZ::F15D, 31U },
|
|
{ SystemZ::F16D, 68U },
|
|
{ SystemZ::F17D, 72U },
|
|
{ SystemZ::F18D, 69U },
|
|
{ SystemZ::F19D, 73U },
|
|
{ SystemZ::F20D, 70U },
|
|
{ SystemZ::F21D, 74U },
|
|
{ SystemZ::F22D, 71U },
|
|
{ SystemZ::F23D, 75U },
|
|
{ SystemZ::F24D, 76U },
|
|
{ SystemZ::F25D, 80U },
|
|
{ SystemZ::F26D, 77U },
|
|
{ SystemZ::F27D, 81U },
|
|
{ SystemZ::F28D, 78U },
|
|
{ SystemZ::F29D, 82U },
|
|
{ SystemZ::F30D, 79U },
|
|
{ SystemZ::F31D, 83U },
|
|
{ SystemZ::R0D, 0U },
|
|
{ SystemZ::R1D, 1U },
|
|
{ SystemZ::R2D, 2U },
|
|
{ SystemZ::R3D, 3U },
|
|
{ SystemZ::R4D, 4U },
|
|
{ SystemZ::R5D, 5U },
|
|
{ SystemZ::R6D, 6U },
|
|
{ SystemZ::R7D, 7U },
|
|
{ SystemZ::R8D, 8U },
|
|
{ SystemZ::R9D, 9U },
|
|
{ SystemZ::R10D, 10U },
|
|
{ SystemZ::R11D, 11U },
|
|
{ SystemZ::R12D, 12U },
|
|
{ SystemZ::R13D, 13U },
|
|
{ SystemZ::R14D, 14U },
|
|
{ SystemZ::R15D, 15U },
|
|
};
|
|
extern const unsigned SystemZEHFlavour0L2DwarfSize = array_lengthof(SystemZEHFlavour0L2Dwarf);
|
|
|
|
extern const uint16_t SystemZRegEncodingTable[] = {
|
|
0,
|
|
0,
|
|
0,
|
|
1,
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0,
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0,
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12,
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0,
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0,
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1,
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10,
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11,
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12,
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15,
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0,
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1,
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2,
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3,
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4,
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5,
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10,
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11,
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12,
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14,
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15,
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0,
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1,
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2,
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3,
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4,
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5,
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6,
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10,
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11,
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12,
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13,
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14,
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15,
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0,
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2,
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4,
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6,
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8,
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10,
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12,
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14,
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};
|
|
static inline void InitSystemZMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
|
|
RI->InitMCRegisterInfo(SystemZRegDesc, 162, RA, PC, SystemZMCRegisterClasses, 16, SystemZRegUnitRoots, 65, SystemZRegDiffLists, SystemZLaneMaskLists, SystemZRegStrings, SystemZRegClassStrings, SystemZSubRegIdxLists, 10,
|
|
SystemZSubRegIdxRanges, SystemZRegEncodingTable);
|
|
|
|
switch (DwarfFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapDwarfRegsToLLVMRegs(SystemZDwarfFlavour0Dwarf2L, SystemZDwarfFlavour0Dwarf2LSize, false);
|
|
break;
|
|
}
|
|
switch (EHFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapDwarfRegsToLLVMRegs(SystemZEHFlavour0Dwarf2L, SystemZEHFlavour0Dwarf2LSize, true);
|
|
break;
|
|
}
|
|
switch (DwarfFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapLLVMRegsToDwarfRegs(SystemZDwarfFlavour0L2Dwarf, SystemZDwarfFlavour0L2DwarfSize, false);
|
|
break;
|
|
}
|
|
switch (EHFlavour) {
|
|
default:
|
|
llvm_unreachable("Unknown DWARF flavour");
|
|
case 0:
|
|
RI->mapLLVMRegsToDwarfRegs(SystemZEHFlavour0L2Dwarf, SystemZEHFlavour0L2DwarfSize, true);
|
|
break;
|
|
}
|
|
}
|
|
|
|
} // End llvm namespace
|
|
#endif // GET_REGINFO_MC_DESC
|