

###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-reg-tables.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL
########################################################################
## file: xed-reg-tables.txt
########################################################################

# Need to handle flags, rIP, seg-selectors, pseudo regs
# Also does not specify register width

# What about something like this:
#     op1=GPRv_R():rw
# we need to know what to bind the result to ultimately.
# Just specifying a register is confusing to me. Don't know where to store it.
# Have a "store-here" location for this kind of thing?

#######################################################################
# Expand the generic registers using the effective address size EASZ
#######################################################################
xed_reg_enum_t ArAX()::
EASZ=1 | OUTREG=XED_REG_AX
EASZ=2 | OUTREG=XED_REG_EAX
EASZ=3 | OUTREG=XED_REG_RAX
xed_reg_enum_t ArBX()::
EASZ=1 | OUTREG=XED_REG_BX
EASZ=2 | OUTREG=XED_REG_EBX
EASZ=3 | OUTREG=XED_REG_RBX
xed_reg_enum_t ArCX()::
EASZ=1 | OUTREG=XED_REG_CX
EASZ=2 | OUTREG=XED_REG_ECX
EASZ=3 | OUTREG=XED_REG_RCX
xed_reg_enum_t ArDX()::
EASZ=1 | OUTREG=XED_REG_DX
EASZ=2 | OUTREG=XED_REG_EDX
EASZ=3 | OUTREG=XED_REG_RDX

xed_reg_enum_t ArSI()::
EASZ=1 | OUTREG=XED_REG_SI
EASZ=2 | OUTREG=XED_REG_ESI
EASZ=3 | OUTREG=XED_REG_RSI
xed_reg_enum_t ArDI()::
EASZ=1 | OUTREG=XED_REG_DI
EASZ=2 | OUTREG=XED_REG_EDI
EASZ=3 | OUTREG=XED_REG_RDI
xed_reg_enum_t ArSP()::
EASZ=1 | OUTREG=XED_REG_SP
EASZ=2 | OUTREG=XED_REG_ESP
EASZ=3 | OUTREG=XED_REG_RSP
xed_reg_enum_t ArBP()::
EASZ=1 | OUTREG=XED_REG_BP
EASZ=2 | OUTREG=XED_REG_EBP
EASZ=3 | OUTREG=XED_REG_RBP

xed_reg_enum_t SrSP()::
smode16 | OUTREG=XED_REG_SP
smode32 | OUTREG=XED_REG_ESP
smode64 | OUTREG=XED_REG_RSP
xed_reg_enum_t SrBP()::
smode16 | OUTREG=XED_REG_BP
smode32 | OUTREG=XED_REG_EBP
smode64 | OUTREG=XED_REG_RBP

xed_reg_enum_t Ar8()::
EASZ=1 | OUTREG=XED_REG_R8W
EASZ=2 | OUTREG=XED_REG_R8D
EASZ=3 | OUTREG=XED_REG_R8
xed_reg_enum_t Ar9()::
EASZ=1 | OUTREG=XED_REG_R9W
EASZ=2 | OUTREG=XED_REG_R9D
EASZ=3 | OUTREG=XED_REG_R9
xed_reg_enum_t Ar10()::
EASZ=1 | OUTREG=XED_REG_R10W
EASZ=2 | OUTREG=XED_REG_R10D
EASZ=3 | OUTREG=XED_REG_R10
xed_reg_enum_t Ar11()::
EASZ=1 | OUTREG=XED_REG_R11W
EASZ=2 | OUTREG=XED_REG_R11D
EASZ=3 | OUTREG=XED_REG_R11
xed_reg_enum_t Ar12()::
EASZ=1 | OUTREG=XED_REG_R12W
EASZ=2 | OUTREG=XED_REG_R12D
EASZ=3 | OUTREG=XED_REG_R12
xed_reg_enum_t Ar13()::
EASZ=1 | OUTREG=XED_REG_R13W
EASZ=2 | OUTREG=XED_REG_R13D
EASZ=3 | OUTREG=XED_REG_R13
xed_reg_enum_t Ar14()::
EASZ=1 | OUTREG=XED_REG_R14W
EASZ=2 | OUTREG=XED_REG_R14D
EASZ=3 | OUTREG=XED_REG_R14
xed_reg_enum_t Ar15()::
EASZ=1 | OUTREG=XED_REG_R15W
EASZ=2 | OUTREG=XED_REG_R15D
EASZ=3 | OUTREG=XED_REG_R15

xed_reg_enum_t rIP()::
mode16 | OUTREG=XED_REG_EIP
mode32 | OUTREG=XED_REG_EIP
mode64 | OUTREG=XED_REG_RIP

xed_reg_enum_t rIPa()::
EASZ=2 | OUTREG=XED_REG_EIP
EASZ=3 | OUTREG=XED_REG_RIP

#######################################################################
# Expand the generic registers using the effective address size EOSZ - limit 32b
#######################################################################


xed_reg_enum_t OeAX()::
EOSZ=1 | OUTREG=XED_REG_AX
EOSZ=2 | OUTREG=XED_REG_EAX
EOSZ=3 | OUTREG=XED_REG_EAX


#######################################################################
# Expand the generic registers using the effective address size EOSZ - limit 64b
#######################################################################

xed_reg_enum_t OrAX()::
EOSZ=1 | OUTREG=XED_REG_AX
EOSZ=2 | OUTREG=XED_REG_EAX
EOSZ=3 | OUTREG=XED_REG_RAX
xed_reg_enum_t OrDX()::
EOSZ=1 | OUTREG=XED_REG_DX
EOSZ=2 | OUTREG=XED_REG_EDX
EOSZ=3 | OUTREG=XED_REG_RDX

# only used for VIA PADLOCK ISA:
xed_reg_enum_t OrCX()::
EOSZ=1 | OUTREG=XED_REG_CX
EOSZ=2 | OUTREG=XED_REG_ECX
EOSZ=3 | OUTREG=XED_REG_RCX
# only used for VIA PADLOCK ISA:
xed_reg_enum_t OrBX()::
EOSZ=1 | OUTREG=XED_REG_BX
EOSZ=2 | OUTREG=XED_REG_EBX
EOSZ=3 | OUTREG=XED_REG_RBX

xed_reg_enum_t OrSP()::
EOSZ=1 | OUTREG=XED_REG_SP
EOSZ=2 | OUTREG=XED_REG_ESP
EOSZ=3 | OUTREG=XED_REG_RSP
xed_reg_enum_t OrBP()::
EOSZ=1 | OUTREG=XED_REG_BP
EOSZ=2 | OUTREG=XED_REG_EBP
EOSZ=3 | OUTREG=XED_REG_RBP


#####################################################

xed_reg_enum_t rFLAGS()::
mode16 | OUTREG=XED_REG_FLAGS
mode32 | OUTREG=XED_REG_EFLAGS
mode64 | OUTREG=XED_REG_RFLAGS

#####################################################


xed_reg_enum_t MMX_R()::
REG=0x0  | OUTREG=XED_REG_MMX0
REG=0x1  | OUTREG=XED_REG_MMX1
REG=0x2  | OUTREG=XED_REG_MMX2
REG=0x3  | OUTREG=XED_REG_MMX3
REG=0x4  | OUTREG=XED_REG_MMX4
REG=0x5  | OUTREG=XED_REG_MMX5
REG=0x6  | OUTREG=XED_REG_MMX6
REG=0x7  | OUTREG=XED_REG_MMX7

xed_reg_enum_t MMX_B()::
RM=0x0  | OUTREG=XED_REG_MMX0
RM=0x1  | OUTREG=XED_REG_MMX1
RM=0x2  | OUTREG=XED_REG_MMX2
RM=0x3  | OUTREG=XED_REG_MMX3
RM=0x4  | OUTREG=XED_REG_MMX4
RM=0x5  | OUTREG=XED_REG_MMX5
RM=0x6  | OUTREG=XED_REG_MMX6
RM=0x7  | OUTREG=XED_REG_MMX7

#################################

# Things that scale with effective operand size



# When used as the MODRM.REG register
xed_reg_enum_t GPRv_R()::
EOSZ=3 | OUTREG=GPR64_R()
EOSZ=2 | OUTREG=GPR32_R()
EOSZ=1 | OUTREG=GPR16_R()

xed_reg_enum_t GPRv_SB()::
EOSZ=3 | OUTREG=GPR64_SB()
EOSZ=2 | OUTREG=GPR32_SB()
EOSZ=1 | OUTREG=GPR16_SB()

xed_reg_enum_t GPRz_R()::
EOSZ=3 | OUTREG=GPR32_R()
EOSZ=2 | OUTREG=GPR32_R()
EOSZ=1 | OUTREG=GPR16_R()

# When used as the MOD=11/RM register
xed_reg_enum_t GPRv_B()::
EOSZ=3 | OUTREG=GPR64_B()
EOSZ=2 | OUTREG=GPR32_B()
EOSZ=1 | OUTREG=GPR16_B()

xed_reg_enum_t GPRz_B()::
EOSZ=3 | OUTREG=GPR32_B()
EOSZ=2 | OUTREG=GPR32_B()
EOSZ=1 | OUTREG=GPR16_B()

xed_reg_enum_t GPRy_B()::
EOSZ=3 | OUTREG=GPR64_B()
EOSZ=2 | OUTREG=GPR32_B()
EOSZ=1 | OUTREG=GPR32_B()

xed_reg_enum_t GPRy_R()::
EOSZ=3 | OUTREG=GPR64_R()
EOSZ=2 | OUTREG=GPR32_R()
EOSZ=1 | OUTREG=GPR32_R()

#####################################

xed_reg_enum_t GPR64_R()::
REXR=0 REG=0x0  | OUTREG=XED_REG_RAX
REXR=0 REG=0x1  | OUTREG=XED_REG_RCX
REXR=0 REG=0x2  | OUTREG=XED_REG_RDX
REXR=0 REG=0x3  | OUTREG=XED_REG_RBX
REXR=0 REG=0x4  | OUTREG=XED_REG_RSP
REXR=0 REG=0x5  | OUTREG=XED_REG_RBP
REXR=0 REG=0x6  | OUTREG=XED_REG_RSI
REXR=0 REG=0x7  | OUTREG=XED_REG_RDI
REXR=1 REG=0x0  | OUTREG=XED_REG_R8
REXR=1 REG=0x1  | OUTREG=XED_REG_R9
REXR=1 REG=0x2  | OUTREG=XED_REG_R10
REXR=1 REG=0x3  | OUTREG=XED_REG_R11
REXR=1 REG=0x4  | OUTREG=XED_REG_R12
REXR=1 REG=0x5  | OUTREG=XED_REG_R13
REXR=1 REG=0x6  | OUTREG=XED_REG_R14
REXR=1 REG=0x7  | OUTREG=XED_REG_R15


xed_reg_enum_t GPR64_B()::
REXB=0 RM=0x0  | OUTREG=XED_REG_RAX
REXB=0 RM=0x1  | OUTREG=XED_REG_RCX
REXB=0 RM=0x2  | OUTREG=XED_REG_RDX
REXB=0 RM=0x3  | OUTREG=XED_REG_RBX
REXB=0 RM=0x4  | OUTREG=XED_REG_RSP
REXB=0 RM=0x5  | OUTREG=XED_REG_RBP
REXB=0 RM=0x6  | OUTREG=XED_REG_RSI
REXB=0 RM=0x7  | OUTREG=XED_REG_RDI
REXB=1 RM=0x0  | OUTREG=XED_REG_R8
REXB=1 RM=0x1  | OUTREG=XED_REG_R9
REXB=1 RM=0x2  | OUTREG=XED_REG_R10
REXB=1 RM=0x3  | OUTREG=XED_REG_R11
REXB=1 RM=0x4  | OUTREG=XED_REG_R12
REXB=1 RM=0x5  | OUTREG=XED_REG_R13
REXB=1 RM=0x6  | OUTREG=XED_REG_R14
REXB=1 RM=0x7  | OUTREG=XED_REG_R15

xed_reg_enum_t GPR64_SB()::
REXB=0 SRM=0x0  | OUTREG=XED_REG_RAX
REXB=0 SRM=0x1  | OUTREG=XED_REG_RCX
REXB=0 SRM=0x2  | OUTREG=XED_REG_RDX
REXB=0 SRM=0x3  | OUTREG=XED_REG_RBX
REXB=0 SRM=0x4  | OUTREG=XED_REG_RSP
REXB=0 SRM=0x5  | OUTREG=XED_REG_RBP
REXB=0 SRM=0x6  | OUTREG=XED_REG_RSI
REXB=0 SRM=0x7  | OUTREG=XED_REG_RDI
REXB=1 SRM=0x0  | OUTREG=XED_REG_R8
REXB=1 SRM=0x1  | OUTREG=XED_REG_R9
REXB=1 SRM=0x2  | OUTREG=XED_REG_R10
REXB=1 SRM=0x3  | OUTREG=XED_REG_R11
REXB=1 SRM=0x4  | OUTREG=XED_REG_R12
REXB=1 SRM=0x5  | OUTREG=XED_REG_R13
REXB=1 SRM=0x6  | OUTREG=XED_REG_R14
REXB=1 SRM=0x7  | OUTREG=XED_REG_R15



xed_reg_enum_t GPR64_X()::
REXX=0 SIBINDEX=0x0  | OUTREG=XED_REG_RAX
REXX=0 SIBINDEX=0x1  | OUTREG=XED_REG_RCX
REXX=0 SIBINDEX=0x2  | OUTREG=XED_REG_RDX
REXX=0 SIBINDEX=0x3  | OUTREG=XED_REG_RBX
REXX=0 SIBINDEX=0x4  | OUTREG=XED_REG_INVALID
REXX=0 SIBINDEX=0x5  | OUTREG=XED_REG_RBP
REXX=0 SIBINDEX=0x6  | OUTREG=XED_REG_RSI
REXX=0 SIBINDEX=0x7  | OUTREG=XED_REG_RDI
REXX=1 SIBINDEX=0x0  | OUTREG=XED_REG_R8
REXX=1 SIBINDEX=0x1  | OUTREG=XED_REG_R9
REXX=1 SIBINDEX=0x2  | OUTREG=XED_REG_R10
REXX=1 SIBINDEX=0x3  | OUTREG=XED_REG_R11
REXX=1 SIBINDEX=0x4  | OUTREG=XED_REG_R12
REXX=1 SIBINDEX=0x5  | OUTREG=XED_REG_R13
REXX=1 SIBINDEX=0x6  | OUTREG=XED_REG_R14
REXX=1 SIBINDEX=0x7  | OUTREG=XED_REG_R15


#################################


xed_reg_enum_t GPR32_R()::
REXR=0 REG=0x0  | OUTREG=XED_REG_EAX
REXR=0 REG=0x1  | OUTREG=XED_REG_ECX
REXR=0 REG=0x2  | OUTREG=XED_REG_EDX
REXR=0 REG=0x3  | OUTREG=XED_REG_EBX
REXR=0 REG=0x4  | OUTREG=XED_REG_ESP
REXR=0 REG=0x5  | OUTREG=XED_REG_EBP
REXR=0 REG=0x6  | OUTREG=XED_REG_ESI
REXR=0 REG=0x7  | OUTREG=XED_REG_EDI
REXR=1 REG=0x0  | OUTREG=XED_REG_R8D
REXR=1 REG=0x1  | OUTREG=XED_REG_R9D
REXR=1 REG=0x2  | OUTREG=XED_REG_R10D
REXR=1 REG=0x3  | OUTREG=XED_REG_R11D
REXR=1 REG=0x4  | OUTREG=XED_REG_R12D
REXR=1 REG=0x5  | OUTREG=XED_REG_R13D
REXR=1 REG=0x6  | OUTREG=XED_REG_R14D
REXR=1 REG=0x7  | OUTREG=XED_REG_R15D

xed_reg_enum_t GPR32_B()::
REXB=0 RM=0x0  | OUTREG=XED_REG_EAX
REXB=0 RM=0x1  | OUTREG=XED_REG_ECX
REXB=0 RM=0x2  | OUTREG=XED_REG_EDX
REXB=0 RM=0x3  | OUTREG=XED_REG_EBX
REXB=0 RM=0x4  | OUTREG=XED_REG_ESP
REXB=0 RM=0x5  | OUTREG=XED_REG_EBP
REXB=0 RM=0x6  | OUTREG=XED_REG_ESI
REXB=0 RM=0x7  | OUTREG=XED_REG_EDI
REXB=1 RM=0x0  | OUTREG=XED_REG_R8D
REXB=1 RM=0x1  | OUTREG=XED_REG_R9D
REXB=1 RM=0x2  | OUTREG=XED_REG_R10D
REXB=1 RM=0x3  | OUTREG=XED_REG_R11D
REXB=1 RM=0x4  | OUTREG=XED_REG_R12D
REXB=1 RM=0x5  | OUTREG=XED_REG_R13D
REXB=1 RM=0x6  | OUTREG=XED_REG_R14D
REXB=1 RM=0x7  | OUTREG=XED_REG_R15D

xed_reg_enum_t GPR32_SB()::
REXB=0 SRM=0x0  | OUTREG=XED_REG_EAX
REXB=0 SRM=0x1  | OUTREG=XED_REG_ECX
REXB=0 SRM=0x2  | OUTREG=XED_REG_EDX
REXB=0 SRM=0x3  | OUTREG=XED_REG_EBX
REXB=0 SRM=0x4  | OUTREG=XED_REG_ESP
REXB=0 SRM=0x5  | OUTREG=XED_REG_EBP
REXB=0 SRM=0x6  | OUTREG=XED_REG_ESI
REXB=0 SRM=0x7  | OUTREG=XED_REG_EDI
REXB=1 SRM=0x0  | OUTREG=XED_REG_R8D
REXB=1 SRM=0x1  | OUTREG=XED_REG_R9D
REXB=1 SRM=0x2  | OUTREG=XED_REG_R10D
REXB=1 SRM=0x3  | OUTREG=XED_REG_R11D
REXB=1 SRM=0x4  | OUTREG=XED_REG_R12D
REXB=1 SRM=0x5  | OUTREG=XED_REG_R13D
REXB=1 SRM=0x6  | OUTREG=XED_REG_R14D
REXB=1 SRM=0x7  | OUTREG=XED_REG_R15D





xed_reg_enum_t GPR32_X()::
REXX=0 SIBINDEX=0x0  | OUTREG=XED_REG_EAX
REXX=0 SIBINDEX=0x1  | OUTREG=XED_REG_ECX
REXX=0 SIBINDEX=0x2  | OUTREG=XED_REG_EDX
REXX=0 SIBINDEX=0x3  | OUTREG=XED_REG_EBX
REXX=0 SIBINDEX=0x4  | OUTREG=XED_REG_INVALID
REXX=0 SIBINDEX=0x5  | OUTREG=XED_REG_EBP
REXX=0 SIBINDEX=0x6  | OUTREG=XED_REG_ESI
REXX=0 SIBINDEX=0x7  | OUTREG=XED_REG_EDI
REXX=1 SIBINDEX=0x0  | OUTREG=XED_REG_R8D
REXX=1 SIBINDEX=0x1  | OUTREG=XED_REG_R9D
REXX=1 SIBINDEX=0x2  | OUTREG=XED_REG_R10D
REXX=1 SIBINDEX=0x3  | OUTREG=XED_REG_R11D
REXX=1 SIBINDEX=0x4  | OUTREG=XED_REG_R12D
REXX=1 SIBINDEX=0x5  | OUTREG=XED_REG_R13D
REXX=1 SIBINDEX=0x6  | OUTREG=XED_REG_R14D
REXX=1 SIBINDEX=0x7  | OUTREG=XED_REG_R15D


#############################


xed_reg_enum_t GPR16_R()::
REXR=0 REG=0x0  | OUTREG=XED_REG_AX
REXR=0 REG=0x1  | OUTREG=XED_REG_CX
REXR=0 REG=0x2  | OUTREG=XED_REG_DX
REXR=0 REG=0x3  | OUTREG=XED_REG_BX
REXR=0 REG=0x4  | OUTREG=XED_REG_SP
REXR=0 REG=0x5  | OUTREG=XED_REG_BP
REXR=0 REG=0x6  | OUTREG=XED_REG_SI
REXR=0 REG=0x7  | OUTREG=XED_REG_DI
REXR=1 REG=0x0  | OUTREG=XED_REG_R8W
REXR=1 REG=0x1  | OUTREG=XED_REG_R9W
REXR=1 REG=0x2  | OUTREG=XED_REG_R10W
REXR=1 REG=0x3  | OUTREG=XED_REG_R11W
REXR=1 REG=0x4  | OUTREG=XED_REG_R12W
REXR=1 REG=0x5  | OUTREG=XED_REG_R13W
REXR=1 REG=0x6  | OUTREG=XED_REG_R14W
REXR=1 REG=0x7  | OUTREG=XED_REG_R15W



xed_reg_enum_t GPR16_B()::
REXB=0 RM=0x0  | OUTREG=XED_REG_AX
REXB=0 RM=0x1  | OUTREG=XED_REG_CX
REXB=0 RM=0x2  | OUTREG=XED_REG_DX
REXB=0 RM=0x3  | OUTREG=XED_REG_BX
REXB=0 RM=0x4  | OUTREG=XED_REG_SP
REXB=0 RM=0x5  | OUTREG=XED_REG_BP
REXB=0 RM=0x6  | OUTREG=XED_REG_SI
REXB=0 RM=0x7  | OUTREG=XED_REG_DI
REXB=1 RM=0x0  | OUTREG=XED_REG_R8W
REXB=1 RM=0x1  | OUTREG=XED_REG_R9W
REXB=1 RM=0x2  | OUTREG=XED_REG_R10W
REXB=1 RM=0x3  | OUTREG=XED_REG_R11W
REXB=1 RM=0x4  | OUTREG=XED_REG_R12W
REXB=1 RM=0x5  | OUTREG=XED_REG_R13W
REXB=1 RM=0x6  | OUTREG=XED_REG_R14W
REXB=1 RM=0x7  | OUTREG=XED_REG_R15W

xed_reg_enum_t GPR16_SB()::
REXB=0 SRM=0x0  | OUTREG=XED_REG_AX
REXB=0 SRM=0x1  | OUTREG=XED_REG_CX
REXB=0 SRM=0x2  | OUTREG=XED_REG_DX
REXB=0 SRM=0x3  | OUTREG=XED_REG_BX
REXB=0 SRM=0x4  | OUTREG=XED_REG_SP
REXB=0 SRM=0x5  | OUTREG=XED_REG_BP
REXB=0 SRM=0x6  | OUTREG=XED_REG_SI
REXB=0 SRM=0x7  | OUTREG=XED_REG_DI
REXB=1 SRM=0x0  | OUTREG=XED_REG_R8W
REXB=1 SRM=0x1  | OUTREG=XED_REG_R9W
REXB=1 SRM=0x2  | OUTREG=XED_REG_R10W
REXB=1 SRM=0x3  | OUTREG=XED_REG_R11W
REXB=1 SRM=0x4  | OUTREG=XED_REG_R12W
REXB=1 SRM=0x5  | OUTREG=XED_REG_R13W
REXB=1 SRM=0x6  | OUTREG=XED_REG_R14W
REXB=1 SRM=0x7  | OUTREG=XED_REG_R15W



#############################

# GPR8_R and GPR8_B are handled in separate files -- grep for them.

###########################a

xed_reg_enum_t CR_R()::
REXR=0 REG=0x0  | OUTREG=XED_REG_CR0
REXR=0 REG=0x1  | OUTREG=XED_REG_ERROR  enc
REXR=0 REG=0x2  | OUTREG=XED_REG_CR2
REXR=0 REG=0x3  | OUTREG=XED_REG_CR3
REXR=0 REG=0x4  | OUTREG=XED_REG_CR4
REXR=0 REG=0x5  | OUTREG=XED_REG_ERROR
REXR=0 REG=0x6  | OUTREG=XED_REG_ERROR
REXR=0 REG=0x7  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x0  | OUTREG=XED_REG_CR8
REXR=1 REG=0x1  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x2  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x3  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x4  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x5  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x6  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x7  | OUTREG=XED_REG_ERROR

# FIXME: not used
xed_reg_enum_t CR_B()::
REXB=0 RM=0x0  | OUTREG=XED_REG_CR0
REXB=0 RM=0x1  | OUTREG=XED_REG_ERROR   enc
REXB=0 RM=0x2  | OUTREG=XED_REG_CR2
REXB=0 RM=0x3  | OUTREG=XED_REG_CR3
REXB=0 RM=0x4  | OUTREG=XED_REG_CR4
REXB=0 RM=0x5  | OUTREG=XED_REG_ERROR
REXB=0 RM=0x6  | OUTREG=XED_REG_ERROR
REXB=0 RM=0x7  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x0  | OUTREG=XED_REG_CR8
REXB=1 RM=0x1  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x2  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x3  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x4  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x5  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x6  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x7  | OUTREG=XED_REG_ERROR

########################

xed_reg_enum_t DR_R()::
REXR=0 REG=0x0  | OUTREG=XED_REG_DR0
REXR=0 REG=0x1  | OUTREG=XED_REG_DR1
REXR=0 REG=0x2  | OUTREG=XED_REG_DR2
REXR=0 REG=0x3  | OUTREG=XED_REG_DR3
REXR=0 REG=0x4  | OUTREG=XED_REG_DR4
REXR=0 REG=0x5  | OUTREG=XED_REG_DR5
REXR=0 REG=0x6  | OUTREG=XED_REG_DR6
REXR=0 REG=0x7  | OUTREG=XED_REG_DR7
REXR=1 REG=0x0  | OUTREG=XED_REG_ERROR enc
REXR=1 REG=0x1  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x2  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x3  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x4  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x5  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x6  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x7  | OUTREG=XED_REG_ERROR

#######################


xed_reg_enum_t X87()::
RM=0x0  | OUTREG=XED_REG_ST0
RM=0x1  | OUTREG=XED_REG_ST1
RM=0x2  | OUTREG=XED_REG_ST2
RM=0x3  | OUTREG=XED_REG_ST3
RM=0x4  | OUTREG=XED_REG_ST4
RM=0x5  | OUTREG=XED_REG_ST5
RM=0x6  | OUTREG=XED_REG_ST6
RM=0x7  | OUTREG=XED_REG_ST7

###################

xed_reg_enum_t SEG()::
REG=0x0  | OUTREG=XED_REG_ES
REG=0x1  | OUTREG=XED_REG_CS
REG=0x2  | OUTREG=XED_REG_SS
REG=0x3  | OUTREG=XED_REG_DS
REG=0x4  | OUTREG=XED_REG_FS
REG=0x5  | OUTREG=XED_REG_GS
REG=0x6  | OUTREG=XED_REG_ERROR     enc
REG=0x7  | OUTREG=XED_REG_ERROR

# MOV to SEG cannot load CS
xed_reg_enum_t SEG_MOV()::
REG=0x0  | OUTREG=XED_REG_ES
REG=0x1  | OUTREG=XED_REG_ERROR
REG=0x2  | OUTREG=XED_REG_SS
REG=0x3  | OUTREG=XED_REG_DS
REG=0x4  | OUTREG=XED_REG_FS
REG=0x5  | OUTREG=XED_REG_GS
REG=0x6  | OUTREG=XED_REG_ERROR     enc
REG=0x7  | OUTREG=XED_REG_ERROR


###################################################

# We have two versions of FINAL_DSEG called FINAL_DSEG and
# FINAL_DSEG1. This is required because in the nonterminal function, I
# don't know if which memop (MEM0 or MEM1) the segment selector is
# being applied to. I set USING_DEFAULT_SEGMENT0 for MEM0 and
# USING_DEFAULT_SEGMENT1 for MEM1.


# These set USING_DEFAULT_SEGMENT0

xed_reg_enum_t FINAL_DSEG()::
mode16 | OUTREG=FINAL_DSEG_NOT64()
mode32 | OUTREG=FINAL_DSEG_NOT64()
mode64 | OUTREG=FINAL_DSEG_MODE64()

xed_reg_enum_t FINAL_DSEG_NOT64()::
SEG_OVD=0 | OUTREG=XED_REG_DS  USING_DEFAULT_SEGMENT0=1 enc # default data seg
SEG_OVD=1 | OUTREG=XED_REG_CS  USING_DEFAULT_SEGMENT0=0
SEG_OVD=2 | OUTREG=XED_REG_DS  USING_DEFAULT_SEGMENT0=1 # explicit ds seg
SEG_OVD=3 | OUTREG=XED_REG_ES  USING_DEFAULT_SEGMENT0=0
SEG_OVD=4 | OUTREG=XED_REG_FS  USING_DEFAULT_SEGMENT0=0
SEG_OVD=5 | OUTREG=XED_REG_GS  USING_DEFAULT_SEGMENT0=0
SEG_OVD=6 | OUTREG=XED_REG_SS  USING_DEFAULT_SEGMENT0=0

xed_reg_enum_t FINAL_DSEG_MODE64()::
SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1  enc
SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1
SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1
SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1
SEG_OVD=4 | OUTREG=XED_REG_FS      USING_DEFAULT_SEGMENT0=0
SEG_OVD=5 | OUTREG=XED_REG_GS      USING_DEFAULT_SEGMENT0=0
SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1


# These set USING_DEFAULT_SEGMENT1

xed_reg_enum_t FINAL_DSEG1()::
mode16 | OUTREG=FINAL_DSEG1_NOT64()
mode32 | OUTREG=FINAL_DSEG1_NOT64()
mode64 | OUTREG=FINAL_DSEG1_MODE64()

xed_reg_enum_t FINAL_DSEG1_NOT64()::
SEG_OVD=0 | OUTREG=XED_REG_DS  USING_DEFAULT_SEGMENT1=1 enc # default data seg
SEG_OVD=1 | OUTREG=XED_REG_CS  USING_DEFAULT_SEGMENT1=0
SEG_OVD=2 | OUTREG=XED_REG_DS  USING_DEFAULT_SEGMENT1=1 # explicit ds seg
SEG_OVD=3 | OUTREG=XED_REG_ES  USING_DEFAULT_SEGMENT1=0
SEG_OVD=4 | OUTREG=XED_REG_FS  USING_DEFAULT_SEGMENT1=0
SEG_OVD=5 | OUTREG=XED_REG_GS  USING_DEFAULT_SEGMENT1=0
SEG_OVD=6 | OUTREG=XED_REG_SS  USING_DEFAULT_SEGMENT1=0

xed_reg_enum_t FINAL_DSEG1_MODE64()::
SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1  enc
SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1
SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1
SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1
SEG_OVD=4 | OUTREG=XED_REG_FS      USING_DEFAULT_SEGMENT1=0
SEG_OVD=5 | OUTREG=XED_REG_GS      USING_DEFAULT_SEGMENT1=0
SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1





###################################################

# FINAL_ESEG is only called for STRING OPS and only specifies MEM0's SEG0.

xed_reg_enum_t FINAL_ESEG()::
mode16 | OUTREG=XED_REG_ES        USING_DEFAULT_SEGMENT0=1
mode32 | OUTREG=XED_REG_ES        USING_DEFAULT_SEGMENT0=1
mode64 | OUTREG=XED_REG_INVALID   USING_DEFAULT_SEGMENT0=1

xed_reg_enum_t FINAL_ESEG1()::
mode16 | OUTREG=XED_REG_ES        USING_DEFAULT_SEGMENT1=1
mode32 | OUTREG=XED_REG_ES        USING_DEFAULT_SEGMENT1=1
mode64 | OUTREG=XED_REG_INVALID   USING_DEFAULT_SEGMENT1=1

# For synthesized stack operands (see generator.py)
xed_reg_enum_t FINAL_SSEG1()::
mode16 | OUTREG=XED_REG_SS       USING_DEFAULT_SEGMENT1=1
mode32 | OUTREG=XED_REG_SS       USING_DEFAULT_SEGMENT1=1
mode64 | OUTREG=XED_REG_INVALID  USING_DEFAULT_SEGMENT1=1

# For stack operands that cannot be overridden
xed_reg_enum_t FINAL_SSEG0()::
mode16 | OUTREG=XED_REG_SS       USING_DEFAULT_SEGMENT0=1
mode32 | OUTREG=XED_REG_SS       USING_DEFAULT_SEGMENT0=1
mode64 | OUTREG=XED_REG_INVALID  USING_DEFAULT_SEGMENT0=1

# This is only called for MODRM BYTEs and they only set MEM0's SEG0.

xed_reg_enum_t FINAL_SSEG()::
mode16 | OUTREG=FINAL_SSEG_NOT64()
mode32 | OUTREG=FINAL_SSEG_NOT64()
mode64 | OUTREG=FINAL_SSEG_MODE64()

xed_reg_enum_t FINAL_SSEG_NOT64()::
SEG_OVD=0 | OUTREG=XED_REG_SS  USING_DEFAULT_SEGMENT0=1     enc # default stack seg
SEG_OVD=1 | OUTREG=XED_REG_CS  USING_DEFAULT_SEGMENT0=0
SEG_OVD=2 | OUTREG=XED_REG_DS  USING_DEFAULT_SEGMENT0=0
SEG_OVD=3 | OUTREG=XED_REG_ES  USING_DEFAULT_SEGMENT0=0
SEG_OVD=4 | OUTREG=XED_REG_FS  USING_DEFAULT_SEGMENT0=0
SEG_OVD=5 | OUTREG=XED_REG_GS  USING_DEFAULT_SEGMENT0=0
SEG_OVD=6 | OUTREG=XED_REG_SS  USING_DEFAULT_SEGMENT0=1 # explicit ss seg

xed_reg_enum_t FINAL_SSEG_MODE64()::
SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1  enc
SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1
SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1
SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1
SEG_OVD=4 | OUTREG=XED_REG_FS      USING_DEFAULT_SEGMENT0=0
SEG_OVD=5 | OUTREG=XED_REG_GS      USING_DEFAULT_SEGMENT0=0
SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1



###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-eASZ.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL
###########################################################################
## file: xed-eASZ.txt
###########################################################################
# Call this after all legacy prefixes and before every instruction!


ASZ_NONTERM()::

mode16 no67_prefix  | eamode16
mode16   67_prefix  | eamode32

mode32 no67_prefix  | eamode32
mode32   67_prefix  | eamode16

mode64 no67_prefix  | eamode64
mode64   67_prefix  | eamode32


###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-immediates.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL
###########################################################################
## file: xed-immediates.txt
###########################################################################
# Immediates and displacements
# FIXME: when there are multiple immediates, need separate storage
# FIXME: record the width of the immediate

# FIXME: for encode we'll sometimes have to choose between SIMMv and
#        SIMMz to pick a MOV, for 16 and 32b widths.
##########################################################################################
## 2-BYTE STORAGE UNITS
##########################################################################################

ONE()::
mode16  | IMM_WIDTH=8 UIMM0=1
mode32  | IMM_WIDTH=8 UIMM0=1
mode64  | IMM_WIDTH=8 UIMM0=1


UIMMv()::
EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16
EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32
EOSZ=3 UIMM0[i/64] | IMM_WIDTH=64

SIMMz()::
EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16 IMM0SIGNED=1
EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1
EOSZ=3 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1

SIMM8()::
 UIMM0[i/8] | IMM_WIDTH=8 IMM0SIGNED=1

UIMM8()::
 UIMM0[i/8] | IMM_WIDTH=8

# For ENTER. separate storage.
UIMM8_1()::
 UIMM1[i/8] | true

UIMM16()::
 UIMM0[i/16] | IMM_WIDTH=16

UIMM32()::
 UIMM0[i/32]  | IMM_WIDTH=32

BRDISP8()::
 DISP[d/8]  |BRDISP_WIDTH=8

BRDISP32()::
 DISP[d/32] |  BRDISP_WIDTH=32

BRDISPz()::
EOSZ=1 DISP[d/16]  | BRDISP_WIDTH=16
EOSZ=2 DISP[d/32]  | BRDISP_WIDTH=32
EOSZ=3 DISP[d/32]  | BRDISP_WIDTH=32


MEMDISPv()::
EASZ=1 DISP[a/16]  | DISP_WIDTH=16
EASZ=2 DISP[a/32]  | DISP_WIDTH=32
EASZ=3 DISP[a/64]  | DISP_WIDTH=64


MEMDISP32()::
DISP[a/32] | DISP_WIDTH=32

MEMDISP16()::
DISP[a/16] | DISP_WIDTH=16

MEMDISP8()::
DISP[a/8]  | DISP_WIDTH=8


MEMDISP()::
NEED_MEMDISP=0               | DISP_WIDTH=0
NEED_MEMDISP=8   DISP[a/8]   | DISP_WIDTH=8
NEED_MEMDISP=16  DISP[a/16]  | DISP_WIDTH=16
NEED_MEMDISP=32  DISP[a/32]  | DISP_WIDTH=32



###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-reg-tables-xmm.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

xed_reg_enum_t XMM_R()::
mode16 | OUTREG=XMM_R_32()
mode32 | OUTREG=XMM_R_32()
mode64 | OUTREG=XMM_R_64()

xed_reg_enum_t XMM_R_32()::
REG=0x0  | OUTREG=XED_REG_XMM0
REG=0x1  | OUTREG=XED_REG_XMM1
REG=0x2  | OUTREG=XED_REG_XMM2
REG=0x3  | OUTREG=XED_REG_XMM3
REG=0x4  | OUTREG=XED_REG_XMM4
REG=0x5  | OUTREG=XED_REG_XMM5
REG=0x6  | OUTREG=XED_REG_XMM6
REG=0x7  | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_R_64()::
REXR=0 REG=0x0  | OUTREG=XED_REG_XMM0
REXR=0 REG=0x1  | OUTREG=XED_REG_XMM1
REXR=0 REG=0x2  | OUTREG=XED_REG_XMM2
REXR=0 REG=0x3  | OUTREG=XED_REG_XMM3
REXR=0 REG=0x4  | OUTREG=XED_REG_XMM4
REXR=0 REG=0x5  | OUTREG=XED_REG_XMM5
REXR=0 REG=0x6  | OUTREG=XED_REG_XMM6
REXR=0 REG=0x7  | OUTREG=XED_REG_XMM7
REXR=1 REG=0x0  | OUTREG=XED_REG_XMM8
REXR=1 REG=0x1  | OUTREG=XED_REG_XMM9
REXR=1 REG=0x2  | OUTREG=XED_REG_XMM10
REXR=1 REG=0x3  | OUTREG=XED_REG_XMM11
REXR=1 REG=0x4  | OUTREG=XED_REG_XMM12
REXR=1 REG=0x5  | OUTREG=XED_REG_XMM13
REXR=1 REG=0x6  | OUTREG=XED_REG_XMM14
REXR=1 REG=0x7  | OUTREG=XED_REG_XMM15


xed_reg_enum_t XMM_B()::
mode16 | OUTREG=XMM_B_32()
mode32 | OUTREG=XMM_B_32()
mode64 | OUTREG=XMM_B_64()

xed_reg_enum_t XMM_B_32()::
RM=0x0  | OUTREG=XED_REG_XMM0
RM=0x1  | OUTREG=XED_REG_XMM1
RM=0x2  | OUTREG=XED_REG_XMM2
RM=0x3  | OUTREG=XED_REG_XMM3
RM=0x4  | OUTREG=XED_REG_XMM4
RM=0x5  | OUTREG=XED_REG_XMM5
RM=0x6  | OUTREG=XED_REG_XMM6
RM=0x7  | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_B_64()::
REXB=0 RM=0x0  | OUTREG=XED_REG_XMM0
REXB=0 RM=0x1  | OUTREG=XED_REG_XMM1
REXB=0 RM=0x2  | OUTREG=XED_REG_XMM2
REXB=0 RM=0x3  | OUTREG=XED_REG_XMM3
REXB=0 RM=0x4  | OUTREG=XED_REG_XMM4
REXB=0 RM=0x5  | OUTREG=XED_REG_XMM5
REXB=0 RM=0x6  | OUTREG=XED_REG_XMM6
REXB=0 RM=0x7  | OUTREG=XED_REG_XMM7
REXB=1 RM=0x0  | OUTREG=XED_REG_XMM8
REXB=1 RM=0x1  | OUTREG=XED_REG_XMM9
REXB=1 RM=0x2  | OUTREG=XED_REG_XMM10
REXB=1 RM=0x3  | OUTREG=XED_REG_XMM11
REXB=1 RM=0x4  | OUTREG=XED_REG_XMM12
REXB=1 RM=0x5  | OUTREG=XED_REG_XMM13
REXB=1 RM=0x6  | OUTREG=XED_REG_XMM14
REXB=1 RM=0x7  | OUTREG=XED_REG_XMM15



###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-reg-tables.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL
xed_reg_enum_t BND_R()::
REXR=0 REG=0x0  | OUTREG=XED_REG_BND0
REXR=0 REG=0x1  | OUTREG=XED_REG_BND1
REXR=0 REG=0x2  | OUTREG=XED_REG_BND2
REXR=0 REG=0x3  | OUTREG=XED_REG_BND3
REXR=0 REG=0x4  | OUTREG=XED_REG_ERROR  enc
REXR=0 REG=0x5  | OUTREG=XED_REG_ERROR
REXR=0 REG=0x6  | OUTREG=XED_REG_ERROR
REXR=0 REG=0x7  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x0  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x1  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x2  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x3  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x4  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x5  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x6  | OUTREG=XED_REG_ERROR
REXR=1 REG=0x7  | OUTREG=XED_REG_ERROR

xed_reg_enum_t BND_B()::
REXB=0 RM=0x0  | OUTREG=XED_REG_BND0
REXB=0 RM=0x1  | OUTREG=XED_REG_BND1
REXB=0 RM=0x2  | OUTREG=XED_REG_BND2
REXB=0 RM=0x3  | OUTREG=XED_REG_BND3
REXB=0 RM=0x4  | OUTREG=XED_REG_ERROR   enc
REXB=0 RM=0x5  | OUTREG=XED_REG_ERROR
REXB=0 RM=0x6  | OUTREG=XED_REG_ERROR
REXB=0 RM=0x7  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x0  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x1  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x2  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x3  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x4  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x5  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x6  | OUTREG=XED_REG_ERROR
REXB=1 RM=0x7  | OUTREG=XED_REG_ERROR


###FILE: C:/$Fanta/IntelXED/xed/datafiles/movdir/asize-reg-table.xed.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

xed_reg_enum_t A_GPR_R()::
REXR=0 REG=0x0  | OUTREG=ArAX()
REXR=0 REG=0x1  | OUTREG=ArCX()
REXR=0 REG=0x2  | OUTREG=ArDX()
REXR=0 REG=0x3  | OUTREG=ArBX()
REXR=0 REG=0x4  | OUTREG=ArSP()
REXR=0 REG=0x5  | OUTREG=ArBP()
REXR=0 REG=0x6  | OUTREG=ArSI()
REXR=0 REG=0x7  | OUTREG=ArDI()
REXR=1 REG=0x0  | OUTREG=Ar8()
REXR=1 REG=0x1  | OUTREG=Ar9()
REXR=1 REG=0x2  | OUTREG=Ar10()
REXR=1 REG=0x3  | OUTREG=Ar11()
REXR=1 REG=0x4  | OUTREG=Ar12()
REXR=1 REG=0x5  | OUTREG=Ar13()
REXR=1 REG=0x6  | OUTREG=Ar14()
REXR=1 REG=0x7  | OUTREG=Ar15()


###FILE: C:/$Fanta/IntelXED/xed/datafiles/waitpkg/asize-rm-table.xed.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

xed_reg_enum_t A_GPR_B()::
REXB=0 RM=0x0  | OUTREG=ArAX()
REXB=0 RM=0x1  | OUTREG=ArCX()
REXB=0 RM=0x2  | OUTREG=ArDX()
REXB=0 RM=0x3  | OUTREG=ArBX()
REXB=0 RM=0x4  | OUTREG=ArSP()
REXB=0 RM=0x5  | OUTREG=ArBP()
REXB=0 RM=0x6  | OUTREG=ArSI()
REXB=0 RM=0x7  | OUTREG=ArDI()
REXB=1 RM=0x0  | OUTREG=Ar8()
REXB=1 RM=0x1  | OUTREG=Ar9()
REXB=1 RM=0x2  | OUTREG=Ar10()
REXB=1 RM=0x3  | OUTREG=Ar11()
REXB=1 RM=0x4  | OUTREG=Ar12()
REXB=1 RM=0x5  | OUTREG=Ar13()
REXB=1 RM=0x6  | OUTREG=Ar14()
REXB=1 RM=0x7  | OUTREG=Ar15()


###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-reg-table.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL
xed_reg_enum_t XMM_SE()::
mode16 | OUTREG=XMM_SE32()
mode32 | OUTREG=XMM_SE32()
mode64 | OUTREG=XMM_SE64()

xed_reg_enum_t XMM_SE64()::
ESRC=0x0 | OUTREG=XED_REG_XMM0
ESRC=0x1 | OUTREG=XED_REG_XMM1
ESRC=0x2 | OUTREG=XED_REG_XMM2
ESRC=0x3 | OUTREG=XED_REG_XMM3
ESRC=0x4 | OUTREG=XED_REG_XMM4
ESRC=0x5 | OUTREG=XED_REG_XMM5
ESRC=0x6 | OUTREG=XED_REG_XMM6
ESRC=0x7 | OUTREG=XED_REG_XMM7
ESRC=0x8 | OUTREG=XED_REG_XMM8
ESRC=0x9 | OUTREG=XED_REG_XMM9
ESRC=0xA | OUTREG=XED_REG_XMM10
ESRC=0xB | OUTREG=XED_REG_XMM11
ESRC=0xC | OUTREG=XED_REG_XMM12
ESRC=0xD | OUTREG=XED_REG_XMM13
ESRC=0xE | OUTREG=XED_REG_XMM14
ESRC=0xF | OUTREG=XED_REG_XMM15

xed_reg_enum_t XMM_SE32()::
ESRC=0 | OUTREG=XED_REG_XMM0    enc
ESRC=1 | OUTREG=XED_REG_XMM1    enc
ESRC=2 | OUTREG=XED_REG_XMM2    enc
ESRC=3 | OUTREG=XED_REG_XMM3    enc
ESRC=4 | OUTREG=XED_REG_XMM4    enc
ESRC=5 | OUTREG=XED_REG_XMM5    enc
ESRC=6 | OUTREG=XED_REG_XMM6    enc
ESRC=7 | OUTREG=XED_REG_XMM7    enc
# ignoring the high bit in non64b modes. Really just 0...7
ESRC=0x8 | OUTREG=XED_REG_XMM0
ESRC=0x9 | OUTREG=XED_REG_XMM1
ESRC=0xA | OUTREG=XED_REG_XMM2
ESRC=0xB | OUTREG=XED_REG_XMM3
ESRC=0xC | OUTREG=XED_REG_XMM4
ESRC=0xD | OUTREG=XED_REG_XMM5
ESRC=0xE | OUTREG=XED_REG_XMM6
ESRC=0xF | OUTREG=XED_REG_XMM7

xed_reg_enum_t YMM_SE()::
mode16 | OUTREG=YMM_SE32()
mode32 | OUTREG=YMM_SE32()
mode64 | OUTREG=YMM_SE64()

xed_reg_enum_t YMM_SE64()::
ESRC=0x0 | OUTREG=XED_REG_YMM0
ESRC=0x1 | OUTREG=XED_REG_YMM1
ESRC=0x2 | OUTREG=XED_REG_YMM2
ESRC=0x3 | OUTREG=XED_REG_YMM3
ESRC=0x4 | OUTREG=XED_REG_YMM4
ESRC=0x5 | OUTREG=XED_REG_YMM5
ESRC=0x6 | OUTREG=XED_REG_YMM6
ESRC=0x7 | OUTREG=XED_REG_YMM7
ESRC=0x8 | OUTREG=XED_REG_YMM8
ESRC=0x9 | OUTREG=XED_REG_YMM9
ESRC=0xA | OUTREG=XED_REG_YMM10
ESRC=0xB | OUTREG=XED_REG_YMM11
ESRC=0xC | OUTREG=XED_REG_YMM12
ESRC=0xD | OUTREG=XED_REG_YMM13
ESRC=0xE | OUTREG=XED_REG_YMM14
ESRC=0xF | OUTREG=XED_REG_YMM15

xed_reg_enum_t YMM_SE32()::
ESRC=0 | OUTREG=XED_REG_YMM0        enc
ESRC=1 | OUTREG=XED_REG_YMM1        enc
ESRC=2 | OUTREG=XED_REG_YMM2        enc
ESRC=3 | OUTREG=XED_REG_YMM3        enc
ESRC=4 | OUTREG=XED_REG_YMM4        enc
ESRC=5 | OUTREG=XED_REG_YMM5        enc
ESRC=6 | OUTREG=XED_REG_YMM6        enc
ESRC=7 | OUTREG=XED_REG_YMM7        enc
# ignoring the high bit in non64b modes. Really just 0...7
ESRC=0x8 | OUTREG=XED_REG_YMM0
ESRC=0x9 | OUTREG=XED_REG_YMM1
ESRC=0xA | OUTREG=XED_REG_YMM2
ESRC=0xB | OUTREG=XED_REG_YMM3
ESRC=0xC | OUTREG=XED_REG_YMM4
ESRC=0xD | OUTREG=XED_REG_YMM5
ESRC=0xE | OUTREG=XED_REG_YMM6
ESRC=0xF | OUTREG=XED_REG_YMM7


xed_reg_enum_t XMM_N()::
mode16 | OUTREG=XMM_N_32():
mode32 | OUTREG=XMM_N_32():
mode64 | OUTREG=XMM_N_64():

xed_reg_enum_t XMM_N_32()::
VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST210=0 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_N_64()::
VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7
VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8
VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9
VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10
VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11
VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12
VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13
VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14
VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15

xed_reg_enum_t YMM_N()::
mode16 | OUTREG=YMM_N_32():
mode32 | OUTREG=YMM_N_32():
mode64 | OUTREG=YMM_N_64():

xed_reg_enum_t YMM_N_32()::
VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST210=0 | OUTREG=XED_REG_YMM7
xed_reg_enum_t YMM_N_64()::
VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7
VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8
VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9
VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10
VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11
VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12
VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13
VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14
VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15

xed_reg_enum_t YMM_R()::
mode16 | OUTREG=YMM_R_32():
mode32 | OUTREG=YMM_R_32():
mode64 | OUTREG=YMM_R_64():


xed_reg_enum_t YMM_R_32()::
REG=0  | OUTREG=XED_REG_YMM0
REG=1  | OUTREG=XED_REG_YMM1
REG=2  | OUTREG=XED_REG_YMM2
REG=3  | OUTREG=XED_REG_YMM3
REG=4  | OUTREG=XED_REG_YMM4
REG=5  | OUTREG=XED_REG_YMM5
REG=6  | OUTREG=XED_REG_YMM6
REG=7  | OUTREG=XED_REG_YMM7

xed_reg_enum_t YMM_R_64()::
REXR=0 REG=0  | OUTREG=XED_REG_YMM0
REXR=0 REG=1  | OUTREG=XED_REG_YMM1
REXR=0 REG=2  | OUTREG=XED_REG_YMM2
REXR=0 REG=3  | OUTREG=XED_REG_YMM3
REXR=0 REG=4  | OUTREG=XED_REG_YMM4
REXR=0 REG=5  | OUTREG=XED_REG_YMM5
REXR=0 REG=6  | OUTREG=XED_REG_YMM6
REXR=0 REG=7  | OUTREG=XED_REG_YMM7
REXR=1 REG=0  | OUTREG=XED_REG_YMM8
REXR=1 REG=1  | OUTREG=XED_REG_YMM9
REXR=1 REG=2  | OUTREG=XED_REG_YMM10
REXR=1 REG=3  | OUTREG=XED_REG_YMM11
REXR=1 REG=4  | OUTREG=XED_REG_YMM12
REXR=1 REG=5  | OUTREG=XED_REG_YMM13
REXR=1 REG=6  | OUTREG=XED_REG_YMM14
REXR=1 REG=7  | OUTREG=XED_REG_YMM15


xed_reg_enum_t YMM_B()::
mode16 | OUTREG=YMM_B_32():
mode32 | OUTREG=YMM_B_32():
mode64 | OUTREG=YMM_B_64():


xed_reg_enum_t YMM_B_32()::
RM=0  | OUTREG=XED_REG_YMM0
RM=1  | OUTREG=XED_REG_YMM1
RM=2  | OUTREG=XED_REG_YMM2
RM=3  | OUTREG=XED_REG_YMM3
RM=4  | OUTREG=XED_REG_YMM4
RM=5  | OUTREG=XED_REG_YMM5
RM=6  | OUTREG=XED_REG_YMM6
RM=7  | OUTREG=XED_REG_YMM7

xed_reg_enum_t YMM_B_64()::
REXB=0 RM=0  | OUTREG=XED_REG_YMM0
REXB=0 RM=1  | OUTREG=XED_REG_YMM1
REXB=0 RM=2  | OUTREG=XED_REG_YMM2
REXB=0 RM=3  | OUTREG=XED_REG_YMM3
REXB=0 RM=4  | OUTREG=XED_REG_YMM4
REXB=0 RM=5  | OUTREG=XED_REG_YMM5
REXB=0 RM=6  | OUTREG=XED_REG_YMM6
REXB=0 RM=7  | OUTREG=XED_REG_YMM7
REXB=1 RM=0  | OUTREG=XED_REG_YMM8
REXB=1 RM=1  | OUTREG=XED_REG_YMM9
REXB=1 RM=2  | OUTREG=XED_REG_YMM10
REXB=1 RM=3  | OUTREG=XED_REG_YMM11
REXB=1 RM=4  | OUTREG=XED_REG_YMM12
REXB=1 RM=5  | OUTREG=XED_REG_YMM13
REXB=1 RM=6  | OUTREG=XED_REG_YMM14
REXB=1 RM=7  | OUTREG=XED_REG_YMM15


###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/hsw-reg-table.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

# VGPRy_N, VGPRy_B, and VGPRy_R are used by AMD XOP.
# Only but the lower level stuff is used by HSW NI.

xed_reg_enum_t VGPRy_R()::
EOSZ=1 | OUTREG=VGPR32_R()
EOSZ=2 | OUTREG=VGPR32_R()
EOSZ=3 | OUTREG=VGPR64_R()

xed_reg_enum_t VGPRy_B()::
EOSZ=1 | OUTREG=VGPR32_B()
EOSZ=2 | OUTREG=VGPR32_B()
EOSZ=3 | OUTREG=VGPR64_B()

xed_reg_enum_t VGPRy_N()::
EOSZ=1 | OUTREG=VGPR32_N()
EOSZ=2 | OUTREG=VGPR32_N()
EOSZ=3 | OUTREG=VGPR64_N()

xed_reg_enum_t VGPR32_N()::
mode16 | OUTREG=VGPR32_N_32()
mode32 | OUTREG=VGPR32_N_32()
mode64 | OUTREG=VGPR32_N_64()

xed_reg_enum_t VGPR32_B()::
mode16 | OUTREG=VGPR32_B_32()
mode32 | OUTREG=VGPR32_B_32()
mode64 | OUTREG=VGPR32_B_64()

xed_reg_enum_t VGPR32_R()::
mode16 | OUTREG=VGPR32_R_32()
mode32 | OUTREG=VGPR32_R_32()
mode64 | OUTREG=VGPR32_R_64()






xed_reg_enum_t VGPR32_N_32():: # IGNORES UPPER BIT  (VEXDEST3) IN 32b mode
VEXDEST210=7   | OUTREG=XED_REG_EAX
VEXDEST210=6   | OUTREG=XED_REG_ECX
VEXDEST210=5   | OUTREG=XED_REG_EDX
VEXDEST210=4   | OUTREG=XED_REG_EBX
VEXDEST210=3   | OUTREG=XED_REG_ESP
VEXDEST210=2   | OUTREG=XED_REG_EBP
VEXDEST210=1   | OUTREG=XED_REG_ESI
VEXDEST210=0   | OUTREG=XED_REG_EDI

xed_reg_enum_t VGPR32_N_64():: # IGNORES UPPER BIT  (VEXDEST3) IN 32b mode
VEXDEST3=1 VEXDEST210=7   | OUTREG=XED_REG_EAX
VEXDEST3=1 VEXDEST210=6   | OUTREG=XED_REG_ECX
VEXDEST3=1 VEXDEST210=5   | OUTREG=XED_REG_EDX
VEXDEST3=1 VEXDEST210=4   | OUTREG=XED_REG_EBX
VEXDEST3=1 VEXDEST210=3   | OUTREG=XED_REG_ESP
VEXDEST3=1 VEXDEST210=2   | OUTREG=XED_REG_EBP
VEXDEST3=1 VEXDEST210=1   | OUTREG=XED_REG_ESI
VEXDEST3=1 VEXDEST210=0   | OUTREG=XED_REG_EDI
VEXDEST3=0 VEXDEST210=7   | OUTREG=XED_REG_R8D
VEXDEST3=0 VEXDEST210=6   | OUTREG=XED_REG_R9D
VEXDEST3=0 VEXDEST210=5   | OUTREG=XED_REG_R10D
VEXDEST3=0 VEXDEST210=4   | OUTREG=XED_REG_R11D
VEXDEST3=0 VEXDEST210=3   | OUTREG=XED_REG_R12D
VEXDEST3=0 VEXDEST210=2   | OUTREG=XED_REG_R13D
VEXDEST3=0 VEXDEST210=1   | OUTREG=XED_REG_R14D
VEXDEST3=0 VEXDEST210=0   | OUTREG=XED_REG_R15D


xed_reg_enum_t VGPR64_N()::
VEXDEST3=1 VEXDEST210=7  | OUTREG=XED_REG_RAX
VEXDEST3=1 VEXDEST210=6  | OUTREG=XED_REG_RCX
VEXDEST3=1 VEXDEST210=5  | OUTREG=XED_REG_RDX
VEXDEST3=1 VEXDEST210=4  | OUTREG=XED_REG_RBX
VEXDEST3=1 VEXDEST210=3  | OUTREG=XED_REG_RSP
VEXDEST3=1 VEXDEST210=2  | OUTREG=XED_REG_RBP
VEXDEST3=1 VEXDEST210=1  | OUTREG=XED_REG_RSI
VEXDEST3=1 VEXDEST210=0  | OUTREG=XED_REG_RDI
VEXDEST3=0 VEXDEST210=7  | OUTREG=XED_REG_R8
VEXDEST3=0 VEXDEST210=6  | OUTREG=XED_REG_R9
VEXDEST3=0 VEXDEST210=5  | OUTREG=XED_REG_R10
VEXDEST3=0 VEXDEST210=4  | OUTREG=XED_REG_R11
VEXDEST3=0 VEXDEST210=3  | OUTREG=XED_REG_R12
VEXDEST3=0 VEXDEST210=2  | OUTREG=XED_REG_R13
VEXDEST3=0 VEXDEST210=1  | OUTREG=XED_REG_R14
VEXDEST3=0 VEXDEST210=0  | OUTREG=XED_REG_R15


###########

xed_reg_enum_t VGPR32_R_32():: # IGNORES  (REXR) IN 32b mode
REG=0   | OUTREG=XED_REG_EAX
REG=1   | OUTREG=XED_REG_ECX
REG=2   | OUTREG=XED_REG_EDX
REG=3   | OUTREG=XED_REG_EBX
REG=4   | OUTREG=XED_REG_ESP
REG=5   | OUTREG=XED_REG_EBP
REG=6   | OUTREG=XED_REG_ESI
REG=7   | OUTREG=XED_REG_EDI


xed_reg_enum_t VGPR32_R_64()::
REXR=0 REG=0  | OUTREG=XED_REG_EAX
REXR=0 REG=1  | OUTREG=XED_REG_ECX
REXR=0 REG=2  | OUTREG=XED_REG_EDX
REXR=0 REG=3  | OUTREG=XED_REG_EBX
REXR=0 REG=4  | OUTREG=XED_REG_ESP
REXR=0 REG=5  | OUTREG=XED_REG_EBP
REXR=0 REG=6  | OUTREG=XED_REG_ESI
REXR=0 REG=7  | OUTREG=XED_REG_EDI
REXR=1 REG=0  | OUTREG=XED_REG_R8D
REXR=1 REG=1  | OUTREG=XED_REG_R9D
REXR=1 REG=2  | OUTREG=XED_REG_R10D
REXR=1 REG=3  | OUTREG=XED_REG_R11D
REXR=1 REG=4  | OUTREG=XED_REG_R12D
REXR=1 REG=5  | OUTREG=XED_REG_R13D
REXR=1 REG=6  | OUTREG=XED_REG_R14D
REXR=1 REG=7  | OUTREG=XED_REG_R15D

xed_reg_enum_t VGPR64_R()::
REXR=0 REG=0  | OUTREG=XED_REG_RAX
REXR=0 REG=1  | OUTREG=XED_REG_RCX
REXR=0 REG=2  | OUTREG=XED_REG_RDX
REXR=0 REG=3  | OUTREG=XED_REG_RBX
REXR=0 REG=4  | OUTREG=XED_REG_RSP
REXR=0 REG=5  | OUTREG=XED_REG_RBP
REXR=0 REG=6  | OUTREG=XED_REG_RSI
REXR=0 REG=7  | OUTREG=XED_REG_RDI
REXR=1 REG=0  | OUTREG=XED_REG_R8
REXR=1 REG=1  | OUTREG=XED_REG_R9
REXR=1 REG=2  | OUTREG=XED_REG_R10
REXR=1 REG=3  | OUTREG=XED_REG_R11
REXR=1 REG=4  | OUTREG=XED_REG_R12
REXR=1 REG=5  | OUTREG=XED_REG_R13
REXR=1 REG=6  | OUTREG=XED_REG_R14
REXR=1 REG=7  | OUTREG=XED_REG_R15


###################

xed_reg_enum_t VGPR32_B_32()::  # IGNORES  (REXB) IN 32b mode
RM=0   | OUTREG=XED_REG_EAX
RM=1   | OUTREG=XED_REG_ECX
RM=2   | OUTREG=XED_REG_EDX
RM=3   | OUTREG=XED_REG_EBX
RM=4   | OUTREG=XED_REG_ESP
RM=5   | OUTREG=XED_REG_EBP
RM=6   | OUTREG=XED_REG_ESI
RM=7   | OUTREG=XED_REG_EDI


xed_reg_enum_t VGPR32_B_64()::
REXB=0 RM=0  | OUTREG=XED_REG_EAX
REXB=0 RM=1  | OUTREG=XED_REG_ECX
REXB=0 RM=2  | OUTREG=XED_REG_EDX
REXB=0 RM=3  | OUTREG=XED_REG_EBX
REXB=0 RM=4  | OUTREG=XED_REG_ESP
REXB=0 RM=5  | OUTREG=XED_REG_EBP
REXB=0 RM=6  | OUTREG=XED_REG_ESI
REXB=0 RM=7  | OUTREG=XED_REG_EDI
REXB=1 RM=0  | OUTREG=XED_REG_R8D
REXB=1 RM=1  | OUTREG=XED_REG_R9D
REXB=1 RM=2  | OUTREG=XED_REG_R10D
REXB=1 RM=3  | OUTREG=XED_REG_R11D
REXB=1 RM=4  | OUTREG=XED_REG_R12D
REXB=1 RM=5  | OUTREG=XED_REG_R13D
REXB=1 RM=6  | OUTREG=XED_REG_R14D
REXB=1 RM=7  | OUTREG=XED_REG_R15D

xed_reg_enum_t VGPR64_B()::
REXB=0 RM=0  | OUTREG=XED_REG_RAX
REXB=0 RM=1  | OUTREG=XED_REG_RCX
REXB=0 RM=2  | OUTREG=XED_REG_RDX
REXB=0 RM=3  | OUTREG=XED_REG_RBX
REXB=0 RM=4  | OUTREG=XED_REG_RSP
REXB=0 RM=5  | OUTREG=XED_REG_RBP
REXB=0 RM=6  | OUTREG=XED_REG_RSI
REXB=0 RM=7  | OUTREG=XED_REG_RDI
REXB=1 RM=0  | OUTREG=XED_REG_R8
REXB=1 RM=1  | OUTREG=XED_REG_R9
REXB=1 RM=2  | OUTREG=XED_REG_R10
REXB=1 RM=3  | OUTREG=XED_REG_R11
REXB=1 RM=4  | OUTREG=XED_REG_R12
REXB=1 RM=5  | OUTREG=XED_REG_R13
REXB=1 RM=6  | OUTREG=XED_REG_R14
REXB=1 RM=7  | OUTREG=XED_REG_R15




###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-table-mask.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

# FIXME: the rest of this file is common w/KNC. Split it out to avoid
#  duplication

xed_reg_enum_t MASK1()::
MASK=0x0  | OUTREG=XED_REG_K0
MASK=0x1  | OUTREG=XED_REG_K1
MASK=0x2  | OUTREG=XED_REG_K2
MASK=0x3  | OUTREG=XED_REG_K3
MASK=0x4  | OUTREG=XED_REG_K4
MASK=0x5  | OUTREG=XED_REG_K5
MASK=0x6  | OUTREG=XED_REG_K6
MASK=0x7  | OUTREG=XED_REG_K7

xed_reg_enum_t MASKNOT0()::
MASK=0x0  | OUTREG=XED_REG_ERROR
MASK=0x1  | OUTREG=XED_REG_K1
MASK=0x2  | OUTREG=XED_REG_K2
MASK=0x3  | OUTREG=XED_REG_K3
MASK=0x4  | OUTREG=XED_REG_K4
MASK=0x5  | OUTREG=XED_REG_K5
MASK=0x6  | OUTREG=XED_REG_K6
MASK=0x7  | OUTREG=XED_REG_K7

# used for compares in EVEX
xed_reg_enum_t MASK_R()::
REXRR=0 REXR=0 REG=0x0 | OUTREG=XED_REG_K0
REXRR=0 REXR=0 REG=0x1 | OUTREG=XED_REG_K1
REXRR=0 REXR=0 REG=0x2 | OUTREG=XED_REG_K2
REXRR=0 REXR=0 REG=0x3 | OUTREG=XED_REG_K3
REXRR=0 REXR=0 REG=0x4 | OUTREG=XED_REG_K4
REXRR=0 REXR=0 REG=0x5 | OUTREG=XED_REG_K5
REXRR=0 REXR=0 REG=0x6 | OUTREG=XED_REG_K6
REXRR=0 REXR=0 REG=0x7 | OUTREG=XED_REG_K7

# MASK_B is used by VEX and EVEX encodings. SDM (rev 062) states in
# EVEX, EVEX.B (REXB) is ignored. SDM does not (yet) say what happens
# on VEX.B but assuming it is similar.

xed_reg_enum_t MASK_B()::
RM=0x0 | OUTREG=XED_REG_K0
RM=0x1 | OUTREG=XED_REG_K1
RM=0x2 | OUTREG=XED_REG_K2
RM=0x3 | OUTREG=XED_REG_K3
RM=0x4 | OUTREG=XED_REG_K4
RM=0x5 | OUTREG=XED_REG_K5
RM=0x6 | OUTREG=XED_REG_K6
RM=0x7 | OUTREG=XED_REG_K7

# only used in VEX space for K-mask ops
# stored inverted
xed_reg_enum_t MASK_N()::
mode64  | OUTREG=MASK_N64()
mode32  | OUTREG=MASK_N32()
mode16  | OUTREG=MASK_N32()

xed_reg_enum_t MASK_N64()::
VEXDEST3=1 VEXDEST210=0x0 | OUTREG=XED_REG_K7
VEXDEST3=1 VEXDEST210=0x1 | OUTREG=XED_REG_K6
VEXDEST3=1 VEXDEST210=0x2 | OUTREG=XED_REG_K5
VEXDEST3=1 VEXDEST210=0x3 | OUTREG=XED_REG_K4
VEXDEST3=1 VEXDEST210=0x4 | OUTREG=XED_REG_K3
VEXDEST3=1 VEXDEST210=0x5 | OUTREG=XED_REG_K2
VEXDEST3=1 VEXDEST210=0x6 | OUTREG=XED_REG_K1
VEXDEST3=1 VEXDEST210=0x7 | OUTREG=XED_REG_K0

xed_reg_enum_t MASK_N32()::
VEXDEST210=0x0 | OUTREG=XED_REG_K7
VEXDEST210=0x1 | OUTREG=XED_REG_K6
VEXDEST210=0x2 | OUTREG=XED_REG_K5
VEXDEST210=0x3 | OUTREG=XED_REG_K4
VEXDEST210=0x4 | OUTREG=XED_REG_K3
VEXDEST210=0x5 | OUTREG=XED_REG_K2
VEXDEST210=0x6 | OUTREG=XED_REG_K1
VEXDEST210=0x7 | OUTREG=XED_REG_K0



###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-r3.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

xed_reg_enum_t XMM_R3()::
mode16 | OUTREG=XMM_R3_32()
mode32 | OUTREG=XMM_R3_32()
mode64 | OUTREG=XMM_R3_64()

xed_reg_enum_t XMM_R3_32()::
REG=0 | OUTREG=XED_REG_XMM0
REG=1 | OUTREG=XED_REG_XMM1
REG=2 | OUTREG=XED_REG_XMM2
REG=3 | OUTREG=XED_REG_XMM3
REG=4 | OUTREG=XED_REG_XMM4
REG=5 | OUTREG=XED_REG_XMM5
REG=6 | OUTREG=XED_REG_XMM6
REG=7 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_R3_64()::
REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_XMM0
REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_XMM1
REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_XMM2
REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_XMM3
REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_XMM4
REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_XMM5
REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_XMM6
REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_XMM7

REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_XMM8
REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_XMM9
REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_XMM10
REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_XMM11
REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_XMM12
REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_XMM13
REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_XMM14
REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_XMM15

REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_XMM16
REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_XMM17
REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_XMM18
REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_XMM19
REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_XMM20
REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_XMM21
REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_XMM22
REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_XMM23
REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_XMM24
REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_XMM25
REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_XMM26
REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_XMM27
REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_XMM28
REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_XMM29
REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_XMM30
REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_XMM31


xed_reg_enum_t YMM_R3()::
mode16 | OUTREG=YMM_R3_32()
mode32 | OUTREG=YMM_R3_32()
mode64 | OUTREG=YMM_R3_64()

xed_reg_enum_t YMM_R3_32()::
REG=0 | OUTREG=XED_REG_YMM0
REG=1 | OUTREG=XED_REG_YMM1
REG=2 | OUTREG=XED_REG_YMM2
REG=3 | OUTREG=XED_REG_YMM3
REG=4 | OUTREG=XED_REG_YMM4
REG=5 | OUTREG=XED_REG_YMM5
REG=6 | OUTREG=XED_REG_YMM6
REG=7 | OUTREG=XED_REG_YMM7
xed_reg_enum_t YMM_R3_64()::
REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_YMM0
REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_YMM1
REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_YMM2
REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_YMM3
REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_YMM4
REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_YMM5
REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_YMM6
REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_YMM7
REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_YMM8
REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_YMM9
REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_YMM10
REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_YMM11
REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_YMM12
REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_YMM13
REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_YMM14
REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_YMM15

REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_YMM16
REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_YMM17
REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_YMM18
REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_YMM19
REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_YMM20
REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_YMM21
REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_YMM22
REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_YMM23
REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_YMM24
REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_YMM25
REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_YMM26
REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_YMM27
REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_YMM28
REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_YMM29
REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_YMM30
REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_YMM31



xed_reg_enum_t ZMM_R3()::
mode16 | OUTREG=ZMM_R3_32()
mode32 | OUTREG=ZMM_R3_32()
mode64 | OUTREG=ZMM_R3_64()

xed_reg_enum_t ZMM_R3_32()::
REG=0 | OUTREG=XED_REG_ZMM0
REG=1 | OUTREG=XED_REG_ZMM1
REG=2 | OUTREG=XED_REG_ZMM2
REG=3 | OUTREG=XED_REG_ZMM3
REG=4 | OUTREG=XED_REG_ZMM4
REG=5 | OUTREG=XED_REG_ZMM5
REG=6 | OUTREG=XED_REG_ZMM6
REG=7 | OUTREG=XED_REG_ZMM7

xed_reg_enum_t ZMM_R3_64()::
REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0
REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1
REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2
REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3
REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4
REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5
REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6
REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7
REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8
REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9
REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10
REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11
REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12
REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13
REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14
REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15

REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16
REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17
REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18
REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19
REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20
REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21
REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22
REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23
REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24
REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25
REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26
REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27
REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28
REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29
REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30
REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31



###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-b3.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

xed_reg_enum_t XMM_B3()::
mode16 | OUTREG=XMM_B3_32()
mode32 | OUTREG=XMM_B3_32()
mode64 | OUTREG=XMM_B3_64()

xed_reg_enum_t XMM_B3_32()::
RM=0 | OUTREG=XED_REG_XMM0
RM=1 | OUTREG=XED_REG_XMM1
RM=2 | OUTREG=XED_REG_XMM2
RM=3 | OUTREG=XED_REG_XMM3
RM=4 | OUTREG=XED_REG_XMM4
RM=5 | OUTREG=XED_REG_XMM5
RM=6 | OUTREG=XED_REG_XMM6
RM=7 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_B3_64()::
REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_XMM0
REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_XMM1
REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_XMM2
REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_XMM3
REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_XMM4
REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_XMM5
REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_XMM6
REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_XMM7

REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_XMM8
REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_XMM9
REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_XMM10
REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_XMM11
REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_XMM12
REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_XMM13
REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_XMM14
REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_XMM15

REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_XMM16
REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_XMM17
REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_XMM18
REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_XMM19
REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_XMM20
REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_XMM21
REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_XMM22
REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_XMM23
REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_XMM24
REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_XMM25
REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_XMM26
REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_XMM27
REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_XMM28
REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_XMM29
REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_XMM30
REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_XMM31



xed_reg_enum_t YMM_B3()::
mode16 | OUTREG=YMM_B3_32()
mode32 | OUTREG=YMM_B3_32()
mode64 | OUTREG=YMM_B3_64()

xed_reg_enum_t YMM_B3_32()::
RM=0 | OUTREG=XED_REG_YMM0
RM=1 | OUTREG=XED_REG_YMM1
RM=2 | OUTREG=XED_REG_YMM2
RM=3 | OUTREG=XED_REG_YMM3
RM=4 | OUTREG=XED_REG_YMM4
RM=5 | OUTREG=XED_REG_YMM5
RM=6 | OUTREG=XED_REG_YMM6
RM=7 | OUTREG=XED_REG_YMM7

xed_reg_enum_t YMM_B3_64()::
REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_YMM0
REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_YMM1
REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_YMM2
REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_YMM3
REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_YMM4
REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_YMM5
REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_YMM6
REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_YMM7
REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_YMM8
REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_YMM9
REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_YMM10
REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_YMM11
REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_YMM12
REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_YMM13
REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_YMM14
REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_YMM15

REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_YMM16
REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_YMM17
REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_YMM18
REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_YMM19
REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_YMM20
REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_YMM21
REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_YMM22
REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_YMM23
REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_YMM24
REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_YMM25
REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_YMM26
REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_YMM27
REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_YMM28
REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_YMM29
REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_YMM30
REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_YMM31



xed_reg_enum_t ZMM_B3()::
mode16 | OUTREG=ZMM_B3_32()
mode32 | OUTREG=ZMM_B3_32()
mode64 | OUTREG=ZMM_B3_64()

xed_reg_enum_t ZMM_B3_32()::
RM=0 | OUTREG=XED_REG_ZMM0
RM=1 | OUTREG=XED_REG_ZMM1
RM=2 | OUTREG=XED_REG_ZMM2
RM=3 | OUTREG=XED_REG_ZMM3
RM=4 | OUTREG=XED_REG_ZMM4
RM=5 | OUTREG=XED_REG_ZMM5
RM=6 | OUTREG=XED_REG_ZMM6
RM=7 | OUTREG=XED_REG_ZMM7

xed_reg_enum_t ZMM_B3_64()::
REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_ZMM0
REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_ZMM1
REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_ZMM2
REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_ZMM3
REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_ZMM4
REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_ZMM5
REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_ZMM6
REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_ZMM7
REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_ZMM8
REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_ZMM9
REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_ZMM10
REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_ZMM11
REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_ZMM12
REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_ZMM13
REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_ZMM14
REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_ZMM15
REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_ZMM16
REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_ZMM17
REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_ZMM18
REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_ZMM19
REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_ZMM20
REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_ZMM21
REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_ZMM22
REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_ZMM23
REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_ZMM24
REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_ZMM25
REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_ZMM26
REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_ZMM27
REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_ZMM28
REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_ZMM29
REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_ZMM30
REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_ZMM31



###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-n3.txt

#BEGIN_LEGAL
#
#Copyright (c) 2019 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL

xed_reg_enum_t XMM_N3()::
mode16 | OUTREG=XMM_N3_32()
mode32 | OUTREG=XMM_N3_32()
mode64 | OUTREG=XMM_N3_64()

xed_reg_enum_t XMM_N3_32()::
VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST210=0 | OUTREG=XED_REG_XMM7

xed_reg_enum_t XMM_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7

VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM16
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM17
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM18
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM19
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM20
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM21
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM22
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM23
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM24
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM25
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM26
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM27
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM28
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM29
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM30
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM31


xed_reg_enum_t YMM_N3()::
mode16 | OUTREG=YMM_N3_32()
mode32 | OUTREG=YMM_N3_32()
mode64 | OUTREG=YMM_N3_64()

xed_reg_enum_t YMM_N3_32()::
VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST210=0 | OUTREG=XED_REG_YMM7


xed_reg_enum_t YMM_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM16
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM17
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM18
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM19
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM20
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM21
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM22
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM23
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM24
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM25
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM26
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM27
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM28
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM29
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM30
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM31


xed_reg_enum_t ZMM_N3()::
mode16 | OUTREG=ZMM_N3_32()
mode32 | OUTREG=ZMM_N3_32()
mode64 | OUTREG=ZMM_N3_64()


xed_reg_enum_t ZMM_N3_32()::
VEXDEST210=7 | OUTREG=XED_REG_ZMM0
VEXDEST210=6 | OUTREG=XED_REG_ZMM1
VEXDEST210=5 | OUTREG=XED_REG_ZMM2
VEXDEST210=4 | OUTREG=XED_REG_ZMM3
VEXDEST210=3 | OUTREG=XED_REG_ZMM4
VEXDEST210=2 | OUTREG=XED_REG_ZMM5
VEXDEST210=1 | OUTREG=XED_REG_ZMM6
VEXDEST210=0 | OUTREG=XED_REG_ZMM7


xed_reg_enum_t ZMM_N3_64()::
VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0
VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1
VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2
VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3
VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4
VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5
VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6
VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7
VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8
VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9
VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10
VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11
VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12
VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13
VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14
VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15

VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16
VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17
VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18
VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19
VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20
VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21
VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22
VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23
VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24
VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25
VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26
VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27
VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28
VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29
VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30
VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31



###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-reg-tables.txt

#BEGIN_LEGAL
#
#Copyright (c) 2020 Intel Corporation
#
#  Licensed under the Apache License, Version 2.0 (the "License");
#  you may not use this file except in compliance with the License.
#  You may obtain a copy of the License at
#
#      http://www.apache.org/licenses/LICENSE-2.0
#
#  Unless required by applicable law or agreed to in writing, software
#  distributed under the License is distributed on an "AS IS" BASIS,
#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#  See the License for the specific language governing permissions and
#  limitations under the License.
#
#END_LEGAL
xed_reg_enum_t TMM_R()::
REXR=0 REG=0 | OUTREG=XED_REG_TMM0
REXR=0 REG=1 | OUTREG=XED_REG_TMM1
REXR=0 REG=2 | OUTREG=XED_REG_TMM2
REXR=0 REG=3 | OUTREG=XED_REG_TMM3
REXR=0 REG=4 | OUTREG=XED_REG_TMM4
REXR=0 REG=5 | OUTREG=XED_REG_TMM5
REXR=0 REG=6 | OUTREG=XED_REG_TMM6
REXR=0 REG=7 | OUTREG=XED_REG_TMM7

xed_reg_enum_t TMM_B()::
REXB=0 RM=0 | OUTREG=XED_REG_TMM0
REXB=0 RM=1 | OUTREG=XED_REG_TMM1
REXB=0 RM=2 | OUTREG=XED_REG_TMM2
REXB=0 RM=3 | OUTREG=XED_REG_TMM3
REXB=0 RM=4 | OUTREG=XED_REG_TMM4
REXB=0 RM=5 | OUTREG=XED_REG_TMM5
REXB=0 RM=6 | OUTREG=XED_REG_TMM6
REXB=0 RM=7 | OUTREG=XED_REG_TMM7


xed_reg_enum_t TMM_N()::
VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_TMM0
VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_TMM1
VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_TMM2
VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_TMM3
VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_TMM4
VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_TMM5
VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_TMM6
VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_TMM7
