Code_Virtualizer/CodeVirtualizer/build/obj/wkit/include/xed/xed-iform-enum.h

/* BEGIN_LEGAL 

Copyright (c) 2021 Intel Corporation

  Licensed under the Apache License, Version 2.0 (the "License");
  you may not use this file except in compliance with the License.
  You may obtain a copy of the License at

      http://www.apache.org/licenses/LICENSE-2.0

  Unless required by applicable law or agreed to in writing, software
  distributed under the License is distributed on an "AS IS" BASIS,
  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  See the License for the specific language governing permissions and
  limitations under the License.
  
END_LEGAL */
/// @file xed-iform-enum.h

// This file was automatically generated.
// Do not edit this file.

#if !defined(XED_IFORM_ENUM_H)
# define XED_IFORM_ENUM_H
#include "xed-common-hdrs.h"
#include "xed-iclass-enum.h"
#define XED_IFORM_INVALID_DEFINED 1
#define XED_IFORM_AAA_DEFINED 1
#define XED_IFORM_AAD_IMMb_DEFINED 1
#define XED_IFORM_AAM_IMMb_DEFINED 1
#define XED_IFORM_AAS_DEFINED 1
#define XED_IFORM_ADC_AL_IMMb_DEFINED 1
#define XED_IFORM_ADC_GPR8_GPR8_10_DEFINED 1
#define XED_IFORM_ADC_GPR8_GPR8_12_DEFINED 1
#define XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED 1
#define XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED 1
#define XED_IFORM_ADC_GPR8_MEMb_DEFINED 1
#define XED_IFORM_ADC_GPRv_GPRv_11_DEFINED 1
#define XED_IFORM_ADC_GPRv_GPRv_13_DEFINED 1
#define XED_IFORM_ADC_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ADC_GPRv_IMMz_DEFINED 1
#define XED_IFORM_ADC_GPRv_MEMv_DEFINED 1
#define XED_IFORM_ADC_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED 1
#define XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED 1
#define XED_IFORM_ADC_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADC_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADC_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADC_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED 1
#define XED_IFORM_ADCX_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED 1
#define XED_IFORM_ADCX_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADD_AL_IMMb_DEFINED 1
#define XED_IFORM_ADD_GPR8_GPR8_00_DEFINED 1
#define XED_IFORM_ADD_GPR8_GPR8_02_DEFINED 1
#define XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED 1
#define XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED 1
#define XED_IFORM_ADD_GPR8_MEMb_DEFINED 1
#define XED_IFORM_ADD_GPRv_GPRv_01_DEFINED 1
#define XED_IFORM_ADD_GPRv_GPRv_03_DEFINED 1
#define XED_IFORM_ADD_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ADD_GPRv_IMMz_DEFINED 1
#define XED_IFORM_ADD_GPRv_MEMv_DEFINED 1
#define XED_IFORM_ADD_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED 1
#define XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED 1
#define XED_IFORM_ADD_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADD_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADD_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADD_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_ADDPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_ADDPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_ADDSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_ADDSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED 1
#define XED_IFORM_ADOX_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED 1
#define XED_IFORM_ADOX_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESDEC128KL_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_AESDEC256KL_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESDECWIDE128KL_MEMu8_DEFINED 1
#define XED_IFORM_AESDECWIDE256KL_MEMu8_DEFINED 1
#define XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESENC128KL_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_AESENC256KL_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESENCWIDE128KL_MEMu8_DEFINED 1
#define XED_IFORM_AESENCWIDE256KL_MEMu8_DEFINED 1
#define XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_AND_AL_IMMb_DEFINED 1
#define XED_IFORM_AND_GPR8_GPR8_20_DEFINED 1
#define XED_IFORM_AND_GPR8_GPR8_22_DEFINED 1
#define XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED 1
#define XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED 1
#define XED_IFORM_AND_GPR8_MEMb_DEFINED 1
#define XED_IFORM_AND_GPRv_GPRv_21_DEFINED 1
#define XED_IFORM_AND_GPRv_GPRv_23_DEFINED 1
#define XED_IFORM_AND_GPRv_IMMb_DEFINED 1
#define XED_IFORM_AND_GPRv_IMMz_DEFINED 1
#define XED_IFORM_AND_GPRv_MEMv_DEFINED 1
#define XED_IFORM_AND_MEMb_GPR8_DEFINED 1
#define XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED 1
#define XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED 1
#define XED_IFORM_AND_MEMv_GPRv_DEFINED 1
#define XED_IFORM_AND_MEMv_IMMb_DEFINED 1
#define XED_IFORM_AND_MEMv_IMMz_DEFINED 1
#define XED_IFORM_AND_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_ARPL_GPR16_GPR16_DEFINED 1
#define XED_IFORM_ARPL_MEMw_GPR16_DEFINED 1
#define XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd_DEFINED 1
#define XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd_DEFINED 1
#define XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd_DEFINED 1
#define XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd_DEFINED 1
#define XED_IFORM_BLCFILL_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCFILL_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLCFILL_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCFILL_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_BLCI_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCI_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLCI_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCI_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_BLCIC_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCIC_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLCIC_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCIC_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_BLCMSK_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCMSK_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLCMSK_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCMSK_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_BLCS_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLCS_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLCS_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLCS_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_BLSFILL_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSFILL_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSFILL_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLSFILL_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_BLSI_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSI_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSI_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_BLSI_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BLSIC_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSIC_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSIC_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_BLSIC_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_BLSMSK_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BLSR_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_BLSR_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BLSR_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_BLSR_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_BNDCL_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDCL_BND_GPR32_DEFINED 1
#define XED_IFORM_BNDCL_BND_GPR64_DEFINED 1
#define XED_IFORM_BNDCN_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDCN_BND_GPR32_DEFINED 1
#define XED_IFORM_BNDCN_BND_GPR64_DEFINED 1
#define XED_IFORM_BNDCU_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDCU_BND_GPR32_DEFINED 1
#define XED_IFORM_BNDCU_BND_GPR64_DEFINED 1
#define XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED 1
#define XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED 1
#define XED_IFORM_BNDMK_BND_AGEN_DEFINED 1
#define XED_IFORM_BNDMOV_BND_BND_DEFINED 1
#define XED_IFORM_BNDMOV_BND_MEMdq_DEFINED 1
#define XED_IFORM_BNDMOV_BND_MEMq_DEFINED 1
#define XED_IFORM_BNDMOV_MEMdq_BND_DEFINED 1
#define XED_IFORM_BNDMOV_MEMq_BND_DEFINED 1
#define XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED 1
#define XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED 1
#define XED_IFORM_BOUND_GPRv_MEMa16_DEFINED 1
#define XED_IFORM_BOUND_GPRv_MEMa32_DEFINED 1
#define XED_IFORM_BSF_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BSF_GPRv_MEMv_DEFINED 1
#define XED_IFORM_BSR_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BSR_GPRv_MEMv_DEFINED 1
#define XED_IFORM_BSWAP_GPRv_DEFINED 1
#define XED_IFORM_BT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BT_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BT_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BT_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTC_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BTC_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BTC_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTC_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTR_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BTR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BTR_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTS_GPRv_GPRv_DEFINED 1
#define XED_IFORM_BTS_GPRv_IMMb_DEFINED 1
#define XED_IFORM_BTS_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTS_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_CALL_FAR_MEMp2_DEFINED 1
#define XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED 1
#define XED_IFORM_CALL_NEAR_GPRv_DEFINED 1
#define XED_IFORM_CALL_NEAR_MEMv_DEFINED 1
#define XED_IFORM_CALL_NEAR_RELBRd_DEFINED 1
#define XED_IFORM_CALL_NEAR_RELBRz_DEFINED 1
#define XED_IFORM_CBW_DEFINED 1
#define XED_IFORM_CDQ_DEFINED 1
#define XED_IFORM_CDQE_DEFINED 1
#define XED_IFORM_CLAC_DEFINED 1
#define XED_IFORM_CLC_DEFINED 1
#define XED_IFORM_CLD_DEFINED 1
#define XED_IFORM_CLDEMOTE_MEMu8_DEFINED 1
#define XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED 1
#define XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED 1
#define XED_IFORM_CLGI_DEFINED 1
#define XED_IFORM_CLI_DEFINED 1
#define XED_IFORM_CLRSSBSY_MEMu64_DEFINED 1
#define XED_IFORM_CLTS_DEFINED 1
#define XED_IFORM_CLUI_DEFINED 1
#define XED_IFORM_CLWB_MEMmprefetch_DEFINED 1
#define XED_IFORM_CLZERO_DEFINED 1
#define XED_IFORM_CMC_DEFINED 1
#define XED_IFORM_CMOVB_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVL_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVL_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVO_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVO_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVP_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVP_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVS_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVS_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMP_AL_IMMb_DEFINED 1
#define XED_IFORM_CMP_GPR8_GPR8_38_DEFINED 1
#define XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED 1
#define XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED 1
#define XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED 1
#define XED_IFORM_CMP_GPR8_MEMb_DEFINED 1
#define XED_IFORM_CMP_GPRv_GPRv_39_DEFINED 1
#define XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED 1
#define XED_IFORM_CMP_GPRv_IMMb_DEFINED 1
#define XED_IFORM_CMP_GPRv_IMMz_DEFINED 1
#define XED_IFORM_CMP_GPRv_MEMv_DEFINED 1
#define XED_IFORM_CMP_MEMb_GPR8_DEFINED 1
#define XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED 1
#define XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED 1
#define XED_IFORM_CMP_MEMv_GPRv_DEFINED 1
#define XED_IFORM_CMP_MEMv_IMMb_DEFINED 1
#define XED_IFORM_CMP_MEMv_IMMz_DEFINED 1
#define XED_IFORM_CMP_OrAX_IMMz_DEFINED 1
#define XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED 1
#define XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED 1
#define XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED 1
#define XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_CMPSB_DEFINED 1
#define XED_IFORM_CMPSD_DEFINED 1
#define XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED 1
#define XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED 1
#define XED_IFORM_CMPSQ_DEFINED 1
#define XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED 1
#define XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED 1
#define XED_IFORM_CMPSW_DEFINED 1
#define XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED 1
#define XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED 1
#define XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED 1
#define XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED 1
#define XED_IFORM_CMPXCHG16B_MEMdq_DEFINED 1
#define XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED 1
#define XED_IFORM_CMPXCHG8B_MEMq_DEFINED 1
#define XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED 1
#define XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_COMISS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_COMISS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_CPUID_DEFINED 1
#define XED_IFORM_CQO_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_GPRv_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_MEMb_DEFINED 1
#define XED_IFORM_CRC32_GPRyy_MEMv_DEFINED 1
#define XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED 1
#define XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED 1
#define XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED 1
#define XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED 1
#define XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED 1
#define XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED 1
#define XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED 1
#define XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED 1
#define XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED 1
#define XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED 1
#define XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED 1
#define XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED 1
#define XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED 1
#define XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED 1
#define XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED 1
#define XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED 1
#define XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED 1
#define XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED 1
#define XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED 1
#define XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED 1
#define XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED 1
#define XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED 1
#define XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED 1
#define XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED 1
#define XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED 1
#define XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED 1
#define XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED 1
#define XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED 1
#define XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED 1
#define XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED 1
#define XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED 1
#define XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED 1
#define XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED 1
#define XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED 1
#define XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED 1
#define XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED 1
#define XED_IFORM_CWD_DEFINED 1
#define XED_IFORM_CWDE_DEFINED 1
#define XED_IFORM_DAA_DEFINED 1
#define XED_IFORM_DAS_DEFINED 1
#define XED_IFORM_DEC_GPR8_DEFINED 1
#define XED_IFORM_DEC_GPRv_48_DEFINED 1
#define XED_IFORM_DEC_GPRv_FFr1_DEFINED 1
#define XED_IFORM_DEC_MEMb_DEFINED 1
#define XED_IFORM_DEC_MEMv_DEFINED 1
#define XED_IFORM_DEC_LOCK_MEMb_DEFINED 1
#define XED_IFORM_DEC_LOCK_MEMv_DEFINED 1
#define XED_IFORM_DIV_GPR8_DEFINED 1
#define XED_IFORM_DIV_GPRv_DEFINED 1
#define XED_IFORM_DIV_MEMb_DEFINED 1
#define XED_IFORM_DIV_MEMv_DEFINED 1
#define XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_DIVPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_DIVPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_DIVSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_DIVSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_EMMS_DEFINED 1
#define XED_IFORM_ENCLS_DEFINED 1
#define XED_IFORM_ENCLU_DEFINED 1
#define XED_IFORM_ENCLV_DEFINED 1
#define XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_DEFINED 1
#define XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_DEFINED 1
#define XED_IFORM_ENDBR32_DEFINED 1
#define XED_IFORM_ENDBR64_DEFINED 1
#define XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED 1
#define XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED 1
#define XED_IFORM_ENTER_IMMw_IMMb_DEFINED 1
#define XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED 1
#define XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED 1
#define XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED 1
#define XED_IFORM_F2XM1_DEFINED 1
#define XED_IFORM_FABS_DEFINED 1
#define XED_IFORM_FADD_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FADD_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FADD_ST0_X87_DEFINED 1
#define XED_IFORM_FADD_X87_ST0_DEFINED 1
#define XED_IFORM_FADDP_X87_ST0_DEFINED 1
#define XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED 1
#define XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED 1
#define XED_IFORM_FCHS_DEFINED 1
#define XED_IFORM_FCMOVB_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVBE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNB_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNBE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNE_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVNU_ST0_X87_DEFINED 1
#define XED_IFORM_FCMOVU_ST0_X87_DEFINED 1
#define XED_IFORM_FCOM_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FCOM_ST0_X87_DEFINED 1
#define XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED 1
#define XED_IFORM_FCOMI_ST0_X87_DEFINED 1
#define XED_IFORM_FCOMIP_ST0_X87_DEFINED 1
#define XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FCOMP_ST0_X87_DEFINED 1
#define XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED 1
#define XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED 1
#define XED_IFORM_FCOMPP_DEFINED 1
#define XED_IFORM_FCOS_DEFINED 1
#define XED_IFORM_FDECSTP_DEFINED 1
#define XED_IFORM_FDISI8087_NOP_DEFINED 1
#define XED_IFORM_FDIV_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FDIV_ST0_X87_DEFINED 1
#define XED_IFORM_FDIV_X87_ST0_DEFINED 1
#define XED_IFORM_FDIVP_X87_ST0_DEFINED 1
#define XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FDIVR_ST0_X87_DEFINED 1
#define XED_IFORM_FDIVR_X87_ST0_DEFINED 1
#define XED_IFORM_FDIVRP_X87_ST0_DEFINED 1
#define XED_IFORM_FEMMS_DEFINED 1
#define XED_IFORM_FENI8087_NOP_DEFINED 1
#define XED_IFORM_FFREE_X87_DEFINED 1
#define XED_IFORM_FFREEP_X87_DEFINED 1
#define XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FILD_ST0_MEMm64int_DEFINED 1
#define XED_IFORM_FILD_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FILD_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FINCSTP_DEFINED 1
#define XED_IFORM_FIST_MEMmem16int_ST0_DEFINED 1
#define XED_IFORM_FIST_MEMmem32int_ST0_DEFINED 1
#define XED_IFORM_FISTP_MEMm64int_ST0_DEFINED 1
#define XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED 1
#define XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED 1
#define XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED 1
#define XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED 1
#define XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED 1
#define XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED 1
#define XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED 1
#define XED_IFORM_FLD_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FLD_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FLD_ST0_MEMmem80real_DEFINED 1
#define XED_IFORM_FLD_ST0_X87_DEFINED 1
#define XED_IFORM_FLD1_DEFINED 1
#define XED_IFORM_FLDCW_MEMmem16_DEFINED 1
#define XED_IFORM_FLDENV_MEMmem14_DEFINED 1
#define XED_IFORM_FLDENV_MEMmem28_DEFINED 1
#define XED_IFORM_FLDL2E_DEFINED 1
#define XED_IFORM_FLDL2T_DEFINED 1
#define XED_IFORM_FLDLG2_DEFINED 1
#define XED_IFORM_FLDLN2_DEFINED 1
#define XED_IFORM_FLDPI_DEFINED 1
#define XED_IFORM_FLDZ_DEFINED 1
#define XED_IFORM_FMUL_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FMUL_ST0_X87_DEFINED 1
#define XED_IFORM_FMUL_X87_ST0_DEFINED 1
#define XED_IFORM_FMULP_X87_ST0_DEFINED 1
#define XED_IFORM_FNCLEX_DEFINED 1
#define XED_IFORM_FNINIT_DEFINED 1
#define XED_IFORM_FNOP_DEFINED 1
#define XED_IFORM_FNSAVE_MEMmem108_DEFINED 1
#define XED_IFORM_FNSAVE_MEMmem94_DEFINED 1
#define XED_IFORM_FNSTCW_MEMmem16_DEFINED 1
#define XED_IFORM_FNSTENV_MEMmem14_DEFINED 1
#define XED_IFORM_FNSTENV_MEMmem28_DEFINED 1
#define XED_IFORM_FNSTSW_AX_DEFINED 1
#define XED_IFORM_FNSTSW_MEMmem16_DEFINED 1
#define XED_IFORM_FPATAN_DEFINED 1
#define XED_IFORM_FPREM_DEFINED 1
#define XED_IFORM_FPREM1_DEFINED 1
#define XED_IFORM_FPTAN_DEFINED 1
#define XED_IFORM_FRNDINT_DEFINED 1
#define XED_IFORM_FRSTOR_MEMmem108_DEFINED 1
#define XED_IFORM_FRSTOR_MEMmem94_DEFINED 1
#define XED_IFORM_FSCALE_DEFINED 1
#define XED_IFORM_FSETPM287_NOP_DEFINED 1
#define XED_IFORM_FSIN_DEFINED 1
#define XED_IFORM_FSINCOS_DEFINED 1
#define XED_IFORM_FSQRT_DEFINED 1
#define XED_IFORM_FST_MEMm64real_ST0_DEFINED 1
#define XED_IFORM_FST_MEMmem32real_ST0_DEFINED 1
#define XED_IFORM_FST_X87_ST0_DEFINED 1
#define XED_IFORM_FSTP_MEMm64real_ST0_DEFINED 1
#define XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED 1
#define XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED 1
#define XED_IFORM_FSTP_X87_ST0_DEFINED 1
#define XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED 1
#define XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED 1
#define XED_IFORM_FSTPNCE_X87_ST0_DEFINED 1
#define XED_IFORM_FSUB_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FSUB_ST0_X87_DEFINED 1
#define XED_IFORM_FSUB_X87_ST0_DEFINED 1
#define XED_IFORM_FSUBP_X87_ST0_DEFINED 1
#define XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED 1
#define XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED 1
#define XED_IFORM_FSUBR_ST0_X87_DEFINED 1
#define XED_IFORM_FSUBR_X87_ST0_DEFINED 1
#define XED_IFORM_FSUBRP_X87_ST0_DEFINED 1
#define XED_IFORM_FTST_DEFINED 1
#define XED_IFORM_FUCOM_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMI_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMIP_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMP_ST0_X87_DEFINED 1
#define XED_IFORM_FUCOMPP_DEFINED 1
#define XED_IFORM_FWAIT_DEFINED 1
#define XED_IFORM_FXAM_DEFINED 1
#define XED_IFORM_FXCH_ST0_X87_DEFINED 1
#define XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED 1
#define XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED 1
#define XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED 1
#define XED_IFORM_FXTRACT_DEFINED 1
#define XED_IFORM_FYL2X_DEFINED 1
#define XED_IFORM_FYL2XP1_DEFINED 1
#define XED_IFORM_GETSEC_DEFINED 1
#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED 1
#define XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_HADDPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_HADDPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_HLT_DEFINED 1
#define XED_IFORM_HRESET_IMM8_DEFINED 1
#define XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_IDIV_GPR8_DEFINED 1
#define XED_IFORM_IDIV_GPRv_DEFINED 1
#define XED_IFORM_IDIV_MEMb_DEFINED 1
#define XED_IFORM_IDIV_MEMv_DEFINED 1
#define XED_IFORM_IMUL_GPR8_DEFINED 1
#define XED_IFORM_IMUL_GPRv_DEFINED 1
#define XED_IFORM_IMUL_GPRv_GPRv_DEFINED 1
#define XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED 1
#define XED_IFORM_IMUL_GPRv_MEMv_DEFINED 1
#define XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED 1
#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED 1
#define XED_IFORM_IMUL_MEMb_DEFINED 1
#define XED_IFORM_IMUL_MEMv_DEFINED 1
#define XED_IFORM_IN_AL_DX_DEFINED 1
#define XED_IFORM_IN_AL_IMMb_DEFINED 1
#define XED_IFORM_IN_OeAX_DX_DEFINED 1
#define XED_IFORM_IN_OeAX_IMMb_DEFINED 1
#define XED_IFORM_INC_GPR8_DEFINED 1
#define XED_IFORM_INC_GPRv_40_DEFINED 1
#define XED_IFORM_INC_GPRv_FFr0_DEFINED 1
#define XED_IFORM_INC_MEMb_DEFINED 1
#define XED_IFORM_INC_MEMv_DEFINED 1
#define XED_IFORM_INCSSPD_GPR32u8_DEFINED 1
#define XED_IFORM_INCSSPQ_GPR64u8_DEFINED 1
#define XED_IFORM_INC_LOCK_MEMb_DEFINED 1
#define XED_IFORM_INC_LOCK_MEMv_DEFINED 1
#define XED_IFORM_INSB_DEFINED 1
#define XED_IFORM_INSD_DEFINED 1
#define XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED 1
#define XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED 1
#define XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED 1
#define XED_IFORM_INSW_DEFINED 1
#define XED_IFORM_INT_IMMb_DEFINED 1
#define XED_IFORM_INT1_DEFINED 1
#define XED_IFORM_INT3_DEFINED 1
#define XED_IFORM_INTO_DEFINED 1
#define XED_IFORM_INVD_DEFINED 1
#define XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED 1
#define XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED 1
#define XED_IFORM_INVLPG_MEMb_DEFINED 1
#define XED_IFORM_INVLPGA_ArAX_ECX_DEFINED 1
#define XED_IFORM_INVLPGB_EAX_EDX_ECX_DEFINED 1
#define XED_IFORM_INVLPGB_RAX_EDX_ECX_DEFINED 1
#define XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED 1
#define XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED 1
#define XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED 1
#define XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED 1
#define XED_IFORM_IRET_DEFINED 1
#define XED_IFORM_IRETD_DEFINED 1
#define XED_IFORM_IRETQ_DEFINED 1
#define XED_IFORM_JB_RELBRb_DEFINED 1
#define XED_IFORM_JB_RELBRd_DEFINED 1
#define XED_IFORM_JB_RELBRz_DEFINED 1
#define XED_IFORM_JBE_RELBRb_DEFINED 1
#define XED_IFORM_JBE_RELBRd_DEFINED 1
#define XED_IFORM_JBE_RELBRz_DEFINED 1
#define XED_IFORM_JCXZ_RELBRb_DEFINED 1
#define XED_IFORM_JECXZ_RELBRb_DEFINED 1
#define XED_IFORM_JL_RELBRb_DEFINED 1
#define XED_IFORM_JL_RELBRd_DEFINED 1
#define XED_IFORM_JL_RELBRz_DEFINED 1
#define XED_IFORM_JLE_RELBRb_DEFINED 1
#define XED_IFORM_JLE_RELBRd_DEFINED 1
#define XED_IFORM_JLE_RELBRz_DEFINED 1
#define XED_IFORM_JMP_GPRv_DEFINED 1
#define XED_IFORM_JMP_MEMv_DEFINED 1
#define XED_IFORM_JMP_RELBRb_DEFINED 1
#define XED_IFORM_JMP_RELBRd_DEFINED 1
#define XED_IFORM_JMP_RELBRz_DEFINED 1
#define XED_IFORM_JMP_FAR_MEMp2_DEFINED 1
#define XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED 1
#define XED_IFORM_JNB_RELBRb_DEFINED 1
#define XED_IFORM_JNB_RELBRd_DEFINED 1
#define XED_IFORM_JNB_RELBRz_DEFINED 1
#define XED_IFORM_JNBE_RELBRb_DEFINED 1
#define XED_IFORM_JNBE_RELBRd_DEFINED 1
#define XED_IFORM_JNBE_RELBRz_DEFINED 1
#define XED_IFORM_JNL_RELBRb_DEFINED 1
#define XED_IFORM_JNL_RELBRd_DEFINED 1
#define XED_IFORM_JNL_RELBRz_DEFINED 1
#define XED_IFORM_JNLE_RELBRb_DEFINED 1
#define XED_IFORM_JNLE_RELBRd_DEFINED 1
#define XED_IFORM_JNLE_RELBRz_DEFINED 1
#define XED_IFORM_JNO_RELBRb_DEFINED 1
#define XED_IFORM_JNO_RELBRd_DEFINED 1
#define XED_IFORM_JNO_RELBRz_DEFINED 1
#define XED_IFORM_JNP_RELBRb_DEFINED 1
#define XED_IFORM_JNP_RELBRd_DEFINED 1
#define XED_IFORM_JNP_RELBRz_DEFINED 1
#define XED_IFORM_JNS_RELBRb_DEFINED 1
#define XED_IFORM_JNS_RELBRd_DEFINED 1
#define XED_IFORM_JNS_RELBRz_DEFINED 1
#define XED_IFORM_JNZ_RELBRb_DEFINED 1
#define XED_IFORM_JNZ_RELBRd_DEFINED 1
#define XED_IFORM_JNZ_RELBRz_DEFINED 1
#define XED_IFORM_JO_RELBRb_DEFINED 1
#define XED_IFORM_JO_RELBRd_DEFINED 1
#define XED_IFORM_JO_RELBRz_DEFINED 1
#define XED_IFORM_JP_RELBRb_DEFINED 1
#define XED_IFORM_JP_RELBRd_DEFINED 1
#define XED_IFORM_JP_RELBRz_DEFINED 1
#define XED_IFORM_JRCXZ_RELBRb_DEFINED 1
#define XED_IFORM_JS_RELBRb_DEFINED 1
#define XED_IFORM_JS_RELBRd_DEFINED 1
#define XED_IFORM_JS_RELBRz_DEFINED 1
#define XED_IFORM_JZ_RELBRb_DEFINED 1
#define XED_IFORM_JZ_RELBRd_DEFINED 1
#define XED_IFORM_JZ_RELBRz_DEFINED 1
#define XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1
#define XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_LAHF_DEFINED 1
#define XED_IFORM_LAR_GPRv_GPRv_DEFINED 1
#define XED_IFORM_LAR_GPRv_MEMw_DEFINED 1
#define XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED 1
#define XED_IFORM_LDMXCSR_MEMd_DEFINED 1
#define XED_IFORM_LDS_GPRz_MEMp_DEFINED 1
#define XED_IFORM_LDTILECFG_MEM_DEFINED 1
#define XED_IFORM_LEA_GPRv_AGEN_DEFINED 1
#define XED_IFORM_LEAVE_DEFINED 1
#define XED_IFORM_LES_GPRz_MEMp_DEFINED 1
#define XED_IFORM_LFENCE_DEFINED 1
#define XED_IFORM_LFS_GPRv_MEMp2_DEFINED 1
#define XED_IFORM_LGDT_MEMs_DEFINED 1
#define XED_IFORM_LGDT_MEMs64_DEFINED 1
#define XED_IFORM_LGS_GPRv_MEMp2_DEFINED 1
#define XED_IFORM_LIDT_MEMs_DEFINED 1
#define XED_IFORM_LIDT_MEMs64_DEFINED 1
#define XED_IFORM_LLDT_GPR16_DEFINED 1
#define XED_IFORM_LLDT_MEMw_DEFINED 1
#define XED_IFORM_LLWPCB_VGPRyy_DEFINED 1
#define XED_IFORM_LMSW_GPR16_DEFINED 1
#define XED_IFORM_LMSW_MEMw_DEFINED 1
#define XED_IFORM_LOADIWKEY_XMMu8_XMMu8_DEFINED 1
#define XED_IFORM_LODSB_DEFINED 1
#define XED_IFORM_LODSD_DEFINED 1
#define XED_IFORM_LODSQ_DEFINED 1
#define XED_IFORM_LODSW_DEFINED 1
#define XED_IFORM_LOOP_RELBRb_DEFINED 1
#define XED_IFORM_LOOPE_RELBRb_DEFINED 1
#define XED_IFORM_LOOPNE_RELBRb_DEFINED 1
#define XED_IFORM_LSL_GPRv_GPRz_DEFINED 1
#define XED_IFORM_LSL_GPRv_MEMw_DEFINED 1
#define XED_IFORM_LSS_GPRv_MEMp2_DEFINED 1
#define XED_IFORM_LTR_GPR16_DEFINED 1
#define XED_IFORM_LTR_MEMw_DEFINED 1
#define XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd_DEFINED 1
#define XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd_DEFINED 1
#define XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd_DEFINED 1
#define XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd_DEFINED 1
#define XED_IFORM_LZCNT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_LZCNT_GPRv_MEMv_DEFINED 1
#define XED_IFORM_MASKMOVDQU_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_MAXPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MAXPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_MAXSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_MAXSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_MCOMMIT_DEFINED 1
#define XED_IFORM_MFENCE_DEFINED 1
#define XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_MINPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MINPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_MINSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_MINSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_MONITOR_DEFINED 1
#define XED_IFORM_MONITORX_DEFINED 1
#define XED_IFORM_MOV_AL_MEMb_DEFINED 1
#define XED_IFORM_MOV_GPR8_GPR8_88_DEFINED 1
#define XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED 1
#define XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED 1
#define XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED 1
#define XED_IFORM_MOV_GPR8_MEMb_DEFINED 1
#define XED_IFORM_MOV_GPRv_GPRv_89_DEFINED 1
#define XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED 1
#define XED_IFORM_MOV_GPRv_IMMv_DEFINED 1
#define XED_IFORM_MOV_GPRv_IMMz_DEFINED 1
#define XED_IFORM_MOV_GPRv_MEMv_DEFINED 1
#define XED_IFORM_MOV_GPRv_SEG_DEFINED 1
#define XED_IFORM_MOV_MEMb_AL_DEFINED 1
#define XED_IFORM_MOV_MEMb_GPR8_DEFINED 1
#define XED_IFORM_MOV_MEMb_IMMb_DEFINED 1
#define XED_IFORM_MOV_MEMv_GPRv_DEFINED 1
#define XED_IFORM_MOV_MEMv_IMMz_DEFINED 1
#define XED_IFORM_MOV_MEMv_OrAX_DEFINED 1
#define XED_IFORM_MOV_MEMw_SEG_DEFINED 1
#define XED_IFORM_MOV_OrAX_MEMv_DEFINED 1
#define XED_IFORM_MOV_SEG_GPR16_DEFINED 1
#define XED_IFORM_MOV_SEG_MEMw_DEFINED 1
#define XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED 1
#define XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED 1
#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED 1
#define XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED 1
#define XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED 1
#define XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED 1
#define XED_IFORM_MOVBE_GPRv_MEMv_DEFINED 1
#define XED_IFORM_MOVBE_MEMv_GPRv_DEFINED 1
#define XED_IFORM_MOVD_GPR32_MMXd_DEFINED 1
#define XED_IFORM_MOVD_GPR32_XMMd_DEFINED 1
#define XED_IFORM_MOVD_MEMd_MMXd_DEFINED 1
#define XED_IFORM_MOVD_MEMd_XMMd_DEFINED 1
#define XED_IFORM_MOVD_MMXq_GPR32_DEFINED 1
#define XED_IFORM_MOVD_MMXq_MEMd_DEFINED 1
#define XED_IFORM_MOVD_XMMdq_GPR32_DEFINED 1
#define XED_IFORM_MOVD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED 1
#define XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED 1
#define XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED 1
#define XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED 1
#define XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED 1
#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED 1
#define XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED 1
#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED 1
#define XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED 1
#define XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED 1
#define XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED 1
#define XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED 1
#define XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED 1
#define XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED 1
#define XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED 1
#define XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED 1
#define XED_IFORM_MOVLPS_MEMq_XMMq_DEFINED 1
#define XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED 1
#define XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED 1
#define XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED 1
#define XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED 1
#define XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED 1
#define XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED 1
#define XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED 1
#define XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED 1
#define XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED 1
#define XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED 1
#define XED_IFORM_MOVQ_GPR64_MMXq_DEFINED 1
#define XED_IFORM_MOVQ_GPR64_XMMq_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_GPR64_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED 1
#define XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED 1
#define XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED 1
#define XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED 1
#define XED_IFORM_MOVSB_DEFINED 1
#define XED_IFORM_MOVSD_DEFINED 1
#define XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED 1
#define XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED 1
#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED 1
#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED 1
#define XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MOVSQ_DEFINED 1
#define XED_IFORM_MOVSS_MEMss_XMMss_DEFINED 1
#define XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED 1
#define XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED 1
#define XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED 1
#define XED_IFORM_MOVSW_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_GPR16_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_GPR8_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_MEMb_DEFINED 1
#define XED_IFORM_MOVSX_GPRv_MEMw_DEFINED 1
#define XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED 1
#define XED_IFORM_MOVSXD_GPRv_MEMz_DEFINED 1
#define XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED 1
#define XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED 1
#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED 1
#define XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED 1
#define XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED 1
#define XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_GPR16_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_GPR8_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_MEMb_DEFINED 1
#define XED_IFORM_MOVZX_GPRv_MEMw_DEFINED 1
#define XED_IFORM_MOV_CR_CR_GPR32_DEFINED 1
#define XED_IFORM_MOV_CR_CR_GPR64_DEFINED 1
#define XED_IFORM_MOV_CR_GPR32_CR_DEFINED 1
#define XED_IFORM_MOV_CR_GPR64_CR_DEFINED 1
#define XED_IFORM_MOV_DR_DR_GPR32_DEFINED 1
#define XED_IFORM_MOV_DR_DR_GPR64_DEFINED 1
#define XED_IFORM_MOV_DR_GPR32_DR_DEFINED 1
#define XED_IFORM_MOV_DR_GPR64_DR_DEFINED 1
#define XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_MUL_GPR8_DEFINED 1
#define XED_IFORM_MUL_GPRv_DEFINED 1
#define XED_IFORM_MUL_MEMb_DEFINED 1
#define XED_IFORM_MUL_MEMv_DEFINED 1
#define XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_MULPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_MULPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_MULSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_MULSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_MWAIT_DEFINED 1
#define XED_IFORM_MWAITX_DEFINED 1
#define XED_IFORM_NEG_GPR8_DEFINED 1
#define XED_IFORM_NEG_GPRv_DEFINED 1
#define XED_IFORM_NEG_MEMb_DEFINED 1
#define XED_IFORM_NEG_MEMv_DEFINED 1
#define XED_IFORM_NEG_LOCK_MEMb_DEFINED 1
#define XED_IFORM_NEG_LOCK_MEMv_DEFINED 1
#define XED_IFORM_NOP_90_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r0_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r1_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r2_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r3_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r4_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r5_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r6_DEFINED 1
#define XED_IFORM_NOP_GPRv_0F18r7_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED 1
#define XED_IFORM_NOP_GPRv_GPRv_0F1F_DEFINED 1
#define XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED 1
#define XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r5_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r6_DEFINED 1
#define XED_IFORM_NOP_MEMv_0F18r7_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED 1
#define XED_IFORM_NOP_MEMv_GPRv_0F1F_DEFINED 1
#define XED_IFORM_NOT_GPR8_DEFINED 1
#define XED_IFORM_NOT_GPRv_DEFINED 1
#define XED_IFORM_NOT_MEMb_DEFINED 1
#define XED_IFORM_NOT_MEMv_DEFINED 1
#define XED_IFORM_NOT_LOCK_MEMb_DEFINED 1
#define XED_IFORM_NOT_LOCK_MEMv_DEFINED 1
#define XED_IFORM_OR_AL_IMMb_DEFINED 1
#define XED_IFORM_OR_GPR8_GPR8_08_DEFINED 1
#define XED_IFORM_OR_GPR8_GPR8_0A_DEFINED 1
#define XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED 1
#define XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED 1
#define XED_IFORM_OR_GPR8_MEMb_DEFINED 1
#define XED_IFORM_OR_GPRv_GPRv_09_DEFINED 1
#define XED_IFORM_OR_GPRv_GPRv_0B_DEFINED 1
#define XED_IFORM_OR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_OR_GPRv_IMMz_DEFINED 1
#define XED_IFORM_OR_GPRv_MEMv_DEFINED 1
#define XED_IFORM_OR_MEMb_GPR8_DEFINED 1
#define XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED 1
#define XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED 1
#define XED_IFORM_OR_MEMv_GPRv_DEFINED 1
#define XED_IFORM_OR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_OR_MEMv_IMMz_DEFINED 1
#define XED_IFORM_OR_OrAX_IMMz_DEFINED 1
#define XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_OUT_DX_AL_DEFINED 1
#define XED_IFORM_OUT_DX_OeAX_DEFINED 1
#define XED_IFORM_OUT_IMMb_AL_DEFINED 1
#define XED_IFORM_OUT_IMMb_OeAX_DEFINED 1
#define XED_IFORM_OUTSB_DEFINED 1
#define XED_IFORM_OUTSD_DEFINED 1
#define XED_IFORM_OUTSW_DEFINED 1
#define XED_IFORM_PABSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PABSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PABSD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PABSD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PABSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PABSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PADDW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PADDW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PAND_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAND_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAND_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PAND_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PANDN_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PANDN_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PAUSE_DEFINED 1
#define XED_IFORM_PAVGB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAVGB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAVGW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PAVGW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PCONFIG_DEFINED 1
#define XED_IFORM_PCONFIG64_DEFINED 1
#define XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq_DEFINED 1
#define XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PF2ID_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PF2ID_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PF2IW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PF2IW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFACC_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFACC_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFADD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFADD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFMAX_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFMAX_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFMIN_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFMIN_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFMUL_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFMUL_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFNACC_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFNACC_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRCP_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRCP_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFSUB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFSUB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHADDD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHADDW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHADDW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PI2FD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PI2FD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PI2FW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PI2FW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED 1
#define XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED 1
#define XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED 1
#define XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED 1
#define XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMINSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINUB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMINUB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED 1
#define XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED 1
#define XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULHW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULHW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULLW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULLW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_POP_DS_DEFINED 1
#define XED_IFORM_POP_ES_DEFINED 1
#define XED_IFORM_POP_FS_DEFINED 1
#define XED_IFORM_POP_GPRv_58_DEFINED 1
#define XED_IFORM_POP_GPRv_8F_DEFINED 1
#define XED_IFORM_POP_GS_DEFINED 1
#define XED_IFORM_POP_MEMv_DEFINED 1
#define XED_IFORM_POP_SS_DEFINED 1
#define XED_IFORM_POPA_DEFINED 1
#define XED_IFORM_POPAD_DEFINED 1
#define XED_IFORM_POPCNT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_POPCNT_GPRv_MEMv_DEFINED 1
#define XED_IFORM_POPF_DEFINED 1
#define XED_IFORM_POPFD_DEFINED 1
#define XED_IFORM_POPFQ_DEFINED 1
#define XED_IFORM_POR_MMXq_MEMq_DEFINED 1
#define XED_IFORM_POR_MMXq_MMXq_DEFINED 1
#define XED_IFORM_POR_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_POR_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCHW_0F0Dr1_DEFINED 1
#define XED_IFORM_PREFETCHW_0F0Dr3_DEFINED 1
#define XED_IFORM_PREFETCHWT1_MEMu8_DEFINED 1
#define XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED 1
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED 1
#define XED_IFORM_PSADBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSADBW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSIGND_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSIGND_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSLLD_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSLLD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSLLD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSLLW_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSLLW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSLLW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSMASH_RAX_DEFINED 1
#define XED_IFORM_PSRAD_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRAD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRAD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRAW_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRAW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRAW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRLD_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRLD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRLD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSRLW_MMXq_IMMb_DEFINED 1
#define XED_IFORM_PSRLW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSRLW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSUBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSUBW_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_PTWRITE_GPRy_DEFINED 1
#define XED_IFORM_PTWRITE_MEMy_DEFINED 1
#define XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED 1
#define XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED 1
#define XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED 1
#define XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_PUSH_CS_DEFINED 1
#define XED_IFORM_PUSH_DS_DEFINED 1
#define XED_IFORM_PUSH_ES_DEFINED 1
#define XED_IFORM_PUSH_FS_DEFINED 1
#define XED_IFORM_PUSH_GPRv_50_DEFINED 1
#define XED_IFORM_PUSH_GPRv_FFr6_DEFINED 1
#define XED_IFORM_PUSH_GS_DEFINED 1
#define XED_IFORM_PUSH_IMMb_DEFINED 1
#define XED_IFORM_PUSH_IMMz_DEFINED 1
#define XED_IFORM_PUSH_MEMv_DEFINED 1
#define XED_IFORM_PUSH_SS_DEFINED 1
#define XED_IFORM_PUSHA_DEFINED 1
#define XED_IFORM_PUSHAD_DEFINED 1
#define XED_IFORM_PUSHF_DEFINED 1
#define XED_IFORM_PUSHFD_DEFINED 1
#define XED_IFORM_PUSHFQ_DEFINED 1
#define XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED 1
#define XED_IFORM_PXOR_MMXq_MEMq_DEFINED 1
#define XED_IFORM_PXOR_MMXq_MMXq_DEFINED 1
#define XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_RCL_GPR8_CL_DEFINED 1
#define XED_IFORM_RCL_GPR8_IMMb_DEFINED 1
#define XED_IFORM_RCL_GPR8_ONE_DEFINED 1
#define XED_IFORM_RCL_GPRv_CL_DEFINED 1
#define XED_IFORM_RCL_GPRv_IMMb_DEFINED 1
#define XED_IFORM_RCL_GPRv_ONE_DEFINED 1
#define XED_IFORM_RCL_MEMb_CL_DEFINED 1
#define XED_IFORM_RCL_MEMb_IMMb_DEFINED 1
#define XED_IFORM_RCL_MEMb_ONE_DEFINED 1
#define XED_IFORM_RCL_MEMv_CL_DEFINED 1
#define XED_IFORM_RCL_MEMv_IMMb_DEFINED 1
#define XED_IFORM_RCL_MEMv_ONE_DEFINED 1
#define XED_IFORM_RCPPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_RCPPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_RCPSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_RCPSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_RCR_GPR8_CL_DEFINED 1
#define XED_IFORM_RCR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_RCR_GPR8_ONE_DEFINED 1
#define XED_IFORM_RCR_GPRv_CL_DEFINED 1
#define XED_IFORM_RCR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_RCR_GPRv_ONE_DEFINED 1
#define XED_IFORM_RCR_MEMb_CL_DEFINED 1
#define XED_IFORM_RCR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_RCR_MEMb_ONE_DEFINED 1
#define XED_IFORM_RCR_MEMv_CL_DEFINED 1
#define XED_IFORM_RCR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_RCR_MEMv_ONE_DEFINED 1
#define XED_IFORM_RDFSBASE_GPRy_DEFINED 1
#define XED_IFORM_RDGSBASE_GPRy_DEFINED 1
#define XED_IFORM_RDMSR_DEFINED 1
#define XED_IFORM_RDPID_GPR32u32_DEFINED 1
#define XED_IFORM_RDPID_GPR64u64_DEFINED 1
#define XED_IFORM_RDPKRU_DEFINED 1
#define XED_IFORM_RDPMC_DEFINED 1
#define XED_IFORM_RDPRU_DEFINED 1
#define XED_IFORM_RDRAND_GPRv_DEFINED 1
#define XED_IFORM_RDSEED_GPRv_DEFINED 1
#define XED_IFORM_RDSSPD_GPR32u32_DEFINED 1
#define XED_IFORM_RDSSPQ_GPR64u64_DEFINED 1
#define XED_IFORM_RDTSC_DEFINED 1
#define XED_IFORM_RDTSCP_DEFINED 1
#define XED_IFORM_REPE_CMPSB_DEFINED 1
#define XED_IFORM_REPE_CMPSD_DEFINED 1
#define XED_IFORM_REPE_CMPSQ_DEFINED 1
#define XED_IFORM_REPE_CMPSW_DEFINED 1
#define XED_IFORM_REPE_SCASB_DEFINED 1
#define XED_IFORM_REPE_SCASD_DEFINED 1
#define XED_IFORM_REPE_SCASQ_DEFINED 1
#define XED_IFORM_REPE_SCASW_DEFINED 1
#define XED_IFORM_REPNE_CMPSB_DEFINED 1
#define XED_IFORM_REPNE_CMPSD_DEFINED 1
#define XED_IFORM_REPNE_CMPSQ_DEFINED 1
#define XED_IFORM_REPNE_CMPSW_DEFINED 1
#define XED_IFORM_REPNE_SCASB_DEFINED 1
#define XED_IFORM_REPNE_SCASD_DEFINED 1
#define XED_IFORM_REPNE_SCASQ_DEFINED 1
#define XED_IFORM_REPNE_SCASW_DEFINED 1
#define XED_IFORM_REP_INSB_DEFINED 1
#define XED_IFORM_REP_INSD_DEFINED 1
#define XED_IFORM_REP_INSW_DEFINED 1
#define XED_IFORM_REP_LODSB_DEFINED 1
#define XED_IFORM_REP_LODSD_DEFINED 1
#define XED_IFORM_REP_LODSQ_DEFINED 1
#define XED_IFORM_REP_LODSW_DEFINED 1
#define XED_IFORM_REP_MONTMUL_DEFINED 1
#define XED_IFORM_REP_MOVSB_DEFINED 1
#define XED_IFORM_REP_MOVSD_DEFINED 1
#define XED_IFORM_REP_MOVSQ_DEFINED 1
#define XED_IFORM_REP_MOVSW_DEFINED 1
#define XED_IFORM_REP_OUTSB_DEFINED 1
#define XED_IFORM_REP_OUTSD_DEFINED 1
#define XED_IFORM_REP_OUTSW_DEFINED 1
#define XED_IFORM_REP_STOSB_DEFINED 1
#define XED_IFORM_REP_STOSD_DEFINED 1
#define XED_IFORM_REP_STOSQ_DEFINED 1
#define XED_IFORM_REP_STOSW_DEFINED 1
#define XED_IFORM_REP_XCRYPTCBC_DEFINED 1
#define XED_IFORM_REP_XCRYPTCFB_DEFINED 1
#define XED_IFORM_REP_XCRYPTCTR_DEFINED 1
#define XED_IFORM_REP_XCRYPTECB_DEFINED 1
#define XED_IFORM_REP_XCRYPTOFB_DEFINED 1
#define XED_IFORM_REP_XSHA1_DEFINED 1
#define XED_IFORM_REP_XSHA256_DEFINED 1
#define XED_IFORM_REP_XSTORE_DEFINED 1
#define XED_IFORM_RET_FAR_DEFINED 1
#define XED_IFORM_RET_FAR_IMMw_DEFINED 1
#define XED_IFORM_RET_NEAR_DEFINED 1
#define XED_IFORM_RET_NEAR_IMMw_DEFINED 1
#define XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED 1
#define XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED 1
#define XED_IFORM_ROL_GPR8_CL_DEFINED 1
#define XED_IFORM_ROL_GPR8_IMMb_DEFINED 1
#define XED_IFORM_ROL_GPR8_ONE_DEFINED 1
#define XED_IFORM_ROL_GPRv_CL_DEFINED 1
#define XED_IFORM_ROL_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ROL_GPRv_ONE_DEFINED 1
#define XED_IFORM_ROL_MEMb_CL_DEFINED 1
#define XED_IFORM_ROL_MEMb_IMMb_DEFINED 1
#define XED_IFORM_ROL_MEMb_ONE_DEFINED 1
#define XED_IFORM_ROL_MEMv_CL_DEFINED 1
#define XED_IFORM_ROL_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ROL_MEMv_ONE_DEFINED 1
#define XED_IFORM_ROR_GPR8_CL_DEFINED 1
#define XED_IFORM_ROR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_ROR_GPR8_ONE_DEFINED 1
#define XED_IFORM_ROR_GPRv_CL_DEFINED 1
#define XED_IFORM_ROR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_ROR_GPRv_ONE_DEFINED 1
#define XED_IFORM_ROR_MEMb_CL_DEFINED 1
#define XED_IFORM_ROR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_ROR_MEMb_ONE_DEFINED 1
#define XED_IFORM_ROR_MEMv_CL_DEFINED 1
#define XED_IFORM_ROR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_ROR_MEMv_ONE_DEFINED 1
#define XED_IFORM_RORX_VGPR32d_MEMd_IMMb_DEFINED 1
#define XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb_DEFINED 1
#define XED_IFORM_RORX_VGPR64q_MEMq_IMMb_DEFINED 1
#define XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED 1
#define XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED 1
#define XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED 1
#define XED_IFORM_RSM_DEFINED 1
#define XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_RSTORSSP_MEMu64_DEFINED 1
#define XED_IFORM_SAHF_DEFINED 1
#define XED_IFORM_SALC_DEFINED 1
#define XED_IFORM_SAR_GPR8_CL_DEFINED 1
#define XED_IFORM_SAR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_SAR_GPR8_ONE_DEFINED 1
#define XED_IFORM_SAR_GPRv_CL_DEFINED 1
#define XED_IFORM_SAR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SAR_GPRv_ONE_DEFINED 1
#define XED_IFORM_SAR_MEMb_CL_DEFINED 1
#define XED_IFORM_SAR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_SAR_MEMb_ONE_DEFINED 1
#define XED_IFORM_SAR_MEMv_CL_DEFINED 1
#define XED_IFORM_SAR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SAR_MEMv_ONE_DEFINED 1
#define XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_SAVEPREVSSP_DEFINED 1
#define XED_IFORM_SBB_AL_IMMb_DEFINED 1
#define XED_IFORM_SBB_GPR8_GPR8_18_DEFINED 1
#define XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED 1
#define XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED 1
#define XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED 1
#define XED_IFORM_SBB_GPR8_MEMb_DEFINED 1
#define XED_IFORM_SBB_GPRv_GPRv_19_DEFINED 1
#define XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED 1
#define XED_IFORM_SBB_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SBB_GPRv_IMMz_DEFINED 1
#define XED_IFORM_SBB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_SBB_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED 1
#define XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED 1
#define XED_IFORM_SBB_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SBB_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SBB_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SBB_OrAX_IMMz_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SCASB_DEFINED 1
#define XED_IFORM_SCASD_DEFINED 1
#define XED_IFORM_SCASQ_DEFINED 1
#define XED_IFORM_SCASW_DEFINED 1
#define XED_IFORM_SEAMCALL_DEFINED 1
#define XED_IFORM_SEAMOPS_DEFINED 1
#define XED_IFORM_SEAMRET_DEFINED 1
#define XED_IFORM_SENDUIPI_GPR32u32_DEFINED 1
#define XED_IFORM_SERIALIZE_DEFINED 1
#define XED_IFORM_SETB_GPR8_DEFINED 1
#define XED_IFORM_SETB_MEMb_DEFINED 1
#define XED_IFORM_SETBE_GPR8_DEFINED 1
#define XED_IFORM_SETBE_MEMb_DEFINED 1
#define XED_IFORM_SETL_GPR8_DEFINED 1
#define XED_IFORM_SETL_MEMb_DEFINED 1
#define XED_IFORM_SETLE_GPR8_DEFINED 1
#define XED_IFORM_SETLE_MEMb_DEFINED 1
#define XED_IFORM_SETNB_GPR8_DEFINED 1
#define XED_IFORM_SETNB_MEMb_DEFINED 1
#define XED_IFORM_SETNBE_GPR8_DEFINED 1
#define XED_IFORM_SETNBE_MEMb_DEFINED 1
#define XED_IFORM_SETNL_GPR8_DEFINED 1
#define XED_IFORM_SETNL_MEMb_DEFINED 1
#define XED_IFORM_SETNLE_GPR8_DEFINED 1
#define XED_IFORM_SETNLE_MEMb_DEFINED 1
#define XED_IFORM_SETNO_GPR8_DEFINED 1
#define XED_IFORM_SETNO_MEMb_DEFINED 1
#define XED_IFORM_SETNP_GPR8_DEFINED 1
#define XED_IFORM_SETNP_MEMb_DEFINED 1
#define XED_IFORM_SETNS_GPR8_DEFINED 1
#define XED_IFORM_SETNS_MEMb_DEFINED 1
#define XED_IFORM_SETNZ_GPR8_DEFINED 1
#define XED_IFORM_SETNZ_MEMb_DEFINED 1
#define XED_IFORM_SETO_GPR8_DEFINED 1
#define XED_IFORM_SETO_MEMb_DEFINED 1
#define XED_IFORM_SETP_GPR8_DEFINED 1
#define XED_IFORM_SETP_MEMb_DEFINED 1
#define XED_IFORM_SETS_GPR8_DEFINED 1
#define XED_IFORM_SETS_MEMb_DEFINED 1
#define XED_IFORM_SETSSBSY_DEFINED 1
#define XED_IFORM_SETZ_GPR8_DEFINED 1
#define XED_IFORM_SETZ_MEMb_DEFINED 1
#define XED_IFORM_SFENCE_DEFINED 1
#define XED_IFORM_SGDT_MEMs_DEFINED 1
#define XED_IFORM_SGDT_MEMs64_DEFINED 1
#define XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED 1
#define XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED 1
#define XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED 1
#define XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED 1
#define XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED 1
#define XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED 1
#define XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED 1
#define XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED 1
#define XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED 1
#define XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED 1
#define XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED 1
#define XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED 1
#define XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED 1
#define XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED 1
#define XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED 1
#define XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED 1
#define XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED 1
#define XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED 1
#define XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED 1
#define XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED 1
#define XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED 1
#define XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED 1
#define XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED 1
#define XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED 1
#define XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED 1
#define XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED 1
#define XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED 1
#define XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_SHR_GPR8_CL_DEFINED 1
#define XED_IFORM_SHR_GPR8_IMMb_DEFINED 1
#define XED_IFORM_SHR_GPR8_ONE_DEFINED 1
#define XED_IFORM_SHR_GPRv_CL_DEFINED 1
#define XED_IFORM_SHR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHR_GPRv_ONE_DEFINED 1
#define XED_IFORM_SHR_MEMb_CL_DEFINED 1
#define XED_IFORM_SHR_MEMb_IMMb_DEFINED 1
#define XED_IFORM_SHR_MEMb_ONE_DEFINED 1
#define XED_IFORM_SHR_MEMv_CL_DEFINED 1
#define XED_IFORM_SHR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SHR_MEMv_ONE_DEFINED 1
#define XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED 1
#define XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d_DEFINED 1
#define XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q_DEFINED 1
#define XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1
#define XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED 1
#define XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED 1
#define XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED 1
#define XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED 1
#define XED_IFORM_SIDT_MEMs_DEFINED 1
#define XED_IFORM_SIDT_MEMs64_DEFINED 1
#define XED_IFORM_SKINIT_EAX_DEFINED 1
#define XED_IFORM_SLDT_GPRv_DEFINED 1
#define XED_IFORM_SLDT_MEMw_DEFINED 1
#define XED_IFORM_SLWPCB_VGPRyy_DEFINED 1
#define XED_IFORM_SMSW_GPRv_DEFINED 1
#define XED_IFORM_SMSW_MEMw_DEFINED 1
#define XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_STAC_DEFINED 1
#define XED_IFORM_STC_DEFINED 1
#define XED_IFORM_STD_DEFINED 1
#define XED_IFORM_STGI_DEFINED 1
#define XED_IFORM_STI_DEFINED 1
#define XED_IFORM_STMXCSR_MEMd_DEFINED 1
#define XED_IFORM_STOSB_DEFINED 1
#define XED_IFORM_STOSD_DEFINED 1
#define XED_IFORM_STOSQ_DEFINED 1
#define XED_IFORM_STOSW_DEFINED 1
#define XED_IFORM_STR_GPRv_DEFINED 1
#define XED_IFORM_STR_MEMw_DEFINED 1
#define XED_IFORM_STTILECFG_MEM_DEFINED 1
#define XED_IFORM_STUI_DEFINED 1
#define XED_IFORM_SUB_AL_IMMb_DEFINED 1
#define XED_IFORM_SUB_GPR8_GPR8_28_DEFINED 1
#define XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED 1
#define XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED 1
#define XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED 1
#define XED_IFORM_SUB_GPR8_MEMb_DEFINED 1
#define XED_IFORM_SUB_GPRv_GPRv_29_DEFINED 1
#define XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED 1
#define XED_IFORM_SUB_GPRv_IMMb_DEFINED 1
#define XED_IFORM_SUB_GPRv_IMMz_DEFINED 1
#define XED_IFORM_SUB_GPRv_MEMv_DEFINED 1
#define XED_IFORM_SUB_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED 1
#define XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED 1
#define XED_IFORM_SUB_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SUB_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SUB_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SUB_OrAX_IMMz_DEFINED 1
#define XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED 1
#define XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED 1
#define XED_IFORM_SUBPS_XMMps_MEMps_DEFINED 1
#define XED_IFORM_SUBPS_XMMps_XMMps_DEFINED 1
#define XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_SUBSS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_SUBSS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_SWAPGS_DEFINED 1
#define XED_IFORM_SYSCALL_DEFINED 1
#define XED_IFORM_SYSCALL_AMD_DEFINED 1
#define XED_IFORM_SYSENTER_DEFINED 1
#define XED_IFORM_SYSEXIT_DEFINED 1
#define XED_IFORM_SYSRET_DEFINED 1
#define XED_IFORM_SYSRET64_DEFINED 1
#define XED_IFORM_SYSRET_AMD_DEFINED 1
#define XED_IFORM_T1MSKC_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_T1MSKC_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_T1MSKC_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_T1MSKC_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_TDCALL_DEFINED 1
#define XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32_DEFINED 1
#define XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32_DEFINED 1
#define XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32_DEFINED 1
#define XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32_DEFINED 1
#define XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32_DEFINED 1
#define XED_IFORM_TEST_AL_IMMb_DEFINED 1
#define XED_IFORM_TEST_GPR8_GPR8_DEFINED 1
#define XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED 1
#define XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED 1
#define XED_IFORM_TEST_GPRv_GPRv_DEFINED 1
#define XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED 1
#define XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED 1
#define XED_IFORM_TEST_MEMb_GPR8_DEFINED 1
#define XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED 1
#define XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED 1
#define XED_IFORM_TEST_MEMv_GPRv_DEFINED 1
#define XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED 1
#define XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED 1
#define XED_IFORM_TEST_OrAX_IMMz_DEFINED 1
#define XED_IFORM_TESTUI_DEFINED 1
#define XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED 1
#define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED 1
#define XED_IFORM_TILERELEASE_DEFINED 1
#define XED_IFORM_TILESTORED_MEMu32_TMMu32_DEFINED 1
#define XED_IFORM_TILEZERO_TMMu32_DEFINED 1
#define XED_IFORM_TLBSYNC_DEFINED 1
#define XED_IFORM_TPAUSE_GPR32u32_DEFINED 1
#define XED_IFORM_TZCNT_GPRv_GPRv_DEFINED 1
#define XED_IFORM_TZCNT_GPRv_MEMv_DEFINED 1
#define XED_IFORM_TZMSK_VGPR32d_MEMd_DEFINED 1
#define XED_IFORM_TZMSK_VGPR32d_VGPR32d_DEFINED 1
#define XED_IFORM_TZMSK_VGPRyy_MEMy_DEFINED 1
#define XED_IFORM_TZMSK_VGPRyy_VGPRyy_DEFINED 1
#define XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED 1
#define XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED 1
#define XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED 1
#define XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED 1
#define XED_IFORM_UD0_DEFINED 1
#define XED_IFORM_UD0_GPR32_GPR32_DEFINED 1
#define XED_IFORM_UD0_GPR32_MEMd_DEFINED 1
#define XED_IFORM_UD1_GPR32_GPR32_DEFINED 1
#define XED_IFORM_UD1_GPR32_MEMd_DEFINED 1
#define XED_IFORM_UD2_DEFINED 1
#define XED_IFORM_UIRET_DEFINED 1
#define XED_IFORM_UMONITOR_GPRa_DEFINED 1
#define XED_IFORM_UMWAIT_GPR32_DEFINED 1
#define XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED 1
#define XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED 1
#define XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED 1
#define XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED 1
#define XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED 1
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1
#define XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1
#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1
#define XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED 1
#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED 1
#define XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED 1
#define XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VERR_GPR16_DEFINED 1
#define XED_IFORM_VERR_MEMw_DEFINED 1
#define XED_IFORM_VERW_GPR16_DEFINED 1
#define XED_IFORM_VERW_MEMw_DEFINED 1
#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128_DEFINED 1
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256_DEFINED 1
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512_DEFINED 1
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED 1
#define XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED 1
#define XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED 1
#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VLDMXCSR_MEMd_DEFINED 1
#define XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMCALL_DEFINED 1
#define XED_IFORM_VMCLEAR_MEMq_DEFINED 1
#define XED_IFORM_VMFUNC_DEFINED 1
#define XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMLAUNCH_DEFINED 1
#define XED_IFORM_VMLOAD_ArAX_DEFINED 1
#define XED_IFORM_VMMCALL_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED 1
#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED 1
#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED 1
#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED 1
#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED 1
#define XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED 1
#define XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED 1
#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED 1
#define XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED 1
#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED 1
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED 1
#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED 1
#define XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED 1
#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED 1
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED 1
#define XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED 1
#define XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED 1
#define XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED 1
#define XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED 1
#define XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED 1
#define XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED 1
#define XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED 1
#define XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED 1
#define XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED 1
#define XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED 1
#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED 1
#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED 1
#define XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED 1
#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED 1
#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED 1
#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED 1
#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED 1
#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED 1
#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED 1
#define XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VMPTRLD_MEMq_DEFINED 1
#define XED_IFORM_VMPTRST_MEMq_DEFINED 1
#define XED_IFORM_VMREAD_GPR32_GPR32_DEFINED 1
#define XED_IFORM_VMREAD_GPR64_GPR64_DEFINED 1
#define XED_IFORM_VMREAD_MEMd_GPR32_DEFINED 1
#define XED_IFORM_VMREAD_MEMq_GPR64_DEFINED 1
#define XED_IFORM_VMRESUME_DEFINED 1
#define XED_IFORM_VMRUN_ArAX_DEFINED 1
#define XED_IFORM_VMSAVE_DEFINED 1
#define XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED 1
#define XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED 1
#define XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED 1
#define XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED 1
#define XED_IFORM_VMXOFF_DEFINED 1
#define XED_IFORM_VMXON_MEMq_DEFINED 1
#define XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32_DEFINED 1
#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32_DEFINED 1
#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32_DEFINED 1
#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32_DEFINED 1
#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32_DEFINED 1
#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32_DEFINED 1
#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32_DEFINED 1
#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32_DEFINED 1
#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32_DEFINED 1
#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED 1
#define XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1
#define XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1
#define XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED 1
#define XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1
#define XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED 1
#define XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1
#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1
#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED 1
#define XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED 1
#define XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED 1
#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED 1
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1
#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1
#define XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1
#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1
#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1
#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED 1
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1
#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSTMXCSR_MEMd_DEFINED 1
#define XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1
#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED 1
#define XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED 1
#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED 1
#define XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED 1
#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1
#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1
#define XED_IFORM_VZEROALL_DEFINED 1
#define XED_IFORM_VZEROUPPER_DEFINED 1
#define XED_IFORM_WBINVD_DEFINED 1
#define XED_IFORM_WBNOINVD_DEFINED 1
#define XED_IFORM_WRFSBASE_GPRy_DEFINED 1
#define XED_IFORM_WRGSBASE_GPRy_DEFINED 1
#define XED_IFORM_WRMSR_DEFINED 1
#define XED_IFORM_WRPKRU_DEFINED 1
#define XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED 1
#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED 1
#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED 1
#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED 1
#define XED_IFORM_XABORT_IMMb_DEFINED 1
#define XED_IFORM_XADD_GPR8_GPR8_DEFINED 1
#define XED_IFORM_XADD_GPRv_GPRv_DEFINED 1
#define XED_IFORM_XADD_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XADD_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XBEGIN_RELBRz_DEFINED 1
#define XED_IFORM_XCHG_GPR8_GPR8_DEFINED 1
#define XED_IFORM_XCHG_GPRv_GPRv_DEFINED 1
#define XED_IFORM_XCHG_GPRv_OrAX_DEFINED 1
#define XED_IFORM_XCHG_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XCHG_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XEND_DEFINED 1
#define XED_IFORM_XGETBV_DEFINED 1
#define XED_IFORM_XLAT_DEFINED 1
#define XED_IFORM_XOR_AL_IMMb_DEFINED 1
#define XED_IFORM_XOR_GPR8_GPR8_30_DEFINED 1
#define XED_IFORM_XOR_GPR8_GPR8_32_DEFINED 1
#define XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED 1
#define XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED 1
#define XED_IFORM_XOR_GPR8_MEMb_DEFINED 1
#define XED_IFORM_XOR_GPRv_GPRv_31_DEFINED 1
#define XED_IFORM_XOR_GPRv_GPRv_33_DEFINED 1
#define XED_IFORM_XOR_GPRv_IMMb_DEFINED 1
#define XED_IFORM_XOR_GPRv_IMMz_DEFINED 1
#define XED_IFORM_XOR_GPRv_MEMv_DEFINED 1
#define XED_IFORM_XOR_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED 1
#define XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED 1
#define XED_IFORM_XOR_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XOR_MEMv_IMMb_DEFINED 1
#define XED_IFORM_XOR_MEMv_IMMz_DEFINED 1
#define XED_IFORM_XOR_OrAX_IMMz_DEFINED 1
#define XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED 1
#define XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED 1
#define XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED 1
#define XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED 1
#define XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED 1
#define XED_IFORM_XRESLDTRK_DEFINED 1
#define XED_IFORM_XRSTOR_MEMmxsave_DEFINED 1
#define XED_IFORM_XRSTOR64_MEMmxsave_DEFINED 1
#define XED_IFORM_XRSTORS_MEMmxsave_DEFINED 1
#define XED_IFORM_XRSTORS64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVE_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVE64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEC_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEC64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVES_MEMmxsave_DEFINED 1
#define XED_IFORM_XSAVES64_MEMmxsave_DEFINED 1
#define XED_IFORM_XSETBV_DEFINED 1
#define XED_IFORM_XSTORE_DEFINED 1
#define XED_IFORM_XSUSLDTRK_DEFINED 1
#define XED_IFORM_XTEST_DEFINED 1
#define XED_IFORM_LAST_DEFINED 1
typedef enum {
  XED_IFORM_INVALID=0, 
  XED_IFORM_AAA=1, 
  XED_IFORM_AAD_IMMb=2, 
  XED_IFORM_AAM_IMMb=3, 
  XED_IFORM_AAS=4, 
  XED_IFORM_ADC_AL_IMMb=5, 
  XED_IFORM_ADC_GPR8_GPR8_10=6, 
  XED_IFORM_ADC_GPR8_GPR8_12=7, 
  XED_IFORM_ADC_GPR8_IMMb_80r2=8, 
  XED_IFORM_ADC_GPR8_IMMb_82r2=9, 
  XED_IFORM_ADC_GPR8_MEMb=10, 
  XED_IFORM_ADC_GPRv_GPRv_11=11, 
  XED_IFORM_ADC_GPRv_GPRv_13=12, 
  XED_IFORM_ADC_GPRv_IMMb=13, 
  XED_IFORM_ADC_GPRv_IMMz=14, 
  XED_IFORM_ADC_GPRv_MEMv=15, 
  XED_IFORM_ADC_MEMb_GPR8=16, 
  XED_IFORM_ADC_MEMb_IMMb_80r2=17, 
  XED_IFORM_ADC_MEMb_IMMb_82r2=18, 
  XED_IFORM_ADC_MEMv_GPRv=19, 
  XED_IFORM_ADC_MEMv_IMMb=20, 
  XED_IFORM_ADC_MEMv_IMMz=21, 
  XED_IFORM_ADC_OrAX_IMMz=22, 
  XED_IFORM_ADCX_GPR32d_GPR32d=23, 
  XED_IFORM_ADCX_GPR32d_MEMd=24, 
  XED_IFORM_ADCX_GPR64q_GPR64q=25, 
  XED_IFORM_ADCX_GPR64q_MEMq=26, 
  XED_IFORM_ADC_LOCK_MEMb_GPR8=27, 
  XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2=28, 
  XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2=29, 
  XED_IFORM_ADC_LOCK_MEMv_GPRv=30, 
  XED_IFORM_ADC_LOCK_MEMv_IMMb=31, 
  XED_IFORM_ADC_LOCK_MEMv_IMMz=32, 
  XED_IFORM_ADD_AL_IMMb=33, 
  XED_IFORM_ADD_GPR8_GPR8_00=34, 
  XED_IFORM_ADD_GPR8_GPR8_02=35, 
  XED_IFORM_ADD_GPR8_IMMb_80r0=36, 
  XED_IFORM_ADD_GPR8_IMMb_82r0=37, 
  XED_IFORM_ADD_GPR8_MEMb=38, 
  XED_IFORM_ADD_GPRv_GPRv_01=39, 
  XED_IFORM_ADD_GPRv_GPRv_03=40, 
  XED_IFORM_ADD_GPRv_IMMb=41, 
  XED_IFORM_ADD_GPRv_IMMz=42, 
  XED_IFORM_ADD_GPRv_MEMv=43, 
  XED_IFORM_ADD_MEMb_GPR8=44, 
  XED_IFORM_ADD_MEMb_IMMb_80r0=45, 
  XED_IFORM_ADD_MEMb_IMMb_82r0=46, 
  XED_IFORM_ADD_MEMv_GPRv=47, 
  XED_IFORM_ADD_MEMv_IMMb=48, 
  XED_IFORM_ADD_MEMv_IMMz=49, 
  XED_IFORM_ADD_OrAX_IMMz=50, 
  XED_IFORM_ADDPD_XMMpd_MEMpd=51, 
  XED_IFORM_ADDPD_XMMpd_XMMpd=52, 
  XED_IFORM_ADDPS_XMMps_MEMps=53, 
  XED_IFORM_ADDPS_XMMps_XMMps=54, 
  XED_IFORM_ADDSD_XMMsd_MEMsd=55, 
  XED_IFORM_ADDSD_XMMsd_XMMsd=56, 
  XED_IFORM_ADDSS_XMMss_MEMss=57, 
  XED_IFORM_ADDSS_XMMss_XMMss=58, 
  XED_IFORM_ADDSUBPD_XMMpd_MEMpd=59, 
  XED_IFORM_ADDSUBPD_XMMpd_XMMpd=60, 
  XED_IFORM_ADDSUBPS_XMMps_MEMps=61, 
  XED_IFORM_ADDSUBPS_XMMps_XMMps=62, 
  XED_IFORM_ADD_LOCK_MEMb_GPR8=63, 
  XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0=64, 
  XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0=65, 
  XED_IFORM_ADD_LOCK_MEMv_GPRv=66, 
  XED_IFORM_ADD_LOCK_MEMv_IMMb=67, 
  XED_IFORM_ADD_LOCK_MEMv_IMMz=68, 
  XED_IFORM_ADOX_GPR32d_GPR32d=69, 
  XED_IFORM_ADOX_GPR32d_MEMd=70, 
  XED_IFORM_ADOX_GPR64q_GPR64q=71, 
  XED_IFORM_ADOX_GPR64q_MEMq=72, 
  XED_IFORM_AESDEC_XMMdq_MEMdq=73, 
  XED_IFORM_AESDEC_XMMdq_XMMdq=74, 
  XED_IFORM_AESDEC128KL_XMMu8_MEMu8=75, 
  XED_IFORM_AESDEC256KL_XMMu8_MEMu8=76, 
  XED_IFORM_AESDECLAST_XMMdq_MEMdq=77, 
  XED_IFORM_AESDECLAST_XMMdq_XMMdq=78, 
  XED_IFORM_AESDECWIDE128KL_MEMu8=79, 
  XED_IFORM_AESDECWIDE256KL_MEMu8=80, 
  XED_IFORM_AESENC_XMMdq_MEMdq=81, 
  XED_IFORM_AESENC_XMMdq_XMMdq=82, 
  XED_IFORM_AESENC128KL_XMMu8_MEMu8=83, 
  XED_IFORM_AESENC256KL_XMMu8_MEMu8=84, 
  XED_IFORM_AESENCLAST_XMMdq_MEMdq=85, 
  XED_IFORM_AESENCLAST_XMMdq_XMMdq=86, 
  XED_IFORM_AESENCWIDE128KL_MEMu8=87, 
  XED_IFORM_AESENCWIDE256KL_MEMu8=88, 
  XED_IFORM_AESIMC_XMMdq_MEMdq=89, 
  XED_IFORM_AESIMC_XMMdq_XMMdq=90, 
  XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb=91, 
  XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb=92, 
  XED_IFORM_AND_AL_IMMb=93, 
  XED_IFORM_AND_GPR8_GPR8_20=94, 
  XED_IFORM_AND_GPR8_GPR8_22=95, 
  XED_IFORM_AND_GPR8_IMMb_80r4=96, 
  XED_IFORM_AND_GPR8_IMMb_82r4=97, 
  XED_IFORM_AND_GPR8_MEMb=98, 
  XED_IFORM_AND_GPRv_GPRv_21=99, 
  XED_IFORM_AND_GPRv_GPRv_23=100, 
  XED_IFORM_AND_GPRv_IMMb=101, 
  XED_IFORM_AND_GPRv_IMMz=102, 
  XED_IFORM_AND_GPRv_MEMv=103, 
  XED_IFORM_AND_MEMb_GPR8=104, 
  XED_IFORM_AND_MEMb_IMMb_80r4=105, 
  XED_IFORM_AND_MEMb_IMMb_82r4=106, 
  XED_IFORM_AND_MEMv_GPRv=107, 
  XED_IFORM_AND_MEMv_IMMb=108, 
  XED_IFORM_AND_MEMv_IMMz=109, 
  XED_IFORM_AND_OrAX_IMMz=110, 
  XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd=111, 
  XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d=112, 
  XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq=113, 
  XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q=114, 
  XED_IFORM_ANDNPD_XMMxuq_MEMxuq=115, 
  XED_IFORM_ANDNPD_XMMxuq_XMMxuq=116, 
  XED_IFORM_ANDNPS_XMMxud_MEMxud=117, 
  XED_IFORM_ANDNPS_XMMxud_XMMxud=118, 
  XED_IFORM_ANDPD_XMMxuq_MEMxuq=119, 
  XED_IFORM_ANDPD_XMMxuq_XMMxuq=120, 
  XED_IFORM_ANDPS_XMMxud_MEMxud=121, 
  XED_IFORM_ANDPS_XMMxud_XMMxud=122, 
  XED_IFORM_AND_LOCK_MEMb_GPR8=123, 
  XED_IFORM_AND_LOCK_MEMb_IMMb_80r4=124, 
  XED_IFORM_AND_LOCK_MEMb_IMMb_82r4=125, 
  XED_IFORM_AND_LOCK_MEMv_GPRv=126, 
  XED_IFORM_AND_LOCK_MEMv_IMMb=127, 
  XED_IFORM_AND_LOCK_MEMv_IMMz=128, 
  XED_IFORM_ARPL_GPR16_GPR16=129, 
  XED_IFORM_ARPL_MEMw_GPR16=130, 
  XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d=131, 
  XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d=132, 
  XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q=133, 
  XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q=134, 
  XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd=135, 
  XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd=136, 
  XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd=137, 
  XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd=138, 
  XED_IFORM_BLCFILL_VGPR32d_MEMd=139, 
  XED_IFORM_BLCFILL_VGPR32d_VGPR32d=140, 
  XED_IFORM_BLCFILL_VGPRyy_MEMy=141, 
  XED_IFORM_BLCFILL_VGPRyy_VGPRyy=142, 
  XED_IFORM_BLCI_VGPR32d_MEMd=143, 
  XED_IFORM_BLCI_VGPR32d_VGPR32d=144, 
  XED_IFORM_BLCI_VGPRyy_MEMy=145, 
  XED_IFORM_BLCI_VGPRyy_VGPRyy=146, 
  XED_IFORM_BLCIC_VGPR32d_MEMd=147, 
  XED_IFORM_BLCIC_VGPR32d_VGPR32d=148, 
  XED_IFORM_BLCIC_VGPRyy_MEMy=149, 
  XED_IFORM_BLCIC_VGPRyy_VGPRyy=150, 
  XED_IFORM_BLCMSK_VGPR32d_MEMd=151, 
  XED_IFORM_BLCMSK_VGPR32d_VGPR32d=152, 
  XED_IFORM_BLCMSK_VGPRyy_MEMy=153, 
  XED_IFORM_BLCMSK_VGPRyy_VGPRyy=154, 
  XED_IFORM_BLCS_VGPR32d_MEMd=155, 
  XED_IFORM_BLCS_VGPR32d_VGPR32d=156, 
  XED_IFORM_BLCS_VGPRyy_MEMy=157, 
  XED_IFORM_BLCS_VGPRyy_VGPRyy=158, 
  XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb=159, 
  XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb=160, 
  XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb=161, 
  XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb=162, 
  XED_IFORM_BLENDVPD_XMMdq_MEMdq=163, 
  XED_IFORM_BLENDVPD_XMMdq_XMMdq=164, 
  XED_IFORM_BLENDVPS_XMMdq_MEMdq=165, 
  XED_IFORM_BLENDVPS_XMMdq_XMMdq=166, 
  XED_IFORM_BLSFILL_VGPR32d_MEMd=167, 
  XED_IFORM_BLSFILL_VGPR32d_VGPR32d=168, 
  XED_IFORM_BLSFILL_VGPRyy_MEMy=169, 
  XED_IFORM_BLSFILL_VGPRyy_VGPRyy=170, 
  XED_IFORM_BLSI_VGPR32d_MEMd=171, 
  XED_IFORM_BLSI_VGPR32d_VGPR32d=172, 
  XED_IFORM_BLSI_VGPR64q_MEMq=173, 
  XED_IFORM_BLSI_VGPR64q_VGPR64q=174, 
  XED_IFORM_BLSIC_VGPR32d_MEMd=175, 
  XED_IFORM_BLSIC_VGPR32d_VGPR32d=176, 
  XED_IFORM_BLSIC_VGPRyy_MEMy=177, 
  XED_IFORM_BLSIC_VGPRyy_VGPRyy=178, 
  XED_IFORM_BLSMSK_VGPR32d_MEMd=179, 
  XED_IFORM_BLSMSK_VGPR32d_VGPR32d=180, 
  XED_IFORM_BLSMSK_VGPR64q_MEMq=181, 
  XED_IFORM_BLSMSK_VGPR64q_VGPR64q=182, 
  XED_IFORM_BLSR_VGPR32d_MEMd=183, 
  XED_IFORM_BLSR_VGPR32d_VGPR32d=184, 
  XED_IFORM_BLSR_VGPR64q_MEMq=185, 
  XED_IFORM_BLSR_VGPR64q_VGPR64q=186, 
  XED_IFORM_BNDCL_BND_AGEN=187, 
  XED_IFORM_BNDCL_BND_GPR32=188, 
  XED_IFORM_BNDCL_BND_GPR64=189, 
  XED_IFORM_BNDCN_BND_AGEN=190, 
  XED_IFORM_BNDCN_BND_GPR32=191, 
  XED_IFORM_BNDCN_BND_GPR64=192, 
  XED_IFORM_BNDCU_BND_AGEN=193, 
  XED_IFORM_BNDCU_BND_GPR32=194, 
  XED_IFORM_BNDCU_BND_GPR64=195, 
  XED_IFORM_BNDLDX_BND_MEMbnd32=196, 
  XED_IFORM_BNDLDX_BND_MEMbnd64=197, 
  XED_IFORM_BNDMK_BND_AGEN=198, 
  XED_IFORM_BNDMOV_BND_BND=199, 
  XED_IFORM_BNDMOV_BND_MEMdq=200, 
  XED_IFORM_BNDMOV_BND_MEMq=201, 
  XED_IFORM_BNDMOV_MEMdq_BND=202, 
  XED_IFORM_BNDMOV_MEMq_BND=203, 
  XED_IFORM_BNDSTX_MEMbnd32_BND=204, 
  XED_IFORM_BNDSTX_MEMbnd64_BND=205, 
  XED_IFORM_BOUND_GPRv_MEMa16=206, 
  XED_IFORM_BOUND_GPRv_MEMa32=207, 
  XED_IFORM_BSF_GPRv_GPRv=208, 
  XED_IFORM_BSF_GPRv_MEMv=209, 
  XED_IFORM_BSR_GPRv_GPRv=210, 
  XED_IFORM_BSR_GPRv_MEMv=211, 
  XED_IFORM_BSWAP_GPRv=212, 
  XED_IFORM_BT_GPRv_GPRv=213, 
  XED_IFORM_BT_GPRv_IMMb=214, 
  XED_IFORM_BT_MEMv_GPRv=215, 
  XED_IFORM_BT_MEMv_IMMb=216, 
  XED_IFORM_BTC_GPRv_GPRv=217, 
  XED_IFORM_BTC_GPRv_IMMb=218, 
  XED_IFORM_BTC_MEMv_GPRv=219, 
  XED_IFORM_BTC_MEMv_IMMb=220, 
  XED_IFORM_BTC_LOCK_MEMv_GPRv=221, 
  XED_IFORM_BTC_LOCK_MEMv_IMMb=222, 
  XED_IFORM_BTR_GPRv_GPRv=223, 
  XED_IFORM_BTR_GPRv_IMMb=224, 
  XED_IFORM_BTR_MEMv_GPRv=225, 
  XED_IFORM_BTR_MEMv_IMMb=226, 
  XED_IFORM_BTR_LOCK_MEMv_GPRv=227, 
  XED_IFORM_BTR_LOCK_MEMv_IMMb=228, 
  XED_IFORM_BTS_GPRv_GPRv=229, 
  XED_IFORM_BTS_GPRv_IMMb=230, 
  XED_IFORM_BTS_MEMv_GPRv=231, 
  XED_IFORM_BTS_MEMv_IMMb=232, 
  XED_IFORM_BTS_LOCK_MEMv_GPRv=233, 
  XED_IFORM_BTS_LOCK_MEMv_IMMb=234, 
  XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d=235, 
  XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d=236, 
  XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q=237, 
  XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q=238, 
  XED_IFORM_CALL_FAR_MEMp2=239, 
  XED_IFORM_CALL_FAR_PTRp_IMMw=240, 
  XED_IFORM_CALL_NEAR_GPRv=241, 
  XED_IFORM_CALL_NEAR_MEMv=242, 
  XED_IFORM_CALL_NEAR_RELBRd=243, 
  XED_IFORM_CALL_NEAR_RELBRz=244, 
  XED_IFORM_CBW=245, 
  XED_IFORM_CDQ=246, 
  XED_IFORM_CDQE=247, 
  XED_IFORM_CLAC=248, 
  XED_IFORM_CLC=249, 
  XED_IFORM_CLD=250, 
  XED_IFORM_CLDEMOTE_MEMu8=251, 
  XED_IFORM_CLFLUSH_MEMmprefetch=252, 
  XED_IFORM_CLFLUSHOPT_MEMmprefetch=253, 
  XED_IFORM_CLGI=254, 
  XED_IFORM_CLI=255, 
  XED_IFORM_CLRSSBSY_MEMu64=256, 
  XED_IFORM_CLTS=257, 
  XED_IFORM_CLUI=258, 
  XED_IFORM_CLWB_MEMmprefetch=259, 
  XED_IFORM_CLZERO=260, 
  XED_IFORM_CMC=261, 
  XED_IFORM_CMOVB_GPRv_GPRv=262, 
  XED_IFORM_CMOVB_GPRv_MEMv=263, 
  XED_IFORM_CMOVBE_GPRv_GPRv=264, 
  XED_IFORM_CMOVBE_GPRv_MEMv=265, 
  XED_IFORM_CMOVL_GPRv_GPRv=266, 
  XED_IFORM_CMOVL_GPRv_MEMv=267, 
  XED_IFORM_CMOVLE_GPRv_GPRv=268, 
  XED_IFORM_CMOVLE_GPRv_MEMv=269, 
  XED_IFORM_CMOVNB_GPRv_GPRv=270, 
  XED_IFORM_CMOVNB_GPRv_MEMv=271, 
  XED_IFORM_CMOVNBE_GPRv_GPRv=272, 
  XED_IFORM_CMOVNBE_GPRv_MEMv=273, 
  XED_IFORM_CMOVNL_GPRv_GPRv=274, 
  XED_IFORM_CMOVNL_GPRv_MEMv=275, 
  XED_IFORM_CMOVNLE_GPRv_GPRv=276, 
  XED_IFORM_CMOVNLE_GPRv_MEMv=277, 
  XED_IFORM_CMOVNO_GPRv_GPRv=278, 
  XED_IFORM_CMOVNO_GPRv_MEMv=279, 
  XED_IFORM_CMOVNP_GPRv_GPRv=280, 
  XED_IFORM_CMOVNP_GPRv_MEMv=281, 
  XED_IFORM_CMOVNS_GPRv_GPRv=282, 
  XED_IFORM_CMOVNS_GPRv_MEMv=283, 
  XED_IFORM_CMOVNZ_GPRv_GPRv=284, 
  XED_IFORM_CMOVNZ_GPRv_MEMv=285, 
  XED_IFORM_CMOVO_GPRv_GPRv=286, 
  XED_IFORM_CMOVO_GPRv_MEMv=287, 
  XED_IFORM_CMOVP_GPRv_GPRv=288, 
  XED_IFORM_CMOVP_GPRv_MEMv=289, 
  XED_IFORM_CMOVS_GPRv_GPRv=290, 
  XED_IFORM_CMOVS_GPRv_MEMv=291, 
  XED_IFORM_CMOVZ_GPRv_GPRv=292, 
  XED_IFORM_CMOVZ_GPRv_MEMv=293, 
  XED_IFORM_CMP_AL_IMMb=294, 
  XED_IFORM_CMP_GPR8_GPR8_38=295, 
  XED_IFORM_CMP_GPR8_GPR8_3A=296, 
  XED_IFORM_CMP_GPR8_IMMb_80r7=297, 
  XED_IFORM_CMP_GPR8_IMMb_82r7=298, 
  XED_IFORM_CMP_GPR8_MEMb=299, 
  XED_IFORM_CMP_GPRv_GPRv_39=300, 
  XED_IFORM_CMP_GPRv_GPRv_3B=301, 
  XED_IFORM_CMP_GPRv_IMMb=302, 
  XED_IFORM_CMP_GPRv_IMMz=303, 
  XED_IFORM_CMP_GPRv_MEMv=304, 
  XED_IFORM_CMP_MEMb_GPR8=305, 
  XED_IFORM_CMP_MEMb_IMMb_80r7=306, 
  XED_IFORM_CMP_MEMb_IMMb_82r7=307, 
  XED_IFORM_CMP_MEMv_GPRv=308, 
  XED_IFORM_CMP_MEMv_IMMb=309, 
  XED_IFORM_CMP_MEMv_IMMz=310, 
  XED_IFORM_CMP_OrAX_IMMz=311, 
  XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb=312, 
  XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb=313, 
  XED_IFORM_CMPPS_XMMps_MEMps_IMMb=314, 
  XED_IFORM_CMPPS_XMMps_XMMps_IMMb=315, 
  XED_IFORM_CMPSB=316, 
  XED_IFORM_CMPSD=317, 
  XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb=318, 
  XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb=319, 
  XED_IFORM_CMPSQ=320, 
  XED_IFORM_CMPSS_XMMss_MEMss_IMMb=321, 
  XED_IFORM_CMPSS_XMMss_XMMss_IMMb=322, 
  XED_IFORM_CMPSW=323, 
  XED_IFORM_CMPXCHG_GPR8_GPR8=324, 
  XED_IFORM_CMPXCHG_GPRv_GPRv=325, 
  XED_IFORM_CMPXCHG_MEMb_GPR8=326, 
  XED_IFORM_CMPXCHG_MEMv_GPRv=327, 
  XED_IFORM_CMPXCHG16B_MEMdq=328, 
  XED_IFORM_CMPXCHG16B_LOCK_MEMdq=329, 
  XED_IFORM_CMPXCHG8B_MEMq=330, 
  XED_IFORM_CMPXCHG8B_LOCK_MEMq=331, 
  XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8=332, 
  XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv=333, 
  XED_IFORM_COMISD_XMMsd_MEMsd=334, 
  XED_IFORM_COMISD_XMMsd_XMMsd=335, 
  XED_IFORM_COMISS_XMMss_MEMss=336, 
  XED_IFORM_COMISS_XMMss_XMMss=337, 
  XED_IFORM_CPUID=338, 
  XED_IFORM_CQO=339, 
  XED_IFORM_CRC32_GPRyy_GPR8b=340, 
  XED_IFORM_CRC32_GPRyy_GPRv=341, 
  XED_IFORM_CRC32_GPRyy_MEMb=342, 
  XED_IFORM_CRC32_GPRyy_MEMv=343, 
  XED_IFORM_CVTDQ2PD_XMMpd_MEMq=344, 
  XED_IFORM_CVTDQ2PD_XMMpd_XMMq=345, 
  XED_IFORM_CVTDQ2PS_XMMps_MEMdq=346, 
  XED_IFORM_CVTDQ2PS_XMMps_XMMdq=347, 
  XED_IFORM_CVTPD2DQ_XMMdq_MEMpd=348, 
  XED_IFORM_CVTPD2DQ_XMMdq_XMMpd=349, 
  XED_IFORM_CVTPD2PI_MMXq_MEMpd=350, 
  XED_IFORM_CVTPD2PI_MMXq_XMMpd=351, 
  XED_IFORM_CVTPD2PS_XMMps_MEMpd=352, 
  XED_IFORM_CVTPD2PS_XMMps_XMMpd=353, 
  XED_IFORM_CVTPI2PD_XMMpd_MEMq=354, 
  XED_IFORM_CVTPI2PD_XMMpd_MMXq=355, 
  XED_IFORM_CVTPI2PS_XMMq_MEMq=356, 
  XED_IFORM_CVTPI2PS_XMMq_MMXq=357, 
  XED_IFORM_CVTPS2DQ_XMMdq_MEMps=358, 
  XED_IFORM_CVTPS2DQ_XMMdq_XMMps=359, 
  XED_IFORM_CVTPS2PD_XMMpd_MEMq=360, 
  XED_IFORM_CVTPS2PD_XMMpd_XMMq=361, 
  XED_IFORM_CVTPS2PI_MMXq_MEMq=362, 
  XED_IFORM_CVTPS2PI_MMXq_XMMq=363, 
  XED_IFORM_CVTSD2SI_GPR32d_MEMsd=364, 
  XED_IFORM_CVTSD2SI_GPR32d_XMMsd=365, 
  XED_IFORM_CVTSD2SI_GPR64q_MEMsd=366, 
  XED_IFORM_CVTSD2SI_GPR64q_XMMsd=367, 
  XED_IFORM_CVTSD2SS_XMMss_MEMsd=368, 
  XED_IFORM_CVTSD2SS_XMMss_XMMsd=369, 
  XED_IFORM_CVTSI2SD_XMMsd_GPR32d=370, 
  XED_IFORM_CVTSI2SD_XMMsd_GPR64q=371, 
  XED_IFORM_CVTSI2SD_XMMsd_MEMd=372, 
  XED_IFORM_CVTSI2SD_XMMsd_MEMq=373, 
  XED_IFORM_CVTSI2SS_XMMss_GPR32d=374, 
  XED_IFORM_CVTSI2SS_XMMss_GPR64q=375, 
  XED_IFORM_CVTSI2SS_XMMss_MEMd=376, 
  XED_IFORM_CVTSI2SS_XMMss_MEMq=377, 
  XED_IFORM_CVTSS2SD_XMMsd_MEMss=378, 
  XED_IFORM_CVTSS2SD_XMMsd_XMMss=379, 
  XED_IFORM_CVTSS2SI_GPR32d_MEMss=380, 
  XED_IFORM_CVTSS2SI_GPR32d_XMMss=381, 
  XED_IFORM_CVTSS2SI_GPR64q_MEMss=382, 
  XED_IFORM_CVTSS2SI_GPR64q_XMMss=383, 
  XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd=384, 
  XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd=385, 
  XED_IFORM_CVTTPD2PI_MMXq_MEMpd=386, 
  XED_IFORM_CVTTPD2PI_MMXq_XMMpd=387, 
  XED_IFORM_CVTTPS2DQ_XMMdq_MEMps=388, 
  XED_IFORM_CVTTPS2DQ_XMMdq_XMMps=389, 
  XED_IFORM_CVTTPS2PI_MMXq_MEMq=390, 
  XED_IFORM_CVTTPS2PI_MMXq_XMMq=391, 
  XED_IFORM_CVTTSD2SI_GPR32d_MEMsd=392, 
  XED_IFORM_CVTTSD2SI_GPR32d_XMMsd=393, 
  XED_IFORM_CVTTSD2SI_GPR64q_MEMsd=394, 
  XED_IFORM_CVTTSD2SI_GPR64q_XMMsd=395, 
  XED_IFORM_CVTTSS2SI_GPR32d_MEMss=396, 
  XED_IFORM_CVTTSS2SI_GPR32d_XMMss=397, 
  XED_IFORM_CVTTSS2SI_GPR64q_MEMss=398, 
  XED_IFORM_CVTTSS2SI_GPR64q_XMMss=399, 
  XED_IFORM_CWD=400, 
  XED_IFORM_CWDE=401, 
  XED_IFORM_DAA=402, 
  XED_IFORM_DAS=403, 
  XED_IFORM_DEC_GPR8=404, 
  XED_IFORM_DEC_GPRv_48=405, 
  XED_IFORM_DEC_GPRv_FFr1=406, 
  XED_IFORM_DEC_MEMb=407, 
  XED_IFORM_DEC_MEMv=408, 
  XED_IFORM_DEC_LOCK_MEMb=409, 
  XED_IFORM_DEC_LOCK_MEMv=410, 
  XED_IFORM_DIV_GPR8=411, 
  XED_IFORM_DIV_GPRv=412, 
  XED_IFORM_DIV_MEMb=413, 
  XED_IFORM_DIV_MEMv=414, 
  XED_IFORM_DIVPD_XMMpd_MEMpd=415, 
  XED_IFORM_DIVPD_XMMpd_XMMpd=416, 
  XED_IFORM_DIVPS_XMMps_MEMps=417, 
  XED_IFORM_DIVPS_XMMps_XMMps=418, 
  XED_IFORM_DIVSD_XMMsd_MEMsd=419, 
  XED_IFORM_DIVSD_XMMsd_XMMsd=420, 
  XED_IFORM_DIVSS_XMMss_MEMss=421, 
  XED_IFORM_DIVSS_XMMss_XMMss=422, 
  XED_IFORM_DPPD_XMMdq_MEMdq_IMMb=423, 
  XED_IFORM_DPPD_XMMdq_XMMdq_IMMb=424, 
  XED_IFORM_DPPS_XMMdq_MEMdq_IMMb=425, 
  XED_IFORM_DPPS_XMMdq_XMMdq_IMMb=426, 
  XED_IFORM_EMMS=427, 
  XED_IFORM_ENCLS=428, 
  XED_IFORM_ENCLU=429, 
  XED_IFORM_ENCLV=430, 
  XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8=431, 
  XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8=432, 
  XED_IFORM_ENDBR32=433, 
  XED_IFORM_ENDBR64=434, 
  XED_IFORM_ENQCMD_GPRa_MEMu32=435, 
  XED_IFORM_ENQCMDS_GPRa_MEMu32=436, 
  XED_IFORM_ENTER_IMMw_IMMb=437, 
  XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb=438, 
  XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb=439, 
  XED_IFORM_EXTRQ_XMMq_IMMb_IMMb=440, 
  XED_IFORM_EXTRQ_XMMq_XMMdq=441, 
  XED_IFORM_F2XM1=442, 
  XED_IFORM_FABS=443, 
  XED_IFORM_FADD_ST0_MEMm64real=444, 
  XED_IFORM_FADD_ST0_MEMmem32real=445, 
  XED_IFORM_FADD_ST0_X87=446, 
  XED_IFORM_FADD_X87_ST0=447, 
  XED_IFORM_FADDP_X87_ST0=448, 
  XED_IFORM_FBLD_ST0_MEMmem80dec=449, 
  XED_IFORM_FBSTP_MEMmem80dec_ST0=450, 
  XED_IFORM_FCHS=451, 
  XED_IFORM_FCMOVB_ST0_X87=452, 
  XED_IFORM_FCMOVBE_ST0_X87=453, 
  XED_IFORM_FCMOVE_ST0_X87=454, 
  XED_IFORM_FCMOVNB_ST0_X87=455, 
  XED_IFORM_FCMOVNBE_ST0_X87=456, 
  XED_IFORM_FCMOVNE_ST0_X87=457, 
  XED_IFORM_FCMOVNU_ST0_X87=458, 
  XED_IFORM_FCMOVU_ST0_X87=459, 
  XED_IFORM_FCOM_ST0_MEMm64real=460, 
  XED_IFORM_FCOM_ST0_MEMmem32real=461, 
  XED_IFORM_FCOM_ST0_X87=462, 
  XED_IFORM_FCOM_ST0_X87_DCD0=463, 
  XED_IFORM_FCOMI_ST0_X87=464, 
  XED_IFORM_FCOMIP_ST0_X87=465, 
  XED_IFORM_FCOMP_ST0_MEMm64real=466, 
  XED_IFORM_FCOMP_ST0_MEMmem32real=467, 
  XED_IFORM_FCOMP_ST0_X87=468, 
  XED_IFORM_FCOMP_ST0_X87_DCD1=469, 
  XED_IFORM_FCOMP_ST0_X87_DED0=470, 
  XED_IFORM_FCOMPP=471, 
  XED_IFORM_FCOS=472, 
  XED_IFORM_FDECSTP=473, 
  XED_IFORM_FDISI8087_NOP=474, 
  XED_IFORM_FDIV_ST0_MEMm64real=475, 
  XED_IFORM_FDIV_ST0_MEMmem32real=476, 
  XED_IFORM_FDIV_ST0_X87=477, 
  XED_IFORM_FDIV_X87_ST0=478, 
  XED_IFORM_FDIVP_X87_ST0=479, 
  XED_IFORM_FDIVR_ST0_MEMm64real=480, 
  XED_IFORM_FDIVR_ST0_MEMmem32real=481, 
  XED_IFORM_FDIVR_ST0_X87=482, 
  XED_IFORM_FDIVR_X87_ST0=483, 
  XED_IFORM_FDIVRP_X87_ST0=484, 
  XED_IFORM_FEMMS=485, 
  XED_IFORM_FENI8087_NOP=486, 
  XED_IFORM_FFREE_X87=487, 
  XED_IFORM_FFREEP_X87=488, 
  XED_IFORM_FIADD_ST0_MEMmem16int=489, 
  XED_IFORM_FIADD_ST0_MEMmem32int=490, 
  XED_IFORM_FICOM_ST0_MEMmem16int=491, 
  XED_IFORM_FICOM_ST0_MEMmem32int=492, 
  XED_IFORM_FICOMP_ST0_MEMmem16int=493, 
  XED_IFORM_FICOMP_ST0_MEMmem32int=494, 
  XED_IFORM_FIDIV_ST0_MEMmem16int=495, 
  XED_IFORM_FIDIV_ST0_MEMmem32int=496, 
  XED_IFORM_FIDIVR_ST0_MEMmem16int=497, 
  XED_IFORM_FIDIVR_ST0_MEMmem32int=498, 
  XED_IFORM_FILD_ST0_MEMm64int=499, 
  XED_IFORM_FILD_ST0_MEMmem16int=500, 
  XED_IFORM_FILD_ST0_MEMmem32int=501, 
  XED_IFORM_FIMUL_ST0_MEMmem16int=502, 
  XED_IFORM_FIMUL_ST0_MEMmem32int=503, 
  XED_IFORM_FINCSTP=504, 
  XED_IFORM_FIST_MEMmem16int_ST0=505, 
  XED_IFORM_FIST_MEMmem32int_ST0=506, 
  XED_IFORM_FISTP_MEMm64int_ST0=507, 
  XED_IFORM_FISTP_MEMmem16int_ST0=508, 
  XED_IFORM_FISTP_MEMmem32int_ST0=509, 
  XED_IFORM_FISTTP_MEMm64int_ST0=510, 
  XED_IFORM_FISTTP_MEMmem16int_ST0=511, 
  XED_IFORM_FISTTP_MEMmem32int_ST0=512, 
  XED_IFORM_FISUB_ST0_MEMmem16int=513, 
  XED_IFORM_FISUB_ST0_MEMmem32int=514, 
  XED_IFORM_FISUBR_ST0_MEMmem16int=515, 
  XED_IFORM_FISUBR_ST0_MEMmem32int=516, 
  XED_IFORM_FLD_ST0_MEMm64real=517, 
  XED_IFORM_FLD_ST0_MEMmem32real=518, 
  XED_IFORM_FLD_ST0_MEMmem80real=519, 
  XED_IFORM_FLD_ST0_X87=520, 
  XED_IFORM_FLD1=521, 
  XED_IFORM_FLDCW_MEMmem16=522, 
  XED_IFORM_FLDENV_MEMmem14=523, 
  XED_IFORM_FLDENV_MEMmem28=524, 
  XED_IFORM_FLDL2E=525, 
  XED_IFORM_FLDL2T=526, 
  XED_IFORM_FLDLG2=527, 
  XED_IFORM_FLDLN2=528, 
  XED_IFORM_FLDPI=529, 
  XED_IFORM_FLDZ=530, 
  XED_IFORM_FMUL_ST0_MEMm64real=531, 
  XED_IFORM_FMUL_ST0_MEMmem32real=532, 
  XED_IFORM_FMUL_ST0_X87=533, 
  XED_IFORM_FMUL_X87_ST0=534, 
  XED_IFORM_FMULP_X87_ST0=535, 
  XED_IFORM_FNCLEX=536, 
  XED_IFORM_FNINIT=537, 
  XED_IFORM_FNOP=538, 
  XED_IFORM_FNSAVE_MEMmem108=539, 
  XED_IFORM_FNSAVE_MEMmem94=540, 
  XED_IFORM_FNSTCW_MEMmem16=541, 
  XED_IFORM_FNSTENV_MEMmem14=542, 
  XED_IFORM_FNSTENV_MEMmem28=543, 
  XED_IFORM_FNSTSW_AX=544, 
  XED_IFORM_FNSTSW_MEMmem16=545, 
  XED_IFORM_FPATAN=546, 
  XED_IFORM_FPREM=547, 
  XED_IFORM_FPREM1=548, 
  XED_IFORM_FPTAN=549, 
  XED_IFORM_FRNDINT=550, 
  XED_IFORM_FRSTOR_MEMmem108=551, 
  XED_IFORM_FRSTOR_MEMmem94=552, 
  XED_IFORM_FSCALE=553, 
  XED_IFORM_FSETPM287_NOP=554, 
  XED_IFORM_FSIN=555, 
  XED_IFORM_FSINCOS=556, 
  XED_IFORM_FSQRT=557, 
  XED_IFORM_FST_MEMm64real_ST0=558, 
  XED_IFORM_FST_MEMmem32real_ST0=559, 
  XED_IFORM_FST_X87_ST0=560, 
  XED_IFORM_FSTP_MEMm64real_ST0=561, 
  XED_IFORM_FSTP_MEMmem32real_ST0=562, 
  XED_IFORM_FSTP_MEMmem80real_ST0=563, 
  XED_IFORM_FSTP_X87_ST0=564, 
  XED_IFORM_FSTP_X87_ST0_DFD0=565, 
  XED_IFORM_FSTP_X87_ST0_DFD1=566, 
  XED_IFORM_FSTPNCE_X87_ST0=567, 
  XED_IFORM_FSUB_ST0_MEMm64real=568, 
  XED_IFORM_FSUB_ST0_MEMmem32real=569, 
  XED_IFORM_FSUB_ST0_X87=570, 
  XED_IFORM_FSUB_X87_ST0=571, 
  XED_IFORM_FSUBP_X87_ST0=572, 
  XED_IFORM_FSUBR_ST0_MEMm64real=573, 
  XED_IFORM_FSUBR_ST0_MEMmem32real=574, 
  XED_IFORM_FSUBR_ST0_X87=575, 
  XED_IFORM_FSUBR_X87_ST0=576, 
  XED_IFORM_FSUBRP_X87_ST0=577, 
  XED_IFORM_FTST=578, 
  XED_IFORM_FUCOM_ST0_X87=579, 
  XED_IFORM_FUCOMI_ST0_X87=580, 
  XED_IFORM_FUCOMIP_ST0_X87=581, 
  XED_IFORM_FUCOMP_ST0_X87=582, 
  XED_IFORM_FUCOMPP=583, 
  XED_IFORM_FWAIT=584, 
  XED_IFORM_FXAM=585, 
  XED_IFORM_FXCH_ST0_X87=586, 
  XED_IFORM_FXCH_ST0_X87_DDC1=587, 
  XED_IFORM_FXCH_ST0_X87_DFC1=588, 
  XED_IFORM_FXRSTOR_MEMmfpxenv=589, 
  XED_IFORM_FXRSTOR64_MEMmfpxenv=590, 
  XED_IFORM_FXSAVE_MEMmfpxenv=591, 
  XED_IFORM_FXSAVE64_MEMmfpxenv=592, 
  XED_IFORM_FXTRACT=593, 
  XED_IFORM_FYL2X=594, 
  XED_IFORM_FYL2XP1=595, 
  XED_IFORM_GETSEC=596, 
  XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8=597, 
  XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8=598, 
  XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8=599, 
  XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8=600, 
  XED_IFORM_GF2P8MULB_XMMu8_MEMu8=601, 
  XED_IFORM_GF2P8MULB_XMMu8_XMMu8=602, 
  XED_IFORM_HADDPD_XMMpd_MEMpd=603, 
  XED_IFORM_HADDPD_XMMpd_XMMpd=604, 
  XED_IFORM_HADDPS_XMMps_MEMps=605, 
  XED_IFORM_HADDPS_XMMps_XMMps=606, 
  XED_IFORM_HLT=607, 
  XED_IFORM_HRESET_IMM8=608, 
  XED_IFORM_HSUBPD_XMMpd_MEMpd=609, 
  XED_IFORM_HSUBPD_XMMpd_XMMpd=610, 
  XED_IFORM_HSUBPS_XMMps_MEMps=611, 
  XED_IFORM_HSUBPS_XMMps_XMMps=612, 
  XED_IFORM_IDIV_GPR8=613, 
  XED_IFORM_IDIV_GPRv=614, 
  XED_IFORM_IDIV_MEMb=615, 
  XED_IFORM_IDIV_MEMv=616, 
  XED_IFORM_IMUL_GPR8=617, 
  XED_IFORM_IMUL_GPRv=618, 
  XED_IFORM_IMUL_GPRv_GPRv=619, 
  XED_IFORM_IMUL_GPRv_GPRv_IMMb=620, 
  XED_IFORM_IMUL_GPRv_GPRv_IMMz=621, 
  XED_IFORM_IMUL_GPRv_MEMv=622, 
  XED_IFORM_IMUL_GPRv_MEMv_IMMb=623, 
  XED_IFORM_IMUL_GPRv_MEMv_IMMz=624, 
  XED_IFORM_IMUL_MEMb=625, 
  XED_IFORM_IMUL_MEMv=626, 
  XED_IFORM_IN_AL_DX=627, 
  XED_IFORM_IN_AL_IMMb=628, 
  XED_IFORM_IN_OeAX_DX=629, 
  XED_IFORM_IN_OeAX_IMMb=630, 
  XED_IFORM_INC_GPR8=631, 
  XED_IFORM_INC_GPRv_40=632, 
  XED_IFORM_INC_GPRv_FFr0=633, 
  XED_IFORM_INC_MEMb=634, 
  XED_IFORM_INC_MEMv=635, 
  XED_IFORM_INCSSPD_GPR32u8=636, 
  XED_IFORM_INCSSPQ_GPR64u8=637, 
  XED_IFORM_INC_LOCK_MEMb=638, 
  XED_IFORM_INC_LOCK_MEMv=639, 
  XED_IFORM_INSB=640, 
  XED_IFORM_INSD=641, 
  XED_IFORM_INSERTPS_XMMps_MEMd_IMMb=642, 
  XED_IFORM_INSERTPS_XMMps_XMMps_IMMb=643, 
  XED_IFORM_INSERTQ_XMMq_XMMdq=644, 
  XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb=645, 
  XED_IFORM_INSW=646, 
  XED_IFORM_INT_IMMb=647, 
  XED_IFORM_INT1=648, 
  XED_IFORM_INT3=649, 
  XED_IFORM_INTO=650, 
  XED_IFORM_INVD=651, 
  XED_IFORM_INVEPT_GPR32_MEMdq=652, 
  XED_IFORM_INVEPT_GPR64_MEMdq=653, 
  XED_IFORM_INVLPG_MEMb=654, 
  XED_IFORM_INVLPGA_ArAX_ECX=655, 
  XED_IFORM_INVLPGB_EAX_EDX_ECX=656, 
  XED_IFORM_INVLPGB_RAX_EDX_ECX=657, 
  XED_IFORM_INVPCID_GPR32_MEMdq=658, 
  XED_IFORM_INVPCID_GPR64_MEMdq=659, 
  XED_IFORM_INVVPID_GPR32_MEMdq=660, 
  XED_IFORM_INVVPID_GPR64_MEMdq=661, 
  XED_IFORM_IRET=662, 
  XED_IFORM_IRETD=663, 
  XED_IFORM_IRETQ=664, 
  XED_IFORM_JB_RELBRb=665, 
  XED_IFORM_JB_RELBRd=666, 
  XED_IFORM_JB_RELBRz=667, 
  XED_IFORM_JBE_RELBRb=668, 
  XED_IFORM_JBE_RELBRd=669, 
  XED_IFORM_JBE_RELBRz=670, 
  XED_IFORM_JCXZ_RELBRb=671, 
  XED_IFORM_JECXZ_RELBRb=672, 
  XED_IFORM_JL_RELBRb=673, 
  XED_IFORM_JL_RELBRd=674, 
  XED_IFORM_JL_RELBRz=675, 
  XED_IFORM_JLE_RELBRb=676, 
  XED_IFORM_JLE_RELBRd=677, 
  XED_IFORM_JLE_RELBRz=678, 
  XED_IFORM_JMP_GPRv=679, 
  XED_IFORM_JMP_MEMv=680, 
  XED_IFORM_JMP_RELBRb=681, 
  XED_IFORM_JMP_RELBRd=682, 
  XED_IFORM_JMP_RELBRz=683, 
  XED_IFORM_JMP_FAR_MEMp2=684, 
  XED_IFORM_JMP_FAR_PTRp_IMMw=685, 
  XED_IFORM_JNB_RELBRb=686, 
  XED_IFORM_JNB_RELBRd=687, 
  XED_IFORM_JNB_RELBRz=688, 
  XED_IFORM_JNBE_RELBRb=689, 
  XED_IFORM_JNBE_RELBRd=690, 
  XED_IFORM_JNBE_RELBRz=691, 
  XED_IFORM_JNL_RELBRb=692, 
  XED_IFORM_JNL_RELBRd=693, 
  XED_IFORM_JNL_RELBRz=694, 
  XED_IFORM_JNLE_RELBRb=695, 
  XED_IFORM_JNLE_RELBRd=696, 
  XED_IFORM_JNLE_RELBRz=697, 
  XED_IFORM_JNO_RELBRb=698, 
  XED_IFORM_JNO_RELBRd=699, 
  XED_IFORM_JNO_RELBRz=700, 
  XED_IFORM_JNP_RELBRb=701, 
  XED_IFORM_JNP_RELBRd=702, 
  XED_IFORM_JNP_RELBRz=703, 
  XED_IFORM_JNS_RELBRb=704, 
  XED_IFORM_JNS_RELBRd=705, 
  XED_IFORM_JNS_RELBRz=706, 
  XED_IFORM_JNZ_RELBRb=707, 
  XED_IFORM_JNZ_RELBRd=708, 
  XED_IFORM_JNZ_RELBRz=709, 
  XED_IFORM_JO_RELBRb=710, 
  XED_IFORM_JO_RELBRd=711, 
  XED_IFORM_JO_RELBRz=712, 
  XED_IFORM_JP_RELBRb=713, 
  XED_IFORM_JP_RELBRd=714, 
  XED_IFORM_JP_RELBRz=715, 
  XED_IFORM_JRCXZ_RELBRb=716, 
  XED_IFORM_JS_RELBRb=717, 
  XED_IFORM_JS_RELBRd=718, 
  XED_IFORM_JS_RELBRz=719, 
  XED_IFORM_JZ_RELBRb=720, 
  XED_IFORM_JZ_RELBRd=721, 
  XED_IFORM_JZ_RELBRz=722, 
  XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512=723, 
  XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512=724, 
  XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=725, 
  XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512=726, 
  XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512=727, 
  XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512=728, 
  XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512=729, 
  XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512=730, 
  XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512=731, 
  XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512=732, 
  XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=733, 
  XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512=734, 
  XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512=735, 
  XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512=736, 
  XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512=737, 
  XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512=738, 
  XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512=739, 
  XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512=740, 
  XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512=741, 
  XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512=742, 
  XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512=743, 
  XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512=744, 
  XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512=745, 
  XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512=746, 
  XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512=747, 
  XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512=748, 
  XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512=749, 
  XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512=750, 
  XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512=751, 
  XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512=752, 
  XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512=753, 
  XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512=754, 
  XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512=755, 
  XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512=756, 
  XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512=757, 
  XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512=758, 
  XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512=759, 
  XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512=760, 
  XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=761, 
  XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512=762, 
  XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512=763, 
  XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512=764, 
  XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512=765, 
  XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512=766, 
  XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512=767, 
  XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512=768, 
  XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512=769, 
  XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512=770, 
  XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512=771, 
  XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512=772, 
  XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512=773, 
  XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512=774, 
  XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512=775, 
  XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512=776, 
  XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512=777, 
  XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512=778, 
  XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512=779, 
  XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=780, 
  XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512=781, 
  XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512=782, 
  XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512=783, 
  XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=784, 
  XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512=785, 
  XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512=786, 
  XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512=787, 
  XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=788, 
  XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512=789, 
  XED_IFORM_LAHF=790, 
  XED_IFORM_LAR_GPRv_GPRv=791, 
  XED_IFORM_LAR_GPRv_MEMw=792, 
  XED_IFORM_LDDQU_XMMpd_MEMdq=793, 
  XED_IFORM_LDMXCSR_MEMd=794, 
  XED_IFORM_LDS_GPRz_MEMp=795, 
  XED_IFORM_LDTILECFG_MEM=796, 
  XED_IFORM_LEA_GPRv_AGEN=797, 
  XED_IFORM_LEAVE=798, 
  XED_IFORM_LES_GPRz_MEMp=799, 
  XED_IFORM_LFENCE=800, 
  XED_IFORM_LFS_GPRv_MEMp2=801, 
  XED_IFORM_LGDT_MEMs=802, 
  XED_IFORM_LGDT_MEMs64=803, 
  XED_IFORM_LGS_GPRv_MEMp2=804, 
  XED_IFORM_LIDT_MEMs=805, 
  XED_IFORM_LIDT_MEMs64=806, 
  XED_IFORM_LLDT_GPR16=807, 
  XED_IFORM_LLDT_MEMw=808, 
  XED_IFORM_LLWPCB_VGPRyy=809, 
  XED_IFORM_LMSW_GPR16=810, 
  XED_IFORM_LMSW_MEMw=811, 
  XED_IFORM_LOADIWKEY_XMMu8_XMMu8=812, 
  XED_IFORM_LODSB=813, 
  XED_IFORM_LODSD=814, 
  XED_IFORM_LODSQ=815, 
  XED_IFORM_LODSW=816, 
  XED_IFORM_LOOP_RELBRb=817, 
  XED_IFORM_LOOPE_RELBRb=818, 
  XED_IFORM_LOOPNE_RELBRb=819, 
  XED_IFORM_LSL_GPRv_GPRz=820, 
  XED_IFORM_LSL_GPRv_MEMw=821, 
  XED_IFORM_LSS_GPRv_MEMp2=822, 
  XED_IFORM_LTR_GPR16=823, 
  XED_IFORM_LTR_MEMw=824, 
  XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd=825, 
  XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd=826, 
  XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd=827, 
  XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd=828, 
  XED_IFORM_LZCNT_GPRv_GPRv=829, 
  XED_IFORM_LZCNT_GPRv_MEMv=830, 
  XED_IFORM_MASKMOVDQU_XMMdq_XMMdq=831, 
  XED_IFORM_MASKMOVQ_MMXq_MMXq=832, 
  XED_IFORM_MAXPD_XMMpd_MEMpd=833, 
  XED_IFORM_MAXPD_XMMpd_XMMpd=834, 
  XED_IFORM_MAXPS_XMMps_MEMps=835, 
  XED_IFORM_MAXPS_XMMps_XMMps=836, 
  XED_IFORM_MAXSD_XMMsd_MEMsd=837, 
  XED_IFORM_MAXSD_XMMsd_XMMsd=838, 
  XED_IFORM_MAXSS_XMMss_MEMss=839, 
  XED_IFORM_MAXSS_XMMss_XMMss=840, 
  XED_IFORM_MCOMMIT=841, 
  XED_IFORM_MFENCE=842, 
  XED_IFORM_MINPD_XMMpd_MEMpd=843, 
  XED_IFORM_MINPD_XMMpd_XMMpd=844, 
  XED_IFORM_MINPS_XMMps_MEMps=845, 
  XED_IFORM_MINPS_XMMps_XMMps=846, 
  XED_IFORM_MINSD_XMMsd_MEMsd=847, 
  XED_IFORM_MINSD_XMMsd_XMMsd=848, 
  XED_IFORM_MINSS_XMMss_MEMss=849, 
  XED_IFORM_MINSS_XMMss_XMMss=850, 
  XED_IFORM_MONITOR=851, 
  XED_IFORM_MONITORX=852, 
  XED_IFORM_MOV_AL_MEMb=853, 
  XED_IFORM_MOV_GPR8_GPR8_88=854, 
  XED_IFORM_MOV_GPR8_GPR8_8A=855, 
  XED_IFORM_MOV_GPR8_IMMb_B0=856, 
  XED_IFORM_MOV_GPR8_IMMb_C6r0=857, 
  XED_IFORM_MOV_GPR8_MEMb=858, 
  XED_IFORM_MOV_GPRv_GPRv_89=859, 
  XED_IFORM_MOV_GPRv_GPRv_8B=860, 
  XED_IFORM_MOV_GPRv_IMMv=861, 
  XED_IFORM_MOV_GPRv_IMMz=862, 
  XED_IFORM_MOV_GPRv_MEMv=863, 
  XED_IFORM_MOV_GPRv_SEG=864, 
  XED_IFORM_MOV_MEMb_AL=865, 
  XED_IFORM_MOV_MEMb_GPR8=866, 
  XED_IFORM_MOV_MEMb_IMMb=867, 
  XED_IFORM_MOV_MEMv_GPRv=868, 
  XED_IFORM_MOV_MEMv_IMMz=869, 
  XED_IFORM_MOV_MEMv_OrAX=870, 
  XED_IFORM_MOV_MEMw_SEG=871, 
  XED_IFORM_MOV_OrAX_MEMv=872, 
  XED_IFORM_MOV_SEG_GPR16=873, 
  XED_IFORM_MOV_SEG_MEMw=874, 
  XED_IFORM_MOVAPD_MEMpd_XMMpd=875, 
  XED_IFORM_MOVAPD_XMMpd_MEMpd=876, 
  XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28=877, 
  XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29=878, 
  XED_IFORM_MOVAPS_MEMps_XMMps=879, 
  XED_IFORM_MOVAPS_XMMps_MEMps=880, 
  XED_IFORM_MOVAPS_XMMps_XMMps_0F28=881, 
  XED_IFORM_MOVAPS_XMMps_XMMps_0F29=882, 
  XED_IFORM_MOVBE_GPRv_MEMv=883, 
  XED_IFORM_MOVBE_MEMv_GPRv=884, 
  XED_IFORM_MOVD_GPR32_MMXd=885, 
  XED_IFORM_MOVD_GPR32_XMMd=886, 
  XED_IFORM_MOVD_MEMd_MMXd=887, 
  XED_IFORM_MOVD_MEMd_XMMd=888, 
  XED_IFORM_MOVD_MMXq_GPR32=889, 
  XED_IFORM_MOVD_MMXq_MEMd=890, 
  XED_IFORM_MOVD_XMMdq_GPR32=891, 
  XED_IFORM_MOVD_XMMdq_MEMd=892, 
  XED_IFORM_MOVDDUP_XMMdq_MEMq=893, 
  XED_IFORM_MOVDDUP_XMMdq_XMMq=894, 
  XED_IFORM_MOVDIR64B_GPRa_MEM=895, 
  XED_IFORM_MOVDIRI_MEMu32_GPR32u32=896, 
  XED_IFORM_MOVDIRI_MEMu64_GPR64u64=897, 
  XED_IFORM_MOVDQ2Q_MMXq_XMMq=898, 
  XED_IFORM_MOVDQA_MEMdq_XMMdq=899, 
  XED_IFORM_MOVDQA_XMMdq_MEMdq=900, 
  XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F=901, 
  XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F=902, 
  XED_IFORM_MOVDQU_MEMdq_XMMdq=903, 
  XED_IFORM_MOVDQU_XMMdq_MEMdq=904, 
  XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F=905, 
  XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F=906, 
  XED_IFORM_MOVHLPS_XMMq_XMMq=907, 
  XED_IFORM_MOVHPD_MEMq_XMMsd=908, 
  XED_IFORM_MOVHPD_XMMsd_MEMq=909, 
  XED_IFORM_MOVHPS_MEMq_XMMps=910, 
  XED_IFORM_MOVHPS_XMMq_MEMq=911, 
  XED_IFORM_MOVLHPS_XMMq_XMMq=912, 
  XED_IFORM_MOVLPD_MEMq_XMMsd=913, 
  XED_IFORM_MOVLPD_XMMsd_MEMq=914, 
  XED_IFORM_MOVLPS_MEMq_XMMq=915, 
  XED_IFORM_MOVLPS_XMMq_MEMq=916, 
  XED_IFORM_MOVMSKPD_GPR32_XMMpd=917, 
  XED_IFORM_MOVMSKPS_GPR32_XMMps=918, 
  XED_IFORM_MOVNTDQ_MEMdq_XMMdq=919, 
  XED_IFORM_MOVNTDQA_XMMdq_MEMdq=920, 
  XED_IFORM_MOVNTI_MEMd_GPR32=921, 
  XED_IFORM_MOVNTI_MEMq_GPR64=922, 
  XED_IFORM_MOVNTPD_MEMdq_XMMpd=923, 
  XED_IFORM_MOVNTPS_MEMdq_XMMps=924, 
  XED_IFORM_MOVNTQ_MEMq_MMXq=925, 
  XED_IFORM_MOVNTSD_MEMq_XMMq=926, 
  XED_IFORM_MOVNTSS_MEMd_XMMd=927, 
  XED_IFORM_MOVQ_GPR64_MMXq=928, 
  XED_IFORM_MOVQ_GPR64_XMMq=929, 
  XED_IFORM_MOVQ_MEMq_MMXq_0F7E=930, 
  XED_IFORM_MOVQ_MEMq_MMXq_0F7F=931, 
  XED_IFORM_MOVQ_MEMq_XMMq_0F7E=932, 
  XED_IFORM_MOVQ_MEMq_XMMq_0FD6=933, 
  XED_IFORM_MOVQ_MMXq_GPR64=934, 
  XED_IFORM_MOVQ_MMXq_MEMq_0F6E=935, 
  XED_IFORM_MOVQ_MMXq_MEMq_0F6F=936, 
  XED_IFORM_MOVQ_MMXq_MMXq_0F6F=937, 
  XED_IFORM_MOVQ_MMXq_MMXq_0F7F=938, 
  XED_IFORM_MOVQ_XMMdq_GPR64=939, 
  XED_IFORM_MOVQ_XMMdq_MEMq_0F6E=940, 
  XED_IFORM_MOVQ_XMMdq_MEMq_0F7E=941, 
  XED_IFORM_MOVQ_XMMdq_XMMq_0F7E=942, 
  XED_IFORM_MOVQ_XMMdq_XMMq_0FD6=943, 
  XED_IFORM_MOVQ2DQ_XMMdq_MMXq=944, 
  XED_IFORM_MOVSB=945, 
  XED_IFORM_MOVSD=946, 
  XED_IFORM_MOVSD_XMM_MEMsd_XMMsd=947, 
  XED_IFORM_MOVSD_XMM_XMMdq_MEMsd=948, 
  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10=949, 
  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11=950, 
  XED_IFORM_MOVSHDUP_XMMps_MEMps=951, 
  XED_IFORM_MOVSHDUP_XMMps_XMMps=952, 
  XED_IFORM_MOVSLDUP_XMMps_MEMps=953, 
  XED_IFORM_MOVSLDUP_XMMps_XMMps=954, 
  XED_IFORM_MOVSQ=955, 
  XED_IFORM_MOVSS_MEMss_XMMss=956, 
  XED_IFORM_MOVSS_XMMdq_MEMss=957, 
  XED_IFORM_MOVSS_XMMss_XMMss_0F10=958, 
  XED_IFORM_MOVSS_XMMss_XMMss_0F11=959, 
  XED_IFORM_MOVSW=960, 
  XED_IFORM_MOVSX_GPRv_GPR16=961, 
  XED_IFORM_MOVSX_GPRv_GPR8=962, 
  XED_IFORM_MOVSX_GPRv_MEMb=963, 
  XED_IFORM_MOVSX_GPRv_MEMw=964, 
  XED_IFORM_MOVSXD_GPRv_GPRz=965, 
  XED_IFORM_MOVSXD_GPRv_MEMz=966, 
  XED_IFORM_MOVUPD_MEMpd_XMMpd=967, 
  XED_IFORM_MOVUPD_XMMpd_MEMpd=968, 
  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10=969, 
  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11=970, 
  XED_IFORM_MOVUPS_MEMps_XMMps=971, 
  XED_IFORM_MOVUPS_XMMps_MEMps=972, 
  XED_IFORM_MOVUPS_XMMps_XMMps_0F10=973, 
  XED_IFORM_MOVUPS_XMMps_XMMps_0F11=974, 
  XED_IFORM_MOVZX_GPRv_GPR16=975, 
  XED_IFORM_MOVZX_GPRv_GPR8=976, 
  XED_IFORM_MOVZX_GPRv_MEMb=977, 
  XED_IFORM_MOVZX_GPRv_MEMw=978, 
  XED_IFORM_MOV_CR_CR_GPR32=979, 
  XED_IFORM_MOV_CR_CR_GPR64=980, 
  XED_IFORM_MOV_CR_GPR32_CR=981, 
  XED_IFORM_MOV_CR_GPR64_CR=982, 
  XED_IFORM_MOV_DR_DR_GPR32=983, 
  XED_IFORM_MOV_DR_DR_GPR64=984, 
  XED_IFORM_MOV_DR_GPR32_DR=985, 
  XED_IFORM_MOV_DR_GPR64_DR=986, 
  XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb=987, 
  XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb=988, 
  XED_IFORM_MUL_GPR8=989, 
  XED_IFORM_MUL_GPRv=990, 
  XED_IFORM_MUL_MEMb=991, 
  XED_IFORM_MUL_MEMv=992, 
  XED_IFORM_MULPD_XMMpd_MEMpd=993, 
  XED_IFORM_MULPD_XMMpd_XMMpd=994, 
  XED_IFORM_MULPS_XMMps_MEMps=995, 
  XED_IFORM_MULPS_XMMps_XMMps=996, 
  XED_IFORM_MULSD_XMMsd_MEMsd=997, 
  XED_IFORM_MULSD_XMMsd_XMMsd=998, 
  XED_IFORM_MULSS_XMMss_MEMss=999, 
  XED_IFORM_MULSS_XMMss_XMMss=1000, 
  XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd=1001, 
  XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d=1002, 
  XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq=1003, 
  XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q=1004, 
  XED_IFORM_MWAIT=1005, 
  XED_IFORM_MWAITX=1006, 
  XED_IFORM_NEG_GPR8=1007, 
  XED_IFORM_NEG_GPRv=1008, 
  XED_IFORM_NEG_MEMb=1009, 
  XED_IFORM_NEG_MEMv=1010, 
  XED_IFORM_NEG_LOCK_MEMb=1011, 
  XED_IFORM_NEG_LOCK_MEMv=1012, 
  XED_IFORM_NOP_90=1013, 
  XED_IFORM_NOP_GPRv_0F18r0=1014, 
  XED_IFORM_NOP_GPRv_0F18r1=1015, 
  XED_IFORM_NOP_GPRv_0F18r2=1016, 
  XED_IFORM_NOP_GPRv_0F18r3=1017, 
  XED_IFORM_NOP_GPRv_0F18r4=1018, 
  XED_IFORM_NOP_GPRv_0F18r5=1019, 
  XED_IFORM_NOP_GPRv_0F18r6=1020, 
  XED_IFORM_NOP_GPRv_0F18r7=1021, 
  XED_IFORM_NOP_GPRv_GPRv_0F0D=1022, 
  XED_IFORM_NOP_GPRv_GPRv_0F19=1023, 
  XED_IFORM_NOP_GPRv_GPRv_0F1A=1024, 
  XED_IFORM_NOP_GPRv_GPRv_0F1B=1025, 
  XED_IFORM_NOP_GPRv_GPRv_0F1C=1026, 
  XED_IFORM_NOP_GPRv_GPRv_0F1D=1027, 
  XED_IFORM_NOP_GPRv_GPRv_0F1E=1028, 
  XED_IFORM_NOP_GPRv_GPRv_0F1F=1029, 
  XED_IFORM_NOP_GPRv_MEM_0F1B=1030, 
  XED_IFORM_NOP_GPRv_MEMv_0F1A=1031, 
  XED_IFORM_NOP_MEMv_0F18r4=1032, 
  XED_IFORM_NOP_MEMv_0F18r5=1033, 
  XED_IFORM_NOP_MEMv_0F18r6=1034, 
  XED_IFORM_NOP_MEMv_0F18r7=1035, 
  XED_IFORM_NOP_MEMv_GPRv_0F19=1036, 
  XED_IFORM_NOP_MEMv_GPRv_0F1C=1037, 
  XED_IFORM_NOP_MEMv_GPRv_0F1D=1038, 
  XED_IFORM_NOP_MEMv_GPRv_0F1E=1039, 
  XED_IFORM_NOP_MEMv_GPRv_0F1F=1040, 
  XED_IFORM_NOT_GPR8=1041, 
  XED_IFORM_NOT_GPRv=1042, 
  XED_IFORM_NOT_MEMb=1043, 
  XED_IFORM_NOT_MEMv=1044, 
  XED_IFORM_NOT_LOCK_MEMb=1045, 
  XED_IFORM_NOT_LOCK_MEMv=1046, 
  XED_IFORM_OR_AL_IMMb=1047, 
  XED_IFORM_OR_GPR8_GPR8_08=1048, 
  XED_IFORM_OR_GPR8_GPR8_0A=1049, 
  XED_IFORM_OR_GPR8_IMMb_80r1=1050, 
  XED_IFORM_OR_GPR8_IMMb_82r1=1051, 
  XED_IFORM_OR_GPR8_MEMb=1052, 
  XED_IFORM_OR_GPRv_GPRv_09=1053, 
  XED_IFORM_OR_GPRv_GPRv_0B=1054, 
  XED_IFORM_OR_GPRv_IMMb=1055, 
  XED_IFORM_OR_GPRv_IMMz=1056, 
  XED_IFORM_OR_GPRv_MEMv=1057, 
  XED_IFORM_OR_MEMb_GPR8=1058, 
  XED_IFORM_OR_MEMb_IMMb_80r1=1059, 
  XED_IFORM_OR_MEMb_IMMb_82r1=1060, 
  XED_IFORM_OR_MEMv_GPRv=1061, 
  XED_IFORM_OR_MEMv_IMMb=1062, 
  XED_IFORM_OR_MEMv_IMMz=1063, 
  XED_IFORM_OR_OrAX_IMMz=1064, 
  XED_IFORM_ORPD_XMMxuq_MEMxuq=1065, 
  XED_IFORM_ORPD_XMMxuq_XMMxuq=1066, 
  XED_IFORM_ORPS_XMMxud_MEMxud=1067, 
  XED_IFORM_ORPS_XMMxud_XMMxud=1068, 
  XED_IFORM_OR_LOCK_MEMb_GPR8=1069, 
  XED_IFORM_OR_LOCK_MEMb_IMMb_80r1=1070, 
  XED_IFORM_OR_LOCK_MEMb_IMMb_82r1=1071, 
  XED_IFORM_OR_LOCK_MEMv_GPRv=1072, 
  XED_IFORM_OR_LOCK_MEMv_IMMb=1073, 
  XED_IFORM_OR_LOCK_MEMv_IMMz=1074, 
  XED_IFORM_OUT_DX_AL=1075, 
  XED_IFORM_OUT_DX_OeAX=1076, 
  XED_IFORM_OUT_IMMb_AL=1077, 
  XED_IFORM_OUT_IMMb_OeAX=1078, 
  XED_IFORM_OUTSB=1079, 
  XED_IFORM_OUTSD=1080, 
  XED_IFORM_OUTSW=1081, 
  XED_IFORM_PABSB_MMXq_MEMq=1082, 
  XED_IFORM_PABSB_MMXq_MMXq=1083, 
  XED_IFORM_PABSB_XMMdq_MEMdq=1084, 
  XED_IFORM_PABSB_XMMdq_XMMdq=1085, 
  XED_IFORM_PABSD_MMXq_MEMq=1086, 
  XED_IFORM_PABSD_MMXq_MMXq=1087, 
  XED_IFORM_PABSD_XMMdq_MEMdq=1088, 
  XED_IFORM_PABSD_XMMdq_XMMdq=1089, 
  XED_IFORM_PABSW_MMXq_MEMq=1090, 
  XED_IFORM_PABSW_MMXq_MMXq=1091, 
  XED_IFORM_PABSW_XMMdq_MEMdq=1092, 
  XED_IFORM_PABSW_XMMdq_XMMdq=1093, 
  XED_IFORM_PACKSSDW_MMXq_MEMq=1094, 
  XED_IFORM_PACKSSDW_MMXq_MMXq=1095, 
  XED_IFORM_PACKSSDW_XMMdq_MEMdq=1096, 
  XED_IFORM_PACKSSDW_XMMdq_XMMdq=1097, 
  XED_IFORM_PACKSSWB_MMXq_MEMq=1098, 
  XED_IFORM_PACKSSWB_MMXq_MMXq=1099, 
  XED_IFORM_PACKSSWB_XMMdq_MEMdq=1100, 
  XED_IFORM_PACKSSWB_XMMdq_XMMdq=1101, 
  XED_IFORM_PACKUSDW_XMMdq_MEMdq=1102, 
  XED_IFORM_PACKUSDW_XMMdq_XMMdq=1103, 
  XED_IFORM_PACKUSWB_MMXq_MEMq=1104, 
  XED_IFORM_PACKUSWB_MMXq_MMXq=1105, 
  XED_IFORM_PACKUSWB_XMMdq_MEMdq=1106, 
  XED_IFORM_PACKUSWB_XMMdq_XMMdq=1107, 
  XED_IFORM_PADDB_MMXq_MEMq=1108, 
  XED_IFORM_PADDB_MMXq_MMXq=1109, 
  XED_IFORM_PADDB_XMMdq_MEMdq=1110, 
  XED_IFORM_PADDB_XMMdq_XMMdq=1111, 
  XED_IFORM_PADDD_MMXq_MEMq=1112, 
  XED_IFORM_PADDD_MMXq_MMXq=1113, 
  XED_IFORM_PADDD_XMMdq_MEMdq=1114, 
  XED_IFORM_PADDD_XMMdq_XMMdq=1115, 
  XED_IFORM_PADDQ_MMXq_MEMq=1116, 
  XED_IFORM_PADDQ_MMXq_MMXq=1117, 
  XED_IFORM_PADDQ_XMMdq_MEMdq=1118, 
  XED_IFORM_PADDQ_XMMdq_XMMdq=1119, 
  XED_IFORM_PADDSB_MMXq_MEMq=1120, 
  XED_IFORM_PADDSB_MMXq_MMXq=1121, 
  XED_IFORM_PADDSB_XMMdq_MEMdq=1122, 
  XED_IFORM_PADDSB_XMMdq_XMMdq=1123, 
  XED_IFORM_PADDSW_MMXq_MEMq=1124, 
  XED_IFORM_PADDSW_MMXq_MMXq=1125, 
  XED_IFORM_PADDSW_XMMdq_MEMdq=1126, 
  XED_IFORM_PADDSW_XMMdq_XMMdq=1127, 
  XED_IFORM_PADDUSB_MMXq_MEMq=1128, 
  XED_IFORM_PADDUSB_MMXq_MMXq=1129, 
  XED_IFORM_PADDUSB_XMMdq_MEMdq=1130, 
  XED_IFORM_PADDUSB_XMMdq_XMMdq=1131, 
  XED_IFORM_PADDUSW_MMXq_MEMq=1132, 
  XED_IFORM_PADDUSW_MMXq_MMXq=1133, 
  XED_IFORM_PADDUSW_XMMdq_MEMdq=1134, 
  XED_IFORM_PADDUSW_XMMdq_XMMdq=1135, 
  XED_IFORM_PADDW_MMXq_MEMq=1136, 
  XED_IFORM_PADDW_MMXq_MMXq=1137, 
  XED_IFORM_PADDW_XMMdq_MEMdq=1138, 
  XED_IFORM_PADDW_XMMdq_XMMdq=1139, 
  XED_IFORM_PALIGNR_MMXq_MEMq_IMMb=1140, 
  XED_IFORM_PALIGNR_MMXq_MMXq_IMMb=1141, 
  XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb=1142, 
  XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb=1143, 
  XED_IFORM_PAND_MMXq_MEMq=1144, 
  XED_IFORM_PAND_MMXq_MMXq=1145, 
  XED_IFORM_PAND_XMMdq_MEMdq=1146, 
  XED_IFORM_PAND_XMMdq_XMMdq=1147, 
  XED_IFORM_PANDN_MMXq_MEMq=1148, 
  XED_IFORM_PANDN_MMXq_MMXq=1149, 
  XED_IFORM_PANDN_XMMdq_MEMdq=1150, 
  XED_IFORM_PANDN_XMMdq_XMMdq=1151, 
  XED_IFORM_PAUSE=1152, 
  XED_IFORM_PAVGB_MMXq_MEMq=1153, 
  XED_IFORM_PAVGB_MMXq_MMXq=1154, 
  XED_IFORM_PAVGB_XMMdq_MEMdq=1155, 
  XED_IFORM_PAVGB_XMMdq_XMMdq=1156, 
  XED_IFORM_PAVGUSB_MMXq_MEMq=1157, 
  XED_IFORM_PAVGUSB_MMXq_MMXq=1158, 
  XED_IFORM_PAVGW_MMXq_MEMq=1159, 
  XED_IFORM_PAVGW_MMXq_MMXq=1160, 
  XED_IFORM_PAVGW_XMMdq_MEMdq=1161, 
  XED_IFORM_PAVGW_XMMdq_XMMdq=1162, 
  XED_IFORM_PBLENDVB_XMMdq_MEMdq=1163, 
  XED_IFORM_PBLENDVB_XMMdq_XMMdq=1164, 
  XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb=1165, 
  XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb=1166, 
  XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb=1167, 
  XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb=1168, 
  XED_IFORM_PCMPEQB_MMXq_MEMq=1169, 
  XED_IFORM_PCMPEQB_MMXq_MMXq=1170, 
  XED_IFORM_PCMPEQB_XMMdq_MEMdq=1171, 
  XED_IFORM_PCMPEQB_XMMdq_XMMdq=1172, 
  XED_IFORM_PCMPEQD_MMXq_MEMq=1173, 
  XED_IFORM_PCMPEQD_MMXq_MMXq=1174, 
  XED_IFORM_PCMPEQD_XMMdq_MEMdq=1175, 
  XED_IFORM_PCMPEQD_XMMdq_XMMdq=1176, 
  XED_IFORM_PCMPEQQ_XMMdq_MEMdq=1177, 
  XED_IFORM_PCMPEQQ_XMMdq_XMMdq=1178, 
  XED_IFORM_PCMPEQW_MMXq_MEMq=1179, 
  XED_IFORM_PCMPEQW_MMXq_MMXq=1180, 
  XED_IFORM_PCMPEQW_XMMdq_MEMdq=1181, 
  XED_IFORM_PCMPEQW_XMMdq_XMMdq=1182, 
  XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb=1183, 
  XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb=1184, 
  XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb=1185, 
  XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb=1186, 
  XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb=1187, 
  XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb=1188, 
  XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb=1189, 
  XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb=1190, 
  XED_IFORM_PCMPGTB_MMXq_MEMq=1191, 
  XED_IFORM_PCMPGTB_MMXq_MMXq=1192, 
  XED_IFORM_PCMPGTB_XMMdq_MEMdq=1193, 
  XED_IFORM_PCMPGTB_XMMdq_XMMdq=1194, 
  XED_IFORM_PCMPGTD_MMXq_MEMq=1195, 
  XED_IFORM_PCMPGTD_MMXq_MMXq=1196, 
  XED_IFORM_PCMPGTD_XMMdq_MEMdq=1197, 
  XED_IFORM_PCMPGTD_XMMdq_XMMdq=1198, 
  XED_IFORM_PCMPGTQ_XMMdq_MEMdq=1199, 
  XED_IFORM_PCMPGTQ_XMMdq_XMMdq=1200, 
  XED_IFORM_PCMPGTW_MMXq_MEMq=1201, 
  XED_IFORM_PCMPGTW_MMXq_MMXq=1202, 
  XED_IFORM_PCMPGTW_XMMdq_MEMdq=1203, 
  XED_IFORM_PCMPGTW_XMMdq_XMMdq=1204, 
  XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb=1205, 
  XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb=1206, 
  XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb=1207, 
  XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb=1208, 
  XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb=1209, 
  XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb=1210, 
  XED_IFORM_PCONFIG=1211, 
  XED_IFORM_PCONFIG64=1212, 
  XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd=1213, 
  XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d=1214, 
  XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq=1215, 
  XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q=1216, 
  XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd=1217, 
  XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d=1218, 
  XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq=1219, 
  XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q=1220, 
  XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb=1221, 
  XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb=1222, 
  XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb=1223, 
  XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb=1224, 
  XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb=1225, 
  XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb=1226, 
  XED_IFORM_PEXTRW_GPR32_MMXq_IMMb=1227, 
  XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb=1228, 
  XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb=1229, 
  XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb=1230, 
  XED_IFORM_PF2ID_MMXq_MEMq=1231, 
  XED_IFORM_PF2ID_MMXq_MMXq=1232, 
  XED_IFORM_PF2IW_MMXq_MEMq=1233, 
  XED_IFORM_PF2IW_MMXq_MMXq=1234, 
  XED_IFORM_PFACC_MMXq_MEMq=1235, 
  XED_IFORM_PFACC_MMXq_MMXq=1236, 
  XED_IFORM_PFADD_MMXq_MEMq=1237, 
  XED_IFORM_PFADD_MMXq_MMXq=1238, 
  XED_IFORM_PFCMPEQ_MMXq_MEMq=1239, 
  XED_IFORM_PFCMPEQ_MMXq_MMXq=1240, 
  XED_IFORM_PFCMPGE_MMXq_MEMq=1241, 
  XED_IFORM_PFCMPGE_MMXq_MMXq=1242, 
  XED_IFORM_PFCMPGT_MMXq_MEMq=1243, 
  XED_IFORM_PFCMPGT_MMXq_MMXq=1244, 
  XED_IFORM_PFMAX_MMXq_MEMq=1245, 
  XED_IFORM_PFMAX_MMXq_MMXq=1246, 
  XED_IFORM_PFMIN_MMXq_MEMq=1247, 
  XED_IFORM_PFMIN_MMXq_MMXq=1248, 
  XED_IFORM_PFMUL_MMXq_MEMq=1249, 
  XED_IFORM_PFMUL_MMXq_MMXq=1250, 
  XED_IFORM_PFNACC_MMXq_MEMq=1251, 
  XED_IFORM_PFNACC_MMXq_MMXq=1252, 
  XED_IFORM_PFPNACC_MMXq_MEMq=1253, 
  XED_IFORM_PFPNACC_MMXq_MMXq=1254, 
  XED_IFORM_PFRCP_MMXq_MEMq=1255, 
  XED_IFORM_PFRCP_MMXq_MMXq=1256, 
  XED_IFORM_PFRCPIT1_MMXq_MEMq=1257, 
  XED_IFORM_PFRCPIT1_MMXq_MMXq=1258, 
  XED_IFORM_PFRCPIT2_MMXq_MEMq=1259, 
  XED_IFORM_PFRCPIT2_MMXq_MMXq=1260, 
  XED_IFORM_PFRSQIT1_MMXq_MEMq=1261, 
  XED_IFORM_PFRSQIT1_MMXq_MMXq=1262, 
  XED_IFORM_PFRSQRT_MMXq_MEMq=1263, 
  XED_IFORM_PFRSQRT_MMXq_MMXq=1264, 
  XED_IFORM_PFSUB_MMXq_MEMq=1265, 
  XED_IFORM_PFSUB_MMXq_MMXq=1266, 
  XED_IFORM_PFSUBR_MMXq_MEMq=1267, 
  XED_IFORM_PFSUBR_MMXq_MMXq=1268, 
  XED_IFORM_PHADDD_MMXq_MEMq=1269, 
  XED_IFORM_PHADDD_MMXq_MMXq=1270, 
  XED_IFORM_PHADDD_XMMdq_MEMdq=1271, 
  XED_IFORM_PHADDD_XMMdq_XMMdq=1272, 
  XED_IFORM_PHADDSW_MMXq_MEMq=1273, 
  XED_IFORM_PHADDSW_MMXq_MMXq=1274, 
  XED_IFORM_PHADDSW_XMMdq_MEMdq=1275, 
  XED_IFORM_PHADDSW_XMMdq_XMMdq=1276, 
  XED_IFORM_PHADDW_MMXq_MEMq=1277, 
  XED_IFORM_PHADDW_MMXq_MMXq=1278, 
  XED_IFORM_PHADDW_XMMdq_MEMdq=1279, 
  XED_IFORM_PHADDW_XMMdq_XMMdq=1280, 
  XED_IFORM_PHMINPOSUW_XMMdq_MEMdq=1281, 
  XED_IFORM_PHMINPOSUW_XMMdq_XMMdq=1282, 
  XED_IFORM_PHSUBD_MMXq_MEMq=1283, 
  XED_IFORM_PHSUBD_MMXq_MMXq=1284, 
  XED_IFORM_PHSUBD_XMMdq_MEMdq=1285, 
  XED_IFORM_PHSUBD_XMMdq_XMMdq=1286, 
  XED_IFORM_PHSUBSW_MMXq_MEMq=1287, 
  XED_IFORM_PHSUBSW_MMXq_MMXq=1288, 
  XED_IFORM_PHSUBSW_XMMdq_MEMdq=1289, 
  XED_IFORM_PHSUBSW_XMMdq_XMMdq=1290, 
  XED_IFORM_PHSUBW_MMXq_MEMq=1291, 
  XED_IFORM_PHSUBW_MMXq_MMXq=1292, 
  XED_IFORM_PHSUBW_XMMdq_MEMdq=1293, 
  XED_IFORM_PHSUBW_XMMdq_XMMdq=1294, 
  XED_IFORM_PI2FD_MMXq_MEMq=1295, 
  XED_IFORM_PI2FD_MMXq_MMXq=1296, 
  XED_IFORM_PI2FW_MMXq_MEMq=1297, 
  XED_IFORM_PI2FW_MMXq_MMXq=1298, 
  XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb=1299, 
  XED_IFORM_PINSRB_XMMdq_MEMb_IMMb=1300, 
  XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb=1301, 
  XED_IFORM_PINSRD_XMMdq_MEMd_IMMb=1302, 
  XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb=1303, 
  XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb=1304, 
  XED_IFORM_PINSRW_MMXq_GPR32_IMMb=1305, 
  XED_IFORM_PINSRW_MMXq_MEMw_IMMb=1306, 
  XED_IFORM_PINSRW_XMMdq_GPR32_IMMb=1307, 
  XED_IFORM_PINSRW_XMMdq_MEMw_IMMb=1308, 
  XED_IFORM_PMADDUBSW_MMXq_MEMq=1309, 
  XED_IFORM_PMADDUBSW_MMXq_MMXq=1310, 
  XED_IFORM_PMADDUBSW_XMMdq_MEMdq=1311, 
  XED_IFORM_PMADDUBSW_XMMdq_XMMdq=1312, 
  XED_IFORM_PMADDWD_MMXq_MEMq=1313, 
  XED_IFORM_PMADDWD_MMXq_MMXq=1314, 
  XED_IFORM_PMADDWD_XMMdq_MEMdq=1315, 
  XED_IFORM_PMADDWD_XMMdq_XMMdq=1316, 
  XED_IFORM_PMAXSB_XMMdq_MEMdq=1317, 
  XED_IFORM_PMAXSB_XMMdq_XMMdq=1318, 
  XED_IFORM_PMAXSD_XMMdq_MEMdq=1319, 
  XED_IFORM_PMAXSD_XMMdq_XMMdq=1320, 
  XED_IFORM_PMAXSW_MMXq_MEMq=1321, 
  XED_IFORM_PMAXSW_MMXq_MMXq=1322, 
  XED_IFORM_PMAXSW_XMMdq_MEMdq=1323, 
  XED_IFORM_PMAXSW_XMMdq_XMMdq=1324, 
  XED_IFORM_PMAXUB_MMXq_MEMq=1325, 
  XED_IFORM_PMAXUB_MMXq_MMXq=1326, 
  XED_IFORM_PMAXUB_XMMdq_MEMdq=1327, 
  XED_IFORM_PMAXUB_XMMdq_XMMdq=1328, 
  XED_IFORM_PMAXUD_XMMdq_MEMdq=1329, 
  XED_IFORM_PMAXUD_XMMdq_XMMdq=1330, 
  XED_IFORM_PMAXUW_XMMdq_MEMdq=1331, 
  XED_IFORM_PMAXUW_XMMdq_XMMdq=1332, 
  XED_IFORM_PMINSB_XMMdq_MEMdq=1333, 
  XED_IFORM_PMINSB_XMMdq_XMMdq=1334, 
  XED_IFORM_PMINSD_XMMdq_MEMdq=1335, 
  XED_IFORM_PMINSD_XMMdq_XMMdq=1336, 
  XED_IFORM_PMINSW_MMXq_MEMq=1337, 
  XED_IFORM_PMINSW_MMXq_MMXq=1338, 
  XED_IFORM_PMINSW_XMMdq_MEMdq=1339, 
  XED_IFORM_PMINSW_XMMdq_XMMdq=1340, 
  XED_IFORM_PMINUB_MMXq_MEMq=1341, 
  XED_IFORM_PMINUB_MMXq_MMXq=1342, 
  XED_IFORM_PMINUB_XMMdq_MEMdq=1343, 
  XED_IFORM_PMINUB_XMMdq_XMMdq=1344, 
  XED_IFORM_PMINUD_XMMdq_MEMdq=1345, 
  XED_IFORM_PMINUD_XMMdq_XMMdq=1346, 
  XED_IFORM_PMINUW_XMMdq_MEMdq=1347, 
  XED_IFORM_PMINUW_XMMdq_XMMdq=1348, 
  XED_IFORM_PMOVMSKB_GPR32_MMXq=1349, 
  XED_IFORM_PMOVMSKB_GPR32_XMMdq=1350, 
  XED_IFORM_PMOVSXBD_XMMdq_MEMd=1351, 
  XED_IFORM_PMOVSXBD_XMMdq_XMMd=1352, 
  XED_IFORM_PMOVSXBQ_XMMdq_MEMw=1353, 
  XED_IFORM_PMOVSXBQ_XMMdq_XMMw=1354, 
  XED_IFORM_PMOVSXBW_XMMdq_MEMq=1355, 
  XED_IFORM_PMOVSXBW_XMMdq_XMMq=1356, 
  XED_IFORM_PMOVSXDQ_XMMdq_MEMq=1357, 
  XED_IFORM_PMOVSXDQ_XMMdq_XMMq=1358, 
  XED_IFORM_PMOVSXWD_XMMdq_MEMq=1359, 
  XED_IFORM_PMOVSXWD_XMMdq_XMMq=1360, 
  XED_IFORM_PMOVSXWQ_XMMdq_MEMd=1361, 
  XED_IFORM_PMOVSXWQ_XMMdq_XMMd=1362, 
  XED_IFORM_PMOVZXBD_XMMdq_MEMd=1363, 
  XED_IFORM_PMOVZXBD_XMMdq_XMMd=1364, 
  XED_IFORM_PMOVZXBQ_XMMdq_MEMw=1365, 
  XED_IFORM_PMOVZXBQ_XMMdq_XMMw=1366, 
  XED_IFORM_PMOVZXBW_XMMdq_MEMq=1367, 
  XED_IFORM_PMOVZXBW_XMMdq_XMMq=1368, 
  XED_IFORM_PMOVZXDQ_XMMdq_MEMq=1369, 
  XED_IFORM_PMOVZXDQ_XMMdq_XMMq=1370, 
  XED_IFORM_PMOVZXWD_XMMdq_MEMq=1371, 
  XED_IFORM_PMOVZXWD_XMMdq_XMMq=1372, 
  XED_IFORM_PMOVZXWQ_XMMdq_MEMd=1373, 
  XED_IFORM_PMOVZXWQ_XMMdq_XMMd=1374, 
  XED_IFORM_PMULDQ_XMMdq_MEMdq=1375, 
  XED_IFORM_PMULDQ_XMMdq_XMMdq=1376, 
  XED_IFORM_PMULHRSW_MMXq_MEMq=1377, 
  XED_IFORM_PMULHRSW_MMXq_MMXq=1378, 
  XED_IFORM_PMULHRSW_XMMdq_MEMdq=1379, 
  XED_IFORM_PMULHRSW_XMMdq_XMMdq=1380, 
  XED_IFORM_PMULHRW_MMXq_MEMq=1381, 
  XED_IFORM_PMULHRW_MMXq_MMXq=1382, 
  XED_IFORM_PMULHUW_MMXq_MEMq=1383, 
  XED_IFORM_PMULHUW_MMXq_MMXq=1384, 
  XED_IFORM_PMULHUW_XMMdq_MEMdq=1385, 
  XED_IFORM_PMULHUW_XMMdq_XMMdq=1386, 
  XED_IFORM_PMULHW_MMXq_MEMq=1387, 
  XED_IFORM_PMULHW_MMXq_MMXq=1388, 
  XED_IFORM_PMULHW_XMMdq_MEMdq=1389, 
  XED_IFORM_PMULHW_XMMdq_XMMdq=1390, 
  XED_IFORM_PMULLD_XMMdq_MEMdq=1391, 
  XED_IFORM_PMULLD_XMMdq_XMMdq=1392, 
  XED_IFORM_PMULLW_MMXq_MEMq=1393, 
  XED_IFORM_PMULLW_MMXq_MMXq=1394, 
  XED_IFORM_PMULLW_XMMdq_MEMdq=1395, 
  XED_IFORM_PMULLW_XMMdq_XMMdq=1396, 
  XED_IFORM_PMULUDQ_MMXq_MEMq=1397, 
  XED_IFORM_PMULUDQ_MMXq_MMXq=1398, 
  XED_IFORM_PMULUDQ_XMMdq_MEMdq=1399, 
  XED_IFORM_PMULUDQ_XMMdq_XMMdq=1400, 
  XED_IFORM_POP_DS=1401, 
  XED_IFORM_POP_ES=1402, 
  XED_IFORM_POP_FS=1403, 
  XED_IFORM_POP_GPRv_58=1404, 
  XED_IFORM_POP_GPRv_8F=1405, 
  XED_IFORM_POP_GS=1406, 
  XED_IFORM_POP_MEMv=1407, 
  XED_IFORM_POP_SS=1408, 
  XED_IFORM_POPA=1409, 
  XED_IFORM_POPAD=1410, 
  XED_IFORM_POPCNT_GPRv_GPRv=1411, 
  XED_IFORM_POPCNT_GPRv_MEMv=1412, 
  XED_IFORM_POPF=1413, 
  XED_IFORM_POPFD=1414, 
  XED_IFORM_POPFQ=1415, 
  XED_IFORM_POR_MMXq_MEMq=1416, 
  XED_IFORM_POR_MMXq_MMXq=1417, 
  XED_IFORM_POR_XMMdq_MEMdq=1418, 
  XED_IFORM_POR_XMMdq_XMMdq=1419, 
  XED_IFORM_PREFETCHNTA_MEMmprefetch=1420, 
  XED_IFORM_PREFETCHT0_MEMmprefetch=1421, 
  XED_IFORM_PREFETCHT1_MEMmprefetch=1422, 
  XED_IFORM_PREFETCHT2_MEMmprefetch=1423, 
  XED_IFORM_PREFETCHW_0F0Dr1=1424, 
  XED_IFORM_PREFETCHW_0F0Dr3=1425, 
  XED_IFORM_PREFETCHWT1_MEMu8=1426, 
  XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch=1427, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr4=1428, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr5=1429, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr6=1430, 
  XED_IFORM_PREFETCH_RESERVED_0F0Dr7=1431, 
  XED_IFORM_PSADBW_MMXq_MEMq=1432, 
  XED_IFORM_PSADBW_MMXq_MMXq=1433, 
  XED_IFORM_PSADBW_XMMdq_MEMdq=1434, 
  XED_IFORM_PSADBW_XMMdq_XMMdq=1435, 
  XED_IFORM_PSHUFB_MMXq_MEMq=1436, 
  XED_IFORM_PSHUFB_MMXq_MMXq=1437, 
  XED_IFORM_PSHUFB_XMMdq_MEMdq=1438, 
  XED_IFORM_PSHUFB_XMMdq_XMMdq=1439, 
  XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb=1440, 
  XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb=1441, 
  XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb=1442, 
  XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb=1443, 
  XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb=1444, 
  XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb=1445, 
  XED_IFORM_PSHUFW_MMXq_MEMq_IMMb=1446, 
  XED_IFORM_PSHUFW_MMXq_MMXq_IMMb=1447, 
  XED_IFORM_PSIGNB_MMXq_MEMq=1448, 
  XED_IFORM_PSIGNB_MMXq_MMXq=1449, 
  XED_IFORM_PSIGNB_XMMdq_MEMdq=1450, 
  XED_IFORM_PSIGNB_XMMdq_XMMdq=1451, 
  XED_IFORM_PSIGND_MMXq_MEMq=1452, 
  XED_IFORM_PSIGND_MMXq_MMXq=1453, 
  XED_IFORM_PSIGND_XMMdq_MEMdq=1454, 
  XED_IFORM_PSIGND_XMMdq_XMMdq=1455, 
  XED_IFORM_PSIGNW_MMXq_MEMq=1456, 
  XED_IFORM_PSIGNW_MMXq_MMXq=1457, 
  XED_IFORM_PSIGNW_XMMdq_MEMdq=1458, 
  XED_IFORM_PSIGNW_XMMdq_XMMdq=1459, 
  XED_IFORM_PSLLD_MMXq_IMMb=1460, 
  XED_IFORM_PSLLD_MMXq_MEMq=1461, 
  XED_IFORM_PSLLD_MMXq_MMXq=1462, 
  XED_IFORM_PSLLD_XMMdq_IMMb=1463, 
  XED_IFORM_PSLLD_XMMdq_MEMdq=1464, 
  XED_IFORM_PSLLD_XMMdq_XMMdq=1465, 
  XED_IFORM_PSLLDQ_XMMdq_IMMb=1466, 
  XED_IFORM_PSLLQ_MMXq_IMMb=1467, 
  XED_IFORM_PSLLQ_MMXq_MEMq=1468, 
  XED_IFORM_PSLLQ_MMXq_MMXq=1469, 
  XED_IFORM_PSLLQ_XMMdq_IMMb=1470, 
  XED_IFORM_PSLLQ_XMMdq_MEMdq=1471, 
  XED_IFORM_PSLLQ_XMMdq_XMMdq=1472, 
  XED_IFORM_PSLLW_MMXq_IMMb=1473, 
  XED_IFORM_PSLLW_MMXq_MEMq=1474, 
  XED_IFORM_PSLLW_MMXq_MMXq=1475, 
  XED_IFORM_PSLLW_XMMdq_IMMb=1476, 
  XED_IFORM_PSLLW_XMMdq_MEMdq=1477, 
  XED_IFORM_PSLLW_XMMdq_XMMdq=1478, 
  XED_IFORM_PSMASH_RAX=1479, 
  XED_IFORM_PSRAD_MMXq_IMMb=1480, 
  XED_IFORM_PSRAD_MMXq_MEMq=1481, 
  XED_IFORM_PSRAD_MMXq_MMXq=1482, 
  XED_IFORM_PSRAD_XMMdq_IMMb=1483, 
  XED_IFORM_PSRAD_XMMdq_MEMdq=1484, 
  XED_IFORM_PSRAD_XMMdq_XMMdq=1485, 
  XED_IFORM_PSRAW_MMXq_IMMb=1486, 
  XED_IFORM_PSRAW_MMXq_MEMq=1487, 
  XED_IFORM_PSRAW_MMXq_MMXq=1488, 
  XED_IFORM_PSRAW_XMMdq_IMMb=1489, 
  XED_IFORM_PSRAW_XMMdq_MEMdq=1490, 
  XED_IFORM_PSRAW_XMMdq_XMMdq=1491, 
  XED_IFORM_PSRLD_MMXq_IMMb=1492, 
  XED_IFORM_PSRLD_MMXq_MEMq=1493, 
  XED_IFORM_PSRLD_MMXq_MMXq=1494, 
  XED_IFORM_PSRLD_XMMdq_IMMb=1495, 
  XED_IFORM_PSRLD_XMMdq_MEMdq=1496, 
  XED_IFORM_PSRLD_XMMdq_XMMdq=1497, 
  XED_IFORM_PSRLDQ_XMMdq_IMMb=1498, 
  XED_IFORM_PSRLQ_MMXq_IMMb=1499, 
  XED_IFORM_PSRLQ_MMXq_MEMq=1500, 
  XED_IFORM_PSRLQ_MMXq_MMXq=1501, 
  XED_IFORM_PSRLQ_XMMdq_IMMb=1502, 
  XED_IFORM_PSRLQ_XMMdq_MEMdq=1503, 
  XED_IFORM_PSRLQ_XMMdq_XMMdq=1504, 
  XED_IFORM_PSRLW_MMXq_IMMb=1505, 
  XED_IFORM_PSRLW_MMXq_MEMq=1506, 
  XED_IFORM_PSRLW_MMXq_MMXq=1507, 
  XED_IFORM_PSRLW_XMMdq_IMMb=1508, 
  XED_IFORM_PSRLW_XMMdq_MEMdq=1509, 
  XED_IFORM_PSRLW_XMMdq_XMMdq=1510, 
  XED_IFORM_PSUBB_MMXq_MEMq=1511, 
  XED_IFORM_PSUBB_MMXq_MMXq=1512, 
  XED_IFORM_PSUBB_XMMdq_MEMdq=1513, 
  XED_IFORM_PSUBB_XMMdq_XMMdq=1514, 
  XED_IFORM_PSUBD_MMXq_MEMq=1515, 
  XED_IFORM_PSUBD_MMXq_MMXq=1516, 
  XED_IFORM_PSUBD_XMMdq_MEMdq=1517, 
  XED_IFORM_PSUBD_XMMdq_XMMdq=1518, 
  XED_IFORM_PSUBQ_MMXq_MEMq=1519, 
  XED_IFORM_PSUBQ_MMXq_MMXq=1520, 
  XED_IFORM_PSUBQ_XMMdq_MEMdq=1521, 
  XED_IFORM_PSUBQ_XMMdq_XMMdq=1522, 
  XED_IFORM_PSUBSB_MMXq_MEMq=1523, 
  XED_IFORM_PSUBSB_MMXq_MMXq=1524, 
  XED_IFORM_PSUBSB_XMMdq_MEMdq=1525, 
  XED_IFORM_PSUBSB_XMMdq_XMMdq=1526, 
  XED_IFORM_PSUBSW_MMXq_MEMq=1527, 
  XED_IFORM_PSUBSW_MMXq_MMXq=1528, 
  XED_IFORM_PSUBSW_XMMdq_MEMdq=1529, 
  XED_IFORM_PSUBSW_XMMdq_XMMdq=1530, 
  XED_IFORM_PSUBUSB_MMXq_MEMq=1531, 
  XED_IFORM_PSUBUSB_MMXq_MMXq=1532, 
  XED_IFORM_PSUBUSB_XMMdq_MEMdq=1533, 
  XED_IFORM_PSUBUSB_XMMdq_XMMdq=1534, 
  XED_IFORM_PSUBUSW_MMXq_MEMq=1535, 
  XED_IFORM_PSUBUSW_MMXq_MMXq=1536, 
  XED_IFORM_PSUBUSW_XMMdq_MEMdq=1537, 
  XED_IFORM_PSUBUSW_XMMdq_XMMdq=1538, 
  XED_IFORM_PSUBW_MMXq_MEMq=1539, 
  XED_IFORM_PSUBW_MMXq_MMXq=1540, 
  XED_IFORM_PSUBW_XMMdq_MEMdq=1541, 
  XED_IFORM_PSUBW_XMMdq_XMMdq=1542, 
  XED_IFORM_PSWAPD_MMXq_MEMq=1543, 
  XED_IFORM_PSWAPD_MMXq_MMXq=1544, 
  XED_IFORM_PTEST_XMMdq_MEMdq=1545, 
  XED_IFORM_PTEST_XMMdq_XMMdq=1546, 
  XED_IFORM_PTWRITE_GPRy=1547, 
  XED_IFORM_PTWRITE_MEMy=1548, 
  XED_IFORM_PUNPCKHBW_MMXq_MEMq=1549, 
  XED_IFORM_PUNPCKHBW_MMXq_MMXd=1550, 
  XED_IFORM_PUNPCKHBW_XMMdq_MEMdq=1551, 
  XED_IFORM_PUNPCKHBW_XMMdq_XMMq=1552, 
  XED_IFORM_PUNPCKHDQ_MMXq_MEMq=1553, 
  XED_IFORM_PUNPCKHDQ_MMXq_MMXd=1554, 
  XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq=1555, 
  XED_IFORM_PUNPCKHDQ_XMMdq_XMMq=1556, 
  XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq=1557, 
  XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq=1558, 
  XED_IFORM_PUNPCKHWD_MMXq_MEMq=1559, 
  XED_IFORM_PUNPCKHWD_MMXq_MMXd=1560, 
  XED_IFORM_PUNPCKHWD_XMMdq_MEMdq=1561, 
  XED_IFORM_PUNPCKHWD_XMMdq_XMMq=1562, 
  XED_IFORM_PUNPCKLBW_MMXq_MEMd=1563, 
  XED_IFORM_PUNPCKLBW_MMXq_MMXd=1564, 
  XED_IFORM_PUNPCKLBW_XMMdq_MEMdq=1565, 
  XED_IFORM_PUNPCKLBW_XMMdq_XMMq=1566, 
  XED_IFORM_PUNPCKLDQ_MMXq_MEMd=1567, 
  XED_IFORM_PUNPCKLDQ_MMXq_MMXd=1568, 
  XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq=1569, 
  XED_IFORM_PUNPCKLDQ_XMMdq_XMMq=1570, 
  XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq=1571, 
  XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq=1572, 
  XED_IFORM_PUNPCKLWD_MMXq_MEMd=1573, 
  XED_IFORM_PUNPCKLWD_MMXq_MMXd=1574, 
  XED_IFORM_PUNPCKLWD_XMMdq_MEMdq=1575, 
  XED_IFORM_PUNPCKLWD_XMMdq_XMMq=1576, 
  XED_IFORM_PUSH_CS=1577, 
  XED_IFORM_PUSH_DS=1578, 
  XED_IFORM_PUSH_ES=1579, 
  XED_IFORM_PUSH_FS=1580, 
  XED_IFORM_PUSH_GPRv_50=1581, 
  XED_IFORM_PUSH_GPRv_FFr6=1582, 
  XED_IFORM_PUSH_GS=1583, 
  XED_IFORM_PUSH_IMMb=1584, 
  XED_IFORM_PUSH_IMMz=1585, 
  XED_IFORM_PUSH_MEMv=1586, 
  XED_IFORM_PUSH_SS=1587, 
  XED_IFORM_PUSHA=1588, 
  XED_IFORM_PUSHAD=1589, 
  XED_IFORM_PUSHF=1590, 
  XED_IFORM_PUSHFD=1591, 
  XED_IFORM_PUSHFQ=1592, 
  XED_IFORM_PVALIDATE_RAX_ECX_EDX=1593, 
  XED_IFORM_PXOR_MMXq_MEMq=1594, 
  XED_IFORM_PXOR_MMXq_MMXq=1595, 
  XED_IFORM_PXOR_XMMdq_MEMdq=1596, 
  XED_IFORM_PXOR_XMMdq_XMMdq=1597, 
  XED_IFORM_RCL_GPR8_CL=1598, 
  XED_IFORM_RCL_GPR8_IMMb=1599, 
  XED_IFORM_RCL_GPR8_ONE=1600, 
  XED_IFORM_RCL_GPRv_CL=1601, 
  XED_IFORM_RCL_GPRv_IMMb=1602, 
  XED_IFORM_RCL_GPRv_ONE=1603, 
  XED_IFORM_RCL_MEMb_CL=1604, 
  XED_IFORM_RCL_MEMb_IMMb=1605, 
  XED_IFORM_RCL_MEMb_ONE=1606, 
  XED_IFORM_RCL_MEMv_CL=1607, 
  XED_IFORM_RCL_MEMv_IMMb=1608, 
  XED_IFORM_RCL_MEMv_ONE=1609, 
  XED_IFORM_RCPPS_XMMps_MEMps=1610, 
  XED_IFORM_RCPPS_XMMps_XMMps=1611, 
  XED_IFORM_RCPSS_XMMss_MEMss=1612, 
  XED_IFORM_RCPSS_XMMss_XMMss=1613, 
  XED_IFORM_RCR_GPR8_CL=1614, 
  XED_IFORM_RCR_GPR8_IMMb=1615, 
  XED_IFORM_RCR_GPR8_ONE=1616, 
  XED_IFORM_RCR_GPRv_CL=1617, 
  XED_IFORM_RCR_GPRv_IMMb=1618, 
  XED_IFORM_RCR_GPRv_ONE=1619, 
  XED_IFORM_RCR_MEMb_CL=1620, 
  XED_IFORM_RCR_MEMb_IMMb=1621, 
  XED_IFORM_RCR_MEMb_ONE=1622, 
  XED_IFORM_RCR_MEMv_CL=1623, 
  XED_IFORM_RCR_MEMv_IMMb=1624, 
  XED_IFORM_RCR_MEMv_ONE=1625, 
  XED_IFORM_RDFSBASE_GPRy=1626, 
  XED_IFORM_RDGSBASE_GPRy=1627, 
  XED_IFORM_RDMSR=1628, 
  XED_IFORM_RDPID_GPR32u32=1629, 
  XED_IFORM_RDPID_GPR64u64=1630, 
  XED_IFORM_RDPKRU=1631, 
  XED_IFORM_RDPMC=1632, 
  XED_IFORM_RDPRU=1633, 
  XED_IFORM_RDRAND_GPRv=1634, 
  XED_IFORM_RDSEED_GPRv=1635, 
  XED_IFORM_RDSSPD_GPR32u32=1636, 
  XED_IFORM_RDSSPQ_GPR64u64=1637, 
  XED_IFORM_RDTSC=1638, 
  XED_IFORM_RDTSCP=1639, 
  XED_IFORM_REPE_CMPSB=1640, 
  XED_IFORM_REPE_CMPSD=1641, 
  XED_IFORM_REPE_CMPSQ=1642, 
  XED_IFORM_REPE_CMPSW=1643, 
  XED_IFORM_REPE_SCASB=1644, 
  XED_IFORM_REPE_SCASD=1645, 
  XED_IFORM_REPE_SCASQ=1646, 
  XED_IFORM_REPE_SCASW=1647, 
  XED_IFORM_REPNE_CMPSB=1648, 
  XED_IFORM_REPNE_CMPSD=1649, 
  XED_IFORM_REPNE_CMPSQ=1650, 
  XED_IFORM_REPNE_CMPSW=1651, 
  XED_IFORM_REPNE_SCASB=1652, 
  XED_IFORM_REPNE_SCASD=1653, 
  XED_IFORM_REPNE_SCASQ=1654, 
  XED_IFORM_REPNE_SCASW=1655, 
  XED_IFORM_REP_INSB=1656, 
  XED_IFORM_REP_INSD=1657, 
  XED_IFORM_REP_INSW=1658, 
  XED_IFORM_REP_LODSB=1659, 
  XED_IFORM_REP_LODSD=1660, 
  XED_IFORM_REP_LODSQ=1661, 
  XED_IFORM_REP_LODSW=1662, 
  XED_IFORM_REP_MONTMUL=1663, 
  XED_IFORM_REP_MOVSB=1664, 
  XED_IFORM_REP_MOVSD=1665, 
  XED_IFORM_REP_MOVSQ=1666, 
  XED_IFORM_REP_MOVSW=1667, 
  XED_IFORM_REP_OUTSB=1668, 
  XED_IFORM_REP_OUTSD=1669, 
  XED_IFORM_REP_OUTSW=1670, 
  XED_IFORM_REP_STOSB=1671, 
  XED_IFORM_REP_STOSD=1672, 
  XED_IFORM_REP_STOSQ=1673, 
  XED_IFORM_REP_STOSW=1674, 
  XED_IFORM_REP_XCRYPTCBC=1675, 
  XED_IFORM_REP_XCRYPTCFB=1676, 
  XED_IFORM_REP_XCRYPTCTR=1677, 
  XED_IFORM_REP_XCRYPTECB=1678, 
  XED_IFORM_REP_XCRYPTOFB=1679, 
  XED_IFORM_REP_XSHA1=1680, 
  XED_IFORM_REP_XSHA256=1681, 
  XED_IFORM_REP_XSTORE=1682, 
  XED_IFORM_RET_FAR=1683, 
  XED_IFORM_RET_FAR_IMMw=1684, 
  XED_IFORM_RET_NEAR=1685, 
  XED_IFORM_RET_NEAR_IMMw=1686, 
  XED_IFORM_RMPADJUST_RAX_RCX_RDX=1687, 
  XED_IFORM_RMPUPDATE_RAX_RCX=1688, 
  XED_IFORM_ROL_GPR8_CL=1689, 
  XED_IFORM_ROL_GPR8_IMMb=1690, 
  XED_IFORM_ROL_GPR8_ONE=1691, 
  XED_IFORM_ROL_GPRv_CL=1692, 
  XED_IFORM_ROL_GPRv_IMMb=1693, 
  XED_IFORM_ROL_GPRv_ONE=1694, 
  XED_IFORM_ROL_MEMb_CL=1695, 
  XED_IFORM_ROL_MEMb_IMMb=1696, 
  XED_IFORM_ROL_MEMb_ONE=1697, 
  XED_IFORM_ROL_MEMv_CL=1698, 
  XED_IFORM_ROL_MEMv_IMMb=1699, 
  XED_IFORM_ROL_MEMv_ONE=1700, 
  XED_IFORM_ROR_GPR8_CL=1701, 
  XED_IFORM_ROR_GPR8_IMMb=1702, 
  XED_IFORM_ROR_GPR8_ONE=1703, 
  XED_IFORM_ROR_GPRv_CL=1704, 
  XED_IFORM_ROR_GPRv_IMMb=1705, 
  XED_IFORM_ROR_GPRv_ONE=1706, 
  XED_IFORM_ROR_MEMb_CL=1707, 
  XED_IFORM_ROR_MEMb_IMMb=1708, 
  XED_IFORM_ROR_MEMb_ONE=1709, 
  XED_IFORM_ROR_MEMv_CL=1710, 
  XED_IFORM_ROR_MEMv_IMMb=1711, 
  XED_IFORM_ROR_MEMv_ONE=1712, 
  XED_IFORM_RORX_VGPR32d_MEMd_IMMb=1713, 
  XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb=1714, 
  XED_IFORM_RORX_VGPR64q_MEMq_IMMb=1715, 
  XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb=1716, 
  XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb=1717, 
  XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb=1718, 
  XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb=1719, 
  XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb=1720, 
  XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb=1721, 
  XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb=1722, 
  XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb=1723, 
  XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb=1724, 
  XED_IFORM_RSM=1725, 
  XED_IFORM_RSQRTPS_XMMps_MEMps=1726, 
  XED_IFORM_RSQRTPS_XMMps_XMMps=1727, 
  XED_IFORM_RSQRTSS_XMMss_MEMss=1728, 
  XED_IFORM_RSQRTSS_XMMss_XMMss=1729, 
  XED_IFORM_RSTORSSP_MEMu64=1730, 
  XED_IFORM_SAHF=1731, 
  XED_IFORM_SALC=1732, 
  XED_IFORM_SAR_GPR8_CL=1733, 
  XED_IFORM_SAR_GPR8_IMMb=1734, 
  XED_IFORM_SAR_GPR8_ONE=1735, 
  XED_IFORM_SAR_GPRv_CL=1736, 
  XED_IFORM_SAR_GPRv_IMMb=1737, 
  XED_IFORM_SAR_GPRv_ONE=1738, 
  XED_IFORM_SAR_MEMb_CL=1739, 
  XED_IFORM_SAR_MEMb_IMMb=1740, 
  XED_IFORM_SAR_MEMb_ONE=1741, 
  XED_IFORM_SAR_MEMv_CL=1742, 
  XED_IFORM_SAR_MEMv_IMMb=1743, 
  XED_IFORM_SAR_MEMv_ONE=1744, 
  XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d=1745, 
  XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d=1746, 
  XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q=1747, 
  XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q=1748, 
  XED_IFORM_SAVEPREVSSP=1749, 
  XED_IFORM_SBB_AL_IMMb=1750, 
  XED_IFORM_SBB_GPR8_GPR8_18=1751, 
  XED_IFORM_SBB_GPR8_GPR8_1A=1752, 
  XED_IFORM_SBB_GPR8_IMMb_80r3=1753, 
  XED_IFORM_SBB_GPR8_IMMb_82r3=1754, 
  XED_IFORM_SBB_GPR8_MEMb=1755, 
  XED_IFORM_SBB_GPRv_GPRv_19=1756, 
  XED_IFORM_SBB_GPRv_GPRv_1B=1757, 
  XED_IFORM_SBB_GPRv_IMMb=1758, 
  XED_IFORM_SBB_GPRv_IMMz=1759, 
  XED_IFORM_SBB_GPRv_MEMv=1760, 
  XED_IFORM_SBB_MEMb_GPR8=1761, 
  XED_IFORM_SBB_MEMb_IMMb_80r3=1762, 
  XED_IFORM_SBB_MEMb_IMMb_82r3=1763, 
  XED_IFORM_SBB_MEMv_GPRv=1764, 
  XED_IFORM_SBB_MEMv_IMMb=1765, 
  XED_IFORM_SBB_MEMv_IMMz=1766, 
  XED_IFORM_SBB_OrAX_IMMz=1767, 
  XED_IFORM_SBB_LOCK_MEMb_GPR8=1768, 
  XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3=1769, 
  XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3=1770, 
  XED_IFORM_SBB_LOCK_MEMv_GPRv=1771, 
  XED_IFORM_SBB_LOCK_MEMv_IMMb=1772, 
  XED_IFORM_SBB_LOCK_MEMv_IMMz=1773, 
  XED_IFORM_SCASB=1774, 
  XED_IFORM_SCASD=1775, 
  XED_IFORM_SCASQ=1776, 
  XED_IFORM_SCASW=1777, 
  XED_IFORM_SEAMCALL=1778, 
  XED_IFORM_SEAMOPS=1779, 
  XED_IFORM_SEAMRET=1780, 
  XED_IFORM_SENDUIPI_GPR32u32=1781, 
  XED_IFORM_SERIALIZE=1782, 
  XED_IFORM_SETB_GPR8=1783, 
  XED_IFORM_SETB_MEMb=1784, 
  XED_IFORM_SETBE_GPR8=1785, 
  XED_IFORM_SETBE_MEMb=1786, 
  XED_IFORM_SETL_GPR8=1787, 
  XED_IFORM_SETL_MEMb=1788, 
  XED_IFORM_SETLE_GPR8=1789, 
  XED_IFORM_SETLE_MEMb=1790, 
  XED_IFORM_SETNB_GPR8=1791, 
  XED_IFORM_SETNB_MEMb=1792, 
  XED_IFORM_SETNBE_GPR8=1793, 
  XED_IFORM_SETNBE_MEMb=1794, 
  XED_IFORM_SETNL_GPR8=1795, 
  XED_IFORM_SETNL_MEMb=1796, 
  XED_IFORM_SETNLE_GPR8=1797, 
  XED_IFORM_SETNLE_MEMb=1798, 
  XED_IFORM_SETNO_GPR8=1799, 
  XED_IFORM_SETNO_MEMb=1800, 
  XED_IFORM_SETNP_GPR8=1801, 
  XED_IFORM_SETNP_MEMb=1802, 
  XED_IFORM_SETNS_GPR8=1803, 
  XED_IFORM_SETNS_MEMb=1804, 
  XED_IFORM_SETNZ_GPR8=1805, 
  XED_IFORM_SETNZ_MEMb=1806, 
  XED_IFORM_SETO_GPR8=1807, 
  XED_IFORM_SETO_MEMb=1808, 
  XED_IFORM_SETP_GPR8=1809, 
  XED_IFORM_SETP_MEMb=1810, 
  XED_IFORM_SETS_GPR8=1811, 
  XED_IFORM_SETS_MEMb=1812, 
  XED_IFORM_SETSSBSY=1813, 
  XED_IFORM_SETZ_GPR8=1814, 
  XED_IFORM_SETZ_MEMb=1815, 
  XED_IFORM_SFENCE=1816, 
  XED_IFORM_SGDT_MEMs=1817, 
  XED_IFORM_SGDT_MEMs64=1818, 
  XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA=1819, 
  XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA=1820, 
  XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA=1821, 
  XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA=1822, 
  XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA=1823, 
  XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA=1824, 
  XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA=1825, 
  XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA=1826, 
  XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA=1827, 
  XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA=1828, 
  XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA=1829, 
  XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA=1830, 
  XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA=1831, 
  XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA=1832, 
  XED_IFORM_SHL_GPR8_CL_D2r4=1833, 
  XED_IFORM_SHL_GPR8_CL_D2r6=1834, 
  XED_IFORM_SHL_GPR8_IMMb_C0r4=1835, 
  XED_IFORM_SHL_GPR8_IMMb_C0r6=1836, 
  XED_IFORM_SHL_GPR8_ONE_D0r4=1837, 
  XED_IFORM_SHL_GPR8_ONE_D0r6=1838, 
  XED_IFORM_SHL_GPRv_CL_D3r4=1839, 
  XED_IFORM_SHL_GPRv_CL_D3r6=1840, 
  XED_IFORM_SHL_GPRv_IMMb_C1r4=1841, 
  XED_IFORM_SHL_GPRv_IMMb_C1r6=1842, 
  XED_IFORM_SHL_GPRv_ONE_D1r4=1843, 
  XED_IFORM_SHL_GPRv_ONE_D1r6=1844, 
  XED_IFORM_SHL_MEMb_CL_D2r4=1845, 
  XED_IFORM_SHL_MEMb_CL_D2r6=1846, 
  XED_IFORM_SHL_MEMb_IMMb_C0r4=1847, 
  XED_IFORM_SHL_MEMb_IMMb_C0r6=1848, 
  XED_IFORM_SHL_MEMb_ONE_D0r4=1849, 
  XED_IFORM_SHL_MEMb_ONE_D0r6=1850, 
  XED_IFORM_SHL_MEMv_CL_D3r4=1851, 
  XED_IFORM_SHL_MEMv_CL_D3r6=1852, 
  XED_IFORM_SHL_MEMv_IMMb_C1r4=1853, 
  XED_IFORM_SHL_MEMv_IMMb_C1r6=1854, 
  XED_IFORM_SHL_MEMv_ONE_D1r4=1855, 
  XED_IFORM_SHL_MEMv_ONE_D1r6=1856, 
  XED_IFORM_SHLD_GPRv_GPRv_CL=1857, 
  XED_IFORM_SHLD_GPRv_GPRv_IMMb=1858, 
  XED_IFORM_SHLD_MEMv_GPRv_CL=1859, 
  XED_IFORM_SHLD_MEMv_GPRv_IMMb=1860, 
  XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d=1861, 
  XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d=1862, 
  XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q=1863, 
  XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q=1864, 
  XED_IFORM_SHR_GPR8_CL=1865, 
  XED_IFORM_SHR_GPR8_IMMb=1866, 
  XED_IFORM_SHR_GPR8_ONE=1867, 
  XED_IFORM_SHR_GPRv_CL=1868, 
  XED_IFORM_SHR_GPRv_IMMb=1869, 
  XED_IFORM_SHR_GPRv_ONE=1870, 
  XED_IFORM_SHR_MEMb_CL=1871, 
  XED_IFORM_SHR_MEMb_IMMb=1872, 
  XED_IFORM_SHR_MEMb_ONE=1873, 
  XED_IFORM_SHR_MEMv_CL=1874, 
  XED_IFORM_SHR_MEMv_IMMb=1875, 
  XED_IFORM_SHR_MEMv_ONE=1876, 
  XED_IFORM_SHRD_GPRv_GPRv_CL=1877, 
  XED_IFORM_SHRD_GPRv_GPRv_IMMb=1878, 
  XED_IFORM_SHRD_MEMv_GPRv_CL=1879, 
  XED_IFORM_SHRD_MEMv_GPRv_IMMb=1880, 
  XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d=1881, 
  XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d=1882, 
  XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q=1883, 
  XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q=1884, 
  XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb=1885, 
  XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb=1886, 
  XED_IFORM_SHUFPS_XMMps_MEMps_IMMb=1887, 
  XED_IFORM_SHUFPS_XMMps_XMMps_IMMb=1888, 
  XED_IFORM_SIDT_MEMs=1889, 
  XED_IFORM_SIDT_MEMs64=1890, 
  XED_IFORM_SKINIT_EAX=1891, 
  XED_IFORM_SLDT_GPRv=1892, 
  XED_IFORM_SLDT_MEMw=1893, 
  XED_IFORM_SLWPCB_VGPRyy=1894, 
  XED_IFORM_SMSW_GPRv=1895, 
  XED_IFORM_SMSW_MEMw=1896, 
  XED_IFORM_SQRTPD_XMMpd_MEMpd=1897, 
  XED_IFORM_SQRTPD_XMMpd_XMMpd=1898, 
  XED_IFORM_SQRTPS_XMMps_MEMps=1899, 
  XED_IFORM_SQRTPS_XMMps_XMMps=1900, 
  XED_IFORM_SQRTSD_XMMsd_MEMsd=1901, 
  XED_IFORM_SQRTSD_XMMsd_XMMsd=1902, 
  XED_IFORM_SQRTSS_XMMss_MEMss=1903, 
  XED_IFORM_SQRTSS_XMMss_XMMss=1904, 
  XED_IFORM_STAC=1905, 
  XED_IFORM_STC=1906, 
  XED_IFORM_STD=1907, 
  XED_IFORM_STGI=1908, 
  XED_IFORM_STI=1909, 
  XED_IFORM_STMXCSR_MEMd=1910, 
  XED_IFORM_STOSB=1911, 
  XED_IFORM_STOSD=1912, 
  XED_IFORM_STOSQ=1913, 
  XED_IFORM_STOSW=1914, 
  XED_IFORM_STR_GPRv=1915, 
  XED_IFORM_STR_MEMw=1916, 
  XED_IFORM_STTILECFG_MEM=1917, 
  XED_IFORM_STUI=1918, 
  XED_IFORM_SUB_AL_IMMb=1919, 
  XED_IFORM_SUB_GPR8_GPR8_28=1920, 
  XED_IFORM_SUB_GPR8_GPR8_2A=1921, 
  XED_IFORM_SUB_GPR8_IMMb_80r5=1922, 
  XED_IFORM_SUB_GPR8_IMMb_82r5=1923, 
  XED_IFORM_SUB_GPR8_MEMb=1924, 
  XED_IFORM_SUB_GPRv_GPRv_29=1925, 
  XED_IFORM_SUB_GPRv_GPRv_2B=1926, 
  XED_IFORM_SUB_GPRv_IMMb=1927, 
  XED_IFORM_SUB_GPRv_IMMz=1928, 
  XED_IFORM_SUB_GPRv_MEMv=1929, 
  XED_IFORM_SUB_MEMb_GPR8=1930, 
  XED_IFORM_SUB_MEMb_IMMb_80r5=1931, 
  XED_IFORM_SUB_MEMb_IMMb_82r5=1932, 
  XED_IFORM_SUB_MEMv_GPRv=1933, 
  XED_IFORM_SUB_MEMv_IMMb=1934, 
  XED_IFORM_SUB_MEMv_IMMz=1935, 
  XED_IFORM_SUB_OrAX_IMMz=1936, 
  XED_IFORM_SUBPD_XMMpd_MEMpd=1937, 
  XED_IFORM_SUBPD_XMMpd_XMMpd=1938, 
  XED_IFORM_SUBPS_XMMps_MEMps=1939, 
  XED_IFORM_SUBPS_XMMps_XMMps=1940, 
  XED_IFORM_SUBSD_XMMsd_MEMsd=1941, 
  XED_IFORM_SUBSD_XMMsd_XMMsd=1942, 
  XED_IFORM_SUBSS_XMMss_MEMss=1943, 
  XED_IFORM_SUBSS_XMMss_XMMss=1944, 
  XED_IFORM_SUB_LOCK_MEMb_GPR8=1945, 
  XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5=1946, 
  XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5=1947, 
  XED_IFORM_SUB_LOCK_MEMv_GPRv=1948, 
  XED_IFORM_SUB_LOCK_MEMv_IMMb=1949, 
  XED_IFORM_SUB_LOCK_MEMv_IMMz=1950, 
  XED_IFORM_SWAPGS=1951, 
  XED_IFORM_SYSCALL=1952, 
  XED_IFORM_SYSCALL_AMD=1953, 
  XED_IFORM_SYSENTER=1954, 
  XED_IFORM_SYSEXIT=1955, 
  XED_IFORM_SYSRET=1956, 
  XED_IFORM_SYSRET64=1957, 
  XED_IFORM_SYSRET_AMD=1958, 
  XED_IFORM_T1MSKC_VGPR32d_MEMd=1959, 
  XED_IFORM_T1MSKC_VGPR32d_VGPR32d=1960, 
  XED_IFORM_T1MSKC_VGPRyy_MEMy=1961, 
  XED_IFORM_T1MSKC_VGPRyy_VGPRyy=1962, 
  XED_IFORM_TDCALL=1963, 
  XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32=1964, 
  XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32=1965, 
  XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32=1966, 
  XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32=1967, 
  XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32=1968, 
  XED_IFORM_TEST_AL_IMMb=1969, 
  XED_IFORM_TEST_GPR8_GPR8=1970, 
  XED_IFORM_TEST_GPR8_IMMb_F6r0=1971, 
  XED_IFORM_TEST_GPR8_IMMb_F6r1=1972, 
  XED_IFORM_TEST_GPRv_GPRv=1973, 
  XED_IFORM_TEST_GPRv_IMMz_F7r0=1974, 
  XED_IFORM_TEST_GPRv_IMMz_F7r1=1975, 
  XED_IFORM_TEST_MEMb_GPR8=1976, 
  XED_IFORM_TEST_MEMb_IMMb_F6r0=1977, 
  XED_IFORM_TEST_MEMb_IMMb_F6r1=1978, 
  XED_IFORM_TEST_MEMv_GPRv=1979, 
  XED_IFORM_TEST_MEMv_IMMz_F7r0=1980, 
  XED_IFORM_TEST_MEMv_IMMz_F7r1=1981, 
  XED_IFORM_TEST_OrAX_IMMz=1982, 
  XED_IFORM_TESTUI=1983, 
  XED_IFORM_TILELOADD_TMMu32_MEMu32=1984, 
  XED_IFORM_TILELOADDT1_TMMu32_MEMu32=1985, 
  XED_IFORM_TILERELEASE=1986, 
  XED_IFORM_TILESTORED_MEMu32_TMMu32=1987, 
  XED_IFORM_TILEZERO_TMMu32=1988, 
  XED_IFORM_TLBSYNC=1989, 
  XED_IFORM_TPAUSE_GPR32u32=1990, 
  XED_IFORM_TZCNT_GPRv_GPRv=1991, 
  XED_IFORM_TZCNT_GPRv_MEMv=1992, 
  XED_IFORM_TZMSK_VGPR32d_MEMd=1993, 
  XED_IFORM_TZMSK_VGPR32d_VGPR32d=1994, 
  XED_IFORM_TZMSK_VGPRyy_MEMy=1995, 
  XED_IFORM_TZMSK_VGPRyy_VGPRyy=1996, 
  XED_IFORM_UCOMISD_XMMsd_MEMsd=1997, 
  XED_IFORM_UCOMISD_XMMsd_XMMsd=1998, 
  XED_IFORM_UCOMISS_XMMss_MEMss=1999, 
  XED_IFORM_UCOMISS_XMMss_XMMss=2000, 
  XED_IFORM_UD0=2001, 
  XED_IFORM_UD0_GPR32_GPR32=2002, 
  XED_IFORM_UD0_GPR32_MEMd=2003, 
  XED_IFORM_UD1_GPR32_GPR32=2004, 
  XED_IFORM_UD1_GPR32_MEMd=2005, 
  XED_IFORM_UD2=2006, 
  XED_IFORM_UIRET=2007, 
  XED_IFORM_UMONITOR_GPRa=2008, 
  XED_IFORM_UMWAIT_GPR32=2009, 
  XED_IFORM_UNPCKHPD_XMMpd_MEMdq=2010, 
  XED_IFORM_UNPCKHPD_XMMpd_XMMq=2011, 
  XED_IFORM_UNPCKHPS_XMMps_MEMdq=2012, 
  XED_IFORM_UNPCKHPS_XMMps_XMMdq=2013, 
  XED_IFORM_UNPCKLPD_XMMpd_MEMdq=2014, 
  XED_IFORM_UNPCKLPD_XMMpd_XMMq=2015, 
  XED_IFORM_UNPCKLPS_XMMps_MEMdq=2016, 
  XED_IFORM_UNPCKLPS_XMMps_XMMq=2017, 
  XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2018, 
  XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2019, 
  XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2020, 
  XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2021, 
  XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq=2022, 
  XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq=2023, 
  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2024, 
  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2025, 
  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2026, 
  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2027, 
  XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq=2028, 
  XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq=2029, 
  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2030, 
  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2031, 
  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2032, 
  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2033, 
  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2034, 
  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2035, 
  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2036, 
  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2037, 
  XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq=2038, 
  XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq=2039, 
  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2040, 
  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2041, 
  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2042, 
  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2043, 
  XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq=2044, 
  XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq=2045, 
  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2046, 
  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2047, 
  XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq=2048, 
  XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq=2049, 
  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2050, 
  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2051, 
  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2052, 
  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2053, 
  XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd=2054, 
  XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd=2055, 
  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2056, 
  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2057, 
  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq=2058, 
  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq=2059, 
  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq=2060, 
  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq=2061, 
  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq=2062, 
  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq=2063, 
  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq=2064, 
  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq=2065, 
  XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq=2066, 
  XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq=2067, 
  XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512=2068, 
  XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512=2069, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128=2070, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512=2071, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128=2072, 
  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512=2073, 
  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512=2074, 
  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512=2075, 
  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq=2076, 
  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq=2077, 
  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512=2078, 
  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512=2079, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128=2080, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512=2081, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128=2082, 
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512=2083, 
  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2084, 
  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2085, 
  XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq=2086, 
  XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq=2087, 
  XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512=2088, 
  XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512=2089, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128=2090, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512=2091, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128=2092, 
  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512=2093, 
  XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512=2094, 
  XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512=2095, 
  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq=2096, 
  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq=2097, 
  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512=2098, 
  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512=2099, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128=2100, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512=2101, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128=2102, 
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512=2103, 
  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2104, 
  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2105, 
  XED_IFORM_VAESIMC_XMMdq_MEMdq=2106, 
  XED_IFORM_VAESIMC_XMMdq_XMMdq=2107, 
  XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb=2108, 
  XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb=2109, 
  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=2110, 
  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=2111, 
  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=2112, 
  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=2113, 
  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=2114, 
  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=2115, 
  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=2116, 
  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=2117, 
  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=2118, 
  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=2119, 
  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=2120, 
  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=2121, 
  XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq=2122, 
  XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq=2123, 
  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2124, 
  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2125, 
  XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq=2126, 
  XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq=2127, 
  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2128, 
  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2129, 
  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2130, 
  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2131, 
  XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq=2132, 
  XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq=2133, 
  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2134, 
  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2135, 
  XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq=2136, 
  XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq=2137, 
  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2138, 
  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2139, 
  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2140, 
  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2141, 
  XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq=2142, 
  XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq=2143, 
  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2144, 
  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2145, 
  XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq=2146, 
  XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq=2147, 
  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2148, 
  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2149, 
  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2150, 
  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2151, 
  XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq=2152, 
  XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq=2153, 
  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2154, 
  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2155, 
  XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq=2156, 
  XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq=2157, 
  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2158, 
  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2159, 
  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2160, 
  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2161, 
  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2162, 
  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2163, 
  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2164, 
  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2165, 
  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2166, 
  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2167, 
  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2168, 
  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2169, 
  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2170, 
  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2171, 
  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2172, 
  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2173, 
  XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb=2174, 
  XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb=2175, 
  XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb=2176, 
  XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb=2177, 
  XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb=2178, 
  XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb=2179, 
  XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb=2180, 
  XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb=2181, 
  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq=2182, 
  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq=2183, 
  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq=2184, 
  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq=2185, 
  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq=2186, 
  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq=2187, 
  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq=2188, 
  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq=2189, 
  XED_IFORM_VBROADCASTF128_YMMqq_MEMdq=2190, 
  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512=2191, 
  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512=2192, 
  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512=2193, 
  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512=2194, 
  XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512=2195, 
  XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512=2196, 
  XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512=2197, 
  XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512=2198, 
  XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512=2199, 
  XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512=2200, 
  XED_IFORM_VBROADCASTI128_YMMqq_MEMdq=2201, 
  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512=2202, 
  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512=2203, 
  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512=2204, 
  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512=2205, 
  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512=2206, 
  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512=2207, 
  XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512=2208, 
  XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512=2209, 
  XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512=2210, 
  XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512=2211, 
  XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512=2212, 
  XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512=2213, 
  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512=2214, 
  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512=2215, 
  XED_IFORM_VBROADCASTSD_YMMqq_MEMq=2216, 
  XED_IFORM_VBROADCASTSD_YMMqq_XMMdq=2217, 
  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512=2218, 
  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512=2219, 
  XED_IFORM_VBROADCASTSS_XMMdq_MEMd=2220, 
  XED_IFORM_VBROADCASTSS_XMMdq_XMMdq=2221, 
  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512=2222, 
  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512=2223, 
  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512=2224, 
  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512=2225, 
  XED_IFORM_VBROADCASTSS_YMMqq_MEMd=2226, 
  XED_IFORM_VBROADCASTSS_YMMqq_XMMdq=2227, 
  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512=2228, 
  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512=2229, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2230, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2231, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2232, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2233, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2234, 
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2235, 
  XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb=2236, 
  XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb=2237, 
  XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb=2238, 
  XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb=2239, 
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=2240, 
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=2241, 
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512=2242, 
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512=2243, 
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512=2244, 
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512=2245, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2246, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2247, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2248, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2249, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2250, 
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2251, 
  XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb=2252, 
  XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb=2253, 
  XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb=2254, 
  XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb=2255, 
  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2256, 
  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2257, 
  XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb=2258, 
  XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb=2259, 
  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=2260, 
  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=2261, 
  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2262, 
  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2263, 
  XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb=2264, 
  XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb=2265, 
  XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512=2266, 
  XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512=2267, 
  XED_IFORM_VCOMISD_XMMq_MEMq=2268, 
  XED_IFORM_VCOMISD_XMMq_XMMq=2269, 
  XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512=2270, 
  XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512=2271, 
  XED_IFORM_VCOMISS_XMMd_MEMd=2272, 
  XED_IFORM_VCOMISS_XMMd_XMMd=2273, 
  XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512=2274, 
  XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512=2275, 
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512=2276, 
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512=2277, 
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512=2278, 
  XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512=2279, 
  XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512=2280, 
  XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2281, 
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512=2282, 
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512=2283, 
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512=2284, 
  XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512=2285, 
  XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512=2286, 
  XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2287, 
  XED_IFORM_VCVTDQ2PD_XMMdq_MEMq=2288, 
  XED_IFORM_VCVTDQ2PD_XMMdq_XMMq=2289, 
  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512=2290, 
  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512=2291, 
  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512=2292, 
  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512=2293, 
  XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq=2294, 
  XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq=2295, 
  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512=2296, 
  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512=2297, 
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128=2298, 
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256=2299, 
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512=2300, 
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512=2301, 
  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512=2302, 
  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512=2303, 
  XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq=2304, 
  XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq=2305, 
  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512=2306, 
  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512=2307, 
  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512=2308, 
  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512=2309, 
  XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq=2310, 
  XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq=2311, 
  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512=2312, 
  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512=2313, 
  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128=2314, 
  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512=2315, 
  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256=2316, 
  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512=2317, 
  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512=2318, 
  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512=2319, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128=2320, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256=2321, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512=2322, 
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512=2323, 
  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512=2324, 
  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512=2325, 
  XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq=2326, 
  XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq=2327, 
  XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq=2328, 
  XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq=2329, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2330, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2331, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2332, 
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2333, 
  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2334, 
  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2335, 
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128=2336, 
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256=2337, 
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512=2338, 
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512=2339, 
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512=2340, 
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512=2341, 
  XED_IFORM_VCVTPD2PS_XMMdq_MEMdq=2342, 
  XED_IFORM_VCVTPD2PS_XMMdq_MEMqq=2343, 
  XED_IFORM_VCVTPD2PS_XMMdq_XMMdq=2344, 
  XED_IFORM_VCVTPD2PS_XMMdq_YMMqq=2345, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128=2346, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256=2347, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128=2348, 
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256=2349, 
  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512=2350, 
  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512=2351, 
  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2352, 
  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2353, 
  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2354, 
  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2355, 
  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2356, 
  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2357, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2358, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2359, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2360, 
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2361, 
  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2362, 
  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2363, 
  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2364, 
  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2365, 
  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2366, 
  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2367, 
  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2368, 
  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2369, 
  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512=2370, 
  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512=2371, 
  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512=2372, 
  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512=2373, 
  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512=2374, 
  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512=2375, 
  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512=2376, 
  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512=2377, 
  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512=2378, 
  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512=2379, 
  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512=2380, 
  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512=2381, 
  XED_IFORM_VCVTPH2PS_XMMdq_MEMq=2382, 
  XED_IFORM_VCVTPH2PS_XMMdq_XMMq=2383, 
  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512=2384, 
  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512=2385, 
  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512=2386, 
  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512=2387, 
  XED_IFORM_VCVTPH2PS_YMMqq_MEMdq=2388, 
  XED_IFORM_VCVTPH2PS_YMMqq_XMMdq=2389, 
  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512=2390, 
  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512=2391, 
  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512=2392, 
  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512=2393, 
  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512=2394, 
  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512=2395, 
  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512=2396, 
  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512=2397, 
  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512=2398, 
  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512=2399, 
  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512=2400, 
  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512=2401, 
  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512=2402, 
  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512=2403, 
  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512=2404, 
  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512=2405, 
  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512=2406, 
  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512=2407, 
  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512=2408, 
  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512=2409, 
  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512=2410, 
  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512=2411, 
  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512=2412, 
  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512=2413, 
  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512=2414, 
  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512=2415, 
  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512=2416, 
  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512=2417, 
  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512=2418, 
  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512=2419, 
  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512=2420, 
  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512=2421, 
  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512=2422, 
  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512=2423, 
  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512=2424, 
  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512=2425, 
  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512=2426, 
  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512=2427, 
  XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq=2428, 
  XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq=2429, 
  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2430, 
  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2431, 
  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2432, 
  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2433, 
  XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq=2434, 
  XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq=2435, 
  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2436, 
  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2437, 
  XED_IFORM_VCVTPS2PD_XMMdq_MEMq=2438, 
  XED_IFORM_VCVTPS2PD_XMMdq_XMMq=2439, 
  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512=2440, 
  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512=2441, 
  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512=2442, 
  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512=2443, 
  XED_IFORM_VCVTPS2PD_YMMqq_MEMdq=2444, 
  XED_IFORM_VCVTPS2PD_YMMqq_XMMdq=2445, 
  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512=2446, 
  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512=2447, 
  XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb=2448, 
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512=2449, 
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512=2450, 
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512=2451, 
  XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb=2452, 
  XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb=2453, 
  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512=2454, 
  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512=2455, 
  XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb=2456, 
  XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512=2457, 
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128=2458, 
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256=2459, 
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512=2460, 
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512=2461, 
  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512=2462, 
  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512=2463, 
  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2464, 
  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2465, 
  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2466, 
  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2467, 
  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2468, 
  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2469, 
  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2470, 
  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2471, 
  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2472, 
  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2473, 
  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2474, 
  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2475, 
  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2476, 
  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2477, 
  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2478, 
  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2479, 
  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2480, 
  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2481, 
  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512=2482, 
  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512=2483, 
  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512=2484, 
  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512=2485, 
  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512=2486, 
  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512=2487, 
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128=2488, 
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256=2489, 
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512=2490, 
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512=2491, 
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512=2492, 
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512=2493, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2494, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2495, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2496, 
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2497, 
  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2498, 
  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2499, 
  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512=2500, 
  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512=2501, 
  XED_IFORM_VCVTSD2SI_GPR32d_MEMq=2502, 
  XED_IFORM_VCVTSD2SI_GPR32d_XMMq=2503, 
  XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512=2504, 
  XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512=2505, 
  XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512=2506, 
  XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512=2507, 
  XED_IFORM_VCVTSD2SI_GPR64q_MEMq=2508, 
  XED_IFORM_VCVTSD2SI_GPR64q_XMMq=2509, 
  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq=2510, 
  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq=2511, 
  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512=2512, 
  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512=2513, 
  XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512=2514, 
  XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512=2515, 
  XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512=2516, 
  XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512=2517, 
  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512=2518, 
  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512=2519, 
  XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512=2520, 
  XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512=2521, 
  XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512=2522, 
  XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512=2523, 
  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512=2524, 
  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512=2525, 
  XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512=2526, 
  XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512=2527, 
  XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512=2528, 
  XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512=2529, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d=2530, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q=2531, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd=2532, 
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq=2533, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512=2534, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512=2535, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512=2536, 
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512=2537, 
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512=2538, 
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512=2539, 
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512=2540, 
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512=2541, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d=2542, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q=2543, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd=2544, 
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq=2545, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512=2546, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512=2547, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512=2548, 
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512=2549, 
  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd=2550, 
  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd=2551, 
  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512=2552, 
  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512=2553, 
  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512=2554, 
  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512=2555, 
  XED_IFORM_VCVTSS2SI_GPR32d_MEMd=2556, 
  XED_IFORM_VCVTSS2SI_GPR32d_XMMd=2557, 
  XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512=2558, 
  XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512=2559, 
  XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512=2560, 
  XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512=2561, 
  XED_IFORM_VCVTSS2SI_GPR64q_MEMd=2562, 
  XED_IFORM_VCVTSS2SI_GPR64q_XMMd=2563, 
  XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512=2564, 
  XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512=2565, 
  XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512=2566, 
  XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512=2567, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq=2568, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq=2569, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq=2570, 
  XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq=2571, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2572, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2573, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2574, 
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2575, 
  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2576, 
  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2577, 
  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2578, 
  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2579, 
  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2580, 
  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2581, 
  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2582, 
  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2583, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2584, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2585, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2586, 
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2587, 
  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2588, 
  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2589, 
  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2590, 
  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2591, 
  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2592, 
  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2593, 
  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2594, 
  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2595, 
  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512=2596, 
  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512=2597, 
  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512=2598, 
  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512=2599, 
  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512=2600, 
  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512=2601, 
  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512=2602, 
  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512=2603, 
  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512=2604, 
  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512=2605, 
  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512=2606, 
  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512=2607, 
  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512=2608, 
  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512=2609, 
  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512=2610, 
  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512=2611, 
  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512=2612, 
  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512=2613, 
  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512=2614, 
  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512=2615, 
  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512=2616, 
  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512=2617, 
  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512=2618, 
  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512=2619, 
  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512=2620, 
  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512=2621, 
  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512=2622, 
  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512=2623, 
  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512=2624, 
  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512=2625, 
  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512=2626, 
  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512=2627, 
  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512=2628, 
  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512=2629, 
  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512=2630, 
  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512=2631, 
  XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq=2632, 
  XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq=2633, 
  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2634, 
  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2635, 
  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2636, 
  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2637, 
  XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq=2638, 
  XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq=2639, 
  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2640, 
  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2641, 
  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2642, 
  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2643, 
  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2644, 
  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2645, 
  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2646, 
  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2647, 
  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2648, 
  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2649, 
  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2650, 
  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2651, 
  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2652, 
  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2653, 
  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2654, 
  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2655, 
  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2656, 
  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2657, 
  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2658, 
  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2659, 
  XED_IFORM_VCVTTSD2SI_GPR32d_MEMq=2660, 
  XED_IFORM_VCVTTSD2SI_GPR32d_XMMq=2661, 
  XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512=2662, 
  XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512=2663, 
  XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512=2664, 
  XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512=2665, 
  XED_IFORM_VCVTTSD2SI_GPR64q_MEMq=2666, 
  XED_IFORM_VCVTTSD2SI_GPR64q_XMMq=2667, 
  XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512=2668, 
  XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512=2669, 
  XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512=2670, 
  XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512=2671, 
  XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512=2672, 
  XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512=2673, 
  XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512=2674, 
  XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512=2675, 
  XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512=2676, 
  XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512=2677, 
  XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512=2678, 
  XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512=2679, 
  XED_IFORM_VCVTTSS2SI_GPR32d_MEMd=2680, 
  XED_IFORM_VCVTTSS2SI_GPR32d_XMMd=2681, 
  XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512=2682, 
  XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512=2683, 
  XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512=2684, 
  XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512=2685, 
  XED_IFORM_VCVTTSS2SI_GPR64q_MEMd=2686, 
  XED_IFORM_VCVTTSS2SI_GPR64q_XMMd=2687, 
  XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512=2688, 
  XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512=2689, 
  XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512=2690, 
  XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512=2691, 
  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512=2692, 
  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512=2693, 
  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512=2694, 
  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512=2695, 
  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512=2696, 
  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512=2697, 
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128=2698, 
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256=2699, 
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512=2700, 
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512=2701, 
  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512=2702, 
  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512=2703, 
  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512=2704, 
  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512=2705, 
  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512=2706, 
  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512=2707, 
  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512=2708, 
  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512=2709, 
  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512=2710, 
  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512=2711, 
  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512=2712, 
  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512=2713, 
  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512=2714, 
  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512=2715, 
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128=2716, 
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256=2717, 
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512=2718, 
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512=2719, 
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512=2720, 
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512=2721, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2722, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2723, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2724, 
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2725, 
  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2726, 
  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2727, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512=2728, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512=2729, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512=2730, 
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512=2731, 
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512=2732, 
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512=2733, 
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512=2734, 
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512=2735, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512=2736, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512=2737, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512=2738, 
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512=2739, 
  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512=2740, 
  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512=2741, 
  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512=2742, 
  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512=2743, 
  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512=2744, 
  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512=2745, 
  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512=2746, 
  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512=2747, 
  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512=2748, 
  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512=2749, 
  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512=2750, 
  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512=2751, 
  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=2752, 
  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=2753, 
  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=2754, 
  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=2755, 
  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=2756, 
  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=2757, 
  XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq=2758, 
  XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq=2759, 
  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2760, 
  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2761, 
  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2762, 
  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2763, 
  XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq=2764, 
  XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq=2765, 
  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2766, 
  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2767, 
  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2768, 
  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2769, 
  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2770, 
  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2771, 
  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2772, 
  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2773, 
  XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq=2774, 
  XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq=2775, 
  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2776, 
  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2777, 
  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2778, 
  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2779, 
  XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq=2780, 
  XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq=2781, 
  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2782, 
  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2783, 
  XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq=2784, 
  XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq=2785, 
  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2786, 
  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2787, 
  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2788, 
  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2789, 
  XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd=2790, 
  XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd=2791, 
  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2792, 
  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2793, 
  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512=2794, 
  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512=2795, 
  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512=2796, 
  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512=2797, 
  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512=2798, 
  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512=2799, 
  XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb=2800, 
  XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb=2801, 
  XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb=2802, 
  XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb=2803, 
  XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb=2804, 
  XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb=2805, 
  XED_IFORM_VERR_GPR16=2806, 
  XED_IFORM_VERR_MEMw=2807, 
  XED_IFORM_VERW_GPR16=2808, 
  XED_IFORM_VERW_MEMw=2809, 
  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=2810, 
  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=2811, 
  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=2812, 
  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=2813, 
  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512=2814, 
  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512=2815, 
  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512=2816, 
  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512=2817, 
  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512=2818, 
  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2819, 
  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512=2820, 
  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512=2821, 
  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512=2822, 
  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512=2823, 
  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512=2824, 
  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2825, 
  XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb=2826, 
  XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb=2827, 
  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512=2828, 
  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2829, 
  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512=2830, 
  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2831, 
  XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2832, 
  XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2833, 
  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512=2834, 
  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2835, 
  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512=2836, 
  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2837, 
  XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2838, 
  XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2839, 
  XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb=2840, 
  XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb=2841, 
  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512=2842, 
  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2843, 
  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512=2844, 
  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2845, 
  XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2846, 
  XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2847, 
  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512=2848, 
  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2849, 
  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512=2850, 
  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2851, 
  XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2852, 
  XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2853, 
  XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb=2854, 
  XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512=2855, 
  XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb=2856, 
  XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512=2857, 
  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2858, 
  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2859, 
  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=2860, 
  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=2861, 
  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=2862, 
  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=2863, 
  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2864, 
  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2865, 
  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2866, 
  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2867, 
  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=2868, 
  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=2869, 
  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=2870, 
  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=2871, 
  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2872, 
  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2873, 
  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2874, 
  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2875, 
  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2876, 
  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2877, 
  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2878, 
  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2879, 
  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2880, 
  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2881, 
  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2882, 
  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2883, 
  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2884, 
  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2885, 
  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2886, 
  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2887, 
  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2888, 
  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2889, 
  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq=2890, 
  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq=2891, 
  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2892, 
  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2893, 
  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2894, 
  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2895, 
  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq=2896, 
  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq=2897, 
  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2898, 
  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2899, 
  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2900, 
  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2901, 
  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2902, 
  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2903, 
  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2904, 
  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2905, 
  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq=2906, 
  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq=2907, 
  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2908, 
  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2909, 
  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2910, 
  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2911, 
  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq=2912, 
  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq=2913, 
  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2914, 
  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2915, 
  XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq=2916, 
  XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq=2917, 
  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2918, 
  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2919, 
  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2920, 
  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2921, 
  XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd=2922, 
  XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd=2923, 
  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2924, 
  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2925, 
  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq=2926, 
  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq=2927, 
  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2928, 
  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2929, 
  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2930, 
  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2931, 
  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq=2932, 
  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq=2933, 
  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2934, 
  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2935, 
  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2936, 
  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2937, 
  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2938, 
  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2939, 
  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2940, 
  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2941, 
  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq=2942, 
  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq=2943, 
  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2944, 
  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2945, 
  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2946, 
  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2947, 
  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq=2948, 
  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq=2949, 
  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2950, 
  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2951, 
  XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq=2952, 
  XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq=2953, 
  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2954, 
  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2955, 
  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2956, 
  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2957, 
  XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd=2958, 
  XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd=2959, 
  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2960, 
  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2961, 
  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq=2962, 
  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq=2963, 
  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2964, 
  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2965, 
  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2966, 
  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2967, 
  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq=2968, 
  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq=2969, 
  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2970, 
  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2971, 
  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2972, 
  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2973, 
  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2974, 
  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2975, 
  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2976, 
  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2977, 
  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq=2978, 
  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq=2979, 
  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2980, 
  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2981, 
  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2982, 
  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2983, 
  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq=2984, 
  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq=2985, 
  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2986, 
  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2987, 
  XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq=2988, 
  XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq=2989, 
  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2990, 
  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2991, 
  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2992, 
  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2993, 
  XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd=2994, 
  XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd=2995, 
  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2996, 
  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2997, 
  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2998, 
  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2999, 
  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=3000, 
  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=3001, 
  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=3002, 
  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=3003, 
  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3004, 
  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3005, 
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3006, 
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3007, 
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3008, 
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3009, 
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3010, 
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3011, 
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3012, 
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3013, 
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3014, 
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3015, 
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3016, 
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3017, 
  XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq=3018, 
  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq=3019, 
  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq=3020, 
  XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd=3021, 
  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd=3022, 
  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd=3023, 
  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq=3024, 
  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq=3025, 
  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3026, 
  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3027, 
  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3028, 
  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3029, 
  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq=3030, 
  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq=3031, 
  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3032, 
  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3033, 
  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3034, 
  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3035, 
  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3036, 
  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3037, 
  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3038, 
  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3039, 
  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq=3040, 
  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq=3041, 
  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3042, 
  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3043, 
  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3044, 
  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3045, 
  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq=3046, 
  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq=3047, 
  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3048, 
  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3049, 
  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq=3050, 
  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq=3051, 
  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3052, 
  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3053, 
  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3054, 
  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3055, 
  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq=3056, 
  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq=3057, 
  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3058, 
  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3059, 
  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3060, 
  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3061, 
  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3062, 
  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3063, 
  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3064, 
  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3065, 
  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq=3066, 
  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq=3067, 
  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3068, 
  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3069, 
  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3070, 
  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3071, 
  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq=3072, 
  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq=3073, 
  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3074, 
  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3075, 
  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq=3076, 
  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq=3077, 
  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3078, 
  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3079, 
  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3080, 
  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3081, 
  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq=3082, 
  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq=3083, 
  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3084, 
  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3085, 
  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3086, 
  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3087, 
  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3088, 
  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3089, 
  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3090, 
  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3091, 
  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq=3092, 
  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq=3093, 
  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3094, 
  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3095, 
  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3096, 
  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3097, 
  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq=3098, 
  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq=3099, 
  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3100, 
  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3101, 
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3102, 
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3103, 
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3104, 
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3105, 
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3106, 
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3107, 
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3108, 
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3109, 
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3110, 
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3111, 
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3112, 
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3113, 
  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq=3114, 
  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq=3115, 
  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3116, 
  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3117, 
  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3118, 
  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3119, 
  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq=3120, 
  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq=3121, 
  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3122, 
  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3123, 
  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3124, 
  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3125, 
  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3126, 
  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3127, 
  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3128, 
  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3129, 
  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq=3130, 
  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq=3131, 
  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3132, 
  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3133, 
  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3134, 
  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3135, 
  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq=3136, 
  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq=3137, 
  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3138, 
  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3139, 
  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq=3140, 
  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq=3141, 
  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3142, 
  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3143, 
  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3144, 
  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3145, 
  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd=3146, 
  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd=3147, 
  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3148, 
  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3149, 
  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq=3150, 
  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq=3151, 
  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3152, 
  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3153, 
  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3154, 
  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3155, 
  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq=3156, 
  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq=3157, 
  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3158, 
  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3159, 
  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3160, 
  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3161, 
  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3162, 
  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3163, 
  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3164, 
  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3165, 
  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq=3166, 
  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq=3167, 
  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3168, 
  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3169, 
  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3170, 
  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3171, 
  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq=3172, 
  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq=3173, 
  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3174, 
  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3175, 
  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq=3176, 
  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq=3177, 
  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3178, 
  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3179, 
  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3180, 
  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3181, 
  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd=3182, 
  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd=3183, 
  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3184, 
  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3185, 
  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq=3186, 
  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq=3187, 
  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3188, 
  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3189, 
  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3190, 
  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3191, 
  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq=3192, 
  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq=3193, 
  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3194, 
  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3195, 
  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3196, 
  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3197, 
  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3198, 
  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3199, 
  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3200, 
  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3201, 
  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq=3202, 
  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq=3203, 
  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3204, 
  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3205, 
  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3206, 
  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3207, 
  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq=3208, 
  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq=3209, 
  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3210, 
  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3211, 
  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq=3212, 
  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq=3213, 
  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3214, 
  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3215, 
  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3216, 
  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3217, 
  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd=3218, 
  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd=3219, 
  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3220, 
  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3221, 
  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq=3222, 
  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq=3223, 
  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3224, 
  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3225, 
  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3226, 
  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3227, 
  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq=3228, 
  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq=3229, 
  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3230, 
  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3231, 
  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3232, 
  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3233, 
  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3234, 
  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3235, 
  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3236, 
  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3237, 
  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq=3238, 
  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq=3239, 
  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3240, 
  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3241, 
  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3242, 
  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3243, 
  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq=3244, 
  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq=3245, 
  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3246, 
  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3247, 
  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq=3248, 
  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq=3249, 
  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3250, 
  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3251, 
  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3252, 
  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3253, 
  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq=3254, 
  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq=3255, 
  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3256, 
  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3257, 
  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3258, 
  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3259, 
  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3260, 
  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3261, 
  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3262, 
  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3263, 
  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq=3264, 
  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq=3265, 
  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3266, 
  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3267, 
  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3268, 
  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3269, 
  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq=3270, 
  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq=3271, 
  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3272, 
  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3273, 
  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq=3274, 
  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq=3275, 
  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3276, 
  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3277, 
  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3278, 
  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3279, 
  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq=3280, 
  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq=3281, 
  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3282, 
  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3283, 
  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3284, 
  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3285, 
  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3286, 
  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3287, 
  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3288, 
  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3289, 
  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq=3290, 
  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq=3291, 
  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3292, 
  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3293, 
  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3294, 
  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3295, 
  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq=3296, 
  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq=3297, 
  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3298, 
  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3299, 
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3300, 
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3301, 
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3302, 
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3303, 
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3304, 
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3305, 
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3306, 
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3307, 
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3308, 
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3309, 
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3310, 
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3311, 
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3312, 
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3313, 
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3314, 
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3315, 
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3316, 
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3317, 
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3318, 
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3319, 
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3320, 
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3321, 
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3322, 
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3323, 
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq=3324, 
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq=3325, 
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq=3326, 
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd=3327, 
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd=3328, 
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd=3329, 
  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3330, 
  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3331, 
  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=3332, 
  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=3333, 
  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=3334, 
  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=3335, 
  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3336, 
  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3337, 
  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq=3338, 
  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq=3339, 
  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3340, 
  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3341, 
  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3342, 
  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3343, 
  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq=3344, 
  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq=3345, 
  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3346, 
  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3347, 
  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3348, 
  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3349, 
  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3350, 
  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3351, 
  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3352, 
  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3353, 
  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq=3354, 
  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq=3355, 
  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3356, 
  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3357, 
  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3358, 
  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3359, 
  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq=3360, 
  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq=3361, 
  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3362, 
  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3363, 
  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq=3364, 
  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq=3365, 
  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3366, 
  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3367, 
  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3368, 
  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3369, 
  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd=3370, 
  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd=3371, 
  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3372, 
  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3373, 
  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq=3374, 
  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq=3375, 
  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3376, 
  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3377, 
  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3378, 
  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3379, 
  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq=3380, 
  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq=3381, 
  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3382, 
  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3383, 
  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3384, 
  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3385, 
  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3386, 
  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3387, 
  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3388, 
  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3389, 
  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq=3390, 
  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq=3391, 
  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3392, 
  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3393, 
  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3394, 
  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3395, 
  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq=3396, 
  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq=3397, 
  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3398, 
  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3399, 
  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq=3400, 
  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq=3401, 
  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3402, 
  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3403, 
  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3404, 
  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3405, 
  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd=3406, 
  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd=3407, 
  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3408, 
  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3409, 
  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq=3410, 
  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq=3411, 
  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3412, 
  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3413, 
  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3414, 
  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3415, 
  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq=3416, 
  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq=3417, 
  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3418, 
  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3419, 
  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3420, 
  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3421, 
  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3422, 
  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3423, 
  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3424, 
  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3425, 
  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq=3426, 
  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq=3427, 
  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3428, 
  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3429, 
  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3430, 
  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3431, 
  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq=3432, 
  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq=3433, 
  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3434, 
  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3435, 
  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq=3436, 
  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq=3437, 
  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3438, 
  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3439, 
  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3440, 
  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3441, 
  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd=3442, 
  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd=3443, 
  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3444, 
  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3445, 
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3446, 
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3447, 
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3448, 
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3449, 
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3450, 
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3451, 
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3452, 
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3453, 
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3454, 
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3455, 
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3456, 
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3457, 
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq=3458, 
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq=3459, 
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq=3460, 
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd=3461, 
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd=3462, 
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd=3463, 
  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq=3464, 
  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq=3465, 
  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3466, 
  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3467, 
  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3468, 
  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3469, 
  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq=3470, 
  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq=3471, 
  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3472, 
  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3473, 
  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3474, 
  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3475, 
  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3476, 
  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3477, 
  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3478, 
  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3479, 
  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq=3480, 
  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq=3481, 
  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3482, 
  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3483, 
  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3484, 
  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3485, 
  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq=3486, 
  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq=3487, 
  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3488, 
  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3489, 
  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq=3490, 
  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq=3491, 
  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3492, 
  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3493, 
  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3494, 
  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3495, 
  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd=3496, 
  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd=3497, 
  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3498, 
  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3499, 
  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq=3500, 
  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq=3501, 
  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3502, 
  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3503, 
  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3504, 
  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3505, 
  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq=3506, 
  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq=3507, 
  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3508, 
  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3509, 
  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3510, 
  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3511, 
  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3512, 
  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3513, 
  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3514, 
  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3515, 
  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq=3516, 
  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq=3517, 
  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3518, 
  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3519, 
  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3520, 
  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3521, 
  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq=3522, 
  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq=3523, 
  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3524, 
  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3525, 
  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq=3526, 
  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq=3527, 
  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3528, 
  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3529, 
  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3530, 
  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3531, 
  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd=3532, 
  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd=3533, 
  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3534, 
  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3535, 
  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq=3536, 
  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq=3537, 
  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3538, 
  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3539, 
  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3540, 
  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3541, 
  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq=3542, 
  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq=3543, 
  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3544, 
  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3545, 
  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3546, 
  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3547, 
  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3548, 
  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3549, 
  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3550, 
  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3551, 
  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq=3552, 
  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq=3553, 
  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3554, 
  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3555, 
  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3556, 
  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3557, 
  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq=3558, 
  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq=3559, 
  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3560, 
  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3561, 
  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq=3562, 
  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq=3563, 
  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3564, 
  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3565, 
  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3566, 
  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3567, 
  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd=3568, 
  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd=3569, 
  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3570, 
  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3571, 
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3572, 
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3573, 
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3574, 
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3575, 
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3576, 
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3577, 
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3578, 
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3579, 
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3580, 
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3581, 
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3582, 
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3583, 
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq=3584, 
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq=3585, 
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq=3586, 
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd=3587, 
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd=3588, 
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd=3589, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128=3590, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256=3591, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512=3592, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3593, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512=3594, 
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512=3595, 
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128=3596, 
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256=3597, 
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512=3598, 
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512=3599, 
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512=3600, 
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512=3601, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128=3602, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256=3603, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512=3604, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3605, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512=3606, 
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512=3607, 
  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512=3608, 
  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3609, 
  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512=3610, 
  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512=3611, 
  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512=3612, 
  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3613, 
  XED_IFORM_VFRCZPD_XMMdq_MEMdq=3614, 
  XED_IFORM_VFRCZPD_XMMdq_XMMdq=3615, 
  XED_IFORM_VFRCZPD_YMMqq_MEMqq=3616, 
  XED_IFORM_VFRCZPD_YMMqq_YMMqq=3617, 
  XED_IFORM_VFRCZPS_XMMdq_MEMdq=3618, 
  XED_IFORM_VFRCZPS_XMMdq_XMMdq=3619, 
  XED_IFORM_VFRCZPS_YMMqq_MEMqq=3620, 
  XED_IFORM_VFRCZPS_YMMqq_YMMqq=3621, 
  XED_IFORM_VFRCZSD_XMMdq_MEMq=3622, 
  XED_IFORM_VFRCZSD_XMMdq_XMMq=3623, 
  XED_IFORM_VFRCZSS_XMMdq_MEMd=3624, 
  XED_IFORM_VFRCZSS_XMMdq_XMMd=3625, 
  XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3626, 
  XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128=3627, 
  XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3628, 
  XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256=3629, 
  XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3630, 
  XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3631, 
  XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128=3632, 
  XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256=3633, 
  XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256=3634, 
  XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512=3635, 
  XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=3636, 
  XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=3637, 
  XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=3638, 
  XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=3639, 
  XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=3640, 
  XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=3641, 
  XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=3642, 
  XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=3643, 
  XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3644, 
  XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128=3645, 
  XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3646, 
  XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256=3647, 
  XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3648, 
  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3649, 
  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256=3650, 
  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128=3651, 
  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256=3652, 
  XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512=3653, 
  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512=3654, 
  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512=3655, 
  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512=3656, 
  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512=3657, 
  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512=3658, 
  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3659, 
  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512=3660, 
  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512=3661, 
  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512=3662, 
  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512=3663, 
  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512=3664, 
  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512=3665, 
  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512=3666, 
  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512=3667, 
  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512=3668, 
  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512=3669, 
  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512=3670, 
  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3671, 
  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3672, 
  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3673, 
  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3674, 
  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3675, 
  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3676, 
  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3677, 
  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=3678, 
  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=3679, 
  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=3680, 
  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=3681, 
  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=3682, 
  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=3683, 
  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=3684, 
  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=3685, 
  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=3686, 
  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=3687, 
  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=3688, 
  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=3689, 
  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=3690, 
  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=3691, 
  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=3692, 
  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=3693, 
  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=3694, 
  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=3695, 
  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=3696, 
  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=3697, 
  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=3698, 
  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=3699, 
  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=3700, 
  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=3701, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3702, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3703, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8=3704, 
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8=3705, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3706, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3707, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8=3708, 
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8=3709, 
  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3710, 
  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3711, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3712, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3713, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8=3714, 
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8=3715, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3716, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3717, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8=3718, 
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8=3719, 
  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3720, 
  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3721, 
  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3722, 
  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3723, 
  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8=3724, 
  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8=3725, 
  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3726, 
  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3727, 
  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8=3728, 
  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8=3729, 
  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3730, 
  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3731, 
  XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq=3732, 
  XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq=3733, 
  XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq=3734, 
  XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq=3735, 
  XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq=3736, 
  XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq=3737, 
  XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq=3738, 
  XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq=3739, 
  XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq=3740, 
  XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq=3741, 
  XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq=3742, 
  XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq=3743, 
  XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq=3744, 
  XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq=3745, 
  XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq=3746, 
  XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq=3747, 
  XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb=3748, 
  XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb=3749, 
  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=3750, 
  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512=3751, 
  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3752, 
  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512=3753, 
  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3754, 
  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512=3755, 
  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=3756, 
  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512=3757, 
  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3758, 
  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512=3759, 
  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3760, 
  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512=3761, 
  XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb=3762, 
  XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb=3763, 
  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=3764, 
  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512=3765, 
  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3766, 
  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512=3767, 
  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3768, 
  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512=3769, 
  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=3770, 
  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512=3771, 
  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3772, 
  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512=3773, 
  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3774, 
  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512=3775, 
  XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb=3776, 
  XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb=3777, 
  XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512=3778, 
  XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512=3779, 
  XED_IFORM_VLDDQU_XMMdq_MEMdq=3780, 
  XED_IFORM_VLDDQU_YMMqq_MEMqq=3781, 
  XED_IFORM_VLDMXCSR_MEMd=3782, 
  XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq=3783, 
  XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq=3784, 
  XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq=3785, 
  XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq=3786, 
  XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq=3787, 
  XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq=3788, 
  XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq=3789, 
  XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq=3790, 
  XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq=3791, 
  XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq=3792, 
  XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq=3793, 
  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3794, 
  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3795, 
  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3796, 
  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3797, 
  XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq=3798, 
  XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq=3799, 
  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3800, 
  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3801, 
  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3802, 
  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3803, 
  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3804, 
  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3805, 
  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3806, 
  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3807, 
  XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq=3808, 
  XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq=3809, 
  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3810, 
  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3811, 
  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3812, 
  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3813, 
  XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq=3814, 
  XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq=3815, 
  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3816, 
  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3817, 
  XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq=3818, 
  XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq=3819, 
  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3820, 
  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3821, 
  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3822, 
  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3823, 
  XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd=3824, 
  XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd=3825, 
  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3826, 
  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3827, 
  XED_IFORM_VMCALL=3828, 
  XED_IFORM_VMCLEAR_MEMq=3829, 
  XED_IFORM_VMFUNC=3830, 
  XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq=3831, 
  XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq=3832, 
  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3833, 
  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3834, 
  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3835, 
  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3836, 
  XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq=3837, 
  XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq=3838, 
  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3839, 
  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3840, 
  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3841, 
  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3842, 
  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3843, 
  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3844, 
  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3845, 
  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3846, 
  XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq=3847, 
  XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq=3848, 
  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3849, 
  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3850, 
  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3851, 
  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3852, 
  XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq=3853, 
  XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq=3854, 
  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3855, 
  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3856, 
  XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq=3857, 
  XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq=3858, 
  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3859, 
  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3860, 
  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3861, 
  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3862, 
  XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd=3863, 
  XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd=3864, 
  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3865, 
  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3866, 
  XED_IFORM_VMLAUNCH=3867, 
  XED_IFORM_VMLOAD_ArAX=3868, 
  XED_IFORM_VMMCALL=3869, 
  XED_IFORM_VMOVAPD_MEMdq_XMMdq=3870, 
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512=3871, 
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512=3872, 
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512=3873, 
  XED_IFORM_VMOVAPD_MEMqq_YMMqq=3874, 
  XED_IFORM_VMOVAPD_XMMdq_MEMdq=3875, 
  XED_IFORM_VMOVAPD_XMMdq_XMMdq_28=3876, 
  XED_IFORM_VMOVAPD_XMMdq_XMMdq_29=3877, 
  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512=3878, 
  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512=3879, 
  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512=3880, 
  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512=3881, 
  XED_IFORM_VMOVAPD_YMMqq_MEMqq=3882, 
  XED_IFORM_VMOVAPD_YMMqq_YMMqq_28=3883, 
  XED_IFORM_VMOVAPD_YMMqq_YMMqq_29=3884, 
  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512=3885, 
  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3886, 
  XED_IFORM_VMOVAPS_MEMdq_XMMdq=3887, 
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512=3888, 
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512=3889, 
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512=3890, 
  XED_IFORM_VMOVAPS_MEMqq_YMMqq=3891, 
  XED_IFORM_VMOVAPS_XMMdq_MEMdq=3892, 
  XED_IFORM_VMOVAPS_XMMdq_XMMdq_28=3893, 
  XED_IFORM_VMOVAPS_XMMdq_XMMdq_29=3894, 
  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512=3895, 
  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512=3896, 
  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512=3897, 
  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512=3898, 
  XED_IFORM_VMOVAPS_YMMqq_MEMqq=3899, 
  XED_IFORM_VMOVAPS_YMMqq_YMMqq_28=3900, 
  XED_IFORM_VMOVAPS_YMMqq_YMMqq_29=3901, 
  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512=3902, 
  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3903, 
  XED_IFORM_VMOVD_GPR32d_XMMd=3904, 
  XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512=3905, 
  XED_IFORM_VMOVD_MEMd_XMMd=3906, 
  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512=3907, 
  XED_IFORM_VMOVD_XMMdq_GPR32d=3908, 
  XED_IFORM_VMOVD_XMMdq_MEMd=3909, 
  XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512=3910, 
  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512=3911, 
  XED_IFORM_VMOVDDUP_XMMdq_MEMq=3912, 
  XED_IFORM_VMOVDDUP_XMMdq_XMMq=3913, 
  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512=3914, 
  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512=3915, 
  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512=3916, 
  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512=3917, 
  XED_IFORM_VMOVDDUP_YMMqq_MEMqq=3918, 
  XED_IFORM_VMOVDDUP_YMMqq_YMMqq=3919, 
  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512=3920, 
  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512=3921, 
  XED_IFORM_VMOVDQA_MEMdq_XMMdq=3922, 
  XED_IFORM_VMOVDQA_MEMqq_YMMqq=3923, 
  XED_IFORM_VMOVDQA_XMMdq_MEMdq=3924, 
  XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F=3925, 
  XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F=3926, 
  XED_IFORM_VMOVDQA_YMMqq_MEMqq=3927, 
  XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F=3928, 
  XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F=3929, 
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512=3930, 
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512=3931, 
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512=3932, 
  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512=3933, 
  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512=3934, 
  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512=3935, 
  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512=3936, 
  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512=3937, 
  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512=3938, 
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512=3939, 
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512=3940, 
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512=3941, 
  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512=3942, 
  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512=3943, 
  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512=3944, 
  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512=3945, 
  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512=3946, 
  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512=3947, 
  XED_IFORM_VMOVDQU_MEMdq_XMMdq=3948, 
  XED_IFORM_VMOVDQU_MEMqq_YMMqq=3949, 
  XED_IFORM_VMOVDQU_XMMdq_MEMdq=3950, 
  XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F=3951, 
  XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F=3952, 
  XED_IFORM_VMOVDQU_YMMqq_MEMqq=3953, 
  XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F=3954, 
  XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F=3955, 
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512=3956, 
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512=3957, 
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512=3958, 
  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512=3959, 
  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512=3960, 
  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512=3961, 
  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512=3962, 
  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512=3963, 
  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512=3964, 
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512=3965, 
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512=3966, 
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512=3967, 
  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512=3968, 
  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512=3969, 
  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512=3970, 
  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512=3971, 
  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512=3972, 
  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512=3973, 
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512=3974, 
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512=3975, 
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512=3976, 
  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512=3977, 
  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512=3978, 
  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512=3979, 
  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512=3980, 
  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512=3981, 
  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512=3982, 
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512=3983, 
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512=3984, 
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512=3985, 
  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512=3986, 
  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512=3987, 
  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512=3988, 
  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512=3989, 
  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512=3990, 
  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512=3991, 
  XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq=3992, 
  XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512=3993, 
  XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512=3994, 
  XED_IFORM_VMOVHPD_MEMq_XMMdq=3995, 
  XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq=3996, 
  XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512=3997, 
  XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512=3998, 
  XED_IFORM_VMOVHPS_MEMq_XMMdq=3999, 
  XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq=4000, 
  XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512=4001, 
  XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq=4002, 
  XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512=4003, 
  XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512=4004, 
  XED_IFORM_VMOVLPD_MEMq_XMMq=4005, 
  XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq=4006, 
  XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512=4007, 
  XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512=4008, 
  XED_IFORM_VMOVLPS_MEMq_XMMq=4009, 
  XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq=4010, 
  XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512=4011, 
  XED_IFORM_VMOVMSKPD_GPR32d_XMMdq=4012, 
  XED_IFORM_VMOVMSKPD_GPR32d_YMMqq=4013, 
  XED_IFORM_VMOVMSKPS_GPR32d_XMMdq=4014, 
  XED_IFORM_VMOVMSKPS_GPR32d_YMMqq=4015, 
  XED_IFORM_VMOVNTDQ_MEMdq_XMMdq=4016, 
  XED_IFORM_VMOVNTDQ_MEMqq_YMMqq=4017, 
  XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512=4018, 
  XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512=4019, 
  XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512=4020, 
  XED_IFORM_VMOVNTDQA_XMMdq_MEMdq=4021, 
  XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512=4022, 
  XED_IFORM_VMOVNTDQA_YMMqq_MEMqq=4023, 
  XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512=4024, 
  XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512=4025, 
  XED_IFORM_VMOVNTPD_MEMdq_XMMdq=4026, 
  XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512=4027, 
  XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512=4028, 
  XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512=4029, 
  XED_IFORM_VMOVNTPD_MEMqq_YMMqq=4030, 
  XED_IFORM_VMOVNTPS_MEMdq_XMMdq=4031, 
  XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512=4032, 
  XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512=4033, 
  XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512=4034, 
  XED_IFORM_VMOVNTPS_MEMqq_YMMqq=4035, 
  XED_IFORM_VMOVQ_GPR64q_XMMq=4036, 
  XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512=4037, 
  XED_IFORM_VMOVQ_MEMq_XMMq_7E=4038, 
  XED_IFORM_VMOVQ_MEMq_XMMq_D6=4039, 
  XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512=4040, 
  XED_IFORM_VMOVQ_XMMdq_GPR64q=4041, 
  XED_IFORM_VMOVQ_XMMdq_MEMq_6E=4042, 
  XED_IFORM_VMOVQ_XMMdq_MEMq_7E=4043, 
  XED_IFORM_VMOVQ_XMMdq_XMMq_7E=4044, 
  XED_IFORM_VMOVQ_XMMdq_XMMq_D6=4045, 
  XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512=4046, 
  XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512=4047, 
  XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512=4048, 
  XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512=4049, 
  XED_IFORM_VMOVSD_MEMq_XMMq=4050, 
  XED_IFORM_VMOVSD_XMMdq_MEMq=4051, 
  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10=4052, 
  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11=4053, 
  XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512=4054, 
  XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4055, 
  XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512=4056, 
  XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512=4057, 
  XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4058, 
  XED_IFORM_VMOVSHDUP_XMMdq_MEMdq=4059, 
  XED_IFORM_VMOVSHDUP_XMMdq_XMMdq=4060, 
  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512=4061, 
  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512=4062, 
  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512=4063, 
  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512=4064, 
  XED_IFORM_VMOVSHDUP_YMMqq_MEMqq=4065, 
  XED_IFORM_VMOVSHDUP_YMMqq_YMMqq=4066, 
  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512=4067, 
  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=4068, 
  XED_IFORM_VMOVSLDUP_XMMdq_MEMdq=4069, 
  XED_IFORM_VMOVSLDUP_XMMdq_XMMdq=4070, 
  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512=4071, 
  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512=4072, 
  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512=4073, 
  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512=4074, 
  XED_IFORM_VMOVSLDUP_YMMqq_MEMqq=4075, 
  XED_IFORM_VMOVSLDUP_YMMqq_YMMqq=4076, 
  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512=4077, 
  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=4078, 
  XED_IFORM_VMOVSS_MEMd_XMMd=4079, 
  XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512=4080, 
  XED_IFORM_VMOVSS_XMMdq_MEMd=4081, 
  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10=4082, 
  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11=4083, 
  XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512=4084, 
  XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4085, 
  XED_IFORM_VMOVUPD_MEMdq_XMMdq=4086, 
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512=4087, 
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512=4088, 
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512=4089, 
  XED_IFORM_VMOVUPD_MEMqq_YMMqq=4090, 
  XED_IFORM_VMOVUPD_XMMdq_MEMdq=4091, 
  XED_IFORM_VMOVUPD_XMMdq_XMMdq_10=4092, 
  XED_IFORM_VMOVUPD_XMMdq_XMMdq_11=4093, 
  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512=4094, 
  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512=4095, 
  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512=4096, 
  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512=4097, 
  XED_IFORM_VMOVUPD_YMMqq_MEMqq=4098, 
  XED_IFORM_VMOVUPD_YMMqq_YMMqq_10=4099, 
  XED_IFORM_VMOVUPD_YMMqq_YMMqq_11=4100, 
  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512=4101, 
  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512=4102, 
  XED_IFORM_VMOVUPS_MEMdq_XMMdq=4103, 
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512=4104, 
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512=4105, 
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512=4106, 
  XED_IFORM_VMOVUPS_MEMqq_YMMqq=4107, 
  XED_IFORM_VMOVUPS_XMMdq_MEMdq=4108, 
  XED_IFORM_VMOVUPS_XMMdq_XMMdq_10=4109, 
  XED_IFORM_VMOVUPS_XMMdq_XMMdq_11=4110, 
  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512=4111, 
  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512=4112, 
  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512=4113, 
  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512=4114, 
  XED_IFORM_VMOVUPS_YMMqq_MEMqq=4115, 
  XED_IFORM_VMOVUPS_YMMqq_YMMqq_10=4116, 
  XED_IFORM_VMOVUPS_YMMqq_YMMqq_11=4117, 
  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512=4118, 
  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512=4119, 
  XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512=4120, 
  XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512=4121, 
  XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512=4122, 
  XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512=4123, 
  XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb=4124, 
  XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb=4125, 
  XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb=4126, 
  XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb=4127, 
  XED_IFORM_VMPTRLD_MEMq=4128, 
  XED_IFORM_VMPTRST_MEMq=4129, 
  XED_IFORM_VMREAD_GPR32_GPR32=4130, 
  XED_IFORM_VMREAD_GPR64_GPR64=4131, 
  XED_IFORM_VMREAD_MEMd_GPR32=4132, 
  XED_IFORM_VMREAD_MEMq_GPR64=4133, 
  XED_IFORM_VMRESUME=4134, 
  XED_IFORM_VMRUN_ArAX=4135, 
  XED_IFORM_VMSAVE=4136, 
  XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq=4137, 
  XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq=4138, 
  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4139, 
  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4140, 
  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4141, 
  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4142, 
  XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq=4143, 
  XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq=4144, 
  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4145, 
  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4146, 
  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=4147, 
  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4148, 
  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=4149, 
  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=4150, 
  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=4151, 
  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=4152, 
  XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq=4153, 
  XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq=4154, 
  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4155, 
  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4156, 
  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4157, 
  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4158, 
  XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq=4159, 
  XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq=4160, 
  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4161, 
  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4162, 
  XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq=4163, 
  XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq=4164, 
  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4165, 
  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4166, 
  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=4167, 
  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4168, 
  XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd=4169, 
  XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd=4170, 
  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4171, 
  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4172, 
  XED_IFORM_VMWRITE_GPR32_GPR32=4173, 
  XED_IFORM_VMWRITE_GPR32_MEMd=4174, 
  XED_IFORM_VMWRITE_GPR64_GPR64=4175, 
  XED_IFORM_VMWRITE_GPR64_MEMq=4176, 
  XED_IFORM_VMXOFF=4177, 
  XED_IFORM_VMXON_MEMq=4178, 
  XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq=4179, 
  XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq=4180, 
  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4181, 
  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4182, 
  XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq=4183, 
  XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq=4184, 
  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4185, 
  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4186, 
  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4187, 
  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4188, 
  XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq=4189, 
  XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq=4190, 
  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4191, 
  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4192, 
  XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq=4193, 
  XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq=4194, 
  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4195, 
  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4196, 
  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4197, 
  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4198, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512=4199, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512=4200, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512=4201, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512=4202, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512=4203, 
  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512=4204, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512=4205, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512=4206, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512=4207, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512=4208, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512=4209, 
  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512=4210, 
  XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4211, 
  XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4212, 
  XED_IFORM_VPABSB_XMMdq_MEMdq=4213, 
  XED_IFORM_VPABSB_XMMdq_XMMdq=4214, 
  XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512=4215, 
  XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512=4216, 
  XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512=4217, 
  XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512=4218, 
  XED_IFORM_VPABSB_YMMqq_MEMqq=4219, 
  XED_IFORM_VPABSB_YMMqq_YMMqq=4220, 
  XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512=4221, 
  XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512=4222, 
  XED_IFORM_VPABSD_XMMdq_MEMdq=4223, 
  XED_IFORM_VPABSD_XMMdq_XMMdq=4224, 
  XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512=4225, 
  XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512=4226, 
  XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512=4227, 
  XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512=4228, 
  XED_IFORM_VPABSD_YMMqq_MEMqq=4229, 
  XED_IFORM_VPABSD_YMMqq_YMMqq=4230, 
  XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512=4231, 
  XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512=4232, 
  XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512=4233, 
  XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512=4234, 
  XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512=4235, 
  XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512=4236, 
  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512=4237, 
  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512=4238, 
  XED_IFORM_VPABSW_XMMdq_MEMdq=4239, 
  XED_IFORM_VPABSW_XMMdq_XMMdq=4240, 
  XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512=4241, 
  XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512=4242, 
  XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512=4243, 
  XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512=4244, 
  XED_IFORM_VPABSW_YMMqq_MEMqq=4245, 
  XED_IFORM_VPABSW_YMMqq_YMMqq=4246, 
  XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512=4247, 
  XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512=4248, 
  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq=4249, 
  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq=4250, 
  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512=4251, 
  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512=4252, 
  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512=4253, 
  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512=4254, 
  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq=4255, 
  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq=4256, 
  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512=4257, 
  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512=4258, 
  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq=4259, 
  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq=4260, 
  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512=4261, 
  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512=4262, 
  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512=4263, 
  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512=4264, 
  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq=4265, 
  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq=4266, 
  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512=4267, 
  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512=4268, 
  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq=4269, 
  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq=4270, 
  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512=4271, 
  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512=4272, 
  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq=4273, 
  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq=4274, 
  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512=4275, 
  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512=4276, 
  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512=4277, 
  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512=4278, 
  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq=4279, 
  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq=4280, 
  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512=4281, 
  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512=4282, 
  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq=4283, 
  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq=4284, 
  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512=4285, 
  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512=4286, 
  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512=4287, 
  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512=4288, 
  XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq=4289, 
  XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq=4290, 
  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4291, 
  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4292, 
  XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq=4293, 
  XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq=4294, 
  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4295, 
  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4296, 
  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4297, 
  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4298, 
  XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq=4299, 
  XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq=4300, 
  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4301, 
  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4302, 
  XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq=4303, 
  XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq=4304, 
  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4305, 
  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4306, 
  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4307, 
  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4308, 
  XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq=4309, 
  XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq=4310, 
  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4311, 
  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4312, 
  XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq=4313, 
  XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq=4314, 
  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4315, 
  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4316, 
  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4317, 
  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4318, 
  XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq=4319, 
  XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq=4320, 
  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=4321, 
  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=4322, 
  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=4323, 
  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=4324, 
  XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq=4325, 
  XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq=4326, 
  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=4327, 
  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=4328, 
  XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq=4329, 
  XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq=4330, 
  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=4331, 
  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=4332, 
  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=4333, 
  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=4334, 
  XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq=4335, 
  XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq=4336, 
  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=4337, 
  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=4338, 
  XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq=4339, 
  XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq=4340, 
  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4341, 
  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4342, 
  XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq=4343, 
  XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq=4344, 
  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4345, 
  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4346, 
  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4347, 
  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4348, 
  XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq=4349, 
  XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq=4350, 
  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4351, 
  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4352, 
  XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq=4353, 
  XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq=4354, 
  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4355, 
  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4356, 
  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4357, 
  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4358, 
  XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq=4359, 
  XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq=4360, 
  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4361, 
  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4362, 
  XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq=4363, 
  XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq=4364, 
  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4365, 
  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4366, 
  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4367, 
  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4368, 
  XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb=4369, 
  XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb=4370, 
  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=4371, 
  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=4372, 
  XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb=4373, 
  XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb=4374, 
  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=4375, 
  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=4376, 
  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=4377, 
  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=4378, 
  XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq=4379, 
  XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq=4380, 
  XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq=4381, 
  XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq=4382, 
  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4383, 
  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4384, 
  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4385, 
  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4386, 
  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4387, 
  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4388, 
  XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq=4389, 
  XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq=4390, 
  XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq=4391, 
  XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq=4392, 
  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4393, 
  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4394, 
  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4395, 
  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4396, 
  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4397, 
  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4398, 
  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4399, 
  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4400, 
  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4401, 
  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4402, 
  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4403, 
  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4404, 
  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4405, 
  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4406, 
  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4407, 
  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4408, 
  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4409, 
  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4410, 
  XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq=4411, 
  XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq=4412, 
  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4413, 
  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4414, 
  XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq=4415, 
  XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq=4416, 
  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4417, 
  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4418, 
  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4419, 
  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4420, 
  XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq=4421, 
  XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq=4422, 
  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4423, 
  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4424, 
  XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq=4425, 
  XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq=4426, 
  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4427, 
  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4428, 
  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4429, 
  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4430, 
  XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb=4431, 
  XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb=4432, 
  XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb=4433, 
  XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb=4434, 
  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4435, 
  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4436, 
  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4437, 
  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4438, 
  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4439, 
  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4440, 
  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4441, 
  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4442, 
  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4443, 
  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4444, 
  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4445, 
  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4446, 
  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4447, 
  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4448, 
  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4449, 
  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4450, 
  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4451, 
  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4452, 
  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4453, 
  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4454, 
  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4455, 
  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4456, 
  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4457, 
  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4458, 
  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq=4459, 
  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq=4460, 
  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq=4461, 
  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq=4462, 
  XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb=4463, 
  XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb=4464, 
  XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb=4465, 
  XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb=4466, 
  XED_IFORM_VPBROADCASTB_XMMdq_MEMb=4467, 
  XED_IFORM_VPBROADCASTB_XMMdq_XMMb=4468, 
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512=4469, 
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512=4470, 
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512=4471, 
  XED_IFORM_VPBROADCASTB_YMMqq_MEMb=4472, 
  XED_IFORM_VPBROADCASTB_YMMqq_XMMb=4473, 
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512=4474, 
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512=4475, 
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512=4476, 
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512=4477, 
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512=4478, 
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512=4479, 
  XED_IFORM_VPBROADCASTD_XMMdq_MEMd=4480, 
  XED_IFORM_VPBROADCASTD_XMMdq_XMMd=4481, 
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512=4482, 
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512=4483, 
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512=4484, 
  XED_IFORM_VPBROADCASTD_YMMqq_MEMd=4485, 
  XED_IFORM_VPBROADCASTD_YMMqq_XMMd=4486, 
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512=4487, 
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512=4488, 
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512=4489, 
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512=4490, 
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512=4491, 
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512=4492, 
  XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512=4493, 
  XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512=4494, 
  XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD=4495, 
  XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512=4496, 
  XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512=4497, 
  XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD=4498, 
  XED_IFORM_VPBROADCASTQ_XMMdq_MEMq=4499, 
  XED_IFORM_VPBROADCASTQ_XMMdq_XMMq=4500, 
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512=4501, 
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512=4502, 
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512=4503, 
  XED_IFORM_VPBROADCASTQ_YMMqq_MEMq=4504, 
  XED_IFORM_VPBROADCASTQ_YMMqq_XMMq=4505, 
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512=4506, 
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512=4507, 
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512=4508, 
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512=4509, 
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512=4510, 
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512=4511, 
  XED_IFORM_VPBROADCASTW_XMMdq_MEMw=4512, 
  XED_IFORM_VPBROADCASTW_XMMdq_XMMw=4513, 
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512=4514, 
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512=4515, 
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512=4516, 
  XED_IFORM_VPBROADCASTW_YMMqq_MEMw=4517, 
  XED_IFORM_VPBROADCASTW_YMMqq_XMMw=4518, 
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512=4519, 
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512=4520, 
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512=4521, 
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512=4522, 
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512=4523, 
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512=4524, 
  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb=4525, 
  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb=4526, 
  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512=4527, 
  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512=4528, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8=4529, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512=4530, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8=4531, 
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512=4532, 
  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512=4533, 
  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512=4534, 
  XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq=4535, 
  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq=4536, 
  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq=4537, 
  XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq=4538, 
  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq=4539, 
  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq=4540, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512=4541, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512=4542, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512=4543, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512=4544, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512=4545, 
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512=4546, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512=4547, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512=4548, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512=4549, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512=4550, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512=4551, 
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512=4552, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4553, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4554, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4555, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4556, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4557, 
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4558, 
  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq=4559, 
  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq=4560, 
  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq=4561, 
  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq=4562, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=4563, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=4564, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=4565, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=4566, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=4567, 
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=4568, 
  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq=4569, 
  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq=4570, 
  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq=4571, 
  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq=4572, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=4573, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=4574, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=4575, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=4576, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=4577, 
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=4578, 
  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq=4579, 
  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq=4580, 
  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq=4581, 
  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq=4582, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4583, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4584, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4585, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4586, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4587, 
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4588, 
  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq=4589, 
  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq=4590, 
  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq=4591, 
  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq=4592, 
  XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb=4593, 
  XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb=4594, 
  XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb=4595, 
  XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb=4596, 
  XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb=4597, 
  XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb=4598, 
  XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb=4599, 
  XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb=4600, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4601, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4602, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4603, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4604, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4605, 
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4606, 
  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq=4607, 
  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq=4608, 
  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq=4609, 
  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq=4610, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512=4611, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512=4612, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512=4613, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512=4614, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512=4615, 
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512=4616, 
  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq=4617, 
  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq=4618, 
  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq=4619, 
  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq=4620, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512=4621, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512=4622, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512=4623, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512=4624, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512=4625, 
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512=4626, 
  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq=4627, 
  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq=4628, 
  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq=4629, 
  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq=4630, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4631, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4632, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4633, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4634, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4635, 
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4636, 
  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq=4637, 
  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq=4638, 
  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq=4639, 
  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq=4640, 
  XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb=4641, 
  XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb=4642, 
  XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb=4643, 
  XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb=4644, 
  XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb=4645, 
  XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb=4646, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512=4647, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512=4648, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512=4649, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512=4650, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512=4651, 
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512=4652, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=4653, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=4654, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=4655, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=4656, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=4657, 
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=4658, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=4659, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=4660, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=4661, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=4662, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=4663, 
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=4664, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=4665, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=4666, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=4667, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=4668, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=4669, 
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=4670, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=4671, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=4672, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=4673, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=4674, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=4675, 
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=4676, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512=4677, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512=4678, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512=4679, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512=4680, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512=4681, 
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512=4682, 
  XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb=4683, 
  XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb=4684, 
  XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb=4685, 
  XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb=4686, 
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512=4687, 
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512=4688, 
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512=4689, 
  XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512=4690, 
  XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512=4691, 
  XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512=4692, 
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512=4693, 
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512=4694, 
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512=4695, 
  XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512=4696, 
  XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512=4697, 
  XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512=4698, 
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512=4699, 
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512=4700, 
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512=4701, 
  XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512=4702, 
  XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512=4703, 
  XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4704, 
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512=4705, 
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512=4706, 
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512=4707, 
  XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512=4708, 
  XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512=4709, 
  XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512=4710, 
  XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb=4711, 
  XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb=4712, 
  XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb=4713, 
  XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb=4714, 
  XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb=4715, 
  XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb=4716, 
  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb=4717, 
  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb=4718, 
  XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb=4719, 
  XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb=4720, 
  XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb=4721, 
  XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb=4722, 
  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512=4723, 
  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512=4724, 
  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512=4725, 
  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512=4726, 
  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=4727, 
  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=4728, 
  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512=4729, 
  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512=4730, 
  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512=4731, 
  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512=4732, 
  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=4733, 
  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=4734, 
  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4735, 
  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4736, 
  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32=4737, 
  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32=4738, 
  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4739, 
  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4740, 
  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32=4741, 
  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32=4742, 
  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4743, 
  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4744, 
  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4745, 
  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4746, 
  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32=4747, 
  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32=4748, 
  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4749, 
  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4750, 
  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32=4751, 
  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32=4752, 
  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4753, 
  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4754, 
  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4755, 
  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4756, 
  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32=4757, 
  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32=4758, 
  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4759, 
  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4760, 
  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32=4761, 
  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32=4762, 
  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4763, 
  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4764, 
  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4765, 
  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4766, 
  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32=4767, 
  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32=4768, 
  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4769, 
  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4770, 
  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32=4771, 
  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32=4772, 
  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4773, 
  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4774, 
  XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb=4775, 
  XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb=4776, 
  XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb=4777, 
  XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb=4778, 
  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4779, 
  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4780, 
  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4781, 
  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4782, 
  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4783, 
  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4784, 
  XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq=4785, 
  XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq=4786, 
  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4787, 
  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4788, 
  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4789, 
  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4790, 
  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4791, 
  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4792, 
  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4793, 
  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4794, 
  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4795, 
  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4796, 
  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4797, 
  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4798, 
  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4799, 
  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4800, 
  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4801, 
  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4802, 
  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4803, 
  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4804, 
  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4805, 
  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4806, 
  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4807, 
  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4808, 
  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4809, 
  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4810, 
  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4811, 
  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4812, 
  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4813, 
  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4814, 
  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4815, 
  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4816, 
  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4817, 
  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4818, 
  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4819, 
  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4820, 
  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4821, 
  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4822, 
  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4823, 
  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4824, 
  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4825, 
  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4826, 
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4827, 
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4828, 
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4829, 
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4830, 
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4831, 
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4832, 
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4833, 
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4834, 
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4835, 
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4836, 
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4837, 
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4838, 
  XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb=4839, 
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb=4840, 
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq=4841, 
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq=4842, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=4843, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=4844, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4845, 
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4846, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4847, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4848, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4849, 
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4850, 
  XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb=4851, 
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb=4852, 
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq=4853, 
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq=4854, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4855, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4856, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4857, 
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4858, 
  XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb=4859, 
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb=4860, 
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq=4861, 
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq=4862, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=4863, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=4864, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4865, 
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4866, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=4867, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=4868, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4869, 
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4870, 
  XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb=4871, 
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb=4872, 
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq=4873, 
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq=4874, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=4875, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=4876, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4877, 
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4878, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4879, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4880, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4881, 
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4882, 
  XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb=4883, 
  XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb=4884, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4885, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4886, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4887, 
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4888, 
  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4889, 
  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4890, 
  XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq=4891, 
  XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq=4892, 
  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4893, 
  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4894, 
  XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb=4895, 
  XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb=4896, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=4897, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=4898, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4899, 
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4900, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=4901, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=4902, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4903, 
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4904, 
  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4905, 
  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4906, 
  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4907, 
  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4908, 
  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4909, 
  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4910, 
  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4911, 
  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4912, 
  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4913, 
  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4914, 
  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4915, 
  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4916, 
  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4917, 
  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4918, 
  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4919, 
  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4920, 
  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4921, 
  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4922, 
  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4923, 
  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4924, 
  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4925, 
  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4926, 
  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4927, 
  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4928, 
  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4929, 
  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4930, 
  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4931, 
  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4932, 
  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4933, 
  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4934, 
  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4935, 
  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4936, 
  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4937, 
  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4938, 
  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4939, 
  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4940, 
  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4941, 
  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4942, 
  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4943, 
  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4944, 
  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4945, 
  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4946, 
  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512=4947, 
  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512=4948, 
  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512=4949, 
  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512=4950, 
  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512=4951, 
  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512=4952, 
  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512=4953, 
  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512=4954, 
  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512=4955, 
  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512=4956, 
  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512=4957, 
  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512=4958, 
  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512=4959, 
  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512=4960, 
  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512=4961, 
  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512=4962, 
  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512=4963, 
  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4964, 
  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512=4965, 
  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512=4966, 
  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512=4967, 
  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512=4968, 
  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512=4969, 
  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512=4970, 
  XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb=4971, 
  XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512=4972, 
  XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb=4973, 
  XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512=4974, 
  XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb=4975, 
  XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512=4976, 
  XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb=4977, 
  XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512=4978, 
  XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb=4979, 
  XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512=4980, 
  XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb=4981, 
  XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512=4982, 
  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15=4983, 
  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5=4984, 
  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512=4985, 
  XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512=4986, 
  XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb=4987, 
  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5=4988, 
  XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4989, 
  XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128=4990, 
  XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256=4991, 
  XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256=4992, 
  XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512=4993, 
  XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=4994, 
  XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128=4995, 
  XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=4996, 
  XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256=4997, 
  XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=4998, 
  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4999, 
  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256=5000, 
  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128=5001, 
  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256=5002, 
  XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512=5003, 
  XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=5004, 
  XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128=5005, 
  XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=5006, 
  XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256=5007, 
  XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=5008, 
  XED_IFORM_VPHADDBD_XMMdq_MEMdq=5009, 
  XED_IFORM_VPHADDBD_XMMdq_XMMdq=5010, 
  XED_IFORM_VPHADDBQ_XMMdq_MEMdq=5011, 
  XED_IFORM_VPHADDBQ_XMMdq_XMMdq=5012, 
  XED_IFORM_VPHADDBW_XMMdq_MEMdq=5013, 
  XED_IFORM_VPHADDBW_XMMdq_XMMdq=5014, 
  XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq=5015, 
  XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq=5016, 
  XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq=5017, 
  XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq=5018, 
  XED_IFORM_VPHADDDQ_XMMdq_MEMdq=5019, 
  XED_IFORM_VPHADDDQ_XMMdq_XMMdq=5020, 
  XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq=5021, 
  XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq=5022, 
  XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq=5023, 
  XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq=5024, 
  XED_IFORM_VPHADDUBD_XMMdq_MEMdq=5025, 
  XED_IFORM_VPHADDUBD_XMMdq_XMMdq=5026, 
  XED_IFORM_VPHADDUBQ_XMMdq_MEMdq=5027, 
  XED_IFORM_VPHADDUBQ_XMMdq_XMMdq=5028, 
  XED_IFORM_VPHADDUBW_XMMdq_MEMdq=5029, 
  XED_IFORM_VPHADDUBW_XMMdq_XMMdq=5030, 
  XED_IFORM_VPHADDUDQ_XMMdq_MEMdq=5031, 
  XED_IFORM_VPHADDUDQ_XMMdq_XMMdq=5032, 
  XED_IFORM_VPHADDUWD_XMMdq_MEMdq=5033, 
  XED_IFORM_VPHADDUWD_XMMdq_XMMdq=5034, 
  XED_IFORM_VPHADDUWQ_XMMdq_MEMdq=5035, 
  XED_IFORM_VPHADDUWQ_XMMdq_XMMdq=5036, 
  XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq=5037, 
  XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq=5038, 
  XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq=5039, 
  XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq=5040, 
  XED_IFORM_VPHADDWD_XMMdq_MEMdq=5041, 
  XED_IFORM_VPHADDWD_XMMdq_XMMdq=5042, 
  XED_IFORM_VPHADDWQ_XMMdq_MEMdq=5043, 
  XED_IFORM_VPHADDWQ_XMMdq_XMMdq=5044, 
  XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq=5045, 
  XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq=5046, 
  XED_IFORM_VPHSUBBW_XMMdq_MEMdq=5047, 
  XED_IFORM_VPHSUBBW_XMMdq_XMMdq=5048, 
  XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq=5049, 
  XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq=5050, 
  XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq=5051, 
  XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq=5052, 
  XED_IFORM_VPHSUBDQ_XMMdq_MEMdq=5053, 
  XED_IFORM_VPHSUBDQ_XMMdq_XMMdq=5054, 
  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq=5055, 
  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq=5056, 
  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq=5057, 
  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq=5058, 
  XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq=5059, 
  XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq=5060, 
  XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq=5061, 
  XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq=5062, 
  XED_IFORM_VPHSUBWD_XMMdq_MEMdq=5063, 
  XED_IFORM_VPHSUBWD_XMMdq_XMMdq=5064, 
  XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb=5065, 
  XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb=5066, 
  XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512=5067, 
  XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512=5068, 
  XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb=5069, 
  XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb=5070, 
  XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512=5071, 
  XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512=5072, 
  XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb=5073, 
  XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb=5074, 
  XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512=5075, 
  XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512=5076, 
  XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb=5077, 
  XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb=5078, 
  XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512=5079, 
  XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512=5080, 
  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512=5081, 
  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512=5082, 
  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512=5083, 
  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512=5084, 
  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=5085, 
  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=5086, 
  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=5087, 
  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=5088, 
  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=5089, 
  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=5090, 
  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=5091, 
  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=5092, 
  XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq=5093, 
  XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq=5094, 
  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq=5095, 
  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq=5096, 
  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq=5097, 
  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq=5098, 
  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq=5099, 
  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq=5100, 
  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq=5101, 
  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq=5102, 
  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq=5103, 
  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq=5104, 
  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq=5105, 
  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq=5106, 
  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq=5107, 
  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq=5108, 
  XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq=5109, 
  XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq=5110, 
  XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq=5111, 
  XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq=5112, 
  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq=5113, 
  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq=5114, 
  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq=5115, 
  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq=5116, 
  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5117, 
  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5118, 
  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5119, 
  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5120, 
  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5121, 
  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5122, 
  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5123, 
  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5124, 
  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5125, 
  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5126, 
  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5127, 
  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5128, 
  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq=5129, 
  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq=5130, 
  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5131, 
  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5132, 
  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5133, 
  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5134, 
  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq=5135, 
  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq=5136, 
  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5137, 
  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5138, 
  XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq=5139, 
  XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq=5140, 
  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512=5141, 
  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512=5142, 
  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512=5143, 
  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512=5144, 
  XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq=5145, 
  XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq=5146, 
  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512=5147, 
  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512=5148, 
  XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq=5149, 
  XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq=5150, 
  XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq=5151, 
  XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq=5152, 
  XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq=5153, 
  XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq=5154, 
  XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq=5155, 
  XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq=5156, 
  XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq=5157, 
  XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq=5158, 
  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=5159, 
  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=5160, 
  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=5161, 
  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=5162, 
  XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq=5163, 
  XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq=5164, 
  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=5165, 
  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=5166, 
  XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq=5167, 
  XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq=5168, 
  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=5169, 
  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=5170, 
  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=5171, 
  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=5172, 
  XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq=5173, 
  XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq=5174, 
  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=5175, 
  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=5176, 
  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=5177, 
  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=5178, 
  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=5179, 
  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=5180, 
  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=5181, 
  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=5182, 
  XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq=5183, 
  XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq=5184, 
  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5185, 
  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5186, 
  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5187, 
  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5188, 
  XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq=5189, 
  XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq=5190, 
  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5191, 
  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5192, 
  XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq=5193, 
  XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq=5194, 
  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5195, 
  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5196, 
  XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq=5197, 
  XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq=5198, 
  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5199, 
  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5200, 
  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5201, 
  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5202, 
  XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq=5203, 
  XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq=5204, 
  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5205, 
  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5206, 
  XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq=5207, 
  XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq=5208, 
  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5209, 
  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5210, 
  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5211, 
  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5212, 
  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5213, 
  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5214, 
  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5215, 
  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5216, 
  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5217, 
  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5218, 
  XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq=5219, 
  XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq=5220, 
  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5221, 
  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5222, 
  XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq=5223, 
  XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq=5224, 
  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5225, 
  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5226, 
  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5227, 
  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5228, 
  XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq=5229, 
  XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq=5230, 
  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=5231, 
  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=5232, 
  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=5233, 
  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=5234, 
  XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq=5235, 
  XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq=5236, 
  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=5237, 
  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=5238, 
  XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq=5239, 
  XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq=5240, 
  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=5241, 
  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=5242, 
  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=5243, 
  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=5244, 
  XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq=5245, 
  XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq=5246, 
  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=5247, 
  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=5248, 
  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=5249, 
  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=5250, 
  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=5251, 
  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=5252, 
  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=5253, 
  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=5254, 
  XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq=5255, 
  XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq=5256, 
  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5257, 
  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5258, 
  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5259, 
  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5260, 
  XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq=5261, 
  XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq=5262, 
  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5263, 
  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5264, 
  XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq=5265, 
  XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq=5266, 
  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5267, 
  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5268, 
  XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq=5269, 
  XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq=5270, 
  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5271, 
  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5272, 
  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5273, 
  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5274, 
  XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq=5275, 
  XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq=5276, 
  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5277, 
  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5278, 
  XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq=5279, 
  XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq=5280, 
  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5281, 
  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5282, 
  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5283, 
  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5284, 
  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5285, 
  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5286, 
  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5287, 
  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5288, 
  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5289, 
  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5290, 
  XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq=5291, 
  XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq=5292, 
  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5293, 
  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5294, 
  XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq=5295, 
  XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq=5296, 
  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5297, 
  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5298, 
  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5299, 
  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5300, 
  XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512=5301, 
  XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512=5302, 
  XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512=5303, 
  XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512=5304, 
  XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512=5305, 
  XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512=5306, 
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512=5307, 
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512=5308, 
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512=5309, 
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512=5310, 
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512=5311, 
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512=5312, 
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512=5313, 
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512=5314, 
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512=5315, 
  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512=5316, 
  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512=5317, 
  XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512=5318, 
  XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512=5319, 
  XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512=5320, 
  XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512=5321, 
  XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512=5322, 
  XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512=5323, 
  XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512=5324, 
  XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512=5325, 
  XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512=5326, 
  XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512=5327, 
  XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512=5328, 
  XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512=5329, 
  XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512=5330, 
  XED_IFORM_VPMOVMSKB_GPR32d_XMMdq=5331, 
  XED_IFORM_VPMOVMSKB_GPR32d_YMMqq=5332, 
  XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512=5333, 
  XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512=5334, 
  XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512=5335, 
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512=5336, 
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512=5337, 
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512=5338, 
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512=5339, 
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512=5340, 
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512=5341, 
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512=5342, 
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512=5343, 
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512=5344, 
  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512=5345, 
  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512=5346, 
  XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512=5347, 
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512=5348, 
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512=5349, 
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512=5350, 
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512=5351, 
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512=5352, 
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512=5353, 
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512=5354, 
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512=5355, 
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512=5356, 
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512=5357, 
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512=5358, 
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512=5359, 
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512=5360, 
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512=5361, 
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512=5362, 
  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512=5363, 
  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512=5364, 
  XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512=5365, 
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512=5366, 
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512=5367, 
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512=5368, 
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512=5369, 
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512=5370, 
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512=5371, 
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512=5372, 
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512=5373, 
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512=5374, 
  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512=5375, 
  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512=5376, 
  XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512=5377, 
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512=5378, 
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512=5379, 
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512=5380, 
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512=5381, 
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512=5382, 
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512=5383, 
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512=5384, 
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512=5385, 
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512=5386, 
  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512=5387, 
  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512=5388, 
  XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512=5389, 
  XED_IFORM_VPMOVSXBD_XMMdq_MEMd=5390, 
  XED_IFORM_VPMOVSXBD_XMMdq_XMMd=5391, 
  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512=5392, 
  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512=5393, 
  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512=5394, 
  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512=5395, 
  XED_IFORM_VPMOVSXBD_YMMqq_MEMq=5396, 
  XED_IFORM_VPMOVSXBD_YMMqq_XMMq=5397, 
  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512=5398, 
  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512=5399, 
  XED_IFORM_VPMOVSXBQ_XMMdq_MEMw=5400, 
  XED_IFORM_VPMOVSXBQ_XMMdq_XMMw=5401, 
  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512=5402, 
  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512=5403, 
  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512=5404, 
  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512=5405, 
  XED_IFORM_VPMOVSXBQ_YMMqq_MEMd=5406, 
  XED_IFORM_VPMOVSXBQ_YMMqq_XMMd=5407, 
  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=5408, 
  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=5409, 
  XED_IFORM_VPMOVSXBW_XMMdq_MEMq=5410, 
  XED_IFORM_VPMOVSXBW_XMMdq_XMMq=5411, 
  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512=5412, 
  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512=5413, 
  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512=5414, 
  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512=5415, 
  XED_IFORM_VPMOVSXBW_YMMqq_MEMdq=5416, 
  XED_IFORM_VPMOVSXBW_YMMqq_XMMdq=5417, 
  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512=5418, 
  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512=5419, 
  XED_IFORM_VPMOVSXDQ_XMMdq_MEMq=5420, 
  XED_IFORM_VPMOVSXDQ_XMMdq_XMMq=5421, 
  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512=5422, 
  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512=5423, 
  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512=5424, 
  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512=5425, 
  XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq=5426, 
  XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq=5427, 
  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=5428, 
  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=5429, 
  XED_IFORM_VPMOVSXWD_XMMdq_MEMq=5430, 
  XED_IFORM_VPMOVSXWD_XMMdq_XMMq=5431, 
  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512=5432, 
  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512=5433, 
  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512=5434, 
  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512=5435, 
  XED_IFORM_VPMOVSXWD_YMMqq_MEMdq=5436, 
  XED_IFORM_VPMOVSXWD_YMMqq_XMMdq=5437, 
  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512=5438, 
  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512=5439, 
  XED_IFORM_VPMOVSXWQ_XMMdq_MEMd=5440, 
  XED_IFORM_VPMOVSXWQ_XMMdq_XMMd=5441, 
  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512=5442, 
  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512=5443, 
  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512=5444, 
  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512=5445, 
  XED_IFORM_VPMOVSXWQ_YMMqq_MEMq=5446, 
  XED_IFORM_VPMOVSXWQ_YMMqq_XMMq=5447, 
  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=5448, 
  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=5449, 
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512=5450, 
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512=5451, 
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512=5452, 
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512=5453, 
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512=5454, 
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512=5455, 
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512=5456, 
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512=5457, 
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512=5458, 
  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512=5459, 
  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512=5460, 
  XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512=5461, 
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512=5462, 
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512=5463, 
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512=5464, 
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512=5465, 
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512=5466, 
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512=5467, 
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512=5468, 
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512=5469, 
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512=5470, 
  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512=5471, 
  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512=5472, 
  XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512=5473, 
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512=5474, 
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512=5475, 
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512=5476, 
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512=5477, 
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512=5478, 
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512=5479, 
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512=5480, 
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512=5481, 
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512=5482, 
  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512=5483, 
  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512=5484, 
  XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512=5485, 
  XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512=5486, 
  XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512=5487, 
  XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512=5488, 
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512=5489, 
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512=5490, 
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512=5491, 
  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512=5492, 
  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512=5493, 
  XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512=5494, 
  XED_IFORM_VPMOVZXBD_XMMdq_MEMd=5495, 
  XED_IFORM_VPMOVZXBD_XMMdq_XMMd=5496, 
  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512=5497, 
  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512=5498, 
  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512=5499, 
  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512=5500, 
  XED_IFORM_VPMOVZXBD_YMMqq_MEMq=5501, 
  XED_IFORM_VPMOVZXBD_YMMqq_XMMq=5502, 
  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512=5503, 
  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512=5504, 
  XED_IFORM_VPMOVZXBQ_XMMdq_MEMw=5505, 
  XED_IFORM_VPMOVZXBQ_XMMdq_XMMw=5506, 
  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512=5507, 
  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512=5508, 
  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512=5509, 
  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512=5510, 
  XED_IFORM_VPMOVZXBQ_YMMqq_MEMd=5511, 
  XED_IFORM_VPMOVZXBQ_YMMqq_XMMd=5512, 
  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=5513, 
  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=5514, 
  XED_IFORM_VPMOVZXBW_XMMdq_MEMq=5515, 
  XED_IFORM_VPMOVZXBW_XMMdq_XMMq=5516, 
  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512=5517, 
  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512=5518, 
  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512=5519, 
  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512=5520, 
  XED_IFORM_VPMOVZXBW_YMMqq_MEMdq=5521, 
  XED_IFORM_VPMOVZXBW_YMMqq_XMMdq=5522, 
  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512=5523, 
  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512=5524, 
  XED_IFORM_VPMOVZXDQ_XMMdq_MEMq=5525, 
  XED_IFORM_VPMOVZXDQ_XMMdq_XMMq=5526, 
  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512=5527, 
  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512=5528, 
  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512=5529, 
  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512=5530, 
  XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq=5531, 
  XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq=5532, 
  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=5533, 
  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=5534, 
  XED_IFORM_VPMOVZXWD_XMMdq_MEMq=5535, 
  XED_IFORM_VPMOVZXWD_XMMdq_XMMq=5536, 
  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512=5537, 
  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512=5538, 
  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512=5539, 
  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512=5540, 
  XED_IFORM_VPMOVZXWD_YMMqq_MEMdq=5541, 
  XED_IFORM_VPMOVZXWD_YMMqq_XMMdq=5542, 
  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512=5543, 
  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512=5544, 
  XED_IFORM_VPMOVZXWQ_XMMdq_MEMd=5545, 
  XED_IFORM_VPMOVZXWQ_XMMdq_XMMd=5546, 
  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512=5547, 
  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512=5548, 
  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512=5549, 
  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512=5550, 
  XED_IFORM_VPMOVZXWQ_YMMqq_MEMq=5551, 
  XED_IFORM_VPMOVZXWQ_YMMqq_XMMq=5552, 
  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=5553, 
  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=5554, 
  XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq=5555, 
  XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq=5556, 
  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512=5557, 
  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512=5558, 
  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512=5559, 
  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512=5560, 
  XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq=5561, 
  XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq=5562, 
  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512=5563, 
  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512=5564, 
  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq=5565, 
  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq=5566, 
  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5567, 
  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5568, 
  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5569, 
  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5570, 
  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq=5571, 
  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq=5572, 
  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5573, 
  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5574, 
  XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq=5575, 
  XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq=5576, 
  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5577, 
  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5578, 
  XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq=5579, 
  XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq=5580, 
  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5581, 
  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5582, 
  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5583, 
  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5584, 
  XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq=5585, 
  XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq=5586, 
  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5587, 
  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5588, 
  XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq=5589, 
  XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq=5590, 
  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5591, 
  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5592, 
  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5593, 
  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5594, 
  XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq=5595, 
  XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq=5596, 
  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5597, 
  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5598, 
  XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq=5599, 
  XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq=5600, 
  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5601, 
  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5602, 
  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5603, 
  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5604, 
  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5605, 
  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5606, 
  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5607, 
  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5608, 
  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5609, 
  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5610, 
  XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq=5611, 
  XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq=5612, 
  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5613, 
  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5614, 
  XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq=5615, 
  XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq=5616, 
  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5617, 
  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5618, 
  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5619, 
  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5620, 
  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512=5621, 
  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512=5622, 
  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512=5623, 
  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512=5624, 
  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512=5625, 
  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512=5626, 
  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq=5627, 
  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq=5628, 
  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512=5629, 
  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512=5630, 
  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq=5631, 
  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq=5632, 
  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512=5633, 
  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512=5634, 
  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512=5635, 
  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512=5636, 
  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512=5637, 
  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512=5638, 
  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512=5639, 
  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512=5640, 
  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512=5641, 
  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512=5642, 
  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512=5643, 
  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512=5644, 
  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512=5645, 
  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512=5646, 
  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512=5647, 
  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512=5648, 
  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=5649, 
  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=5650, 
  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=5651, 
  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=5652, 
  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512=5653, 
  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512=5654, 
  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512=5655, 
  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512=5656, 
  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512=5657, 
  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512=5658, 
  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512=5659, 
  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512=5660, 
  XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq=5661, 
  XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq=5662, 
  XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq=5663, 
  XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq=5664, 
  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5665, 
  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5666, 
  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5667, 
  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5668, 
  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5669, 
  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5670, 
  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5671, 
  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5672, 
  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5673, 
  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5674, 
  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5675, 
  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5676, 
  XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq=5677, 
  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq=5678, 
  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq=5679, 
  XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5680, 
  XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5681, 
  XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5682, 
  XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5683, 
  XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5684, 
  XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5685, 
  XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5686, 
  XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5687, 
  XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5688, 
  XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5689, 
  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5690, 
  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5691, 
  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5692, 
  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5693, 
  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5694, 
  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5695, 
  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5696, 
  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5697, 
  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5698, 
  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5699, 
  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5700, 
  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5701, 
  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5702, 
  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5703, 
  XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5704, 
  XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5705, 
  XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5706, 
  XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5707, 
  XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5708, 
  XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5709, 
  XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5710, 
  XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5711, 
  XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5712, 
  XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5713, 
  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5714, 
  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5715, 
  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5716, 
  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5717, 
  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5718, 
  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5719, 
  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5720, 
  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5721, 
  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5722, 
  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5723, 
  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5724, 
  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5725, 
  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5726, 
  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5727, 
  XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb=5728, 
  XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq=5729, 
  XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb=5730, 
  XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq=5731, 
  XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq=5732, 
  XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb=5733, 
  XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq=5734, 
  XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb=5735, 
  XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq=5736, 
  XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq=5737, 
  XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb=5738, 
  XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq=5739, 
  XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb=5740, 
  XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq=5741, 
  XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq=5742, 
  XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb=5743, 
  XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq=5744, 
  XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb=5745, 
  XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq=5746, 
  XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq=5747, 
  XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq=5748, 
  XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq=5749, 
  XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512=5750, 
  XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512=5751, 
  XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq=5752, 
  XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq=5753, 
  XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512=5754, 
  XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512=5755, 
  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512=5756, 
  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512=5757, 
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5758, 
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256=5759, 
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512=5760, 
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5761, 
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5762, 
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5763, 
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5764, 
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256=5765, 
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512=5766, 
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5767, 
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5768, 
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5769, 
  XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq=5770, 
  XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq=5771, 
  XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq=5772, 
  XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq=5773, 
  XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq=5774, 
  XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq=5775, 
  XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq=5776, 
  XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq=5777, 
  XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq=5778, 
  XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq=5779, 
  XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq=5780, 
  XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq=5781, 
  XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq=5782, 
  XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq=5783, 
  XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq=5784, 
  XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq=5785, 
  XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq=5786, 
  XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq=5787, 
  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5788, 
  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5789, 
  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5790, 
  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5791, 
  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5792, 
  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5793, 
  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5794, 
  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5795, 
  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5796, 
  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5797, 
  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5798, 
  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5799, 
  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5800, 
  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5801, 
  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5802, 
  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5803, 
  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5804, 
  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5805, 
  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5806, 
  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5807, 
  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5808, 
  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5809, 
  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5810, 
  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5811, 
  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5812, 
  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5813, 
  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5814, 
  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5815, 
  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5816, 
  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5817, 
  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5818, 
  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5819, 
  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5820, 
  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5821, 
  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5822, 
  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5823, 
  XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq=5824, 
  XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq=5825, 
  XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq=5826, 
  XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq=5827, 
  XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq=5828, 
  XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq=5829, 
  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5830, 
  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5831, 
  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5832, 
  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5833, 
  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5834, 
  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5835, 
  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5836, 
  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5837, 
  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5838, 
  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5839, 
  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5840, 
  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5841, 
  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5842, 
  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5843, 
  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5844, 
  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5845, 
  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5846, 
  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5847, 
  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5848, 
  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5849, 
  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5850, 
  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5851, 
  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5852, 
  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5853, 
  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5854, 
  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5855, 
  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5856, 
  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5857, 
  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5858, 
  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5859, 
  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5860, 
  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5861, 
  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5862, 
  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5863, 
  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5864, 
  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5865, 
  XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq=5866, 
  XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq=5867, 
  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5868, 
  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5869, 
  XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq=5870, 
  XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq=5871, 
  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5872, 
  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5873, 
  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5874, 
  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5875, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512=5876, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512=5877, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512=5878, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512=5879, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512=5880, 
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512=5881, 
  XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb=5882, 
  XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb=5883, 
  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5884, 
  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5885, 
  XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb=5886, 
  XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb=5887, 
  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5888, 
  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5889, 
  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5890, 
  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5891, 
  XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb=5892, 
  XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb=5893, 
  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5894, 
  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5895, 
  XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb=5896, 
  XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb=5897, 
  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5898, 
  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5899, 
  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5900, 
  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5901, 
  XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb=5902, 
  XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb=5903, 
  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5904, 
  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5905, 
  XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb=5906, 
  XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb=5907, 
  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5908, 
  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5909, 
  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5910, 
  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5911, 
  XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq=5912, 
  XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq=5913, 
  XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq=5914, 
  XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq=5915, 
  XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq=5916, 
  XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq=5917, 
  XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq=5918, 
  XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq=5919, 
  XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq=5920, 
  XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq=5921, 
  XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq=5922, 
  XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq=5923, 
  XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb=5924, 
  XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq=5925, 
  XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq=5926, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5927, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5928, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5929, 
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5930, 
  XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb=5931, 
  XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq=5932, 
  XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq=5933, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5934, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5935, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5936, 
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=5937, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5938, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5939, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5940, 
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=5941, 
  XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb=5942, 
  XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512=5943, 
  XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512=5944, 
  XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb=5945, 
  XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512=5946, 
  XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512=5947, 
  XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512=5948, 
  XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512=5949, 
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb=5950, 
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq=5951, 
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq=5952, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5953, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5954, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5955, 
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5956, 
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb=5957, 
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq=5958, 
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq=5959, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5960, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5961, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5962, 
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=5963, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5964, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5965, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5966, 
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=5967, 
  XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq=5968, 
  XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq=5969, 
  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5970, 
  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5971, 
  XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq=5972, 
  XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq=5973, 
  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5974, 
  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5975, 
  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5976, 
  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5977, 
  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq=5978, 
  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq=5979, 
  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5980, 
  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5981, 
  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq=5982, 
  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq=5983, 
  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5984, 
  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5985, 
  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5986, 
  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5987, 
  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5988, 
  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5989, 
  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5990, 
  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5991, 
  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5992, 
  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5993, 
  XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb=5994, 
  XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq=5995, 
  XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq=5996, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5997, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5998, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5999, 
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6000, 
  XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb=6001, 
  XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq=6002, 
  XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq=6003, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6004, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6005, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6006, 
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6007, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6008, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6009, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6010, 
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6011, 
  XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb=6012, 
  XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq=6013, 
  XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq=6014, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=6015, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=6016, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6017, 
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6018, 
  XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb=6019, 
  XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq=6020, 
  XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq=6021, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=6022, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=6023, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6024, 
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=6025, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=6026, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=6027, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6028, 
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=6029, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=6030, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=6031, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6032, 
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6033, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=6034, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=6035, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6036, 
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=6037, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=6038, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=6039, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6040, 
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=6041, 
  XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq=6042, 
  XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq=6043, 
  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6044, 
  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6045, 
  XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq=6046, 
  XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq=6047, 
  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6048, 
  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6049, 
  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6050, 
  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6051, 
  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6052, 
  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6053, 
  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6054, 
  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6055, 
  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6056, 
  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6057, 
  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6058, 
  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6059, 
  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6060, 
  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6061, 
  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6062, 
  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6063, 
  XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb=6064, 
  XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq=6065, 
  XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq=6066, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=6067, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=6068, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6069, 
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6070, 
  XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb=6071, 
  XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq=6072, 
  XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq=6073, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6074, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6075, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6076, 
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6077, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6078, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6079, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6080, 
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6081, 
  XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb=6082, 
  XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq=6083, 
  XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq=6084, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=6085, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=6086, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6087, 
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6088, 
  XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb=6089, 
  XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq=6090, 
  XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq=6091, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=6092, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=6093, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6094, 
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=6095, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=6096, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=6097, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6098, 
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=6099, 
  XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb=6100, 
  XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512=6101, 
  XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512=6102, 
  XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb=6103, 
  XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512=6104, 
  XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512=6105, 
  XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512=6106, 
  XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512=6107, 
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb=6108, 
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq=6109, 
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq=6110, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=6111, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=6112, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6113, 
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6114, 
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb=6115, 
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq=6116, 
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq=6117, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=6118, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=6119, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6120, 
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=6121, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=6122, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=6123, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6124, 
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=6125, 
  XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq=6126, 
  XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq=6127, 
  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6128, 
  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6129, 
  XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq=6130, 
  XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq=6131, 
  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6132, 
  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6133, 
  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6134, 
  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6135, 
  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq=6136, 
  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq=6137, 
  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6138, 
  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6139, 
  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq=6140, 
  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq=6141, 
  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6142, 
  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6143, 
  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6144, 
  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6145, 
  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6146, 
  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6147, 
  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6148, 
  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6149, 
  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6150, 
  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6151, 
  XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb=6152, 
  XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq=6153, 
  XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq=6154, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=6155, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=6156, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6157, 
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6158, 
  XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb=6159, 
  XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq=6160, 
  XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq=6161, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6162, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6163, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6164, 
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6165, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6166, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6167, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6168, 
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6169, 
  XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq=6170, 
  XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq=6171, 
  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6172, 
  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6173, 
  XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq=6174, 
  XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq=6175, 
  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6176, 
  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6177, 
  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6178, 
  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6179, 
  XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq=6180, 
  XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq=6181, 
  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6182, 
  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6183, 
  XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq=6184, 
  XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq=6185, 
  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6186, 
  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6187, 
  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6188, 
  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6189, 
  XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq=6190, 
  XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq=6191, 
  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6192, 
  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6193, 
  XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq=6194, 
  XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq=6195, 
  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6196, 
  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6197, 
  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6198, 
  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6199, 
  XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq=6200, 
  XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq=6201, 
  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=6202, 
  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=6203, 
  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=6204, 
  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=6205, 
  XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq=6206, 
  XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq=6207, 
  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=6208, 
  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=6209, 
  XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq=6210, 
  XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq=6211, 
  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=6212, 
  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=6213, 
  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=6214, 
  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=6215, 
  XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq=6216, 
  XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq=6217, 
  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=6218, 
  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=6219, 
  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq=6220, 
  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq=6221, 
  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6222, 
  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6223, 
  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq=6224, 
  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq=6225, 
  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6226, 
  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6227, 
  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6228, 
  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6229, 
  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq=6230, 
  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq=6231, 
  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6232, 
  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6233, 
  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq=6234, 
  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq=6235, 
  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6236, 
  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6237, 
  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6238, 
  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6239, 
  XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq=6240, 
  XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq=6241, 
  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6242, 
  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6243, 
  XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq=6244, 
  XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq=6245, 
  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6246, 
  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6247, 
  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6248, 
  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6249, 
  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=6250, 
  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=6251, 
  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=6252, 
  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=6253, 
  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=6254, 
  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=6255, 
  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=6256, 
  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=6257, 
  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=6258, 
  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=6259, 
  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=6260, 
  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=6261, 
  XED_IFORM_VPTEST_XMMdq_MEMdq=6262, 
  XED_IFORM_VPTEST_XMMdq_XMMdq=6263, 
  XED_IFORM_VPTEST_YMMqq_MEMqq=6264, 
  XED_IFORM_VPTEST_YMMqq_YMMqq=6265, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=6266, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=6267, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=6268, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=6269, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=6270, 
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=6271, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=6272, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=6273, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=6274, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=6275, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=6276, 
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=6277, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=6278, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=6279, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=6280, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=6281, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=6282, 
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=6283, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=6284, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=6285, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=6286, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=6287, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=6288, 
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=6289, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=6290, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=6291, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=6292, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=6293, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=6294, 
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=6295, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=6296, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=6297, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=6298, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=6299, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=6300, 
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=6301, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=6302, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=6303, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=6304, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=6305, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=6306, 
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=6307, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=6308, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=6309, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=6310, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=6311, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=6312, 
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=6313, 
  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq=6314, 
  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq=6315, 
  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6316, 
  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6317, 
  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq=6318, 
  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq=6319, 
  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6320, 
  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6321, 
  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6322, 
  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6323, 
  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq=6324, 
  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq=6325, 
  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6326, 
  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6327, 
  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq=6328, 
  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq=6329, 
  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6330, 
  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6331, 
  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6332, 
  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6333, 
  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq=6334, 
  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq=6335, 
  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6336, 
  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6337, 
  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq=6338, 
  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq=6339, 
  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6340, 
  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6341, 
  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6342, 
  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6343, 
  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq=6344, 
  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq=6345, 
  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6346, 
  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6347, 
  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq=6348, 
  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq=6349, 
  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6350, 
  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6351, 
  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6352, 
  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6353, 
  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq=6354, 
  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq=6355, 
  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6356, 
  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6357, 
  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq=6358, 
  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq=6359, 
  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6360, 
  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6361, 
  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6362, 
  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6363, 
  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq=6364, 
  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq=6365, 
  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6366, 
  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6367, 
  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq=6368, 
  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq=6369, 
  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6370, 
  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6371, 
  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6372, 
  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6373, 
  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq=6374, 
  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq=6375, 
  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6376, 
  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6377, 
  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq=6378, 
  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq=6379, 
  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6380, 
  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6381, 
  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6382, 
  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6383, 
  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq=6384, 
  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq=6385, 
  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6386, 
  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6387, 
  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq=6388, 
  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq=6389, 
  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6390, 
  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6391, 
  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6392, 
  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6393, 
  XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq=6394, 
  XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq=6395, 
  XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq=6396, 
  XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq=6397, 
  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6398, 
  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6399, 
  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6400, 
  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6401, 
  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6402, 
  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6403, 
  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6404, 
  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6405, 
  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6406, 
  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6407, 
  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6408, 
  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6409, 
  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6410, 
  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6411, 
  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6412, 
  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6413, 
  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6414, 
  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6415, 
  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6416, 
  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6417, 
  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6418, 
  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6419, 
  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6420, 
  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6421, 
  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6422, 
  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6423, 
  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6424, 
  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6425, 
  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512=6426, 
  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512=6427, 
  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512=6428, 
  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512=6429, 
  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512=6430, 
  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=6431, 
  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512=6432, 
  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512=6433, 
  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512=6434, 
  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512=6435, 
  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512=6436, 
  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=6437, 
  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6438, 
  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6439, 
  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6440, 
  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6441, 
  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=6442, 
  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=6443, 
  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=6444, 
  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=6445, 
  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=6446, 
  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=6447, 
  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=6448, 
  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=6449, 
  XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512=6450, 
  XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512=6451, 
  XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512=6452, 
  XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512=6453, 
  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512=6454, 
  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6455, 
  XED_IFORM_VRCPPS_XMMdq_MEMdq=6456, 
  XED_IFORM_VRCPPS_XMMdq_XMMdq=6457, 
  XED_IFORM_VRCPPS_YMMqq_MEMqq=6458, 
  XED_IFORM_VRCPPS_YMMqq_YMMqq=6459, 
  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6460, 
  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6461, 
  XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd=6462, 
  XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd=6463, 
  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=6464, 
  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6465, 
  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6466, 
  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6467, 
  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6468, 
  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6469, 
  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=6470, 
  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=6471, 
  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=6472, 
  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=6473, 
  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=6474, 
  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=6475, 
  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6476, 
  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6477, 
  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6478, 
  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6479, 
  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6480, 
  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6481, 
  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6482, 
  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6483, 
  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=6484, 
  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=6485, 
  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6486, 
  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6487, 
  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=6488, 
  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6489, 
  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6490, 
  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6491, 
  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6492, 
  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6493, 
  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=6494, 
  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=6495, 
  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=6496, 
  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=6497, 
  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=6498, 
  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=6499, 
  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6500, 
  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6501, 
  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6502, 
  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6503, 
  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6504, 
  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6505, 
  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6506, 
  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6507, 
  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=6508, 
  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=6509, 
  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6510, 
  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6511, 
  XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb=6512, 
  XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb=6513, 
  XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb=6514, 
  XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb=6515, 
  XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb=6516, 
  XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb=6517, 
  XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb=6518, 
  XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb=6519, 
  XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb=6520, 
  XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb=6521, 
  XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb=6522, 
  XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb=6523, 
  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512=6524, 
  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512=6525, 
  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512=6526, 
  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512=6527, 
  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512=6528, 
  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=6529, 
  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512=6530, 
  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512=6531, 
  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512=6532, 
  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512=6533, 
  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512=6534, 
  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=6535, 
  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6536, 
  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6537, 
  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6538, 
  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6539, 
  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=6540, 
  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=6541, 
  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=6542, 
  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=6543, 
  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=6544, 
  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=6545, 
  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=6546, 
  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=6547, 
  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512=6548, 
  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512=6549, 
  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512=6550, 
  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512=6551, 
  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512=6552, 
  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6553, 
  XED_IFORM_VRSQRTPS_XMMdq_MEMdq=6554, 
  XED_IFORM_VRSQRTPS_XMMdq_XMMdq=6555, 
  XED_IFORM_VRSQRTPS_YMMqq_MEMqq=6556, 
  XED_IFORM_VRSQRTPS_YMMqq_YMMqq=6557, 
  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6558, 
  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6559, 
  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd=6560, 
  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd=6561, 
  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6562, 
  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6563, 
  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6564, 
  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6565, 
  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6566, 
  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6567, 
  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6568, 
  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6569, 
  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=6570, 
  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=6571, 
  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=6572, 
  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=6573, 
  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6574, 
  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6575, 
  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6576, 
  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6577, 
  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6578, 
  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6579, 
  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6580, 
  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6581, 
  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6582, 
  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6583, 
  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6584, 
  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6585, 
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6586, 
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6587, 
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6588, 
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6589, 
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256=6590, 
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512=6591, 
  XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=6592, 
  XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=6593, 
  XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=6594, 
  XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=6595, 
  XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=6596, 
  XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=6597, 
  XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=6598, 
  XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=6599, 
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6600, 
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6601, 
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6602, 
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6603, 
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256=6604, 
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512=6605, 
  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6606, 
  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6607, 
  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6608, 
  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6609, 
  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6610, 
  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6611, 
  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6612, 
  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6613, 
  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=6614, 
  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=6615, 
  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=6616, 
  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=6617, 
  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=6618, 
  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=6619, 
  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=6620, 
  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=6621, 
  XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb=6622, 
  XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb=6623, 
  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6624, 
  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6625, 
  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6626, 
  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6627, 
  XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb=6628, 
  XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb=6629, 
  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6630, 
  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6631, 
  XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb=6632, 
  XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb=6633, 
  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6634, 
  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6635, 
  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6636, 
  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6637, 
  XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb=6638, 
  XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb=6639, 
  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6640, 
  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6641, 
  XED_IFORM_VSQRTPD_XMMdq_MEMdq=6642, 
  XED_IFORM_VSQRTPD_XMMdq_XMMdq=6643, 
  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512=6644, 
  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512=6645, 
  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512=6646, 
  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512=6647, 
  XED_IFORM_VSQRTPD_YMMqq_MEMqq=6648, 
  XED_IFORM_VSQRTPD_YMMqq_YMMqq=6649, 
  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512=6650, 
  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512=6651, 
  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512=6652, 
  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512=6653, 
  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512=6654, 
  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512=6655, 
  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512=6656, 
  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6657, 
  XED_IFORM_VSQRTPS_XMMdq_MEMdq=6658, 
  XED_IFORM_VSQRTPS_XMMdq_XMMdq=6659, 
  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512=6660, 
  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512=6661, 
  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512=6662, 
  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512=6663, 
  XED_IFORM_VSQRTPS_YMMqq_MEMqq=6664, 
  XED_IFORM_VSQRTPS_YMMqq_YMMqq=6665, 
  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512=6666, 
  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512=6667, 
  XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq=6668, 
  XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq=6669, 
  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6670, 
  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6671, 
  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6672, 
  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6673, 
  XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd=6674, 
  XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd=6675, 
  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6676, 
  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6677, 
  XED_IFORM_VSTMXCSR_MEMd=6678, 
  XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq=6679, 
  XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq=6680, 
  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6681, 
  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6682, 
  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6683, 
  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6684, 
  XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq=6685, 
  XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq=6686, 
  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6687, 
  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6688, 
  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6689, 
  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6690, 
  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=6691, 
  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=6692, 
  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=6693, 
  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=6694, 
  XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq=6695, 
  XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq=6696, 
  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6697, 
  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6698, 
  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6699, 
  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6700, 
  XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq=6701, 
  XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq=6702, 
  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6703, 
  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6704, 
  XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq=6705, 
  XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq=6706, 
  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6707, 
  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6708, 
  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6709, 
  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6710, 
  XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd=6711, 
  XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd=6712, 
  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6713, 
  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6714, 
  XED_IFORM_VTESTPD_XMMdq_MEMdq=6715, 
  XED_IFORM_VTESTPD_XMMdq_XMMdq=6716, 
  XED_IFORM_VTESTPD_YMMqq_MEMqq=6717, 
  XED_IFORM_VTESTPD_YMMqq_YMMqq=6718, 
  XED_IFORM_VTESTPS_XMMdq_MEMdq=6719, 
  XED_IFORM_VTESTPS_XMMdq_XMMdq=6720, 
  XED_IFORM_VTESTPS_YMMqq_MEMqq=6721, 
  XED_IFORM_VTESTPS_YMMqq_YMMqq=6722, 
  XED_IFORM_VUCOMISD_XMMdq_MEMq=6723, 
  XED_IFORM_VUCOMISD_XMMdq_XMMq=6724, 
  XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512=6725, 
  XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512=6726, 
  XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512=6727, 
  XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512=6728, 
  XED_IFORM_VUCOMISS_XMMdq_MEMd=6729, 
  XED_IFORM_VUCOMISS_XMMdq_XMMd=6730, 
  XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512=6731, 
  XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512=6732, 
  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq=6733, 
  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq=6734, 
  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6735, 
  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6736, 
  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6737, 
  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6738, 
  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq=6739, 
  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq=6740, 
  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6741, 
  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6742, 
  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq=6743, 
  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq=6744, 
  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6745, 
  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6746, 
  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6747, 
  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6748, 
  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq=6749, 
  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq=6750, 
  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6751, 
  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6752, 
  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq=6753, 
  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq=6754, 
  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6755, 
  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6756, 
  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6757, 
  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6758, 
  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq=6759, 
  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq=6760, 
  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6761, 
  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6762, 
  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq=6763, 
  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq=6764, 
  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6765, 
  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6766, 
  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6767, 
  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6768, 
  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq=6769, 
  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq=6770, 
  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6771, 
  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6772, 
  XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq=6773, 
  XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq=6774, 
  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6775, 
  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6776, 
  XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq=6777, 
  XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq=6778, 
  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6779, 
  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6780, 
  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6781, 
  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6782, 
  XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq=6783, 
  XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq=6784, 
  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6785, 
  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6786, 
  XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq=6787, 
  XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq=6788, 
  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6789, 
  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6790, 
  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6791, 
  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6792, 
  XED_IFORM_VZEROALL=6793, 
  XED_IFORM_VZEROUPPER=6794, 
  XED_IFORM_WBINVD=6795, 
  XED_IFORM_WBNOINVD=6796, 
  XED_IFORM_WRFSBASE_GPRy=6797, 
  XED_IFORM_WRGSBASE_GPRy=6798, 
  XED_IFORM_WRMSR=6799, 
  XED_IFORM_WRPKRU=6800, 
  XED_IFORM_WRSSD_MEMu32_GPR32u32=6801, 
  XED_IFORM_WRSSQ_MEMu64_GPR64u64=6802, 
  XED_IFORM_WRUSSD_MEMu32_GPR32u32=6803, 
  XED_IFORM_WRUSSQ_MEMu64_GPR64u64=6804, 
  XED_IFORM_XABORT_IMMb=6805, 
  XED_IFORM_XADD_GPR8_GPR8=6806, 
  XED_IFORM_XADD_GPRv_GPRv=6807, 
  XED_IFORM_XADD_MEMb_GPR8=6808, 
  XED_IFORM_XADD_MEMv_GPRv=6809, 
  XED_IFORM_XADD_LOCK_MEMb_GPR8=6810, 
  XED_IFORM_XADD_LOCK_MEMv_GPRv=6811, 
  XED_IFORM_XBEGIN_RELBRz=6812, 
  XED_IFORM_XCHG_GPR8_GPR8=6813, 
  XED_IFORM_XCHG_GPRv_GPRv=6814, 
  XED_IFORM_XCHG_GPRv_OrAX=6815, 
  XED_IFORM_XCHG_MEMb_GPR8=6816, 
  XED_IFORM_XCHG_MEMv_GPRv=6817, 
  XED_IFORM_XEND=6818, 
  XED_IFORM_XGETBV=6819, 
  XED_IFORM_XLAT=6820, 
  XED_IFORM_XOR_AL_IMMb=6821, 
  XED_IFORM_XOR_GPR8_GPR8_30=6822, 
  XED_IFORM_XOR_GPR8_GPR8_32=6823, 
  XED_IFORM_XOR_GPR8_IMMb_80r6=6824, 
  XED_IFORM_XOR_GPR8_IMMb_82r6=6825, 
  XED_IFORM_XOR_GPR8_MEMb=6826, 
  XED_IFORM_XOR_GPRv_GPRv_31=6827, 
  XED_IFORM_XOR_GPRv_GPRv_33=6828, 
  XED_IFORM_XOR_GPRv_IMMb=6829, 
  XED_IFORM_XOR_GPRv_IMMz=6830, 
  XED_IFORM_XOR_GPRv_MEMv=6831, 
  XED_IFORM_XOR_MEMb_GPR8=6832, 
  XED_IFORM_XOR_MEMb_IMMb_80r6=6833, 
  XED_IFORM_XOR_MEMb_IMMb_82r6=6834, 
  XED_IFORM_XOR_MEMv_GPRv=6835, 
  XED_IFORM_XOR_MEMv_IMMb=6836, 
  XED_IFORM_XOR_MEMv_IMMz=6837, 
  XED_IFORM_XOR_OrAX_IMMz=6838, 
  XED_IFORM_XORPD_XMMxuq_MEMxuq=6839, 
  XED_IFORM_XORPD_XMMxuq_XMMxuq=6840, 
  XED_IFORM_XORPS_XMMxud_MEMxud=6841, 
  XED_IFORM_XORPS_XMMxud_XMMxud=6842, 
  XED_IFORM_XOR_LOCK_MEMb_GPR8=6843, 
  XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6=6844, 
  XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6=6845, 
  XED_IFORM_XOR_LOCK_MEMv_GPRv=6846, 
  XED_IFORM_XOR_LOCK_MEMv_IMMb=6847, 
  XED_IFORM_XOR_LOCK_MEMv_IMMz=6848, 
  XED_IFORM_XRESLDTRK=6849, 
  XED_IFORM_XRSTOR_MEMmxsave=6850, 
  XED_IFORM_XRSTOR64_MEMmxsave=6851, 
  XED_IFORM_XRSTORS_MEMmxsave=6852, 
  XED_IFORM_XRSTORS64_MEMmxsave=6853, 
  XED_IFORM_XSAVE_MEMmxsave=6854, 
  XED_IFORM_XSAVE64_MEMmxsave=6855, 
  XED_IFORM_XSAVEC_MEMmxsave=6856, 
  XED_IFORM_XSAVEC64_MEMmxsave=6857, 
  XED_IFORM_XSAVEOPT_MEMmxsave=6858, 
  XED_IFORM_XSAVEOPT64_MEMmxsave=6859, 
  XED_IFORM_XSAVES_MEMmxsave=6860, 
  XED_IFORM_XSAVES64_MEMmxsave=6861, 
  XED_IFORM_XSETBV=6862, 
  XED_IFORM_XSTORE=6863, 
  XED_IFORM_XSUSLDTRK=6864, 
  XED_IFORM_XTEST=6865, 
  XED_IFORM_LAST
} xed_iform_enum_t;

/// This converts strings to #xed_iform_enum_t types.
/// @param s A C-string.
/// @return #xed_iform_enum_t
/// @ingroup ENUM
XED_DLL_EXPORT xed_iform_enum_t str2xed_iform_enum_t(const char* s);
/// This converts strings to #xed_iform_enum_t types.
/// @param p An enumeration element of type xed_iform_enum_t.
/// @return string
/// @ingroup ENUM
XED_DLL_EXPORT const char* xed_iform_enum_t2str(const xed_iform_enum_t p);

/// Returns the last element of the enumeration
/// @return xed_iform_enum_t The last element of the enumeration.
/// @ingroup ENUM
XED_DLL_EXPORT xed_iform_enum_t xed_iform_enum_t_last(void);
#endif