/// @file xed-iform-enum.c

// This file was automatically generated.
// Do not edit this file.

#include <string.h>
#include <assert.h>
#include "xed-iform-enum.h"

typedef struct {
    const char* name;
    xed_iform_enum_t value;
} name_table_xed_iform_enum_t;
static const name_table_xed_iform_enum_t name_array_xed_iform_enum_t[] = {
{"INVALID", XED_IFORM_INVALID},
{"AAA", XED_IFORM_AAA},
{"AAD_IMMb", XED_IFORM_AAD_IMMb},
{"AAM_IMMb", XED_IFORM_AAM_IMMb},
{"AAS", XED_IFORM_AAS},
{"ADC_AL_IMMb", XED_IFORM_ADC_AL_IMMb},
{"ADC_GPR8_GPR8_10", XED_IFORM_ADC_GPR8_GPR8_10},
{"ADC_GPR8_GPR8_12", XED_IFORM_ADC_GPR8_GPR8_12},
{"ADC_GPR8_IMMb_80r2", XED_IFORM_ADC_GPR8_IMMb_80r2},
{"ADC_GPR8_IMMb_82r2", XED_IFORM_ADC_GPR8_IMMb_82r2},
{"ADC_GPR8_MEMb", XED_IFORM_ADC_GPR8_MEMb},
{"ADC_GPRv_GPRv_11", XED_IFORM_ADC_GPRv_GPRv_11},
{"ADC_GPRv_GPRv_13", XED_IFORM_ADC_GPRv_GPRv_13},
{"ADC_GPRv_IMMb", XED_IFORM_ADC_GPRv_IMMb},
{"ADC_GPRv_IMMz", XED_IFORM_ADC_GPRv_IMMz},
{"ADC_GPRv_MEMv", XED_IFORM_ADC_GPRv_MEMv},
{"ADC_MEMb_GPR8", XED_IFORM_ADC_MEMb_GPR8},
{"ADC_MEMb_IMMb_80r2", XED_IFORM_ADC_MEMb_IMMb_80r2},
{"ADC_MEMb_IMMb_82r2", XED_IFORM_ADC_MEMb_IMMb_82r2},
{"ADC_MEMv_GPRv", XED_IFORM_ADC_MEMv_GPRv},
{"ADC_MEMv_IMMb", XED_IFORM_ADC_MEMv_IMMb},
{"ADC_MEMv_IMMz", XED_IFORM_ADC_MEMv_IMMz},
{"ADC_OrAX_IMMz", XED_IFORM_ADC_OrAX_IMMz},
{"ADCX_GPR32d_GPR32d", XED_IFORM_ADCX_GPR32d_GPR32d},
{"ADCX_GPR32d_MEMd", XED_IFORM_ADCX_GPR32d_MEMd},
{"ADCX_GPR64q_GPR64q", XED_IFORM_ADCX_GPR64q_GPR64q},
{"ADCX_GPR64q_MEMq", XED_IFORM_ADCX_GPR64q_MEMq},
{"ADC_LOCK_MEMb_GPR8", XED_IFORM_ADC_LOCK_MEMb_GPR8},
{"ADC_LOCK_MEMb_IMMb_80r2", XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2},
{"ADC_LOCK_MEMb_IMMb_82r2", XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2},
{"ADC_LOCK_MEMv_GPRv", XED_IFORM_ADC_LOCK_MEMv_GPRv},
{"ADC_LOCK_MEMv_IMMb", XED_IFORM_ADC_LOCK_MEMv_IMMb},
{"ADC_LOCK_MEMv_IMMz", XED_IFORM_ADC_LOCK_MEMv_IMMz},
{"ADD_AL_IMMb", XED_IFORM_ADD_AL_IMMb},
{"ADD_GPR8_GPR8_00", XED_IFORM_ADD_GPR8_GPR8_00},
{"ADD_GPR8_GPR8_02", XED_IFORM_ADD_GPR8_GPR8_02},
{"ADD_GPR8_IMMb_80r0", XED_IFORM_ADD_GPR8_IMMb_80r0},
{"ADD_GPR8_IMMb_82r0", XED_IFORM_ADD_GPR8_IMMb_82r0},
{"ADD_GPR8_MEMb", XED_IFORM_ADD_GPR8_MEMb},
{"ADD_GPRv_GPRv_01", XED_IFORM_ADD_GPRv_GPRv_01},
{"ADD_GPRv_GPRv_03", XED_IFORM_ADD_GPRv_GPRv_03},
{"ADD_GPRv_IMMb", XED_IFORM_ADD_GPRv_IMMb},
{"ADD_GPRv_IMMz", XED_IFORM_ADD_GPRv_IMMz},
{"ADD_GPRv_MEMv", XED_IFORM_ADD_GPRv_MEMv},
{"ADD_MEMb_GPR8", XED_IFORM_ADD_MEMb_GPR8},
{"ADD_MEMb_IMMb_80r0", XED_IFORM_ADD_MEMb_IMMb_80r0},
{"ADD_MEMb_IMMb_82r0", XED_IFORM_ADD_MEMb_IMMb_82r0},
{"ADD_MEMv_GPRv", XED_IFORM_ADD_MEMv_GPRv},
{"ADD_MEMv_IMMb", XED_IFORM_ADD_MEMv_IMMb},
{"ADD_MEMv_IMMz", XED_IFORM_ADD_MEMv_IMMz},
{"ADD_OrAX_IMMz", XED_IFORM_ADD_OrAX_IMMz},
{"ADDPD_XMMpd_MEMpd", XED_IFORM_ADDPD_XMMpd_MEMpd},
{"ADDPD_XMMpd_XMMpd", XED_IFORM_ADDPD_XMMpd_XMMpd},
{"ADDPS_XMMps_MEMps", XED_IFORM_ADDPS_XMMps_MEMps},
{"ADDPS_XMMps_XMMps", XED_IFORM_ADDPS_XMMps_XMMps},
{"ADDSD_XMMsd_MEMsd", XED_IFORM_ADDSD_XMMsd_MEMsd},
{"ADDSD_XMMsd_XMMsd", XED_IFORM_ADDSD_XMMsd_XMMsd},
{"ADDSS_XMMss_MEMss", XED_IFORM_ADDSS_XMMss_MEMss},
{"ADDSS_XMMss_XMMss", XED_IFORM_ADDSS_XMMss_XMMss},
{"ADDSUBPD_XMMpd_MEMpd", XED_IFORM_ADDSUBPD_XMMpd_MEMpd},
{"ADDSUBPD_XMMpd_XMMpd", XED_IFORM_ADDSUBPD_XMMpd_XMMpd},
{"ADDSUBPS_XMMps_MEMps", XED_IFORM_ADDSUBPS_XMMps_MEMps},
{"ADDSUBPS_XMMps_XMMps", XED_IFORM_ADDSUBPS_XMMps_XMMps},
{"ADD_LOCK_MEMb_GPR8", XED_IFORM_ADD_LOCK_MEMb_GPR8},
{"ADD_LOCK_MEMb_IMMb_80r0", XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0},
{"ADD_LOCK_MEMb_IMMb_82r0", XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0},
{"ADD_LOCK_MEMv_GPRv", XED_IFORM_ADD_LOCK_MEMv_GPRv},
{"ADD_LOCK_MEMv_IMMb", XED_IFORM_ADD_LOCK_MEMv_IMMb},
{"ADD_LOCK_MEMv_IMMz", XED_IFORM_ADD_LOCK_MEMv_IMMz},
{"ADOX_GPR32d_GPR32d", XED_IFORM_ADOX_GPR32d_GPR32d},
{"ADOX_GPR32d_MEMd", XED_IFORM_ADOX_GPR32d_MEMd},
{"ADOX_GPR64q_GPR64q", XED_IFORM_ADOX_GPR64q_GPR64q},
{"ADOX_GPR64q_MEMq", XED_IFORM_ADOX_GPR64q_MEMq},
{"AESDEC_XMMdq_MEMdq", XED_IFORM_AESDEC_XMMdq_MEMdq},
{"AESDEC_XMMdq_XMMdq", XED_IFORM_AESDEC_XMMdq_XMMdq},
{"AESDEC128KL_XMMu8_MEMu8", XED_IFORM_AESDEC128KL_XMMu8_MEMu8},
{"AESDEC256KL_XMMu8_MEMu8", XED_IFORM_AESDEC256KL_XMMu8_MEMu8},
{"AESDECLAST_XMMdq_MEMdq", XED_IFORM_AESDECLAST_XMMdq_MEMdq},
{"AESDECLAST_XMMdq_XMMdq", XED_IFORM_AESDECLAST_XMMdq_XMMdq},
{"AESDECWIDE128KL_MEMu8", XED_IFORM_AESDECWIDE128KL_MEMu8},
{"AESDECWIDE256KL_MEMu8", XED_IFORM_AESDECWIDE256KL_MEMu8},
{"AESENC_XMMdq_MEMdq", XED_IFORM_AESENC_XMMdq_MEMdq},
{"AESENC_XMMdq_XMMdq", XED_IFORM_AESENC_XMMdq_XMMdq},
{"AESENC128KL_XMMu8_MEMu8", XED_IFORM_AESENC128KL_XMMu8_MEMu8},
{"AESENC256KL_XMMu8_MEMu8", XED_IFORM_AESENC256KL_XMMu8_MEMu8},
{"AESENCLAST_XMMdq_MEMdq", XED_IFORM_AESENCLAST_XMMdq_MEMdq},
{"AESENCLAST_XMMdq_XMMdq", XED_IFORM_AESENCLAST_XMMdq_XMMdq},
{"AESENCWIDE128KL_MEMu8", XED_IFORM_AESENCWIDE128KL_MEMu8},
{"AESENCWIDE256KL_MEMu8", XED_IFORM_AESENCWIDE256KL_MEMu8},
{"AESIMC_XMMdq_MEMdq", XED_IFORM_AESIMC_XMMdq_MEMdq},
{"AESIMC_XMMdq_XMMdq", XED_IFORM_AESIMC_XMMdq_XMMdq},
{"AESKEYGENASSIST_XMMdq_MEMdq_IMMb", XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb},
{"AESKEYGENASSIST_XMMdq_XMMdq_IMMb", XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb},
{"AND_AL_IMMb", XED_IFORM_AND_AL_IMMb},
{"AND_GPR8_GPR8_20", XED_IFORM_AND_GPR8_GPR8_20},
{"AND_GPR8_GPR8_22", XED_IFORM_AND_GPR8_GPR8_22},
{"AND_GPR8_IMMb_80r4", XED_IFORM_AND_GPR8_IMMb_80r4},
{"AND_GPR8_IMMb_82r4", XED_IFORM_AND_GPR8_IMMb_82r4},
{"AND_GPR8_MEMb", XED_IFORM_AND_GPR8_MEMb},
{"AND_GPRv_GPRv_21", XED_IFORM_AND_GPRv_GPRv_21},
{"AND_GPRv_GPRv_23", XED_IFORM_AND_GPRv_GPRv_23},
{"AND_GPRv_IMMb", XED_IFORM_AND_GPRv_IMMb},
{"AND_GPRv_IMMz", XED_IFORM_AND_GPRv_IMMz},
{"AND_GPRv_MEMv", XED_IFORM_AND_GPRv_MEMv},
{"AND_MEMb_GPR8", XED_IFORM_AND_MEMb_GPR8},
{"AND_MEMb_IMMb_80r4", XED_IFORM_AND_MEMb_IMMb_80r4},
{"AND_MEMb_IMMb_82r4", XED_IFORM_AND_MEMb_IMMb_82r4},
{"AND_MEMv_GPRv", XED_IFORM_AND_MEMv_GPRv},
{"AND_MEMv_IMMb", XED_IFORM_AND_MEMv_IMMb},
{"AND_MEMv_IMMz", XED_IFORM_AND_MEMv_IMMz},
{"AND_OrAX_IMMz", XED_IFORM_AND_OrAX_IMMz},
{"ANDN_VGPR32d_VGPR32d_MEMd", XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd},
{"ANDN_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d},
{"ANDN_VGPR64q_VGPR64q_MEMq", XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq},
{"ANDN_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q},
{"ANDNPD_XMMxuq_MEMxuq", XED_IFORM_ANDNPD_XMMxuq_MEMxuq},
{"ANDNPD_XMMxuq_XMMxuq", XED_IFORM_ANDNPD_XMMxuq_XMMxuq},
{"ANDNPS_XMMxud_MEMxud", XED_IFORM_ANDNPS_XMMxud_MEMxud},
{"ANDNPS_XMMxud_XMMxud", XED_IFORM_ANDNPS_XMMxud_XMMxud},
{"ANDPD_XMMxuq_MEMxuq", XED_IFORM_ANDPD_XMMxuq_MEMxuq},
{"ANDPD_XMMxuq_XMMxuq", XED_IFORM_ANDPD_XMMxuq_XMMxuq},
{"ANDPS_XMMxud_MEMxud", XED_IFORM_ANDPS_XMMxud_MEMxud},
{"ANDPS_XMMxud_XMMxud", XED_IFORM_ANDPS_XMMxud_XMMxud},
{"AND_LOCK_MEMb_GPR8", XED_IFORM_AND_LOCK_MEMb_GPR8},
{"AND_LOCK_MEMb_IMMb_80r4", XED_IFORM_AND_LOCK_MEMb_IMMb_80r4},
{"AND_LOCK_MEMb_IMMb_82r4", XED_IFORM_AND_LOCK_MEMb_IMMb_82r4},
{"AND_LOCK_MEMv_GPRv", XED_IFORM_AND_LOCK_MEMv_GPRv},
{"AND_LOCK_MEMv_IMMb", XED_IFORM_AND_LOCK_MEMv_IMMb},
{"AND_LOCK_MEMv_IMMz", XED_IFORM_AND_LOCK_MEMv_IMMz},
{"ARPL_GPR16_GPR16", XED_IFORM_ARPL_GPR16_GPR16},
{"ARPL_MEMw_GPR16", XED_IFORM_ARPL_MEMw_GPR16},
{"BEXTR_VGPR32d_MEMd_VGPR32d", XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d},
{"BEXTR_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d},
{"BEXTR_VGPR64q_MEMq_VGPR64q", XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q},
{"BEXTR_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q},
{"BEXTR_XOP_VGPR32d_MEMd_IMMd", XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd},
{"BEXTR_XOP_VGPR32d_VGPR32d_IMMd", XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd},
{"BEXTR_XOP_VGPRyy_MEMy_IMMd", XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd},
{"BEXTR_XOP_VGPRyy_VGPRyy_IMMd", XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd},
{"BLCFILL_VGPR32d_MEMd", XED_IFORM_BLCFILL_VGPR32d_MEMd},
{"BLCFILL_VGPR32d_VGPR32d", XED_IFORM_BLCFILL_VGPR32d_VGPR32d},
{"BLCFILL_VGPRyy_MEMy", XED_IFORM_BLCFILL_VGPRyy_MEMy},
{"BLCFILL_VGPRyy_VGPRyy", XED_IFORM_BLCFILL_VGPRyy_VGPRyy},
{"BLCI_VGPR32d_MEMd", XED_IFORM_BLCI_VGPR32d_MEMd},
{"BLCI_VGPR32d_VGPR32d", XED_IFORM_BLCI_VGPR32d_VGPR32d},
{"BLCI_VGPRyy_MEMy", XED_IFORM_BLCI_VGPRyy_MEMy},
{"BLCI_VGPRyy_VGPRyy", XED_IFORM_BLCI_VGPRyy_VGPRyy},
{"BLCIC_VGPR32d_MEMd", XED_IFORM_BLCIC_VGPR32d_MEMd},
{"BLCIC_VGPR32d_VGPR32d", XED_IFORM_BLCIC_VGPR32d_VGPR32d},
{"BLCIC_VGPRyy_MEMy", XED_IFORM_BLCIC_VGPRyy_MEMy},
{"BLCIC_VGPRyy_VGPRyy", XED_IFORM_BLCIC_VGPRyy_VGPRyy},
{"BLCMSK_VGPR32d_MEMd", XED_IFORM_BLCMSK_VGPR32d_MEMd},
{"BLCMSK_VGPR32d_VGPR32d", XED_IFORM_BLCMSK_VGPR32d_VGPR32d},
{"BLCMSK_VGPRyy_MEMy", XED_IFORM_BLCMSK_VGPRyy_MEMy},
{"BLCMSK_VGPRyy_VGPRyy", XED_IFORM_BLCMSK_VGPRyy_VGPRyy},
{"BLCS_VGPR32d_MEMd", XED_IFORM_BLCS_VGPR32d_MEMd},
{"BLCS_VGPR32d_VGPR32d", XED_IFORM_BLCS_VGPR32d_VGPR32d},
{"BLCS_VGPRyy_MEMy", XED_IFORM_BLCS_VGPRyy_MEMy},
{"BLCS_VGPRyy_VGPRyy", XED_IFORM_BLCS_VGPRyy_VGPRyy},
{"BLENDPD_XMMdq_MEMdq_IMMb", XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb},
{"BLENDPD_XMMdq_XMMdq_IMMb", XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb},
{"BLENDPS_XMMdq_MEMdq_IMMb", XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb},
{"BLENDPS_XMMdq_XMMdq_IMMb", XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb},
{"BLENDVPD_XMMdq_MEMdq", XED_IFORM_BLENDVPD_XMMdq_MEMdq},
{"BLENDVPD_XMMdq_XMMdq", XED_IFORM_BLENDVPD_XMMdq_XMMdq},
{"BLENDVPS_XMMdq_MEMdq", XED_IFORM_BLENDVPS_XMMdq_MEMdq},
{"BLENDVPS_XMMdq_XMMdq", XED_IFORM_BLENDVPS_XMMdq_XMMdq},
{"BLSFILL_VGPR32d_MEMd", XED_IFORM_BLSFILL_VGPR32d_MEMd},
{"BLSFILL_VGPR32d_VGPR32d", XED_IFORM_BLSFILL_VGPR32d_VGPR32d},
{"BLSFILL_VGPRyy_MEMy", XED_IFORM_BLSFILL_VGPRyy_MEMy},
{"BLSFILL_VGPRyy_VGPRyy", XED_IFORM_BLSFILL_VGPRyy_VGPRyy},
{"BLSI_VGPR32d_MEMd", XED_IFORM_BLSI_VGPR32d_MEMd},
{"BLSI_VGPR32d_VGPR32d", XED_IFORM_BLSI_VGPR32d_VGPR32d},
{"BLSI_VGPR64q_MEMq", XED_IFORM_BLSI_VGPR64q_MEMq},
{"BLSI_VGPR64q_VGPR64q", XED_IFORM_BLSI_VGPR64q_VGPR64q},
{"BLSIC_VGPR32d_MEMd", XED_IFORM_BLSIC_VGPR32d_MEMd},
{"BLSIC_VGPR32d_VGPR32d", XED_IFORM_BLSIC_VGPR32d_VGPR32d},
{"BLSIC_VGPRyy_MEMy", XED_IFORM_BLSIC_VGPRyy_MEMy},
{"BLSIC_VGPRyy_VGPRyy", XED_IFORM_BLSIC_VGPRyy_VGPRyy},
{"BLSMSK_VGPR32d_MEMd", XED_IFORM_BLSMSK_VGPR32d_MEMd},
{"BLSMSK_VGPR32d_VGPR32d", XED_IFORM_BLSMSK_VGPR32d_VGPR32d},
{"BLSMSK_VGPR64q_MEMq", XED_IFORM_BLSMSK_VGPR64q_MEMq},
{"BLSMSK_VGPR64q_VGPR64q", XED_IFORM_BLSMSK_VGPR64q_VGPR64q},
{"BLSR_VGPR32d_MEMd", XED_IFORM_BLSR_VGPR32d_MEMd},
{"BLSR_VGPR32d_VGPR32d", XED_IFORM_BLSR_VGPR32d_VGPR32d},
{"BLSR_VGPR64q_MEMq", XED_IFORM_BLSR_VGPR64q_MEMq},
{"BLSR_VGPR64q_VGPR64q", XED_IFORM_BLSR_VGPR64q_VGPR64q},
{"BNDCL_BND_AGEN", XED_IFORM_BNDCL_BND_AGEN},
{"BNDCL_BND_GPR32", XED_IFORM_BNDCL_BND_GPR32},
{"BNDCL_BND_GPR64", XED_IFORM_BNDCL_BND_GPR64},
{"BNDCN_BND_AGEN", XED_IFORM_BNDCN_BND_AGEN},
{"BNDCN_BND_GPR32", XED_IFORM_BNDCN_BND_GPR32},
{"BNDCN_BND_GPR64", XED_IFORM_BNDCN_BND_GPR64},
{"BNDCU_BND_AGEN", XED_IFORM_BNDCU_BND_AGEN},
{"BNDCU_BND_GPR32", XED_IFORM_BNDCU_BND_GPR32},
{"BNDCU_BND_GPR64", XED_IFORM_BNDCU_BND_GPR64},
{"BNDLDX_BND_MEMbnd32", XED_IFORM_BNDLDX_BND_MEMbnd32},
{"BNDLDX_BND_MEMbnd64", XED_IFORM_BNDLDX_BND_MEMbnd64},
{"BNDMK_BND_AGEN", XED_IFORM_BNDMK_BND_AGEN},
{"BNDMOV_BND_BND", XED_IFORM_BNDMOV_BND_BND},
{"BNDMOV_BND_MEMdq", XED_IFORM_BNDMOV_BND_MEMdq},
{"BNDMOV_BND_MEMq", XED_IFORM_BNDMOV_BND_MEMq},
{"BNDMOV_MEMdq_BND", XED_IFORM_BNDMOV_MEMdq_BND},
{"BNDMOV_MEMq_BND", XED_IFORM_BNDMOV_MEMq_BND},
{"BNDSTX_MEMbnd32_BND", XED_IFORM_BNDSTX_MEMbnd32_BND},
{"BNDSTX_MEMbnd64_BND", XED_IFORM_BNDSTX_MEMbnd64_BND},
{"BOUND_GPRv_MEMa16", XED_IFORM_BOUND_GPRv_MEMa16},
{"BOUND_GPRv_MEMa32", XED_IFORM_BOUND_GPRv_MEMa32},
{"BSF_GPRv_GPRv", XED_IFORM_BSF_GPRv_GPRv},
{"BSF_GPRv_MEMv", XED_IFORM_BSF_GPRv_MEMv},
{"BSR_GPRv_GPRv", XED_IFORM_BSR_GPRv_GPRv},
{"BSR_GPRv_MEMv", XED_IFORM_BSR_GPRv_MEMv},
{"BSWAP_GPRv", XED_IFORM_BSWAP_GPRv},
{"BT_GPRv_GPRv", XED_IFORM_BT_GPRv_GPRv},
{"BT_GPRv_IMMb", XED_IFORM_BT_GPRv_IMMb},
{"BT_MEMv_GPRv", XED_IFORM_BT_MEMv_GPRv},
{"BT_MEMv_IMMb", XED_IFORM_BT_MEMv_IMMb},
{"BTC_GPRv_GPRv", XED_IFORM_BTC_GPRv_GPRv},
{"BTC_GPRv_IMMb", XED_IFORM_BTC_GPRv_IMMb},
{"BTC_MEMv_GPRv", XED_IFORM_BTC_MEMv_GPRv},
{"BTC_MEMv_IMMb", XED_IFORM_BTC_MEMv_IMMb},
{"BTC_LOCK_MEMv_GPRv", XED_IFORM_BTC_LOCK_MEMv_GPRv},
{"BTC_LOCK_MEMv_IMMb", XED_IFORM_BTC_LOCK_MEMv_IMMb},
{"BTR_GPRv_GPRv", XED_IFORM_BTR_GPRv_GPRv},
{"BTR_GPRv_IMMb", XED_IFORM_BTR_GPRv_IMMb},
{"BTR_MEMv_GPRv", XED_IFORM_BTR_MEMv_GPRv},
{"BTR_MEMv_IMMb", XED_IFORM_BTR_MEMv_IMMb},
{"BTR_LOCK_MEMv_GPRv", XED_IFORM_BTR_LOCK_MEMv_GPRv},
{"BTR_LOCK_MEMv_IMMb", XED_IFORM_BTR_LOCK_MEMv_IMMb},
{"BTS_GPRv_GPRv", XED_IFORM_BTS_GPRv_GPRv},
{"BTS_GPRv_IMMb", XED_IFORM_BTS_GPRv_IMMb},
{"BTS_MEMv_GPRv", XED_IFORM_BTS_MEMv_GPRv},
{"BTS_MEMv_IMMb", XED_IFORM_BTS_MEMv_IMMb},
{"BTS_LOCK_MEMv_GPRv", XED_IFORM_BTS_LOCK_MEMv_GPRv},
{"BTS_LOCK_MEMv_IMMb", XED_IFORM_BTS_LOCK_MEMv_IMMb},
{"BZHI_VGPR32d_MEMd_VGPR32d", XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d},
{"BZHI_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d},
{"BZHI_VGPR64q_MEMq_VGPR64q", XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q},
{"BZHI_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q},
{"CALL_FAR_MEMp2", XED_IFORM_CALL_FAR_MEMp2},
{"CALL_FAR_PTRp_IMMw", XED_IFORM_CALL_FAR_PTRp_IMMw},
{"CALL_NEAR_GPRv", XED_IFORM_CALL_NEAR_GPRv},
{"CALL_NEAR_MEMv", XED_IFORM_CALL_NEAR_MEMv},
{"CALL_NEAR_RELBRd", XED_IFORM_CALL_NEAR_RELBRd},
{"CALL_NEAR_RELBRz", XED_IFORM_CALL_NEAR_RELBRz},
{"CBW", XED_IFORM_CBW},
{"CDQ", XED_IFORM_CDQ},
{"CDQE", XED_IFORM_CDQE},
{"CLAC", XED_IFORM_CLAC},
{"CLC", XED_IFORM_CLC},
{"CLD", XED_IFORM_CLD},
{"CLDEMOTE_MEMu8", XED_IFORM_CLDEMOTE_MEMu8},
{"CLFLUSH_MEMmprefetch", XED_IFORM_CLFLUSH_MEMmprefetch},
{"CLFLUSHOPT_MEMmprefetch", XED_IFORM_CLFLUSHOPT_MEMmprefetch},
{"CLGI", XED_IFORM_CLGI},
{"CLI", XED_IFORM_CLI},
{"CLRSSBSY_MEMu64", XED_IFORM_CLRSSBSY_MEMu64},
{"CLTS", XED_IFORM_CLTS},
{"CLUI", XED_IFORM_CLUI},
{"CLWB_MEMmprefetch", XED_IFORM_CLWB_MEMmprefetch},
{"CLZERO", XED_IFORM_CLZERO},
{"CMC", XED_IFORM_CMC},
{"CMOVB_GPRv_GPRv", XED_IFORM_CMOVB_GPRv_GPRv},
{"CMOVB_GPRv_MEMv", XED_IFORM_CMOVB_GPRv_MEMv},
{"CMOVBE_GPRv_GPRv", XED_IFORM_CMOVBE_GPRv_GPRv},
{"CMOVBE_GPRv_MEMv", XED_IFORM_CMOVBE_GPRv_MEMv},
{"CMOVL_GPRv_GPRv", XED_IFORM_CMOVL_GPRv_GPRv},
{"CMOVL_GPRv_MEMv", XED_IFORM_CMOVL_GPRv_MEMv},
{"CMOVLE_GPRv_GPRv", XED_IFORM_CMOVLE_GPRv_GPRv},
{"CMOVLE_GPRv_MEMv", XED_IFORM_CMOVLE_GPRv_MEMv},
{"CMOVNB_GPRv_GPRv", XED_IFORM_CMOVNB_GPRv_GPRv},
{"CMOVNB_GPRv_MEMv", XED_IFORM_CMOVNB_GPRv_MEMv},
{"CMOVNBE_GPRv_GPRv", XED_IFORM_CMOVNBE_GPRv_GPRv},
{"CMOVNBE_GPRv_MEMv", XED_IFORM_CMOVNBE_GPRv_MEMv},
{"CMOVNL_GPRv_GPRv", XED_IFORM_CMOVNL_GPRv_GPRv},
{"CMOVNL_GPRv_MEMv", XED_IFORM_CMOVNL_GPRv_MEMv},
{"CMOVNLE_GPRv_GPRv", XED_IFORM_CMOVNLE_GPRv_GPRv},
{"CMOVNLE_GPRv_MEMv", XED_IFORM_CMOVNLE_GPRv_MEMv},
{"CMOVNO_GPRv_GPRv", XED_IFORM_CMOVNO_GPRv_GPRv},
{"CMOVNO_GPRv_MEMv", XED_IFORM_CMOVNO_GPRv_MEMv},
{"CMOVNP_GPRv_GPRv", XED_IFORM_CMOVNP_GPRv_GPRv},
{"CMOVNP_GPRv_MEMv", XED_IFORM_CMOVNP_GPRv_MEMv},
{"CMOVNS_GPRv_GPRv", XED_IFORM_CMOVNS_GPRv_GPRv},
{"CMOVNS_GPRv_MEMv", XED_IFORM_CMOVNS_GPRv_MEMv},
{"CMOVNZ_GPRv_GPRv", XED_IFORM_CMOVNZ_GPRv_GPRv},
{"CMOVNZ_GPRv_MEMv", XED_IFORM_CMOVNZ_GPRv_MEMv},
{"CMOVO_GPRv_GPRv", XED_IFORM_CMOVO_GPRv_GPRv},
{"CMOVO_GPRv_MEMv", XED_IFORM_CMOVO_GPRv_MEMv},
{"CMOVP_GPRv_GPRv", XED_IFORM_CMOVP_GPRv_GPRv},
{"CMOVP_GPRv_MEMv", XED_IFORM_CMOVP_GPRv_MEMv},
{"CMOVS_GPRv_GPRv", XED_IFORM_CMOVS_GPRv_GPRv},
{"CMOVS_GPRv_MEMv", XED_IFORM_CMOVS_GPRv_MEMv},
{"CMOVZ_GPRv_GPRv", XED_IFORM_CMOVZ_GPRv_GPRv},
{"CMOVZ_GPRv_MEMv", XED_IFORM_CMOVZ_GPRv_MEMv},
{"CMP_AL_IMMb", XED_IFORM_CMP_AL_IMMb},
{"CMP_GPR8_GPR8_38", XED_IFORM_CMP_GPR8_GPR8_38},
{"CMP_GPR8_GPR8_3A", XED_IFORM_CMP_GPR8_GPR8_3A},
{"CMP_GPR8_IMMb_80r7", XED_IFORM_CMP_GPR8_IMMb_80r7},
{"CMP_GPR8_IMMb_82r7", XED_IFORM_CMP_GPR8_IMMb_82r7},
{"CMP_GPR8_MEMb", XED_IFORM_CMP_GPR8_MEMb},
{"CMP_GPRv_GPRv_39", XED_IFORM_CMP_GPRv_GPRv_39},
{"CMP_GPRv_GPRv_3B", XED_IFORM_CMP_GPRv_GPRv_3B},
{"CMP_GPRv_IMMb", XED_IFORM_CMP_GPRv_IMMb},
{"CMP_GPRv_IMMz", XED_IFORM_CMP_GPRv_IMMz},
{"CMP_GPRv_MEMv", XED_IFORM_CMP_GPRv_MEMv},
{"CMP_MEMb_GPR8", XED_IFORM_CMP_MEMb_GPR8},
{"CMP_MEMb_IMMb_80r7", XED_IFORM_CMP_MEMb_IMMb_80r7},
{"CMP_MEMb_IMMb_82r7", XED_IFORM_CMP_MEMb_IMMb_82r7},
{"CMP_MEMv_GPRv", XED_IFORM_CMP_MEMv_GPRv},
{"CMP_MEMv_IMMb", XED_IFORM_CMP_MEMv_IMMb},
{"CMP_MEMv_IMMz", XED_IFORM_CMP_MEMv_IMMz},
{"CMP_OrAX_IMMz", XED_IFORM_CMP_OrAX_IMMz},
{"CMPPD_XMMpd_MEMpd_IMMb", XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb},
{"CMPPD_XMMpd_XMMpd_IMMb", XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb},
{"CMPPS_XMMps_MEMps_IMMb", XED_IFORM_CMPPS_XMMps_MEMps_IMMb},
{"CMPPS_XMMps_XMMps_IMMb", XED_IFORM_CMPPS_XMMps_XMMps_IMMb},
{"CMPSB", XED_IFORM_CMPSB},
{"CMPSD", XED_IFORM_CMPSD},
{"CMPSD_XMM_XMMsd_MEMsd_IMMb", XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb},
{"CMPSD_XMM_XMMsd_XMMsd_IMMb", XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb},
{"CMPSQ", XED_IFORM_CMPSQ},
{"CMPSS_XMMss_MEMss_IMMb", XED_IFORM_CMPSS_XMMss_MEMss_IMMb},
{"CMPSS_XMMss_XMMss_IMMb", XED_IFORM_CMPSS_XMMss_XMMss_IMMb},
{"CMPSW", XED_IFORM_CMPSW},
{"CMPXCHG_GPR8_GPR8", XED_IFORM_CMPXCHG_GPR8_GPR8},
{"CMPXCHG_GPRv_GPRv", XED_IFORM_CMPXCHG_GPRv_GPRv},
{"CMPXCHG_MEMb_GPR8", XED_IFORM_CMPXCHG_MEMb_GPR8},
{"CMPXCHG_MEMv_GPRv", XED_IFORM_CMPXCHG_MEMv_GPRv},
{"CMPXCHG16B_MEMdq", XED_IFORM_CMPXCHG16B_MEMdq},
{"CMPXCHG16B_LOCK_MEMdq", XED_IFORM_CMPXCHG16B_LOCK_MEMdq},
{"CMPXCHG8B_MEMq", XED_IFORM_CMPXCHG8B_MEMq},
{"CMPXCHG8B_LOCK_MEMq", XED_IFORM_CMPXCHG8B_LOCK_MEMq},
{"CMPXCHG_LOCK_MEMb_GPR8", XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8},
{"CMPXCHG_LOCK_MEMv_GPRv", XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv},
{"COMISD_XMMsd_MEMsd", XED_IFORM_COMISD_XMMsd_MEMsd},
{"COMISD_XMMsd_XMMsd", XED_IFORM_COMISD_XMMsd_XMMsd},
{"COMISS_XMMss_MEMss", XED_IFORM_COMISS_XMMss_MEMss},
{"COMISS_XMMss_XMMss", XED_IFORM_COMISS_XMMss_XMMss},
{"CPUID", XED_IFORM_CPUID},
{"CQO", XED_IFORM_CQO},
{"CRC32_GPRyy_GPR8b", XED_IFORM_CRC32_GPRyy_GPR8b},
{"CRC32_GPRyy_GPRv", XED_IFORM_CRC32_GPRyy_GPRv},
{"CRC32_GPRyy_MEMb", XED_IFORM_CRC32_GPRyy_MEMb},
{"CRC32_GPRyy_MEMv", XED_IFORM_CRC32_GPRyy_MEMv},
{"CVTDQ2PD_XMMpd_MEMq", XED_IFORM_CVTDQ2PD_XMMpd_MEMq},
{"CVTDQ2PD_XMMpd_XMMq", XED_IFORM_CVTDQ2PD_XMMpd_XMMq},
{"CVTDQ2PS_XMMps_MEMdq", XED_IFORM_CVTDQ2PS_XMMps_MEMdq},
{"CVTDQ2PS_XMMps_XMMdq", XED_IFORM_CVTDQ2PS_XMMps_XMMdq},
{"CVTPD2DQ_XMMdq_MEMpd", XED_IFORM_CVTPD2DQ_XMMdq_MEMpd},
{"CVTPD2DQ_XMMdq_XMMpd", XED_IFORM_CVTPD2DQ_XMMdq_XMMpd},
{"CVTPD2PI_MMXq_MEMpd", XED_IFORM_CVTPD2PI_MMXq_MEMpd},
{"CVTPD2PI_MMXq_XMMpd", XED_IFORM_CVTPD2PI_MMXq_XMMpd},
{"CVTPD2PS_XMMps_MEMpd", XED_IFORM_CVTPD2PS_XMMps_MEMpd},
{"CVTPD2PS_XMMps_XMMpd", XED_IFORM_CVTPD2PS_XMMps_XMMpd},
{"CVTPI2PD_XMMpd_MEMq", XED_IFORM_CVTPI2PD_XMMpd_MEMq},
{"CVTPI2PD_XMMpd_MMXq", XED_IFORM_CVTPI2PD_XMMpd_MMXq},
{"CVTPI2PS_XMMq_MEMq", XED_IFORM_CVTPI2PS_XMMq_MEMq},
{"CVTPI2PS_XMMq_MMXq", XED_IFORM_CVTPI2PS_XMMq_MMXq},
{"CVTPS2DQ_XMMdq_MEMps", XED_IFORM_CVTPS2DQ_XMMdq_MEMps},
{"CVTPS2DQ_XMMdq_XMMps", XED_IFORM_CVTPS2DQ_XMMdq_XMMps},
{"CVTPS2PD_XMMpd_MEMq", XED_IFORM_CVTPS2PD_XMMpd_MEMq},
{"CVTPS2PD_XMMpd_XMMq", XED_IFORM_CVTPS2PD_XMMpd_XMMq},
{"CVTPS2PI_MMXq_MEMq", XED_IFORM_CVTPS2PI_MMXq_MEMq},
{"CVTPS2PI_MMXq_XMMq", XED_IFORM_CVTPS2PI_MMXq_XMMq},
{"CVTSD2SI_GPR32d_MEMsd", XED_IFORM_CVTSD2SI_GPR32d_MEMsd},
{"CVTSD2SI_GPR32d_XMMsd", XED_IFORM_CVTSD2SI_GPR32d_XMMsd},
{"CVTSD2SI_GPR64q_MEMsd", XED_IFORM_CVTSD2SI_GPR64q_MEMsd},
{"CVTSD2SI_GPR64q_XMMsd", XED_IFORM_CVTSD2SI_GPR64q_XMMsd},
{"CVTSD2SS_XMMss_MEMsd", XED_IFORM_CVTSD2SS_XMMss_MEMsd},
{"CVTSD2SS_XMMss_XMMsd", XED_IFORM_CVTSD2SS_XMMss_XMMsd},
{"CVTSI2SD_XMMsd_GPR32d", XED_IFORM_CVTSI2SD_XMMsd_GPR32d},
{"CVTSI2SD_XMMsd_GPR64q", XED_IFORM_CVTSI2SD_XMMsd_GPR64q},
{"CVTSI2SD_XMMsd_MEMd", XED_IFORM_CVTSI2SD_XMMsd_MEMd},
{"CVTSI2SD_XMMsd_MEMq", XED_IFORM_CVTSI2SD_XMMsd_MEMq},
{"CVTSI2SS_XMMss_GPR32d", XED_IFORM_CVTSI2SS_XMMss_GPR32d},
{"CVTSI2SS_XMMss_GPR64q", XED_IFORM_CVTSI2SS_XMMss_GPR64q},
{"CVTSI2SS_XMMss_MEMd", XED_IFORM_CVTSI2SS_XMMss_MEMd},
{"CVTSI2SS_XMMss_MEMq", XED_IFORM_CVTSI2SS_XMMss_MEMq},
{"CVTSS2SD_XMMsd_MEMss", XED_IFORM_CVTSS2SD_XMMsd_MEMss},
{"CVTSS2SD_XMMsd_XMMss", XED_IFORM_CVTSS2SD_XMMsd_XMMss},
{"CVTSS2SI_GPR32d_MEMss", XED_IFORM_CVTSS2SI_GPR32d_MEMss},
{"CVTSS2SI_GPR32d_XMMss", XED_IFORM_CVTSS2SI_GPR32d_XMMss},
{"CVTSS2SI_GPR64q_MEMss", XED_IFORM_CVTSS2SI_GPR64q_MEMss},
{"CVTSS2SI_GPR64q_XMMss", XED_IFORM_CVTSS2SI_GPR64q_XMMss},
{"CVTTPD2DQ_XMMdq_MEMpd", XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd},
{"CVTTPD2DQ_XMMdq_XMMpd", XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd},
{"CVTTPD2PI_MMXq_MEMpd", XED_IFORM_CVTTPD2PI_MMXq_MEMpd},
{"CVTTPD2PI_MMXq_XMMpd", XED_IFORM_CVTTPD2PI_MMXq_XMMpd},
{"CVTTPS2DQ_XMMdq_MEMps", XED_IFORM_CVTTPS2DQ_XMMdq_MEMps},
{"CVTTPS2DQ_XMMdq_XMMps", XED_IFORM_CVTTPS2DQ_XMMdq_XMMps},
{"CVTTPS2PI_MMXq_MEMq", XED_IFORM_CVTTPS2PI_MMXq_MEMq},
{"CVTTPS2PI_MMXq_XMMq", XED_IFORM_CVTTPS2PI_MMXq_XMMq},
{"CVTTSD2SI_GPR32d_MEMsd", XED_IFORM_CVTTSD2SI_GPR32d_MEMsd},
{"CVTTSD2SI_GPR32d_XMMsd", XED_IFORM_CVTTSD2SI_GPR32d_XMMsd},
{"CVTTSD2SI_GPR64q_MEMsd", XED_IFORM_CVTTSD2SI_GPR64q_MEMsd},
{"CVTTSD2SI_GPR64q_XMMsd", XED_IFORM_CVTTSD2SI_GPR64q_XMMsd},
{"CVTTSS2SI_GPR32d_MEMss", XED_IFORM_CVTTSS2SI_GPR32d_MEMss},
{"CVTTSS2SI_GPR32d_XMMss", XED_IFORM_CVTTSS2SI_GPR32d_XMMss},
{"CVTTSS2SI_GPR64q_MEMss", XED_IFORM_CVTTSS2SI_GPR64q_MEMss},
{"CVTTSS2SI_GPR64q_XMMss", XED_IFORM_CVTTSS2SI_GPR64q_XMMss},
{"CWD", XED_IFORM_CWD},
{"CWDE", XED_IFORM_CWDE},
{"DAA", XED_IFORM_DAA},
{"DAS", XED_IFORM_DAS},
{"DEC_GPR8", XED_IFORM_DEC_GPR8},
{"DEC_GPRv_48", XED_IFORM_DEC_GPRv_48},
{"DEC_GPRv_FFr1", XED_IFORM_DEC_GPRv_FFr1},
{"DEC_MEMb", XED_IFORM_DEC_MEMb},
{"DEC_MEMv", XED_IFORM_DEC_MEMv},
{"DEC_LOCK_MEMb", XED_IFORM_DEC_LOCK_MEMb},
{"DEC_LOCK_MEMv", XED_IFORM_DEC_LOCK_MEMv},
{"DIV_GPR8", XED_IFORM_DIV_GPR8},
{"DIV_GPRv", XED_IFORM_DIV_GPRv},
{"DIV_MEMb", XED_IFORM_DIV_MEMb},
{"DIV_MEMv", XED_IFORM_DIV_MEMv},
{"DIVPD_XMMpd_MEMpd", XED_IFORM_DIVPD_XMMpd_MEMpd},
{"DIVPD_XMMpd_XMMpd", XED_IFORM_DIVPD_XMMpd_XMMpd},
{"DIVPS_XMMps_MEMps", XED_IFORM_DIVPS_XMMps_MEMps},
{"DIVPS_XMMps_XMMps", XED_IFORM_DIVPS_XMMps_XMMps},
{"DIVSD_XMMsd_MEMsd", XED_IFORM_DIVSD_XMMsd_MEMsd},
{"DIVSD_XMMsd_XMMsd", XED_IFORM_DIVSD_XMMsd_XMMsd},
{"DIVSS_XMMss_MEMss", XED_IFORM_DIVSS_XMMss_MEMss},
{"DIVSS_XMMss_XMMss", XED_IFORM_DIVSS_XMMss_XMMss},
{"DPPD_XMMdq_MEMdq_IMMb", XED_IFORM_DPPD_XMMdq_MEMdq_IMMb},
{"DPPD_XMMdq_XMMdq_IMMb", XED_IFORM_DPPD_XMMdq_XMMdq_IMMb},
{"DPPS_XMMdq_MEMdq_IMMb", XED_IFORM_DPPS_XMMdq_MEMdq_IMMb},
{"DPPS_XMMdq_XMMdq_IMMb", XED_IFORM_DPPS_XMMdq_XMMdq_IMMb},
{"EMMS", XED_IFORM_EMMS},
{"ENCLS", XED_IFORM_ENCLS},
{"ENCLU", XED_IFORM_ENCLU},
{"ENCLV", XED_IFORM_ENCLV},
{"ENCODEKEY128_GPR32u8_GPR32u8", XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8},
{"ENCODEKEY256_GPR32u8_GPR32u8", XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8},
{"ENDBR32", XED_IFORM_ENDBR32},
{"ENDBR64", XED_IFORM_ENDBR64},
{"ENQCMD_GPRa_MEMu32", XED_IFORM_ENQCMD_GPRa_MEMu32},
{"ENQCMDS_GPRa_MEMu32", XED_IFORM_ENQCMDS_GPRa_MEMu32},
{"ENTER_IMMw_IMMb", XED_IFORM_ENTER_IMMw_IMMb},
{"EXTRACTPS_GPR32d_XMMdq_IMMb", XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb},
{"EXTRACTPS_MEMd_XMMps_IMMb", XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb},
{"EXTRQ_XMMq_IMMb_IMMb", XED_IFORM_EXTRQ_XMMq_IMMb_IMMb},
{"EXTRQ_XMMq_XMMdq", XED_IFORM_EXTRQ_XMMq_XMMdq},
{"F2XM1", XED_IFORM_F2XM1},
{"FABS", XED_IFORM_FABS},
{"FADD_ST0_MEMm64real", XED_IFORM_FADD_ST0_MEMm64real},
{"FADD_ST0_MEMmem32real", XED_IFORM_FADD_ST0_MEMmem32real},
{"FADD_ST0_X87", XED_IFORM_FADD_ST0_X87},
{"FADD_X87_ST0", XED_IFORM_FADD_X87_ST0},
{"FADDP_X87_ST0", XED_IFORM_FADDP_X87_ST0},
{"FBLD_ST0_MEMmem80dec", XED_IFORM_FBLD_ST0_MEMmem80dec},
{"FBSTP_MEMmem80dec_ST0", XED_IFORM_FBSTP_MEMmem80dec_ST0},
{"FCHS", XED_IFORM_FCHS},
{"FCMOVB_ST0_X87", XED_IFORM_FCMOVB_ST0_X87},
{"FCMOVBE_ST0_X87", XED_IFORM_FCMOVBE_ST0_X87},
{"FCMOVE_ST0_X87", XED_IFORM_FCMOVE_ST0_X87},
{"FCMOVNB_ST0_X87", XED_IFORM_FCMOVNB_ST0_X87},
{"FCMOVNBE_ST0_X87", XED_IFORM_FCMOVNBE_ST0_X87},
{"FCMOVNE_ST0_X87", XED_IFORM_FCMOVNE_ST0_X87},
{"FCMOVNU_ST0_X87", XED_IFORM_FCMOVNU_ST0_X87},
{"FCMOVU_ST0_X87", XED_IFORM_FCMOVU_ST0_X87},
{"FCOM_ST0_MEMm64real", XED_IFORM_FCOM_ST0_MEMm64real},
{"FCOM_ST0_MEMmem32real", XED_IFORM_FCOM_ST0_MEMmem32real},
{"FCOM_ST0_X87", XED_IFORM_FCOM_ST0_X87},
{"FCOM_ST0_X87_DCD0", XED_IFORM_FCOM_ST0_X87_DCD0},
{"FCOMI_ST0_X87", XED_IFORM_FCOMI_ST0_X87},
{"FCOMIP_ST0_X87", XED_IFORM_FCOMIP_ST0_X87},
{"FCOMP_ST0_MEMm64real", XED_IFORM_FCOMP_ST0_MEMm64real},
{"FCOMP_ST0_MEMmem32real", XED_IFORM_FCOMP_ST0_MEMmem32real},
{"FCOMP_ST0_X87", XED_IFORM_FCOMP_ST0_X87},
{"FCOMP_ST0_X87_DCD1", XED_IFORM_FCOMP_ST0_X87_DCD1},
{"FCOMP_ST0_X87_DED0", XED_IFORM_FCOMP_ST0_X87_DED0},
{"FCOMPP", XED_IFORM_FCOMPP},
{"FCOS", XED_IFORM_FCOS},
{"FDECSTP", XED_IFORM_FDECSTP},
{"FDISI8087_NOP", XED_IFORM_FDISI8087_NOP},
{"FDIV_ST0_MEMm64real", XED_IFORM_FDIV_ST0_MEMm64real},
{"FDIV_ST0_MEMmem32real", XED_IFORM_FDIV_ST0_MEMmem32real},
{"FDIV_ST0_X87", XED_IFORM_FDIV_ST0_X87},
{"FDIV_X87_ST0", XED_IFORM_FDIV_X87_ST0},
{"FDIVP_X87_ST0", XED_IFORM_FDIVP_X87_ST0},
{"FDIVR_ST0_MEMm64real", XED_IFORM_FDIVR_ST0_MEMm64real},
{"FDIVR_ST0_MEMmem32real", XED_IFORM_FDIVR_ST0_MEMmem32real},
{"FDIVR_ST0_X87", XED_IFORM_FDIVR_ST0_X87},
{"FDIVR_X87_ST0", XED_IFORM_FDIVR_X87_ST0},
{"FDIVRP_X87_ST0", XED_IFORM_FDIVRP_X87_ST0},
{"FEMMS", XED_IFORM_FEMMS},
{"FENI8087_NOP", XED_IFORM_FENI8087_NOP},
{"FFREE_X87", XED_IFORM_FFREE_X87},
{"FFREEP_X87", XED_IFORM_FFREEP_X87},
{"FIADD_ST0_MEMmem16int", XED_IFORM_FIADD_ST0_MEMmem16int},
{"FIADD_ST0_MEMmem32int", XED_IFORM_FIADD_ST0_MEMmem32int},
{"FICOM_ST0_MEMmem16int", XED_IFORM_FICOM_ST0_MEMmem16int},
{"FICOM_ST0_MEMmem32int", XED_IFORM_FICOM_ST0_MEMmem32int},
{"FICOMP_ST0_MEMmem16int", XED_IFORM_FICOMP_ST0_MEMmem16int},
{"FICOMP_ST0_MEMmem32int", XED_IFORM_FICOMP_ST0_MEMmem32int},
{"FIDIV_ST0_MEMmem16int", XED_IFORM_FIDIV_ST0_MEMmem16int},
{"FIDIV_ST0_MEMmem32int", XED_IFORM_FIDIV_ST0_MEMmem32int},
{"FIDIVR_ST0_MEMmem16int", XED_IFORM_FIDIVR_ST0_MEMmem16int},
{"FIDIVR_ST0_MEMmem32int", XED_IFORM_FIDIVR_ST0_MEMmem32int},
{"FILD_ST0_MEMm64int", XED_IFORM_FILD_ST0_MEMm64int},
{"FILD_ST0_MEMmem16int", XED_IFORM_FILD_ST0_MEMmem16int},
{"FILD_ST0_MEMmem32int", XED_IFORM_FILD_ST0_MEMmem32int},
{"FIMUL_ST0_MEMmem16int", XED_IFORM_FIMUL_ST0_MEMmem16int},
{"FIMUL_ST0_MEMmem32int", XED_IFORM_FIMUL_ST0_MEMmem32int},
{"FINCSTP", XED_IFORM_FINCSTP},
{"FIST_MEMmem16int_ST0", XED_IFORM_FIST_MEMmem16int_ST0},
{"FIST_MEMmem32int_ST0", XED_IFORM_FIST_MEMmem32int_ST0},
{"FISTP_MEMm64int_ST0", XED_IFORM_FISTP_MEMm64int_ST0},
{"FISTP_MEMmem16int_ST0", XED_IFORM_FISTP_MEMmem16int_ST0},
{"FISTP_MEMmem32int_ST0", XED_IFORM_FISTP_MEMmem32int_ST0},
{"FISTTP_MEMm64int_ST0", XED_IFORM_FISTTP_MEMm64int_ST0},
{"FISTTP_MEMmem16int_ST0", XED_IFORM_FISTTP_MEMmem16int_ST0},
{"FISTTP_MEMmem32int_ST0", XED_IFORM_FISTTP_MEMmem32int_ST0},
{"FISUB_ST0_MEMmem16int", XED_IFORM_FISUB_ST0_MEMmem16int},
{"FISUB_ST0_MEMmem32int", XED_IFORM_FISUB_ST0_MEMmem32int},
{"FISUBR_ST0_MEMmem16int", XED_IFORM_FISUBR_ST0_MEMmem16int},
{"FISUBR_ST0_MEMmem32int", XED_IFORM_FISUBR_ST0_MEMmem32int},
{"FLD_ST0_MEMm64real", XED_IFORM_FLD_ST0_MEMm64real},
{"FLD_ST0_MEMmem32real", XED_IFORM_FLD_ST0_MEMmem32real},
{"FLD_ST0_MEMmem80real", XED_IFORM_FLD_ST0_MEMmem80real},
{"FLD_ST0_X87", XED_IFORM_FLD_ST0_X87},
{"FLD1", XED_IFORM_FLD1},
{"FLDCW_MEMmem16", XED_IFORM_FLDCW_MEMmem16},
{"FLDENV_MEMmem14", XED_IFORM_FLDENV_MEMmem14},
{"FLDENV_MEMmem28", XED_IFORM_FLDENV_MEMmem28},
{"FLDL2E", XED_IFORM_FLDL2E},
{"FLDL2T", XED_IFORM_FLDL2T},
{"FLDLG2", XED_IFORM_FLDLG2},
{"FLDLN2", XED_IFORM_FLDLN2},
{"FLDPI", XED_IFORM_FLDPI},
{"FLDZ", XED_IFORM_FLDZ},
{"FMUL_ST0_MEMm64real", XED_IFORM_FMUL_ST0_MEMm64real},
{"FMUL_ST0_MEMmem32real", XED_IFORM_FMUL_ST0_MEMmem32real},
{"FMUL_ST0_X87", XED_IFORM_FMUL_ST0_X87},
{"FMUL_X87_ST0", XED_IFORM_FMUL_X87_ST0},
{"FMULP_X87_ST0", XED_IFORM_FMULP_X87_ST0},
{"FNCLEX", XED_IFORM_FNCLEX},
{"FNINIT", XED_IFORM_FNINIT},
{"FNOP", XED_IFORM_FNOP},
{"FNSAVE_MEMmem108", XED_IFORM_FNSAVE_MEMmem108},
{"FNSAVE_MEMmem94", XED_IFORM_FNSAVE_MEMmem94},
{"FNSTCW_MEMmem16", XED_IFORM_FNSTCW_MEMmem16},
{"FNSTENV_MEMmem14", XED_IFORM_FNSTENV_MEMmem14},
{"FNSTENV_MEMmem28", XED_IFORM_FNSTENV_MEMmem28},
{"FNSTSW_AX", XED_IFORM_FNSTSW_AX},
{"FNSTSW_MEMmem16", XED_IFORM_FNSTSW_MEMmem16},
{"FPATAN", XED_IFORM_FPATAN},
{"FPREM", XED_IFORM_FPREM},
{"FPREM1", XED_IFORM_FPREM1},
{"FPTAN", XED_IFORM_FPTAN},
{"FRNDINT", XED_IFORM_FRNDINT},
{"FRSTOR_MEMmem108", XED_IFORM_FRSTOR_MEMmem108},
{"FRSTOR_MEMmem94", XED_IFORM_FRSTOR_MEMmem94},
{"FSCALE", XED_IFORM_FSCALE},
{"FSETPM287_NOP", XED_IFORM_FSETPM287_NOP},
{"FSIN", XED_IFORM_FSIN},
{"FSINCOS", XED_IFORM_FSINCOS},
{"FSQRT", XED_IFORM_FSQRT},
{"FST_MEMm64real_ST0", XED_IFORM_FST_MEMm64real_ST0},
{"FST_MEMmem32real_ST0", XED_IFORM_FST_MEMmem32real_ST0},
{"FST_X87_ST0", XED_IFORM_FST_X87_ST0},
{"FSTP_MEMm64real_ST0", XED_IFORM_FSTP_MEMm64real_ST0},
{"FSTP_MEMmem32real_ST0", XED_IFORM_FSTP_MEMmem32real_ST0},
{"FSTP_MEMmem80real_ST0", XED_IFORM_FSTP_MEMmem80real_ST0},
{"FSTP_X87_ST0", XED_IFORM_FSTP_X87_ST0},
{"FSTP_X87_ST0_DFD0", XED_IFORM_FSTP_X87_ST0_DFD0},
{"FSTP_X87_ST0_DFD1", XED_IFORM_FSTP_X87_ST0_DFD1},
{"FSTPNCE_X87_ST0", XED_IFORM_FSTPNCE_X87_ST0},
{"FSUB_ST0_MEMm64real", XED_IFORM_FSUB_ST0_MEMm64real},
{"FSUB_ST0_MEMmem32real", XED_IFORM_FSUB_ST0_MEMmem32real},
{"FSUB_ST0_X87", XED_IFORM_FSUB_ST0_X87},
{"FSUB_X87_ST0", XED_IFORM_FSUB_X87_ST0},
{"FSUBP_X87_ST0", XED_IFORM_FSUBP_X87_ST0},
{"FSUBR_ST0_MEMm64real", XED_IFORM_FSUBR_ST0_MEMm64real},
{"FSUBR_ST0_MEMmem32real", XED_IFORM_FSUBR_ST0_MEMmem32real},
{"FSUBR_ST0_X87", XED_IFORM_FSUBR_ST0_X87},
{"FSUBR_X87_ST0", XED_IFORM_FSUBR_X87_ST0},
{"FSUBRP_X87_ST0", XED_IFORM_FSUBRP_X87_ST0},
{"FTST", XED_IFORM_FTST},
{"FUCOM_ST0_X87", XED_IFORM_FUCOM_ST0_X87},
{"FUCOMI_ST0_X87", XED_IFORM_FUCOMI_ST0_X87},
{"FUCOMIP_ST0_X87", XED_IFORM_FUCOMIP_ST0_X87},
{"FUCOMP_ST0_X87", XED_IFORM_FUCOMP_ST0_X87},
{"FUCOMPP", XED_IFORM_FUCOMPP},
{"FWAIT", XED_IFORM_FWAIT},
{"FXAM", XED_IFORM_FXAM},
{"FXCH_ST0_X87", XED_IFORM_FXCH_ST0_X87},
{"FXCH_ST0_X87_DDC1", XED_IFORM_FXCH_ST0_X87_DDC1},
{"FXCH_ST0_X87_DFC1", XED_IFORM_FXCH_ST0_X87_DFC1},
{"FXRSTOR_MEMmfpxenv", XED_IFORM_FXRSTOR_MEMmfpxenv},
{"FXRSTOR64_MEMmfpxenv", XED_IFORM_FXRSTOR64_MEMmfpxenv},
{"FXSAVE_MEMmfpxenv", XED_IFORM_FXSAVE_MEMmfpxenv},
{"FXSAVE64_MEMmfpxenv", XED_IFORM_FXSAVE64_MEMmfpxenv},
{"FXTRACT", XED_IFORM_FXTRACT},
{"FYL2X", XED_IFORM_FYL2X},
{"FYL2XP1", XED_IFORM_FYL2XP1},
{"GETSEC", XED_IFORM_GETSEC},
{"GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8", XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8},
{"GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8", XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8},
{"GF2P8AFFINEQB_XMMu8_MEMu64_IMM8", XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8},
{"GF2P8AFFINEQB_XMMu8_XMMu64_IMM8", XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8},
{"GF2P8MULB_XMMu8_MEMu8", XED_IFORM_GF2P8MULB_XMMu8_MEMu8},
{"GF2P8MULB_XMMu8_XMMu8", XED_IFORM_GF2P8MULB_XMMu8_XMMu8},
{"HADDPD_XMMpd_MEMpd", XED_IFORM_HADDPD_XMMpd_MEMpd},
{"HADDPD_XMMpd_XMMpd", XED_IFORM_HADDPD_XMMpd_XMMpd},
{"HADDPS_XMMps_MEMps", XED_IFORM_HADDPS_XMMps_MEMps},
{"HADDPS_XMMps_XMMps", XED_IFORM_HADDPS_XMMps_XMMps},
{"HLT", XED_IFORM_HLT},
{"HRESET_IMM8", XED_IFORM_HRESET_IMM8},
{"HSUBPD_XMMpd_MEMpd", XED_IFORM_HSUBPD_XMMpd_MEMpd},
{"HSUBPD_XMMpd_XMMpd", XED_IFORM_HSUBPD_XMMpd_XMMpd},
{"HSUBPS_XMMps_MEMps", XED_IFORM_HSUBPS_XMMps_MEMps},
{"HSUBPS_XMMps_XMMps", XED_IFORM_HSUBPS_XMMps_XMMps},
{"IDIV_GPR8", XED_IFORM_IDIV_GPR8},
{"IDIV_GPRv", XED_IFORM_IDIV_GPRv},
{"IDIV_MEMb", XED_IFORM_IDIV_MEMb},
{"IDIV_MEMv", XED_IFORM_IDIV_MEMv},
{"IMUL_GPR8", XED_IFORM_IMUL_GPR8},
{"IMUL_GPRv", XED_IFORM_IMUL_GPRv},
{"IMUL_GPRv_GPRv", XED_IFORM_IMUL_GPRv_GPRv},
{"IMUL_GPRv_GPRv_IMMb", XED_IFORM_IMUL_GPRv_GPRv_IMMb},
{"IMUL_GPRv_GPRv_IMMz", XED_IFORM_IMUL_GPRv_GPRv_IMMz},
{"IMUL_GPRv_MEMv", XED_IFORM_IMUL_GPRv_MEMv},
{"IMUL_GPRv_MEMv_IMMb", XED_IFORM_IMUL_GPRv_MEMv_IMMb},
{"IMUL_GPRv_MEMv_IMMz", XED_IFORM_IMUL_GPRv_MEMv_IMMz},
{"IMUL_MEMb", XED_IFORM_IMUL_MEMb},
{"IMUL_MEMv", XED_IFORM_IMUL_MEMv},
{"IN_AL_DX", XED_IFORM_IN_AL_DX},
{"IN_AL_IMMb", XED_IFORM_IN_AL_IMMb},
{"IN_OeAX_DX", XED_IFORM_IN_OeAX_DX},
{"IN_OeAX_IMMb", XED_IFORM_IN_OeAX_IMMb},
{"INC_GPR8", XED_IFORM_INC_GPR8},
{"INC_GPRv_40", XED_IFORM_INC_GPRv_40},
{"INC_GPRv_FFr0", XED_IFORM_INC_GPRv_FFr0},
{"INC_MEMb", XED_IFORM_INC_MEMb},
{"INC_MEMv", XED_IFORM_INC_MEMv},
{"INCSSPD_GPR32u8", XED_IFORM_INCSSPD_GPR32u8},
{"INCSSPQ_GPR64u8", XED_IFORM_INCSSPQ_GPR64u8},
{"INC_LOCK_MEMb", XED_IFORM_INC_LOCK_MEMb},
{"INC_LOCK_MEMv", XED_IFORM_INC_LOCK_MEMv},
{"INSB", XED_IFORM_INSB},
{"INSD", XED_IFORM_INSD},
{"INSERTPS_XMMps_MEMd_IMMb", XED_IFORM_INSERTPS_XMMps_MEMd_IMMb},
{"INSERTPS_XMMps_XMMps_IMMb", XED_IFORM_INSERTPS_XMMps_XMMps_IMMb},
{"INSERTQ_XMMq_XMMdq", XED_IFORM_INSERTQ_XMMq_XMMdq},
{"INSERTQ_XMMq_XMMq_IMMb_IMMb", XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb},
{"INSW", XED_IFORM_INSW},
{"INT_IMMb", XED_IFORM_INT_IMMb},
{"INT1", XED_IFORM_INT1},
{"INT3", XED_IFORM_INT3},
{"INTO", XED_IFORM_INTO},
{"INVD", XED_IFORM_INVD},
{"INVEPT_GPR32_MEMdq", XED_IFORM_INVEPT_GPR32_MEMdq},
{"INVEPT_GPR64_MEMdq", XED_IFORM_INVEPT_GPR64_MEMdq},
{"INVLPG_MEMb", XED_IFORM_INVLPG_MEMb},
{"INVLPGA_ArAX_ECX", XED_IFORM_INVLPGA_ArAX_ECX},
{"INVLPGB_EAX_EDX_ECX", XED_IFORM_INVLPGB_EAX_EDX_ECX},
{"INVLPGB_RAX_EDX_ECX", XED_IFORM_INVLPGB_RAX_EDX_ECX},
{"INVPCID_GPR32_MEMdq", XED_IFORM_INVPCID_GPR32_MEMdq},
{"INVPCID_GPR64_MEMdq", XED_IFORM_INVPCID_GPR64_MEMdq},
{"INVVPID_GPR32_MEMdq", XED_IFORM_INVVPID_GPR32_MEMdq},
{"INVVPID_GPR64_MEMdq", XED_IFORM_INVVPID_GPR64_MEMdq},
{"IRET", XED_IFORM_IRET},
{"IRETD", XED_IFORM_IRETD},
{"IRETQ", XED_IFORM_IRETQ},
{"JB_RELBRb", XED_IFORM_JB_RELBRb},
{"JB_RELBRd", XED_IFORM_JB_RELBRd},
{"JB_RELBRz", XED_IFORM_JB_RELBRz},
{"JBE_RELBRb", XED_IFORM_JBE_RELBRb},
{"JBE_RELBRd", XED_IFORM_JBE_RELBRd},
{"JBE_RELBRz", XED_IFORM_JBE_RELBRz},
{"JCXZ_RELBRb", XED_IFORM_JCXZ_RELBRb},
{"JECXZ_RELBRb", XED_IFORM_JECXZ_RELBRb},
{"JL_RELBRb", XED_IFORM_JL_RELBRb},
{"JL_RELBRd", XED_IFORM_JL_RELBRd},
{"JL_RELBRz", XED_IFORM_JL_RELBRz},
{"JLE_RELBRb", XED_IFORM_JLE_RELBRb},
{"JLE_RELBRd", XED_IFORM_JLE_RELBRd},
{"JLE_RELBRz", XED_IFORM_JLE_RELBRz},
{"JMP_GPRv", XED_IFORM_JMP_GPRv},
{"JMP_MEMv", XED_IFORM_JMP_MEMv},
{"JMP_RELBRb", XED_IFORM_JMP_RELBRb},
{"JMP_RELBRd", XED_IFORM_JMP_RELBRd},
{"JMP_RELBRz", XED_IFORM_JMP_RELBRz},
{"JMP_FAR_MEMp2", XED_IFORM_JMP_FAR_MEMp2},
{"JMP_FAR_PTRp_IMMw", XED_IFORM_JMP_FAR_PTRp_IMMw},
{"JNB_RELBRb", XED_IFORM_JNB_RELBRb},
{"JNB_RELBRd", XED_IFORM_JNB_RELBRd},
{"JNB_RELBRz", XED_IFORM_JNB_RELBRz},
{"JNBE_RELBRb", XED_IFORM_JNBE_RELBRb},
{"JNBE_RELBRd", XED_IFORM_JNBE_RELBRd},
{"JNBE_RELBRz", XED_IFORM_JNBE_RELBRz},
{"JNL_RELBRb", XED_IFORM_JNL_RELBRb},
{"JNL_RELBRd", XED_IFORM_JNL_RELBRd},
{"JNL_RELBRz", XED_IFORM_JNL_RELBRz},
{"JNLE_RELBRb", XED_IFORM_JNLE_RELBRb},
{"JNLE_RELBRd", XED_IFORM_JNLE_RELBRd},
{"JNLE_RELBRz", XED_IFORM_JNLE_RELBRz},
{"JNO_RELBRb", XED_IFORM_JNO_RELBRb},
{"JNO_RELBRd", XED_IFORM_JNO_RELBRd},
{"JNO_RELBRz", XED_IFORM_JNO_RELBRz},
{"JNP_RELBRb", XED_IFORM_JNP_RELBRb},
{"JNP_RELBRd", XED_IFORM_JNP_RELBRd},
{"JNP_RELBRz", XED_IFORM_JNP_RELBRz},
{"JNS_RELBRb", XED_IFORM_JNS_RELBRb},
{"JNS_RELBRd", XED_IFORM_JNS_RELBRd},
{"JNS_RELBRz", XED_IFORM_JNS_RELBRz},
{"JNZ_RELBRb", XED_IFORM_JNZ_RELBRb},
{"JNZ_RELBRd", XED_IFORM_JNZ_RELBRd},
{"JNZ_RELBRz", XED_IFORM_JNZ_RELBRz},
{"JO_RELBRb", XED_IFORM_JO_RELBRb},
{"JO_RELBRd", XED_IFORM_JO_RELBRd},
{"JO_RELBRz", XED_IFORM_JO_RELBRz},
{"JP_RELBRb", XED_IFORM_JP_RELBRb},
{"JP_RELBRd", XED_IFORM_JP_RELBRd},
{"JP_RELBRz", XED_IFORM_JP_RELBRz},
{"JRCXZ_RELBRb", XED_IFORM_JRCXZ_RELBRb},
{"JS_RELBRb", XED_IFORM_JS_RELBRb},
{"JS_RELBRd", XED_IFORM_JS_RELBRd},
{"JS_RELBRz", XED_IFORM_JS_RELBRz},
{"JZ_RELBRb", XED_IFORM_JZ_RELBRb},
{"JZ_RELBRd", XED_IFORM_JZ_RELBRd},
{"JZ_RELBRz", XED_IFORM_JZ_RELBRz},
{"KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KMOVB_GPR32u32_MASKmskw_AVX512", XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512},
{"KMOVB_MASKmskw_GPR32u32_AVX512", XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512},
{"KMOVB_MASKmskw_MASKu8_AVX512", XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512},
{"KMOVB_MASKmskw_MEMu8_AVX512", XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512},
{"KMOVB_MEMu8_MASKmskw_AVX512", XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512},
{"KMOVD_GPR32u32_MASKmskw_AVX512", XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512},
{"KMOVD_MASKmskw_GPR32u32_AVX512", XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512},
{"KMOVD_MASKmskw_MASKu32_AVX512", XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512},
{"KMOVD_MASKmskw_MEMu32_AVX512", XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512},
{"KMOVD_MEMu32_MASKmskw_AVX512", XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512},
{"KMOVQ_GPR64u64_MASKmskw_AVX512", XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512},
{"KMOVQ_MASKmskw_GPR64u64_AVX512", XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512},
{"KMOVQ_MASKmskw_MASKu64_AVX512", XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512},
{"KMOVQ_MASKmskw_MEMu64_AVX512", XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512},
{"KMOVQ_MEMu64_MASKmskw_AVX512", XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512},
{"KMOVW_GPR32u32_MASKmskw_AVX512", XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512},
{"KMOVW_MASKmskw_GPR32u32_AVX512", XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512},
{"KMOVW_MASKmskw_MASKu16_AVX512", XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512},
{"KMOVW_MASKmskw_MEMu16_AVX512", XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512},
{"KMOVW_MEMu16_MASKmskw_AVX512", XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512},
{"KNOTB_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512},
{"KNOTD_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512},
{"KNOTQ_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512},
{"KNOTW_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512},
{"KORB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KORD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KORTESTB_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512},
{"KORTESTD_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512},
{"KORTESTQ_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512},
{"KORTESTW_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512},
{"KORW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512},
{"KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512},
{"KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512},
{"KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512},
{"KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512},
{"KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512},
{"KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512},
{"KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512},
{"KTESTB_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512},
{"KTESTD_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512},
{"KTESTQ_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512},
{"KTESTW_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512},
{"KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512},
{"LAHF", XED_IFORM_LAHF},
{"LAR_GPRv_GPRv", XED_IFORM_LAR_GPRv_GPRv},
{"LAR_GPRv_MEMw", XED_IFORM_LAR_GPRv_MEMw},
{"LDDQU_XMMpd_MEMdq", XED_IFORM_LDDQU_XMMpd_MEMdq},
{"LDMXCSR_MEMd", XED_IFORM_LDMXCSR_MEMd},
{"LDS_GPRz_MEMp", XED_IFORM_LDS_GPRz_MEMp},
{"LDTILECFG_MEM", XED_IFORM_LDTILECFG_MEM},
{"LEA_GPRv_AGEN", XED_IFORM_LEA_GPRv_AGEN},
{"LEAVE", XED_IFORM_LEAVE},
{"LES_GPRz_MEMp", XED_IFORM_LES_GPRz_MEMp},
{"LFENCE", XED_IFORM_LFENCE},
{"LFS_GPRv_MEMp2", XED_IFORM_LFS_GPRv_MEMp2},
{"LGDT_MEMs", XED_IFORM_LGDT_MEMs},
{"LGDT_MEMs64", XED_IFORM_LGDT_MEMs64},
{"LGS_GPRv_MEMp2", XED_IFORM_LGS_GPRv_MEMp2},
{"LIDT_MEMs", XED_IFORM_LIDT_MEMs},
{"LIDT_MEMs64", XED_IFORM_LIDT_MEMs64},
{"LLDT_GPR16", XED_IFORM_LLDT_GPR16},
{"LLDT_MEMw", XED_IFORM_LLDT_MEMw},
{"LLWPCB_VGPRyy", XED_IFORM_LLWPCB_VGPRyy},
{"LMSW_GPR16", XED_IFORM_LMSW_GPR16},
{"LMSW_MEMw", XED_IFORM_LMSW_MEMw},
{"LOADIWKEY_XMMu8_XMMu8", XED_IFORM_LOADIWKEY_XMMu8_XMMu8},
{"LODSB", XED_IFORM_LODSB},
{"LODSD", XED_IFORM_LODSD},
{"LODSQ", XED_IFORM_LODSQ},
{"LODSW", XED_IFORM_LODSW},
{"LOOP_RELBRb", XED_IFORM_LOOP_RELBRb},
{"LOOPE_RELBRb", XED_IFORM_LOOPE_RELBRb},
{"LOOPNE_RELBRb", XED_IFORM_LOOPNE_RELBRb},
{"LSL_GPRv_GPRz", XED_IFORM_LSL_GPRv_GPRz},
{"LSL_GPRv_MEMw", XED_IFORM_LSL_GPRv_MEMw},
{"LSS_GPRv_MEMp2", XED_IFORM_LSS_GPRv_MEMp2},
{"LTR_GPR16", XED_IFORM_LTR_GPR16},
{"LTR_MEMw", XED_IFORM_LTR_MEMw},
{"LWPINS_VGPRyy_MEMd_IMMd", XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd},
{"LWPINS_VGPRyy_VGPR32y_IMMd", XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd},
{"LWPVAL_VGPRyy_MEMd_IMMd", XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd},
{"LWPVAL_VGPRyy_VGPR32y_IMMd", XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd},
{"LZCNT_GPRv_GPRv", XED_IFORM_LZCNT_GPRv_GPRv},
{"LZCNT_GPRv_MEMv", XED_IFORM_LZCNT_GPRv_MEMv},
{"MASKMOVDQU_XMMdq_XMMdq", XED_IFORM_MASKMOVDQU_XMMdq_XMMdq},
{"MASKMOVQ_MMXq_MMXq", XED_IFORM_MASKMOVQ_MMXq_MMXq},
{"MAXPD_XMMpd_MEMpd", XED_IFORM_MAXPD_XMMpd_MEMpd},
{"MAXPD_XMMpd_XMMpd", XED_IFORM_MAXPD_XMMpd_XMMpd},
{"MAXPS_XMMps_MEMps", XED_IFORM_MAXPS_XMMps_MEMps},
{"MAXPS_XMMps_XMMps", XED_IFORM_MAXPS_XMMps_XMMps},
{"MAXSD_XMMsd_MEMsd", XED_IFORM_MAXSD_XMMsd_MEMsd},
{"MAXSD_XMMsd_XMMsd", XED_IFORM_MAXSD_XMMsd_XMMsd},
{"MAXSS_XMMss_MEMss", XED_IFORM_MAXSS_XMMss_MEMss},
{"MAXSS_XMMss_XMMss", XED_IFORM_MAXSS_XMMss_XMMss},
{"MCOMMIT", XED_IFORM_MCOMMIT},
{"MFENCE", XED_IFORM_MFENCE},
{"MINPD_XMMpd_MEMpd", XED_IFORM_MINPD_XMMpd_MEMpd},
{"MINPD_XMMpd_XMMpd", XED_IFORM_MINPD_XMMpd_XMMpd},
{"MINPS_XMMps_MEMps", XED_IFORM_MINPS_XMMps_MEMps},
{"MINPS_XMMps_XMMps", XED_IFORM_MINPS_XMMps_XMMps},
{"MINSD_XMMsd_MEMsd", XED_IFORM_MINSD_XMMsd_MEMsd},
{"MINSD_XMMsd_XMMsd", XED_IFORM_MINSD_XMMsd_XMMsd},
{"MINSS_XMMss_MEMss", XED_IFORM_MINSS_XMMss_MEMss},
{"MINSS_XMMss_XMMss", XED_IFORM_MINSS_XMMss_XMMss},
{"MONITOR", XED_IFORM_MONITOR},
{"MONITORX", XED_IFORM_MONITORX},
{"MOV_AL_MEMb", XED_IFORM_MOV_AL_MEMb},
{"MOV_GPR8_GPR8_88", XED_IFORM_MOV_GPR8_GPR8_88},
{"MOV_GPR8_GPR8_8A", XED_IFORM_MOV_GPR8_GPR8_8A},
{"MOV_GPR8_IMMb_B0", XED_IFORM_MOV_GPR8_IMMb_B0},
{"MOV_GPR8_IMMb_C6r0", XED_IFORM_MOV_GPR8_IMMb_C6r0},
{"MOV_GPR8_MEMb", XED_IFORM_MOV_GPR8_MEMb},
{"MOV_GPRv_GPRv_89", XED_IFORM_MOV_GPRv_GPRv_89},
{"MOV_GPRv_GPRv_8B", XED_IFORM_MOV_GPRv_GPRv_8B},
{"MOV_GPRv_IMMv", XED_IFORM_MOV_GPRv_IMMv},
{"MOV_GPRv_IMMz", XED_IFORM_MOV_GPRv_IMMz},
{"MOV_GPRv_MEMv", XED_IFORM_MOV_GPRv_MEMv},
{"MOV_GPRv_SEG", XED_IFORM_MOV_GPRv_SEG},
{"MOV_MEMb_AL", XED_IFORM_MOV_MEMb_AL},
{"MOV_MEMb_GPR8", XED_IFORM_MOV_MEMb_GPR8},
{"MOV_MEMb_IMMb", XED_IFORM_MOV_MEMb_IMMb},
{"MOV_MEMv_GPRv", XED_IFORM_MOV_MEMv_GPRv},
{"MOV_MEMv_IMMz", XED_IFORM_MOV_MEMv_IMMz},
{"MOV_MEMv_OrAX", XED_IFORM_MOV_MEMv_OrAX},
{"MOV_MEMw_SEG", XED_IFORM_MOV_MEMw_SEG},
{"MOV_OrAX_MEMv", XED_IFORM_MOV_OrAX_MEMv},
{"MOV_SEG_GPR16", XED_IFORM_MOV_SEG_GPR16},
{"MOV_SEG_MEMw", XED_IFORM_MOV_SEG_MEMw},
{"MOVAPD_MEMpd_XMMpd", XED_IFORM_MOVAPD_MEMpd_XMMpd},
{"MOVAPD_XMMpd_MEMpd", XED_IFORM_MOVAPD_XMMpd_MEMpd},
{"MOVAPD_XMMpd_XMMpd_0F28", XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28},
{"MOVAPD_XMMpd_XMMpd_0F29", XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29},
{"MOVAPS_MEMps_XMMps", XED_IFORM_MOVAPS_MEMps_XMMps},
{"MOVAPS_XMMps_MEMps", XED_IFORM_MOVAPS_XMMps_MEMps},
{"MOVAPS_XMMps_XMMps_0F28", XED_IFORM_MOVAPS_XMMps_XMMps_0F28},
{"MOVAPS_XMMps_XMMps_0F29", XED_IFORM_MOVAPS_XMMps_XMMps_0F29},
{"MOVBE_GPRv_MEMv", XED_IFORM_MOVBE_GPRv_MEMv},
{"MOVBE_MEMv_GPRv", XED_IFORM_MOVBE_MEMv_GPRv},
{"MOVD_GPR32_MMXd", XED_IFORM_MOVD_GPR32_MMXd},
{"MOVD_GPR32_XMMd", XED_IFORM_MOVD_GPR32_XMMd},
{"MOVD_MEMd_MMXd", XED_IFORM_MOVD_MEMd_MMXd},
{"MOVD_MEMd_XMMd", XED_IFORM_MOVD_MEMd_XMMd},
{"MOVD_MMXq_GPR32", XED_IFORM_MOVD_MMXq_GPR32},
{"MOVD_MMXq_MEMd", XED_IFORM_MOVD_MMXq_MEMd},
{"MOVD_XMMdq_GPR32", XED_IFORM_MOVD_XMMdq_GPR32},
{"MOVD_XMMdq_MEMd", XED_IFORM_MOVD_XMMdq_MEMd},
{"MOVDDUP_XMMdq_MEMq", XED_IFORM_MOVDDUP_XMMdq_MEMq},
{"MOVDDUP_XMMdq_XMMq", XED_IFORM_MOVDDUP_XMMdq_XMMq},
{"MOVDIR64B_GPRa_MEM", XED_IFORM_MOVDIR64B_GPRa_MEM},
{"MOVDIRI_MEMu32_GPR32u32", XED_IFORM_MOVDIRI_MEMu32_GPR32u32},
{"MOVDIRI_MEMu64_GPR64u64", XED_IFORM_MOVDIRI_MEMu64_GPR64u64},
{"MOVDQ2Q_MMXq_XMMq", XED_IFORM_MOVDQ2Q_MMXq_XMMq},
{"MOVDQA_MEMdq_XMMdq", XED_IFORM_MOVDQA_MEMdq_XMMdq},
{"MOVDQA_XMMdq_MEMdq", XED_IFORM_MOVDQA_XMMdq_MEMdq},
{"MOVDQA_XMMdq_XMMdq_0F6F", XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F},
{"MOVDQA_XMMdq_XMMdq_0F7F", XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F},
{"MOVDQU_MEMdq_XMMdq", XED_IFORM_MOVDQU_MEMdq_XMMdq},
{"MOVDQU_XMMdq_MEMdq", XED_IFORM_MOVDQU_XMMdq_MEMdq},
{"MOVDQU_XMMdq_XMMdq_0F6F", XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F},
{"MOVDQU_XMMdq_XMMdq_0F7F", XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F},
{"MOVHLPS_XMMq_XMMq", XED_IFORM_MOVHLPS_XMMq_XMMq},
{"MOVHPD_MEMq_XMMsd", XED_IFORM_MOVHPD_MEMq_XMMsd},
{"MOVHPD_XMMsd_MEMq", XED_IFORM_MOVHPD_XMMsd_MEMq},
{"MOVHPS_MEMq_XMMps", XED_IFORM_MOVHPS_MEMq_XMMps},
{"MOVHPS_XMMq_MEMq", XED_IFORM_MOVHPS_XMMq_MEMq},
{"MOVLHPS_XMMq_XMMq", XED_IFORM_MOVLHPS_XMMq_XMMq},
{"MOVLPD_MEMq_XMMsd", XED_IFORM_MOVLPD_MEMq_XMMsd},
{"MOVLPD_XMMsd_MEMq", XED_IFORM_MOVLPD_XMMsd_MEMq},
{"MOVLPS_MEMq_XMMq", XED_IFORM_MOVLPS_MEMq_XMMq},
{"MOVLPS_XMMq_MEMq", XED_IFORM_MOVLPS_XMMq_MEMq},
{"MOVMSKPD_GPR32_XMMpd", XED_IFORM_MOVMSKPD_GPR32_XMMpd},
{"MOVMSKPS_GPR32_XMMps", XED_IFORM_MOVMSKPS_GPR32_XMMps},
{"MOVNTDQ_MEMdq_XMMdq", XED_IFORM_MOVNTDQ_MEMdq_XMMdq},
{"MOVNTDQA_XMMdq_MEMdq", XED_IFORM_MOVNTDQA_XMMdq_MEMdq},
{"MOVNTI_MEMd_GPR32", XED_IFORM_MOVNTI_MEMd_GPR32},
{"MOVNTI_MEMq_GPR64", XED_IFORM_MOVNTI_MEMq_GPR64},
{"MOVNTPD_MEMdq_XMMpd", XED_IFORM_MOVNTPD_MEMdq_XMMpd},
{"MOVNTPS_MEMdq_XMMps", XED_IFORM_MOVNTPS_MEMdq_XMMps},
{"MOVNTQ_MEMq_MMXq", XED_IFORM_MOVNTQ_MEMq_MMXq},
{"MOVNTSD_MEMq_XMMq", XED_IFORM_MOVNTSD_MEMq_XMMq},
{"MOVNTSS_MEMd_XMMd", XED_IFORM_MOVNTSS_MEMd_XMMd},
{"MOVQ_GPR64_MMXq", XED_IFORM_MOVQ_GPR64_MMXq},
{"MOVQ_GPR64_XMMq", XED_IFORM_MOVQ_GPR64_XMMq},
{"MOVQ_MEMq_MMXq_0F7E", XED_IFORM_MOVQ_MEMq_MMXq_0F7E},
{"MOVQ_MEMq_MMXq_0F7F", XED_IFORM_MOVQ_MEMq_MMXq_0F7F},
{"MOVQ_MEMq_XMMq_0F7E", XED_IFORM_MOVQ_MEMq_XMMq_0F7E},
{"MOVQ_MEMq_XMMq_0FD6", XED_IFORM_MOVQ_MEMq_XMMq_0FD6},
{"MOVQ_MMXq_GPR64", XED_IFORM_MOVQ_MMXq_GPR64},
{"MOVQ_MMXq_MEMq_0F6E", XED_IFORM_MOVQ_MMXq_MEMq_0F6E},
{"MOVQ_MMXq_MEMq_0F6F", XED_IFORM_MOVQ_MMXq_MEMq_0F6F},
{"MOVQ_MMXq_MMXq_0F6F", XED_IFORM_MOVQ_MMXq_MMXq_0F6F},
{"MOVQ_MMXq_MMXq_0F7F", XED_IFORM_MOVQ_MMXq_MMXq_0F7F},
{"MOVQ_XMMdq_GPR64", XED_IFORM_MOVQ_XMMdq_GPR64},
{"MOVQ_XMMdq_MEMq_0F6E", XED_IFORM_MOVQ_XMMdq_MEMq_0F6E},
{"MOVQ_XMMdq_MEMq_0F7E", XED_IFORM_MOVQ_XMMdq_MEMq_0F7E},
{"MOVQ_XMMdq_XMMq_0F7E", XED_IFORM_MOVQ_XMMdq_XMMq_0F7E},
{"MOVQ_XMMdq_XMMq_0FD6", XED_IFORM_MOVQ_XMMdq_XMMq_0FD6},
{"MOVQ2DQ_XMMdq_MMXq", XED_IFORM_MOVQ2DQ_XMMdq_MMXq},
{"MOVSB", XED_IFORM_MOVSB},
{"MOVSD", XED_IFORM_MOVSD},
{"MOVSD_XMM_MEMsd_XMMsd", XED_IFORM_MOVSD_XMM_MEMsd_XMMsd},
{"MOVSD_XMM_XMMdq_MEMsd", XED_IFORM_MOVSD_XMM_XMMdq_MEMsd},
{"MOVSD_XMM_XMMsd_XMMsd_0F10", XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10},
{"MOVSD_XMM_XMMsd_XMMsd_0F11", XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11},
{"MOVSHDUP_XMMps_MEMps", XED_IFORM_MOVSHDUP_XMMps_MEMps},
{"MOVSHDUP_XMMps_XMMps", XED_IFORM_MOVSHDUP_XMMps_XMMps},
{"MOVSLDUP_XMMps_MEMps", XED_IFORM_MOVSLDUP_XMMps_MEMps},
{"MOVSLDUP_XMMps_XMMps", XED_IFORM_MOVSLDUP_XMMps_XMMps},
{"MOVSQ", XED_IFORM_MOVSQ},
{"MOVSS_MEMss_XMMss", XED_IFORM_MOVSS_MEMss_XMMss},
{"MOVSS_XMMdq_MEMss", XED_IFORM_MOVSS_XMMdq_MEMss},
{"MOVSS_XMMss_XMMss_0F10", XED_IFORM_MOVSS_XMMss_XMMss_0F10},
{"MOVSS_XMMss_XMMss_0F11", XED_IFORM_MOVSS_XMMss_XMMss_0F11},
{"MOVSW", XED_IFORM_MOVSW},
{"MOVSX_GPRv_GPR16", XED_IFORM_MOVSX_GPRv_GPR16},
{"MOVSX_GPRv_GPR8", XED_IFORM_MOVSX_GPRv_GPR8},
{"MOVSX_GPRv_MEMb", XED_IFORM_MOVSX_GPRv_MEMb},
{"MOVSX_GPRv_MEMw", XED_IFORM_MOVSX_GPRv_MEMw},
{"MOVSXD_GPRv_GPRz", XED_IFORM_MOVSXD_GPRv_GPRz},
{"MOVSXD_GPRv_MEMz", XED_IFORM_MOVSXD_GPRv_MEMz},
{"MOVUPD_MEMpd_XMMpd", XED_IFORM_MOVUPD_MEMpd_XMMpd},
{"MOVUPD_XMMpd_MEMpd", XED_IFORM_MOVUPD_XMMpd_MEMpd},
{"MOVUPD_XMMpd_XMMpd_0F10", XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10},
{"MOVUPD_XMMpd_XMMpd_0F11", XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11},
{"MOVUPS_MEMps_XMMps", XED_IFORM_MOVUPS_MEMps_XMMps},
{"MOVUPS_XMMps_MEMps", XED_IFORM_MOVUPS_XMMps_MEMps},
{"MOVUPS_XMMps_XMMps_0F10", XED_IFORM_MOVUPS_XMMps_XMMps_0F10},
{"MOVUPS_XMMps_XMMps_0F11", XED_IFORM_MOVUPS_XMMps_XMMps_0F11},
{"MOVZX_GPRv_GPR16", XED_IFORM_MOVZX_GPRv_GPR16},
{"MOVZX_GPRv_GPR8", XED_IFORM_MOVZX_GPRv_GPR8},
{"MOVZX_GPRv_MEMb", XED_IFORM_MOVZX_GPRv_MEMb},
{"MOVZX_GPRv_MEMw", XED_IFORM_MOVZX_GPRv_MEMw},
{"MOV_CR_CR_GPR32", XED_IFORM_MOV_CR_CR_GPR32},
{"MOV_CR_CR_GPR64", XED_IFORM_MOV_CR_CR_GPR64},
{"MOV_CR_GPR32_CR", XED_IFORM_MOV_CR_GPR32_CR},
{"MOV_CR_GPR64_CR", XED_IFORM_MOV_CR_GPR64_CR},
{"MOV_DR_DR_GPR32", XED_IFORM_MOV_DR_DR_GPR32},
{"MOV_DR_DR_GPR64", XED_IFORM_MOV_DR_DR_GPR64},
{"MOV_DR_GPR32_DR", XED_IFORM_MOV_DR_GPR32_DR},
{"MOV_DR_GPR64_DR", XED_IFORM_MOV_DR_GPR64_DR},
{"MPSADBW_XMMdq_MEMdq_IMMb", XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb},
{"MPSADBW_XMMdq_XMMdq_IMMb", XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb},
{"MUL_GPR8", XED_IFORM_MUL_GPR8},
{"MUL_GPRv", XED_IFORM_MUL_GPRv},
{"MUL_MEMb", XED_IFORM_MUL_MEMb},
{"MUL_MEMv", XED_IFORM_MUL_MEMv},
{"MULPD_XMMpd_MEMpd", XED_IFORM_MULPD_XMMpd_MEMpd},
{"MULPD_XMMpd_XMMpd", XED_IFORM_MULPD_XMMpd_XMMpd},
{"MULPS_XMMps_MEMps", XED_IFORM_MULPS_XMMps_MEMps},
{"MULPS_XMMps_XMMps", XED_IFORM_MULPS_XMMps_XMMps},
{"MULSD_XMMsd_MEMsd", XED_IFORM_MULSD_XMMsd_MEMsd},
{"MULSD_XMMsd_XMMsd", XED_IFORM_MULSD_XMMsd_XMMsd},
{"MULSS_XMMss_MEMss", XED_IFORM_MULSS_XMMss_MEMss},
{"MULSS_XMMss_XMMss", XED_IFORM_MULSS_XMMss_XMMss},
{"MULX_VGPR32d_VGPR32d_MEMd", XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd},
{"MULX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d},
{"MULX_VGPR64q_VGPR64q_MEMq", XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq},
{"MULX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q},
{"MWAIT", XED_IFORM_MWAIT},
{"MWAITX", XED_IFORM_MWAITX},
{"NEG_GPR8", XED_IFORM_NEG_GPR8},
{"NEG_GPRv", XED_IFORM_NEG_GPRv},
{"NEG_MEMb", XED_IFORM_NEG_MEMb},
{"NEG_MEMv", XED_IFORM_NEG_MEMv},
{"NEG_LOCK_MEMb", XED_IFORM_NEG_LOCK_MEMb},
{"NEG_LOCK_MEMv", XED_IFORM_NEG_LOCK_MEMv},
{"NOP_90", XED_IFORM_NOP_90},
{"NOP_GPRv_0F18r0", XED_IFORM_NOP_GPRv_0F18r0},
{"NOP_GPRv_0F18r1", XED_IFORM_NOP_GPRv_0F18r1},
{"NOP_GPRv_0F18r2", XED_IFORM_NOP_GPRv_0F18r2},
{"NOP_GPRv_0F18r3", XED_IFORM_NOP_GPRv_0F18r3},
{"NOP_GPRv_0F18r4", XED_IFORM_NOP_GPRv_0F18r4},
{"NOP_GPRv_0F18r5", XED_IFORM_NOP_GPRv_0F18r5},
{"NOP_GPRv_0F18r6", XED_IFORM_NOP_GPRv_0F18r6},
{"NOP_GPRv_0F18r7", XED_IFORM_NOP_GPRv_0F18r7},
{"NOP_GPRv_GPRv_0F0D", XED_IFORM_NOP_GPRv_GPRv_0F0D},
{"NOP_GPRv_GPRv_0F19", XED_IFORM_NOP_GPRv_GPRv_0F19},
{"NOP_GPRv_GPRv_0F1A", XED_IFORM_NOP_GPRv_GPRv_0F1A},
{"NOP_GPRv_GPRv_0F1B", XED_IFORM_NOP_GPRv_GPRv_0F1B},
{"NOP_GPRv_GPRv_0F1C", XED_IFORM_NOP_GPRv_GPRv_0F1C},
{"NOP_GPRv_GPRv_0F1D", XED_IFORM_NOP_GPRv_GPRv_0F1D},
{"NOP_GPRv_GPRv_0F1E", XED_IFORM_NOP_GPRv_GPRv_0F1E},
{"NOP_GPRv_GPRv_0F1F", XED_IFORM_NOP_GPRv_GPRv_0F1F},
{"NOP_GPRv_MEM_0F1B", XED_IFORM_NOP_GPRv_MEM_0F1B},
{"NOP_GPRv_MEMv_0F1A", XED_IFORM_NOP_GPRv_MEMv_0F1A},
{"NOP_MEMv_0F18r4", XED_IFORM_NOP_MEMv_0F18r4},
{"NOP_MEMv_0F18r5", XED_IFORM_NOP_MEMv_0F18r5},
{"NOP_MEMv_0F18r6", XED_IFORM_NOP_MEMv_0F18r6},
{"NOP_MEMv_0F18r7", XED_IFORM_NOP_MEMv_0F18r7},
{"NOP_MEMv_GPRv_0F19", XED_IFORM_NOP_MEMv_GPRv_0F19},
{"NOP_MEMv_GPRv_0F1C", XED_IFORM_NOP_MEMv_GPRv_0F1C},
{"NOP_MEMv_GPRv_0F1D", XED_IFORM_NOP_MEMv_GPRv_0F1D},
{"NOP_MEMv_GPRv_0F1E", XED_IFORM_NOP_MEMv_GPRv_0F1E},
{"NOP_MEMv_GPRv_0F1F", XED_IFORM_NOP_MEMv_GPRv_0F1F},
{"NOT_GPR8", XED_IFORM_NOT_GPR8},
{"NOT_GPRv", XED_IFORM_NOT_GPRv},
{"NOT_MEMb", XED_IFORM_NOT_MEMb},
{"NOT_MEMv", XED_IFORM_NOT_MEMv},
{"NOT_LOCK_MEMb", XED_IFORM_NOT_LOCK_MEMb},
{"NOT_LOCK_MEMv", XED_IFORM_NOT_LOCK_MEMv},
{"OR_AL_IMMb", XED_IFORM_OR_AL_IMMb},
{"OR_GPR8_GPR8_08", XED_IFORM_OR_GPR8_GPR8_08},
{"OR_GPR8_GPR8_0A", XED_IFORM_OR_GPR8_GPR8_0A},
{"OR_GPR8_IMMb_80r1", XED_IFORM_OR_GPR8_IMMb_80r1},
{"OR_GPR8_IMMb_82r1", XED_IFORM_OR_GPR8_IMMb_82r1},
{"OR_GPR8_MEMb", XED_IFORM_OR_GPR8_MEMb},
{"OR_GPRv_GPRv_09", XED_IFORM_OR_GPRv_GPRv_09},
{"OR_GPRv_GPRv_0B", XED_IFORM_OR_GPRv_GPRv_0B},
{"OR_GPRv_IMMb", XED_IFORM_OR_GPRv_IMMb},
{"OR_GPRv_IMMz", XED_IFORM_OR_GPRv_IMMz},
{"OR_GPRv_MEMv", XED_IFORM_OR_GPRv_MEMv},
{"OR_MEMb_GPR8", XED_IFORM_OR_MEMb_GPR8},
{"OR_MEMb_IMMb_80r1", XED_IFORM_OR_MEMb_IMMb_80r1},
{"OR_MEMb_IMMb_82r1", XED_IFORM_OR_MEMb_IMMb_82r1},
{"OR_MEMv_GPRv", XED_IFORM_OR_MEMv_GPRv},
{"OR_MEMv_IMMb", XED_IFORM_OR_MEMv_IMMb},
{"OR_MEMv_IMMz", XED_IFORM_OR_MEMv_IMMz},
{"OR_OrAX_IMMz", XED_IFORM_OR_OrAX_IMMz},
{"ORPD_XMMxuq_MEMxuq", XED_IFORM_ORPD_XMMxuq_MEMxuq},
{"ORPD_XMMxuq_XMMxuq", XED_IFORM_ORPD_XMMxuq_XMMxuq},
{"ORPS_XMMxud_MEMxud", XED_IFORM_ORPS_XMMxud_MEMxud},
{"ORPS_XMMxud_XMMxud", XED_IFORM_ORPS_XMMxud_XMMxud},
{"OR_LOCK_MEMb_GPR8", XED_IFORM_OR_LOCK_MEMb_GPR8},
{"OR_LOCK_MEMb_IMMb_80r1", XED_IFORM_OR_LOCK_MEMb_IMMb_80r1},
{"OR_LOCK_MEMb_IMMb_82r1", XED_IFORM_OR_LOCK_MEMb_IMMb_82r1},
{"OR_LOCK_MEMv_GPRv", XED_IFORM_OR_LOCK_MEMv_GPRv},
{"OR_LOCK_MEMv_IMMb", XED_IFORM_OR_LOCK_MEMv_IMMb},
{"OR_LOCK_MEMv_IMMz", XED_IFORM_OR_LOCK_MEMv_IMMz},
{"OUT_DX_AL", XED_IFORM_OUT_DX_AL},
{"OUT_DX_OeAX", XED_IFORM_OUT_DX_OeAX},
{"OUT_IMMb_AL", XED_IFORM_OUT_IMMb_AL},
{"OUT_IMMb_OeAX", XED_IFORM_OUT_IMMb_OeAX},
{"OUTSB", XED_IFORM_OUTSB},
{"OUTSD", XED_IFORM_OUTSD},
{"OUTSW", XED_IFORM_OUTSW},
{"PABSB_MMXq_MEMq", XED_IFORM_PABSB_MMXq_MEMq},
{"PABSB_MMXq_MMXq", XED_IFORM_PABSB_MMXq_MMXq},
{"PABSB_XMMdq_MEMdq", XED_IFORM_PABSB_XMMdq_MEMdq},
{"PABSB_XMMdq_XMMdq", XED_IFORM_PABSB_XMMdq_XMMdq},
{"PABSD_MMXq_MEMq", XED_IFORM_PABSD_MMXq_MEMq},
{"PABSD_MMXq_MMXq", XED_IFORM_PABSD_MMXq_MMXq},
{"PABSD_XMMdq_MEMdq", XED_IFORM_PABSD_XMMdq_MEMdq},
{"PABSD_XMMdq_XMMdq", XED_IFORM_PABSD_XMMdq_XMMdq},
{"PABSW_MMXq_MEMq", XED_IFORM_PABSW_MMXq_MEMq},
{"PABSW_MMXq_MMXq", XED_IFORM_PABSW_MMXq_MMXq},
{"PABSW_XMMdq_MEMdq", XED_IFORM_PABSW_XMMdq_MEMdq},
{"PABSW_XMMdq_XMMdq", XED_IFORM_PABSW_XMMdq_XMMdq},
{"PACKSSDW_MMXq_MEMq", XED_IFORM_PACKSSDW_MMXq_MEMq},
{"PACKSSDW_MMXq_MMXq", XED_IFORM_PACKSSDW_MMXq_MMXq},
{"PACKSSDW_XMMdq_MEMdq", XED_IFORM_PACKSSDW_XMMdq_MEMdq},
{"PACKSSDW_XMMdq_XMMdq", XED_IFORM_PACKSSDW_XMMdq_XMMdq},
{"PACKSSWB_MMXq_MEMq", XED_IFORM_PACKSSWB_MMXq_MEMq},
{"PACKSSWB_MMXq_MMXq", XED_IFORM_PACKSSWB_MMXq_MMXq},
{"PACKSSWB_XMMdq_MEMdq", XED_IFORM_PACKSSWB_XMMdq_MEMdq},
{"PACKSSWB_XMMdq_XMMdq", XED_IFORM_PACKSSWB_XMMdq_XMMdq},
{"PACKUSDW_XMMdq_MEMdq", XED_IFORM_PACKUSDW_XMMdq_MEMdq},
{"PACKUSDW_XMMdq_XMMdq", XED_IFORM_PACKUSDW_XMMdq_XMMdq},
{"PACKUSWB_MMXq_MEMq", XED_IFORM_PACKUSWB_MMXq_MEMq},
{"PACKUSWB_MMXq_MMXq", XED_IFORM_PACKUSWB_MMXq_MMXq},
{"PACKUSWB_XMMdq_MEMdq", XED_IFORM_PACKUSWB_XMMdq_MEMdq},
{"PACKUSWB_XMMdq_XMMdq", XED_IFORM_PACKUSWB_XMMdq_XMMdq},
{"PADDB_MMXq_MEMq", XED_IFORM_PADDB_MMXq_MEMq},
{"PADDB_MMXq_MMXq", XED_IFORM_PADDB_MMXq_MMXq},
{"PADDB_XMMdq_MEMdq", XED_IFORM_PADDB_XMMdq_MEMdq},
{"PADDB_XMMdq_XMMdq", XED_IFORM_PADDB_XMMdq_XMMdq},
{"PADDD_MMXq_MEMq", XED_IFORM_PADDD_MMXq_MEMq},
{"PADDD_MMXq_MMXq", XED_IFORM_PADDD_MMXq_MMXq},
{"PADDD_XMMdq_MEMdq", XED_IFORM_PADDD_XMMdq_MEMdq},
{"PADDD_XMMdq_XMMdq", XED_IFORM_PADDD_XMMdq_XMMdq},
{"PADDQ_MMXq_MEMq", XED_IFORM_PADDQ_MMXq_MEMq},
{"PADDQ_MMXq_MMXq", XED_IFORM_PADDQ_MMXq_MMXq},
{"PADDQ_XMMdq_MEMdq", XED_IFORM_PADDQ_XMMdq_MEMdq},
{"PADDQ_XMMdq_XMMdq", XED_IFORM_PADDQ_XMMdq_XMMdq},
{"PADDSB_MMXq_MEMq", XED_IFORM_PADDSB_MMXq_MEMq},
{"PADDSB_MMXq_MMXq", XED_IFORM_PADDSB_MMXq_MMXq},
{"PADDSB_XMMdq_MEMdq", XED_IFORM_PADDSB_XMMdq_MEMdq},
{"PADDSB_XMMdq_XMMdq", XED_IFORM_PADDSB_XMMdq_XMMdq},
{"PADDSW_MMXq_MEMq", XED_IFORM_PADDSW_MMXq_MEMq},
{"PADDSW_MMXq_MMXq", XED_IFORM_PADDSW_MMXq_MMXq},
{"PADDSW_XMMdq_MEMdq", XED_IFORM_PADDSW_XMMdq_MEMdq},
{"PADDSW_XMMdq_XMMdq", XED_IFORM_PADDSW_XMMdq_XMMdq},
{"PADDUSB_MMXq_MEMq", XED_IFORM_PADDUSB_MMXq_MEMq},
{"PADDUSB_MMXq_MMXq", XED_IFORM_PADDUSB_MMXq_MMXq},
{"PADDUSB_XMMdq_MEMdq", XED_IFORM_PADDUSB_XMMdq_MEMdq},
{"PADDUSB_XMMdq_XMMdq", XED_IFORM_PADDUSB_XMMdq_XMMdq},
{"PADDUSW_MMXq_MEMq", XED_IFORM_PADDUSW_MMXq_MEMq},
{"PADDUSW_MMXq_MMXq", XED_IFORM_PADDUSW_MMXq_MMXq},
{"PADDUSW_XMMdq_MEMdq", XED_IFORM_PADDUSW_XMMdq_MEMdq},
{"PADDUSW_XMMdq_XMMdq", XED_IFORM_PADDUSW_XMMdq_XMMdq},
{"PADDW_MMXq_MEMq", XED_IFORM_PADDW_MMXq_MEMq},
{"PADDW_MMXq_MMXq", XED_IFORM_PADDW_MMXq_MMXq},
{"PADDW_XMMdq_MEMdq", XED_IFORM_PADDW_XMMdq_MEMdq},
{"PADDW_XMMdq_XMMdq", XED_IFORM_PADDW_XMMdq_XMMdq},
{"PALIGNR_MMXq_MEMq_IMMb", XED_IFORM_PALIGNR_MMXq_MEMq_IMMb},
{"PALIGNR_MMXq_MMXq_IMMb", XED_IFORM_PALIGNR_MMXq_MMXq_IMMb},
{"PALIGNR_XMMdq_MEMdq_IMMb", XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb},
{"PALIGNR_XMMdq_XMMdq_IMMb", XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb},
{"PAND_MMXq_MEMq", XED_IFORM_PAND_MMXq_MEMq},
{"PAND_MMXq_MMXq", XED_IFORM_PAND_MMXq_MMXq},
{"PAND_XMMdq_MEMdq", XED_IFORM_PAND_XMMdq_MEMdq},
{"PAND_XMMdq_XMMdq", XED_IFORM_PAND_XMMdq_XMMdq},
{"PANDN_MMXq_MEMq", XED_IFORM_PANDN_MMXq_MEMq},
{"PANDN_MMXq_MMXq", XED_IFORM_PANDN_MMXq_MMXq},
{"PANDN_XMMdq_MEMdq", XED_IFORM_PANDN_XMMdq_MEMdq},
{"PANDN_XMMdq_XMMdq", XED_IFORM_PANDN_XMMdq_XMMdq},
{"PAUSE", XED_IFORM_PAUSE},
{"PAVGB_MMXq_MEMq", XED_IFORM_PAVGB_MMXq_MEMq},
{"PAVGB_MMXq_MMXq", XED_IFORM_PAVGB_MMXq_MMXq},
{"PAVGB_XMMdq_MEMdq", XED_IFORM_PAVGB_XMMdq_MEMdq},
{"PAVGB_XMMdq_XMMdq", XED_IFORM_PAVGB_XMMdq_XMMdq},
{"PAVGUSB_MMXq_MEMq", XED_IFORM_PAVGUSB_MMXq_MEMq},
{"PAVGUSB_MMXq_MMXq", XED_IFORM_PAVGUSB_MMXq_MMXq},
{"PAVGW_MMXq_MEMq", XED_IFORM_PAVGW_MMXq_MEMq},
{"PAVGW_MMXq_MMXq", XED_IFORM_PAVGW_MMXq_MMXq},
{"PAVGW_XMMdq_MEMdq", XED_IFORM_PAVGW_XMMdq_MEMdq},
{"PAVGW_XMMdq_XMMdq", XED_IFORM_PAVGW_XMMdq_XMMdq},
{"PBLENDVB_XMMdq_MEMdq", XED_IFORM_PBLENDVB_XMMdq_MEMdq},
{"PBLENDVB_XMMdq_XMMdq", XED_IFORM_PBLENDVB_XMMdq_XMMdq},
{"PBLENDW_XMMdq_MEMdq_IMMb", XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb},
{"PBLENDW_XMMdq_XMMdq_IMMb", XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb},
{"PCLMULQDQ_XMMdq_MEMdq_IMMb", XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb},
{"PCLMULQDQ_XMMdq_XMMdq_IMMb", XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb},
{"PCMPEQB_MMXq_MEMq", XED_IFORM_PCMPEQB_MMXq_MEMq},
{"PCMPEQB_MMXq_MMXq", XED_IFORM_PCMPEQB_MMXq_MMXq},
{"PCMPEQB_XMMdq_MEMdq", XED_IFORM_PCMPEQB_XMMdq_MEMdq},
{"PCMPEQB_XMMdq_XMMdq", XED_IFORM_PCMPEQB_XMMdq_XMMdq},
{"PCMPEQD_MMXq_MEMq", XED_IFORM_PCMPEQD_MMXq_MEMq},
{"PCMPEQD_MMXq_MMXq", XED_IFORM_PCMPEQD_MMXq_MMXq},
{"PCMPEQD_XMMdq_MEMdq", XED_IFORM_PCMPEQD_XMMdq_MEMdq},
{"PCMPEQD_XMMdq_XMMdq", XED_IFORM_PCMPEQD_XMMdq_XMMdq},
{"PCMPEQQ_XMMdq_MEMdq", XED_IFORM_PCMPEQQ_XMMdq_MEMdq},
{"PCMPEQQ_XMMdq_XMMdq", XED_IFORM_PCMPEQQ_XMMdq_XMMdq},
{"PCMPEQW_MMXq_MEMq", XED_IFORM_PCMPEQW_MMXq_MEMq},
{"PCMPEQW_MMXq_MMXq", XED_IFORM_PCMPEQW_MMXq_MMXq},
{"PCMPEQW_XMMdq_MEMdq", XED_IFORM_PCMPEQW_XMMdq_MEMdq},
{"PCMPEQW_XMMdq_XMMdq", XED_IFORM_PCMPEQW_XMMdq_XMMdq},
{"PCMPESTRI_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb},
{"PCMPESTRI_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb},
{"PCMPESTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb},
{"PCMPESTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb},
{"PCMPESTRM_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb},
{"PCMPESTRM_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb},
{"PCMPESTRM64_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb},
{"PCMPESTRM64_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb},
{"PCMPGTB_MMXq_MEMq", XED_IFORM_PCMPGTB_MMXq_MEMq},
{"PCMPGTB_MMXq_MMXq", XED_IFORM_PCMPGTB_MMXq_MMXq},
{"PCMPGTB_XMMdq_MEMdq", XED_IFORM_PCMPGTB_XMMdq_MEMdq},
{"PCMPGTB_XMMdq_XMMdq", XED_IFORM_PCMPGTB_XMMdq_XMMdq},
{"PCMPGTD_MMXq_MEMq", XED_IFORM_PCMPGTD_MMXq_MEMq},
{"PCMPGTD_MMXq_MMXq", XED_IFORM_PCMPGTD_MMXq_MMXq},
{"PCMPGTD_XMMdq_MEMdq", XED_IFORM_PCMPGTD_XMMdq_MEMdq},
{"PCMPGTD_XMMdq_XMMdq", XED_IFORM_PCMPGTD_XMMdq_XMMdq},
{"PCMPGTQ_XMMdq_MEMdq", XED_IFORM_PCMPGTQ_XMMdq_MEMdq},
{"PCMPGTQ_XMMdq_XMMdq", XED_IFORM_PCMPGTQ_XMMdq_XMMdq},
{"PCMPGTW_MMXq_MEMq", XED_IFORM_PCMPGTW_MMXq_MEMq},
{"PCMPGTW_MMXq_MMXq", XED_IFORM_PCMPGTW_MMXq_MMXq},
{"PCMPGTW_XMMdq_MEMdq", XED_IFORM_PCMPGTW_XMMdq_MEMdq},
{"PCMPGTW_XMMdq_XMMdq", XED_IFORM_PCMPGTW_XMMdq_XMMdq},
{"PCMPISTRI_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb},
{"PCMPISTRI_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb},
{"PCMPISTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb},
{"PCMPISTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb},
{"PCMPISTRM_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb},
{"PCMPISTRM_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb},
{"PCONFIG", XED_IFORM_PCONFIG},
{"PCONFIG64", XED_IFORM_PCONFIG64},
{"PDEP_VGPR32d_VGPR32d_MEMd", XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd},
{"PDEP_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d},
{"PDEP_VGPR64q_VGPR64q_MEMq", XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq},
{"PDEP_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q},
{"PEXT_VGPR32d_VGPR32d_MEMd", XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd},
{"PEXT_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d},
{"PEXT_VGPR64q_VGPR64q_MEMq", XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq},
{"PEXT_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q},
{"PEXTRB_GPR32d_XMMdq_IMMb", XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb},
{"PEXTRB_MEMb_XMMdq_IMMb", XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb},
{"PEXTRD_GPR32d_XMMdq_IMMb", XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb},
{"PEXTRD_MEMd_XMMdq_IMMb", XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb},
{"PEXTRQ_GPR64q_XMMdq_IMMb", XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb},
{"PEXTRQ_MEMq_XMMdq_IMMb", XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb},
{"PEXTRW_GPR32_MMXq_IMMb", XED_IFORM_PEXTRW_GPR32_MMXq_IMMb},
{"PEXTRW_GPR32_XMMdq_IMMb", XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb},
{"PEXTRW_SSE4_GPR32_XMMdq_IMMb", XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb},
{"PEXTRW_SSE4_MEMw_XMMdq_IMMb", XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb},
{"PF2ID_MMXq_MEMq", XED_IFORM_PF2ID_MMXq_MEMq},
{"PF2ID_MMXq_MMXq", XED_IFORM_PF2ID_MMXq_MMXq},
{"PF2IW_MMXq_MEMq", XED_IFORM_PF2IW_MMXq_MEMq},
{"PF2IW_MMXq_MMXq", XED_IFORM_PF2IW_MMXq_MMXq},
{"PFACC_MMXq_MEMq", XED_IFORM_PFACC_MMXq_MEMq},
{"PFACC_MMXq_MMXq", XED_IFORM_PFACC_MMXq_MMXq},
{"PFADD_MMXq_MEMq", XED_IFORM_PFADD_MMXq_MEMq},
{"PFADD_MMXq_MMXq", XED_IFORM_PFADD_MMXq_MMXq},
{"PFCMPEQ_MMXq_MEMq", XED_IFORM_PFCMPEQ_MMXq_MEMq},
{"PFCMPEQ_MMXq_MMXq", XED_IFORM_PFCMPEQ_MMXq_MMXq},
{"PFCMPGE_MMXq_MEMq", XED_IFORM_PFCMPGE_MMXq_MEMq},
{"PFCMPGE_MMXq_MMXq", XED_IFORM_PFCMPGE_MMXq_MMXq},
{"PFCMPGT_MMXq_MEMq", XED_IFORM_PFCMPGT_MMXq_MEMq},
{"PFCMPGT_MMXq_MMXq", XED_IFORM_PFCMPGT_MMXq_MMXq},
{"PFMAX_MMXq_MEMq", XED_IFORM_PFMAX_MMXq_MEMq},
{"PFMAX_MMXq_MMXq", XED_IFORM_PFMAX_MMXq_MMXq},
{"PFMIN_MMXq_MEMq", XED_IFORM_PFMIN_MMXq_MEMq},
{"PFMIN_MMXq_MMXq", XED_IFORM_PFMIN_MMXq_MMXq},
{"PFMUL_MMXq_MEMq", XED_IFORM_PFMUL_MMXq_MEMq},
{"PFMUL_MMXq_MMXq", XED_IFORM_PFMUL_MMXq_MMXq},
{"PFNACC_MMXq_MEMq", XED_IFORM_PFNACC_MMXq_MEMq},
{"PFNACC_MMXq_MMXq", XED_IFORM_PFNACC_MMXq_MMXq},
{"PFPNACC_MMXq_MEMq", XED_IFORM_PFPNACC_MMXq_MEMq},
{"PFPNACC_MMXq_MMXq", XED_IFORM_PFPNACC_MMXq_MMXq},
{"PFRCP_MMXq_MEMq", XED_IFORM_PFRCP_MMXq_MEMq},
{"PFRCP_MMXq_MMXq", XED_IFORM_PFRCP_MMXq_MMXq},
{"PFRCPIT1_MMXq_MEMq", XED_IFORM_PFRCPIT1_MMXq_MEMq},
{"PFRCPIT1_MMXq_MMXq", XED_IFORM_PFRCPIT1_MMXq_MMXq},
{"PFRCPIT2_MMXq_MEMq", XED_IFORM_PFRCPIT2_MMXq_MEMq},
{"PFRCPIT2_MMXq_MMXq", XED_IFORM_PFRCPIT2_MMXq_MMXq},
{"PFRSQIT1_MMXq_MEMq", XED_IFORM_PFRSQIT1_MMXq_MEMq},
{"PFRSQIT1_MMXq_MMXq", XED_IFORM_PFRSQIT1_MMXq_MMXq},
{"PFRSQRT_MMXq_MEMq", XED_IFORM_PFRSQRT_MMXq_MEMq},
{"PFRSQRT_MMXq_MMXq", XED_IFORM_PFRSQRT_MMXq_MMXq},
{"PFSUB_MMXq_MEMq", XED_IFORM_PFSUB_MMXq_MEMq},
{"PFSUB_MMXq_MMXq", XED_IFORM_PFSUB_MMXq_MMXq},
{"PFSUBR_MMXq_MEMq", XED_IFORM_PFSUBR_MMXq_MEMq},
{"PFSUBR_MMXq_MMXq", XED_IFORM_PFSUBR_MMXq_MMXq},
{"PHADDD_MMXq_MEMq", XED_IFORM_PHADDD_MMXq_MEMq},
{"PHADDD_MMXq_MMXq", XED_IFORM_PHADDD_MMXq_MMXq},
{"PHADDD_XMMdq_MEMdq", XED_IFORM_PHADDD_XMMdq_MEMdq},
{"PHADDD_XMMdq_XMMdq", XED_IFORM_PHADDD_XMMdq_XMMdq},
{"PHADDSW_MMXq_MEMq", XED_IFORM_PHADDSW_MMXq_MEMq},
{"PHADDSW_MMXq_MMXq", XED_IFORM_PHADDSW_MMXq_MMXq},
{"PHADDSW_XMMdq_MEMdq", XED_IFORM_PHADDSW_XMMdq_MEMdq},
{"PHADDSW_XMMdq_XMMdq", XED_IFORM_PHADDSW_XMMdq_XMMdq},
{"PHADDW_MMXq_MEMq", XED_IFORM_PHADDW_MMXq_MEMq},
{"PHADDW_MMXq_MMXq", XED_IFORM_PHADDW_MMXq_MMXq},
{"PHADDW_XMMdq_MEMdq", XED_IFORM_PHADDW_XMMdq_MEMdq},
{"PHADDW_XMMdq_XMMdq", XED_IFORM_PHADDW_XMMdq_XMMdq},
{"PHMINPOSUW_XMMdq_MEMdq", XED_IFORM_PHMINPOSUW_XMMdq_MEMdq},
{"PHMINPOSUW_XMMdq_XMMdq", XED_IFORM_PHMINPOSUW_XMMdq_XMMdq},
{"PHSUBD_MMXq_MEMq", XED_IFORM_PHSUBD_MMXq_MEMq},
{"PHSUBD_MMXq_MMXq", XED_IFORM_PHSUBD_MMXq_MMXq},
{"PHSUBD_XMMdq_MEMdq", XED_IFORM_PHSUBD_XMMdq_MEMdq},
{"PHSUBD_XMMdq_XMMdq", XED_IFORM_PHSUBD_XMMdq_XMMdq},
{"PHSUBSW_MMXq_MEMq", XED_IFORM_PHSUBSW_MMXq_MEMq},
{"PHSUBSW_MMXq_MMXq", XED_IFORM_PHSUBSW_MMXq_MMXq},
{"PHSUBSW_XMMdq_MEMdq", XED_IFORM_PHSUBSW_XMMdq_MEMdq},
{"PHSUBSW_XMMdq_XMMdq", XED_IFORM_PHSUBSW_XMMdq_XMMdq},
{"PHSUBW_MMXq_MEMq", XED_IFORM_PHSUBW_MMXq_MEMq},
{"PHSUBW_MMXq_MMXq", XED_IFORM_PHSUBW_MMXq_MMXq},
{"PHSUBW_XMMdq_MEMdq", XED_IFORM_PHSUBW_XMMdq_MEMdq},
{"PHSUBW_XMMdq_XMMdq", XED_IFORM_PHSUBW_XMMdq_XMMdq},
{"PI2FD_MMXq_MEMq", XED_IFORM_PI2FD_MMXq_MEMq},
{"PI2FD_MMXq_MMXq", XED_IFORM_PI2FD_MMXq_MMXq},
{"PI2FW_MMXq_MEMq", XED_IFORM_PI2FW_MMXq_MEMq},
{"PI2FW_MMXq_MMXq", XED_IFORM_PI2FW_MMXq_MMXq},
{"PINSRB_XMMdq_GPR32d_IMMb", XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb},
{"PINSRB_XMMdq_MEMb_IMMb", XED_IFORM_PINSRB_XMMdq_MEMb_IMMb},
{"PINSRD_XMMdq_GPR32d_IMMb", XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb},
{"PINSRD_XMMdq_MEMd_IMMb", XED_IFORM_PINSRD_XMMdq_MEMd_IMMb},
{"PINSRQ_XMMdq_GPR64q_IMMb", XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb},
{"PINSRQ_XMMdq_MEMq_IMMb", XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb},
{"PINSRW_MMXq_GPR32_IMMb", XED_IFORM_PINSRW_MMXq_GPR32_IMMb},
{"PINSRW_MMXq_MEMw_IMMb", XED_IFORM_PINSRW_MMXq_MEMw_IMMb},
{"PINSRW_XMMdq_GPR32_IMMb", XED_IFORM_PINSRW_XMMdq_GPR32_IMMb},
{"PINSRW_XMMdq_MEMw_IMMb", XED_IFORM_PINSRW_XMMdq_MEMw_IMMb},
{"PMADDUBSW_MMXq_MEMq", XED_IFORM_PMADDUBSW_MMXq_MEMq},
{"PMADDUBSW_MMXq_MMXq", XED_IFORM_PMADDUBSW_MMXq_MMXq},
{"PMADDUBSW_XMMdq_MEMdq", XED_IFORM_PMADDUBSW_XMMdq_MEMdq},
{"PMADDUBSW_XMMdq_XMMdq", XED_IFORM_PMADDUBSW_XMMdq_XMMdq},
{"PMADDWD_MMXq_MEMq", XED_IFORM_PMADDWD_MMXq_MEMq},
{"PMADDWD_MMXq_MMXq", XED_IFORM_PMADDWD_MMXq_MMXq},
{"PMADDWD_XMMdq_MEMdq", XED_IFORM_PMADDWD_XMMdq_MEMdq},
{"PMADDWD_XMMdq_XMMdq", XED_IFORM_PMADDWD_XMMdq_XMMdq},
{"PMAXSB_XMMdq_MEMdq", XED_IFORM_PMAXSB_XMMdq_MEMdq},
{"PMAXSB_XMMdq_XMMdq", XED_IFORM_PMAXSB_XMMdq_XMMdq},
{"PMAXSD_XMMdq_MEMdq", XED_IFORM_PMAXSD_XMMdq_MEMdq},
{"PMAXSD_XMMdq_XMMdq", XED_IFORM_PMAXSD_XMMdq_XMMdq},
{"PMAXSW_MMXq_MEMq", XED_IFORM_PMAXSW_MMXq_MEMq},
{"PMAXSW_MMXq_MMXq", XED_IFORM_PMAXSW_MMXq_MMXq},
{"PMAXSW_XMMdq_MEMdq", XED_IFORM_PMAXSW_XMMdq_MEMdq},
{"PMAXSW_XMMdq_XMMdq", XED_IFORM_PMAXSW_XMMdq_XMMdq},
{"PMAXUB_MMXq_MEMq", XED_IFORM_PMAXUB_MMXq_MEMq},
{"PMAXUB_MMXq_MMXq", XED_IFORM_PMAXUB_MMXq_MMXq},
{"PMAXUB_XMMdq_MEMdq", XED_IFORM_PMAXUB_XMMdq_MEMdq},
{"PMAXUB_XMMdq_XMMdq", XED_IFORM_PMAXUB_XMMdq_XMMdq},
{"PMAXUD_XMMdq_MEMdq", XED_IFORM_PMAXUD_XMMdq_MEMdq},
{"PMAXUD_XMMdq_XMMdq", XED_IFORM_PMAXUD_XMMdq_XMMdq},
{"PMAXUW_XMMdq_MEMdq", XED_IFORM_PMAXUW_XMMdq_MEMdq},
{"PMAXUW_XMMdq_XMMdq", XED_IFORM_PMAXUW_XMMdq_XMMdq},
{"PMINSB_XMMdq_MEMdq", XED_IFORM_PMINSB_XMMdq_MEMdq},
{"PMINSB_XMMdq_XMMdq", XED_IFORM_PMINSB_XMMdq_XMMdq},
{"PMINSD_XMMdq_MEMdq", XED_IFORM_PMINSD_XMMdq_MEMdq},
{"PMINSD_XMMdq_XMMdq", XED_IFORM_PMINSD_XMMdq_XMMdq},
{"PMINSW_MMXq_MEMq", XED_IFORM_PMINSW_MMXq_MEMq},
{"PMINSW_MMXq_MMXq", XED_IFORM_PMINSW_MMXq_MMXq},
{"PMINSW_XMMdq_MEMdq", XED_IFORM_PMINSW_XMMdq_MEMdq},
{"PMINSW_XMMdq_XMMdq", XED_IFORM_PMINSW_XMMdq_XMMdq},
{"PMINUB_MMXq_MEMq", XED_IFORM_PMINUB_MMXq_MEMq},
{"PMINUB_MMXq_MMXq", XED_IFORM_PMINUB_MMXq_MMXq},
{"PMINUB_XMMdq_MEMdq", XED_IFORM_PMINUB_XMMdq_MEMdq},
{"PMINUB_XMMdq_XMMdq", XED_IFORM_PMINUB_XMMdq_XMMdq},
{"PMINUD_XMMdq_MEMdq", XED_IFORM_PMINUD_XMMdq_MEMdq},
{"PMINUD_XMMdq_XMMdq", XED_IFORM_PMINUD_XMMdq_XMMdq},
{"PMINUW_XMMdq_MEMdq", XED_IFORM_PMINUW_XMMdq_MEMdq},
{"PMINUW_XMMdq_XMMdq", XED_IFORM_PMINUW_XMMdq_XMMdq},
{"PMOVMSKB_GPR32_MMXq", XED_IFORM_PMOVMSKB_GPR32_MMXq},
{"PMOVMSKB_GPR32_XMMdq", XED_IFORM_PMOVMSKB_GPR32_XMMdq},
{"PMOVSXBD_XMMdq_MEMd", XED_IFORM_PMOVSXBD_XMMdq_MEMd},
{"PMOVSXBD_XMMdq_XMMd", XED_IFORM_PMOVSXBD_XMMdq_XMMd},
{"PMOVSXBQ_XMMdq_MEMw", XED_IFORM_PMOVSXBQ_XMMdq_MEMw},
{"PMOVSXBQ_XMMdq_XMMw", XED_IFORM_PMOVSXBQ_XMMdq_XMMw},
{"PMOVSXBW_XMMdq_MEMq", XED_IFORM_PMOVSXBW_XMMdq_MEMq},
{"PMOVSXBW_XMMdq_XMMq", XED_IFORM_PMOVSXBW_XMMdq_XMMq},
{"PMOVSXDQ_XMMdq_MEMq", XED_IFORM_PMOVSXDQ_XMMdq_MEMq},
{"PMOVSXDQ_XMMdq_XMMq", XED_IFORM_PMOVSXDQ_XMMdq_XMMq},
{"PMOVSXWD_XMMdq_MEMq", XED_IFORM_PMOVSXWD_XMMdq_MEMq},
{"PMOVSXWD_XMMdq_XMMq", XED_IFORM_PMOVSXWD_XMMdq_XMMq},
{"PMOVSXWQ_XMMdq_MEMd", XED_IFORM_PMOVSXWQ_XMMdq_MEMd},
{"PMOVSXWQ_XMMdq_XMMd", XED_IFORM_PMOVSXWQ_XMMdq_XMMd},
{"PMOVZXBD_XMMdq_MEMd", XED_IFORM_PMOVZXBD_XMMdq_MEMd},
{"PMOVZXBD_XMMdq_XMMd", XED_IFORM_PMOVZXBD_XMMdq_XMMd},
{"PMOVZXBQ_XMMdq_MEMw", XED_IFORM_PMOVZXBQ_XMMdq_MEMw},
{"PMOVZXBQ_XMMdq_XMMw", XED_IFORM_PMOVZXBQ_XMMdq_XMMw},
{"PMOVZXBW_XMMdq_MEMq", XED_IFORM_PMOVZXBW_XMMdq_MEMq},
{"PMOVZXBW_XMMdq_XMMq", XED_IFORM_PMOVZXBW_XMMdq_XMMq},
{"PMOVZXDQ_XMMdq_MEMq", XED_IFORM_PMOVZXDQ_XMMdq_MEMq},
{"PMOVZXDQ_XMMdq_XMMq", XED_IFORM_PMOVZXDQ_XMMdq_XMMq},
{"PMOVZXWD_XMMdq_MEMq", XED_IFORM_PMOVZXWD_XMMdq_MEMq},
{"PMOVZXWD_XMMdq_XMMq", XED_IFORM_PMOVZXWD_XMMdq_XMMq},
{"PMOVZXWQ_XMMdq_MEMd", XED_IFORM_PMOVZXWQ_XMMdq_MEMd},
{"PMOVZXWQ_XMMdq_XMMd", XED_IFORM_PMOVZXWQ_XMMdq_XMMd},
{"PMULDQ_XMMdq_MEMdq", XED_IFORM_PMULDQ_XMMdq_MEMdq},
{"PMULDQ_XMMdq_XMMdq", XED_IFORM_PMULDQ_XMMdq_XMMdq},
{"PMULHRSW_MMXq_MEMq", XED_IFORM_PMULHRSW_MMXq_MEMq},
{"PMULHRSW_MMXq_MMXq", XED_IFORM_PMULHRSW_MMXq_MMXq},
{"PMULHRSW_XMMdq_MEMdq", XED_IFORM_PMULHRSW_XMMdq_MEMdq},
{"PMULHRSW_XMMdq_XMMdq", XED_IFORM_PMULHRSW_XMMdq_XMMdq},
{"PMULHRW_MMXq_MEMq", XED_IFORM_PMULHRW_MMXq_MEMq},
{"PMULHRW_MMXq_MMXq", XED_IFORM_PMULHRW_MMXq_MMXq},
{"PMULHUW_MMXq_MEMq", XED_IFORM_PMULHUW_MMXq_MEMq},
{"PMULHUW_MMXq_MMXq", XED_IFORM_PMULHUW_MMXq_MMXq},
{"PMULHUW_XMMdq_MEMdq", XED_IFORM_PMULHUW_XMMdq_MEMdq},
{"PMULHUW_XMMdq_XMMdq", XED_IFORM_PMULHUW_XMMdq_XMMdq},
{"PMULHW_MMXq_MEMq", XED_IFORM_PMULHW_MMXq_MEMq},
{"PMULHW_MMXq_MMXq", XED_IFORM_PMULHW_MMXq_MMXq},
{"PMULHW_XMMdq_MEMdq", XED_IFORM_PMULHW_XMMdq_MEMdq},
{"PMULHW_XMMdq_XMMdq", XED_IFORM_PMULHW_XMMdq_XMMdq},
{"PMULLD_XMMdq_MEMdq", XED_IFORM_PMULLD_XMMdq_MEMdq},
{"PMULLD_XMMdq_XMMdq", XED_IFORM_PMULLD_XMMdq_XMMdq},
{"PMULLW_MMXq_MEMq", XED_IFORM_PMULLW_MMXq_MEMq},
{"PMULLW_MMXq_MMXq", XED_IFORM_PMULLW_MMXq_MMXq},
{"PMULLW_XMMdq_MEMdq", XED_IFORM_PMULLW_XMMdq_MEMdq},
{"PMULLW_XMMdq_XMMdq", XED_IFORM_PMULLW_XMMdq_XMMdq},
{"PMULUDQ_MMXq_MEMq", XED_IFORM_PMULUDQ_MMXq_MEMq},
{"PMULUDQ_MMXq_MMXq", XED_IFORM_PMULUDQ_MMXq_MMXq},
{"PMULUDQ_XMMdq_MEMdq", XED_IFORM_PMULUDQ_XMMdq_MEMdq},
{"PMULUDQ_XMMdq_XMMdq", XED_IFORM_PMULUDQ_XMMdq_XMMdq},
{"POP_DS", XED_IFORM_POP_DS},
{"POP_ES", XED_IFORM_POP_ES},
{"POP_FS", XED_IFORM_POP_FS},
{"POP_GPRv_58", XED_IFORM_POP_GPRv_58},
{"POP_GPRv_8F", XED_IFORM_POP_GPRv_8F},
{"POP_GS", XED_IFORM_POP_GS},
{"POP_MEMv", XED_IFORM_POP_MEMv},
{"POP_SS", XED_IFORM_POP_SS},
{"POPA", XED_IFORM_POPA},
{"POPAD", XED_IFORM_POPAD},
{"POPCNT_GPRv_GPRv", XED_IFORM_POPCNT_GPRv_GPRv},
{"POPCNT_GPRv_MEMv", XED_IFORM_POPCNT_GPRv_MEMv},
{"POPF", XED_IFORM_POPF},
{"POPFD", XED_IFORM_POPFD},
{"POPFQ", XED_IFORM_POPFQ},
{"POR_MMXq_MEMq", XED_IFORM_POR_MMXq_MEMq},
{"POR_MMXq_MMXq", XED_IFORM_POR_MMXq_MMXq},
{"POR_XMMdq_MEMdq", XED_IFORM_POR_XMMdq_MEMdq},
{"POR_XMMdq_XMMdq", XED_IFORM_POR_XMMdq_XMMdq},
{"PREFETCHNTA_MEMmprefetch", XED_IFORM_PREFETCHNTA_MEMmprefetch},
{"PREFETCHT0_MEMmprefetch", XED_IFORM_PREFETCHT0_MEMmprefetch},
{"PREFETCHT1_MEMmprefetch", XED_IFORM_PREFETCHT1_MEMmprefetch},
{"PREFETCHT2_MEMmprefetch", XED_IFORM_PREFETCHT2_MEMmprefetch},
{"PREFETCHW_0F0Dr1", XED_IFORM_PREFETCHW_0F0Dr1},
{"PREFETCHW_0F0Dr3", XED_IFORM_PREFETCHW_0F0Dr3},
{"PREFETCHWT1_MEMu8", XED_IFORM_PREFETCHWT1_MEMu8},
{"PREFETCH_EXCLUSIVE_MEMmprefetch", XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch},
{"PREFETCH_RESERVED_0F0Dr4", XED_IFORM_PREFETCH_RESERVED_0F0Dr4},
{"PREFETCH_RESERVED_0F0Dr5", XED_IFORM_PREFETCH_RESERVED_0F0Dr5},
{"PREFETCH_RESERVED_0F0Dr6", XED_IFORM_PREFETCH_RESERVED_0F0Dr6},
{"PREFETCH_RESERVED_0F0Dr7", XED_IFORM_PREFETCH_RESERVED_0F0Dr7},
{"PSADBW_MMXq_MEMq", XED_IFORM_PSADBW_MMXq_MEMq},
{"PSADBW_MMXq_MMXq", XED_IFORM_PSADBW_MMXq_MMXq},
{"PSADBW_XMMdq_MEMdq", XED_IFORM_PSADBW_XMMdq_MEMdq},
{"PSADBW_XMMdq_XMMdq", XED_IFORM_PSADBW_XMMdq_XMMdq},
{"PSHUFB_MMXq_MEMq", XED_IFORM_PSHUFB_MMXq_MEMq},
{"PSHUFB_MMXq_MMXq", XED_IFORM_PSHUFB_MMXq_MMXq},
{"PSHUFB_XMMdq_MEMdq", XED_IFORM_PSHUFB_XMMdq_MEMdq},
{"PSHUFB_XMMdq_XMMdq", XED_IFORM_PSHUFB_XMMdq_XMMdq},
{"PSHUFD_XMMdq_MEMdq_IMMb", XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb},
{"PSHUFD_XMMdq_XMMdq_IMMb", XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb},
{"PSHUFHW_XMMdq_MEMdq_IMMb", XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb},
{"PSHUFHW_XMMdq_XMMdq_IMMb", XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb},
{"PSHUFLW_XMMdq_MEMdq_IMMb", XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb},
{"PSHUFLW_XMMdq_XMMdq_IMMb", XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb},
{"PSHUFW_MMXq_MEMq_IMMb", XED_IFORM_PSHUFW_MMXq_MEMq_IMMb},
{"PSHUFW_MMXq_MMXq_IMMb", XED_IFORM_PSHUFW_MMXq_MMXq_IMMb},
{"PSIGNB_MMXq_MEMq", XED_IFORM_PSIGNB_MMXq_MEMq},
{"PSIGNB_MMXq_MMXq", XED_IFORM_PSIGNB_MMXq_MMXq},
{"PSIGNB_XMMdq_MEMdq", XED_IFORM_PSIGNB_XMMdq_MEMdq},
{"PSIGNB_XMMdq_XMMdq", XED_IFORM_PSIGNB_XMMdq_XMMdq},
{"PSIGND_MMXq_MEMq", XED_IFORM_PSIGND_MMXq_MEMq},
{"PSIGND_MMXq_MMXq", XED_IFORM_PSIGND_MMXq_MMXq},
{"PSIGND_XMMdq_MEMdq", XED_IFORM_PSIGND_XMMdq_MEMdq},
{"PSIGND_XMMdq_XMMdq", XED_IFORM_PSIGND_XMMdq_XMMdq},
{"PSIGNW_MMXq_MEMq", XED_IFORM_PSIGNW_MMXq_MEMq},
{"PSIGNW_MMXq_MMXq", XED_IFORM_PSIGNW_MMXq_MMXq},
{"PSIGNW_XMMdq_MEMdq", XED_IFORM_PSIGNW_XMMdq_MEMdq},
{"PSIGNW_XMMdq_XMMdq", XED_IFORM_PSIGNW_XMMdq_XMMdq},
{"PSLLD_MMXq_IMMb", XED_IFORM_PSLLD_MMXq_IMMb},
{"PSLLD_MMXq_MEMq", XED_IFORM_PSLLD_MMXq_MEMq},
{"PSLLD_MMXq_MMXq", XED_IFORM_PSLLD_MMXq_MMXq},
{"PSLLD_XMMdq_IMMb", XED_IFORM_PSLLD_XMMdq_IMMb},
{"PSLLD_XMMdq_MEMdq", XED_IFORM_PSLLD_XMMdq_MEMdq},
{"PSLLD_XMMdq_XMMdq", XED_IFORM_PSLLD_XMMdq_XMMdq},
{"PSLLDQ_XMMdq_IMMb", XED_IFORM_PSLLDQ_XMMdq_IMMb},
{"PSLLQ_MMXq_IMMb", XED_IFORM_PSLLQ_MMXq_IMMb},
{"PSLLQ_MMXq_MEMq", XED_IFORM_PSLLQ_MMXq_MEMq},
{"PSLLQ_MMXq_MMXq", XED_IFORM_PSLLQ_MMXq_MMXq},
{"PSLLQ_XMMdq_IMMb", XED_IFORM_PSLLQ_XMMdq_IMMb},
{"PSLLQ_XMMdq_MEMdq", XED_IFORM_PSLLQ_XMMdq_MEMdq},
{"PSLLQ_XMMdq_XMMdq", XED_IFORM_PSLLQ_XMMdq_XMMdq},
{"PSLLW_MMXq_IMMb", XED_IFORM_PSLLW_MMXq_IMMb},
{"PSLLW_MMXq_MEMq", XED_IFORM_PSLLW_MMXq_MEMq},
{"PSLLW_MMXq_MMXq", XED_IFORM_PSLLW_MMXq_MMXq},
{"PSLLW_XMMdq_IMMb", XED_IFORM_PSLLW_XMMdq_IMMb},
{"PSLLW_XMMdq_MEMdq", XED_IFORM_PSLLW_XMMdq_MEMdq},
{"PSLLW_XMMdq_XMMdq", XED_IFORM_PSLLW_XMMdq_XMMdq},
{"PSMASH_RAX", XED_IFORM_PSMASH_RAX},
{"PSRAD_MMXq_IMMb", XED_IFORM_PSRAD_MMXq_IMMb},
{"PSRAD_MMXq_MEMq", XED_IFORM_PSRAD_MMXq_MEMq},
{"PSRAD_MMXq_MMXq", XED_IFORM_PSRAD_MMXq_MMXq},
{"PSRAD_XMMdq_IMMb", XED_IFORM_PSRAD_XMMdq_IMMb},
{"PSRAD_XMMdq_MEMdq", XED_IFORM_PSRAD_XMMdq_MEMdq},
{"PSRAD_XMMdq_XMMdq", XED_IFORM_PSRAD_XMMdq_XMMdq},
{"PSRAW_MMXq_IMMb", XED_IFORM_PSRAW_MMXq_IMMb},
{"PSRAW_MMXq_MEMq", XED_IFORM_PSRAW_MMXq_MEMq},
{"PSRAW_MMXq_MMXq", XED_IFORM_PSRAW_MMXq_MMXq},
{"PSRAW_XMMdq_IMMb", XED_IFORM_PSRAW_XMMdq_IMMb},
{"PSRAW_XMMdq_MEMdq", XED_IFORM_PSRAW_XMMdq_MEMdq},
{"PSRAW_XMMdq_XMMdq", XED_IFORM_PSRAW_XMMdq_XMMdq},
{"PSRLD_MMXq_IMMb", XED_IFORM_PSRLD_MMXq_IMMb},
{"PSRLD_MMXq_MEMq", XED_IFORM_PSRLD_MMXq_MEMq},
{"PSRLD_MMXq_MMXq", XED_IFORM_PSRLD_MMXq_MMXq},
{"PSRLD_XMMdq_IMMb", XED_IFORM_PSRLD_XMMdq_IMMb},
{"PSRLD_XMMdq_MEMdq", XED_IFORM_PSRLD_XMMdq_MEMdq},
{"PSRLD_XMMdq_XMMdq", XED_IFORM_PSRLD_XMMdq_XMMdq},
{"PSRLDQ_XMMdq_IMMb", XED_IFORM_PSRLDQ_XMMdq_IMMb},
{"PSRLQ_MMXq_IMMb", XED_IFORM_PSRLQ_MMXq_IMMb},
{"PSRLQ_MMXq_MEMq", XED_IFORM_PSRLQ_MMXq_MEMq},
{"PSRLQ_MMXq_MMXq", XED_IFORM_PSRLQ_MMXq_MMXq},
{"PSRLQ_XMMdq_IMMb", XED_IFORM_PSRLQ_XMMdq_IMMb},
{"PSRLQ_XMMdq_MEMdq", XED_IFORM_PSRLQ_XMMdq_MEMdq},
{"PSRLQ_XMMdq_XMMdq", XED_IFORM_PSRLQ_XMMdq_XMMdq},
{"PSRLW_MMXq_IMMb", XED_IFORM_PSRLW_MMXq_IMMb},
{"PSRLW_MMXq_MEMq", XED_IFORM_PSRLW_MMXq_MEMq},
{"PSRLW_MMXq_MMXq", XED_IFORM_PSRLW_MMXq_MMXq},
{"PSRLW_XMMdq_IMMb", XED_IFORM_PSRLW_XMMdq_IMMb},
{"PSRLW_XMMdq_MEMdq", XED_IFORM_PSRLW_XMMdq_MEMdq},
{"PSRLW_XMMdq_XMMdq", XED_IFORM_PSRLW_XMMdq_XMMdq},
{"PSUBB_MMXq_MEMq", XED_IFORM_PSUBB_MMXq_MEMq},
{"PSUBB_MMXq_MMXq", XED_IFORM_PSUBB_MMXq_MMXq},
{"PSUBB_XMMdq_MEMdq", XED_IFORM_PSUBB_XMMdq_MEMdq},
{"PSUBB_XMMdq_XMMdq", XED_IFORM_PSUBB_XMMdq_XMMdq},
{"PSUBD_MMXq_MEMq", XED_IFORM_PSUBD_MMXq_MEMq},
{"PSUBD_MMXq_MMXq", XED_IFORM_PSUBD_MMXq_MMXq},
{"PSUBD_XMMdq_MEMdq", XED_IFORM_PSUBD_XMMdq_MEMdq},
{"PSUBD_XMMdq_XMMdq", XED_IFORM_PSUBD_XMMdq_XMMdq},
{"PSUBQ_MMXq_MEMq", XED_IFORM_PSUBQ_MMXq_MEMq},
{"PSUBQ_MMXq_MMXq", XED_IFORM_PSUBQ_MMXq_MMXq},
{"PSUBQ_XMMdq_MEMdq", XED_IFORM_PSUBQ_XMMdq_MEMdq},
{"PSUBQ_XMMdq_XMMdq", XED_IFORM_PSUBQ_XMMdq_XMMdq},
{"PSUBSB_MMXq_MEMq", XED_IFORM_PSUBSB_MMXq_MEMq},
{"PSUBSB_MMXq_MMXq", XED_IFORM_PSUBSB_MMXq_MMXq},
{"PSUBSB_XMMdq_MEMdq", XED_IFORM_PSUBSB_XMMdq_MEMdq},
{"PSUBSB_XMMdq_XMMdq", XED_IFORM_PSUBSB_XMMdq_XMMdq},
{"PSUBSW_MMXq_MEMq", XED_IFORM_PSUBSW_MMXq_MEMq},
{"PSUBSW_MMXq_MMXq", XED_IFORM_PSUBSW_MMXq_MMXq},
{"PSUBSW_XMMdq_MEMdq", XED_IFORM_PSUBSW_XMMdq_MEMdq},
{"PSUBSW_XMMdq_XMMdq", XED_IFORM_PSUBSW_XMMdq_XMMdq},
{"PSUBUSB_MMXq_MEMq", XED_IFORM_PSUBUSB_MMXq_MEMq},
{"PSUBUSB_MMXq_MMXq", XED_IFORM_PSUBUSB_MMXq_MMXq},
{"PSUBUSB_XMMdq_MEMdq", XED_IFORM_PSUBUSB_XMMdq_MEMdq},
{"PSUBUSB_XMMdq_XMMdq", XED_IFORM_PSUBUSB_XMMdq_XMMdq},
{"PSUBUSW_MMXq_MEMq", XED_IFORM_PSUBUSW_MMXq_MEMq},
{"PSUBUSW_MMXq_MMXq", XED_IFORM_PSUBUSW_MMXq_MMXq},
{"PSUBUSW_XMMdq_MEMdq", XED_IFORM_PSUBUSW_XMMdq_MEMdq},
{"PSUBUSW_XMMdq_XMMdq", XED_IFORM_PSUBUSW_XMMdq_XMMdq},
{"PSUBW_MMXq_MEMq", XED_IFORM_PSUBW_MMXq_MEMq},
{"PSUBW_MMXq_MMXq", XED_IFORM_PSUBW_MMXq_MMXq},
{"PSUBW_XMMdq_MEMdq", XED_IFORM_PSUBW_XMMdq_MEMdq},
{"PSUBW_XMMdq_XMMdq", XED_IFORM_PSUBW_XMMdq_XMMdq},
{"PSWAPD_MMXq_MEMq", XED_IFORM_PSWAPD_MMXq_MEMq},
{"PSWAPD_MMXq_MMXq", XED_IFORM_PSWAPD_MMXq_MMXq},
{"PTEST_XMMdq_MEMdq", XED_IFORM_PTEST_XMMdq_MEMdq},
{"PTEST_XMMdq_XMMdq", XED_IFORM_PTEST_XMMdq_XMMdq},
{"PTWRITE_GPRy", XED_IFORM_PTWRITE_GPRy},
{"PTWRITE_MEMy", XED_IFORM_PTWRITE_MEMy},
{"PUNPCKHBW_MMXq_MEMq", XED_IFORM_PUNPCKHBW_MMXq_MEMq},
{"PUNPCKHBW_MMXq_MMXd", XED_IFORM_PUNPCKHBW_MMXq_MMXd},
{"PUNPCKHBW_XMMdq_MEMdq", XED_IFORM_PUNPCKHBW_XMMdq_MEMdq},
{"PUNPCKHBW_XMMdq_XMMq", XED_IFORM_PUNPCKHBW_XMMdq_XMMq},
{"PUNPCKHDQ_MMXq_MEMq", XED_IFORM_PUNPCKHDQ_MMXq_MEMq},
{"PUNPCKHDQ_MMXq_MMXd", XED_IFORM_PUNPCKHDQ_MMXq_MMXd},
{"PUNPCKHDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq},
{"PUNPCKHDQ_XMMdq_XMMq", XED_IFORM_PUNPCKHDQ_XMMdq_XMMq},
{"PUNPCKHQDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq},
{"PUNPCKHQDQ_XMMdq_XMMq", XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq},
{"PUNPCKHWD_MMXq_MEMq", XED_IFORM_PUNPCKHWD_MMXq_MEMq},
{"PUNPCKHWD_MMXq_MMXd", XED_IFORM_PUNPCKHWD_MMXq_MMXd},
{"PUNPCKHWD_XMMdq_MEMdq", XED_IFORM_PUNPCKHWD_XMMdq_MEMdq},
{"PUNPCKHWD_XMMdq_XMMq", XED_IFORM_PUNPCKHWD_XMMdq_XMMq},
{"PUNPCKLBW_MMXq_MEMd", XED_IFORM_PUNPCKLBW_MMXq_MEMd},
{"PUNPCKLBW_MMXq_MMXd", XED_IFORM_PUNPCKLBW_MMXq_MMXd},
{"PUNPCKLBW_XMMdq_MEMdq", XED_IFORM_PUNPCKLBW_XMMdq_MEMdq},
{"PUNPCKLBW_XMMdq_XMMq", XED_IFORM_PUNPCKLBW_XMMdq_XMMq},
{"PUNPCKLDQ_MMXq_MEMd", XED_IFORM_PUNPCKLDQ_MMXq_MEMd},
{"PUNPCKLDQ_MMXq_MMXd", XED_IFORM_PUNPCKLDQ_MMXq_MMXd},
{"PUNPCKLDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq},
{"PUNPCKLDQ_XMMdq_XMMq", XED_IFORM_PUNPCKLDQ_XMMdq_XMMq},
{"PUNPCKLQDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq},
{"PUNPCKLQDQ_XMMdq_XMMq", XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq},
{"PUNPCKLWD_MMXq_MEMd", XED_IFORM_PUNPCKLWD_MMXq_MEMd},
{"PUNPCKLWD_MMXq_MMXd", XED_IFORM_PUNPCKLWD_MMXq_MMXd},
{"PUNPCKLWD_XMMdq_MEMdq", XED_IFORM_PUNPCKLWD_XMMdq_MEMdq},
{"PUNPCKLWD_XMMdq_XMMq", XED_IFORM_PUNPCKLWD_XMMdq_XMMq},
{"PUSH_CS", XED_IFORM_PUSH_CS},
{"PUSH_DS", XED_IFORM_PUSH_DS},
{"PUSH_ES", XED_IFORM_PUSH_ES},
{"PUSH_FS", XED_IFORM_PUSH_FS},
{"PUSH_GPRv_50", XED_IFORM_PUSH_GPRv_50},
{"PUSH_GPRv_FFr6", XED_IFORM_PUSH_GPRv_FFr6},
{"PUSH_GS", XED_IFORM_PUSH_GS},
{"PUSH_IMMb", XED_IFORM_PUSH_IMMb},
{"PUSH_IMMz", XED_IFORM_PUSH_IMMz},
{"PUSH_MEMv", XED_IFORM_PUSH_MEMv},
{"PUSH_SS", XED_IFORM_PUSH_SS},
{"PUSHA", XED_IFORM_PUSHA},
{"PUSHAD", XED_IFORM_PUSHAD},
{"PUSHF", XED_IFORM_PUSHF},
{"PUSHFD", XED_IFORM_PUSHFD},
{"PUSHFQ", XED_IFORM_PUSHFQ},
{"PVALIDATE_RAX_ECX_EDX", XED_IFORM_PVALIDATE_RAX_ECX_EDX},
{"PXOR_MMXq_MEMq", XED_IFORM_PXOR_MMXq_MEMq},
{"PXOR_MMXq_MMXq", XED_IFORM_PXOR_MMXq_MMXq},
{"PXOR_XMMdq_MEMdq", XED_IFORM_PXOR_XMMdq_MEMdq},
{"PXOR_XMMdq_XMMdq", XED_IFORM_PXOR_XMMdq_XMMdq},
{"RCL_GPR8_CL", XED_IFORM_RCL_GPR8_CL},
{"RCL_GPR8_IMMb", XED_IFORM_RCL_GPR8_IMMb},
{"RCL_GPR8_ONE", XED_IFORM_RCL_GPR8_ONE},
{"RCL_GPRv_CL", XED_IFORM_RCL_GPRv_CL},
{"RCL_GPRv_IMMb", XED_IFORM_RCL_GPRv_IMMb},
{"RCL_GPRv_ONE", XED_IFORM_RCL_GPRv_ONE},
{"RCL_MEMb_CL", XED_IFORM_RCL_MEMb_CL},
{"RCL_MEMb_IMMb", XED_IFORM_RCL_MEMb_IMMb},
{"RCL_MEMb_ONE", XED_IFORM_RCL_MEMb_ONE},
{"RCL_MEMv_CL", XED_IFORM_RCL_MEMv_CL},
{"RCL_MEMv_IMMb", XED_IFORM_RCL_MEMv_IMMb},
{"RCL_MEMv_ONE", XED_IFORM_RCL_MEMv_ONE},
{"RCPPS_XMMps_MEMps", XED_IFORM_RCPPS_XMMps_MEMps},
{"RCPPS_XMMps_XMMps", XED_IFORM_RCPPS_XMMps_XMMps},
{"RCPSS_XMMss_MEMss", XED_IFORM_RCPSS_XMMss_MEMss},
{"RCPSS_XMMss_XMMss", XED_IFORM_RCPSS_XMMss_XMMss},
{"RCR_GPR8_CL", XED_IFORM_RCR_GPR8_CL},
{"RCR_GPR8_IMMb", XED_IFORM_RCR_GPR8_IMMb},
{"RCR_GPR8_ONE", XED_IFORM_RCR_GPR8_ONE},
{"RCR_GPRv_CL", XED_IFORM_RCR_GPRv_CL},
{"RCR_GPRv_IMMb", XED_IFORM_RCR_GPRv_IMMb},
{"RCR_GPRv_ONE", XED_IFORM_RCR_GPRv_ONE},
{"RCR_MEMb_CL", XED_IFORM_RCR_MEMb_CL},
{"RCR_MEMb_IMMb", XED_IFORM_RCR_MEMb_IMMb},
{"RCR_MEMb_ONE", XED_IFORM_RCR_MEMb_ONE},
{"RCR_MEMv_CL", XED_IFORM_RCR_MEMv_CL},
{"RCR_MEMv_IMMb", XED_IFORM_RCR_MEMv_IMMb},
{"RCR_MEMv_ONE", XED_IFORM_RCR_MEMv_ONE},
{"RDFSBASE_GPRy", XED_IFORM_RDFSBASE_GPRy},
{"RDGSBASE_GPRy", XED_IFORM_RDGSBASE_GPRy},
{"RDMSR", XED_IFORM_RDMSR},
{"RDPID_GPR32u32", XED_IFORM_RDPID_GPR32u32},
{"RDPID_GPR64u64", XED_IFORM_RDPID_GPR64u64},
{"RDPKRU", XED_IFORM_RDPKRU},
{"RDPMC", XED_IFORM_RDPMC},
{"RDPRU", XED_IFORM_RDPRU},
{"RDRAND_GPRv", XED_IFORM_RDRAND_GPRv},
{"RDSEED_GPRv", XED_IFORM_RDSEED_GPRv},
{"RDSSPD_GPR32u32", XED_IFORM_RDSSPD_GPR32u32},
{"RDSSPQ_GPR64u64", XED_IFORM_RDSSPQ_GPR64u64},
{"RDTSC", XED_IFORM_RDTSC},
{"RDTSCP", XED_IFORM_RDTSCP},
{"REPE_CMPSB", XED_IFORM_REPE_CMPSB},
{"REPE_CMPSD", XED_IFORM_REPE_CMPSD},
{"REPE_CMPSQ", XED_IFORM_REPE_CMPSQ},
{"REPE_CMPSW", XED_IFORM_REPE_CMPSW},
{"REPE_SCASB", XED_IFORM_REPE_SCASB},
{"REPE_SCASD", XED_IFORM_REPE_SCASD},
{"REPE_SCASQ", XED_IFORM_REPE_SCASQ},
{"REPE_SCASW", XED_IFORM_REPE_SCASW},
{"REPNE_CMPSB", XED_IFORM_REPNE_CMPSB},
{"REPNE_CMPSD", XED_IFORM_REPNE_CMPSD},
{"REPNE_CMPSQ", XED_IFORM_REPNE_CMPSQ},
{"REPNE_CMPSW", XED_IFORM_REPNE_CMPSW},
{"REPNE_SCASB", XED_IFORM_REPNE_SCASB},
{"REPNE_SCASD", XED_IFORM_REPNE_SCASD},
{"REPNE_SCASQ", XED_IFORM_REPNE_SCASQ},
{"REPNE_SCASW", XED_IFORM_REPNE_SCASW},
{"REP_INSB", XED_IFORM_REP_INSB},
{"REP_INSD", XED_IFORM_REP_INSD},
{"REP_INSW", XED_IFORM_REP_INSW},
{"REP_LODSB", XED_IFORM_REP_LODSB},
{"REP_LODSD", XED_IFORM_REP_LODSD},
{"REP_LODSQ", XED_IFORM_REP_LODSQ},
{"REP_LODSW", XED_IFORM_REP_LODSW},
{"REP_MONTMUL", XED_IFORM_REP_MONTMUL},
{"REP_MOVSB", XED_IFORM_REP_MOVSB},
{"REP_MOVSD", XED_IFORM_REP_MOVSD},
{"REP_MOVSQ", XED_IFORM_REP_MOVSQ},
{"REP_MOVSW", XED_IFORM_REP_MOVSW},
{"REP_OUTSB", XED_IFORM_REP_OUTSB},
{"REP_OUTSD", XED_IFORM_REP_OUTSD},
{"REP_OUTSW", XED_IFORM_REP_OUTSW},
{"REP_STOSB", XED_IFORM_REP_STOSB},
{"REP_STOSD", XED_IFORM_REP_STOSD},
{"REP_STOSQ", XED_IFORM_REP_STOSQ},
{"REP_STOSW", XED_IFORM_REP_STOSW},
{"REP_XCRYPTCBC", XED_IFORM_REP_XCRYPTCBC},
{"REP_XCRYPTCFB", XED_IFORM_REP_XCRYPTCFB},
{"REP_XCRYPTCTR", XED_IFORM_REP_XCRYPTCTR},
{"REP_XCRYPTECB", XED_IFORM_REP_XCRYPTECB},
{"REP_XCRYPTOFB", XED_IFORM_REP_XCRYPTOFB},
{"REP_XSHA1", XED_IFORM_REP_XSHA1},
{"REP_XSHA256", XED_IFORM_REP_XSHA256},
{"REP_XSTORE", XED_IFORM_REP_XSTORE},
{"RET_FAR", XED_IFORM_RET_FAR},
{"RET_FAR_IMMw", XED_IFORM_RET_FAR_IMMw},
{"RET_NEAR", XED_IFORM_RET_NEAR},
{"RET_NEAR_IMMw", XED_IFORM_RET_NEAR_IMMw},
{"RMPADJUST_RAX_RCX_RDX", XED_IFORM_RMPADJUST_RAX_RCX_RDX},
{"RMPUPDATE_RAX_RCX", XED_IFORM_RMPUPDATE_RAX_RCX},
{"ROL_GPR8_CL", XED_IFORM_ROL_GPR8_CL},
{"ROL_GPR8_IMMb", XED_IFORM_ROL_GPR8_IMMb},
{"ROL_GPR8_ONE", XED_IFORM_ROL_GPR8_ONE},
{"ROL_GPRv_CL", XED_IFORM_ROL_GPRv_CL},
{"ROL_GPRv_IMMb", XED_IFORM_ROL_GPRv_IMMb},
{"ROL_GPRv_ONE", XED_IFORM_ROL_GPRv_ONE},
{"ROL_MEMb_CL", XED_IFORM_ROL_MEMb_CL},
{"ROL_MEMb_IMMb", XED_IFORM_ROL_MEMb_IMMb},
{"ROL_MEMb_ONE", XED_IFORM_ROL_MEMb_ONE},
{"ROL_MEMv_CL", XED_IFORM_ROL_MEMv_CL},
{"ROL_MEMv_IMMb", XED_IFORM_ROL_MEMv_IMMb},
{"ROL_MEMv_ONE", XED_IFORM_ROL_MEMv_ONE},
{"ROR_GPR8_CL", XED_IFORM_ROR_GPR8_CL},
{"ROR_GPR8_IMMb", XED_IFORM_ROR_GPR8_IMMb},
{"ROR_GPR8_ONE", XED_IFORM_ROR_GPR8_ONE},
{"ROR_GPRv_CL", XED_IFORM_ROR_GPRv_CL},
{"ROR_GPRv_IMMb", XED_IFORM_ROR_GPRv_IMMb},
{"ROR_GPRv_ONE", XED_IFORM_ROR_GPRv_ONE},
{"ROR_MEMb_CL", XED_IFORM_ROR_MEMb_CL},
{"ROR_MEMb_IMMb", XED_IFORM_ROR_MEMb_IMMb},
{"ROR_MEMb_ONE", XED_IFORM_ROR_MEMb_ONE},
{"ROR_MEMv_CL", XED_IFORM_ROR_MEMv_CL},
{"ROR_MEMv_IMMb", XED_IFORM_ROR_MEMv_IMMb},
{"ROR_MEMv_ONE", XED_IFORM_ROR_MEMv_ONE},
{"RORX_VGPR32d_MEMd_IMMb", XED_IFORM_RORX_VGPR32d_MEMd_IMMb},
{"RORX_VGPR32d_VGPR32d_IMMb", XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb},
{"RORX_VGPR64q_MEMq_IMMb", XED_IFORM_RORX_VGPR64q_MEMq_IMMb},
{"RORX_VGPR64q_VGPR64q_IMMb", XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb},
{"ROUNDPD_XMMpd_MEMpd_IMMb", XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb},
{"ROUNDPD_XMMpd_XMMpd_IMMb", XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb},
{"ROUNDPS_XMMps_MEMps_IMMb", XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb},
{"ROUNDPS_XMMps_XMMps_IMMb", XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb},
{"ROUNDSD_XMMq_MEMq_IMMb", XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb},
{"ROUNDSD_XMMq_XMMq_IMMb", XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb},
{"ROUNDSS_XMMd_MEMd_IMMb", XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb},
{"ROUNDSS_XMMd_XMMd_IMMb", XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb},
{"RSM", XED_IFORM_RSM},
{"RSQRTPS_XMMps_MEMps", XED_IFORM_RSQRTPS_XMMps_MEMps},
{"RSQRTPS_XMMps_XMMps", XED_IFORM_RSQRTPS_XMMps_XMMps},
{"RSQRTSS_XMMss_MEMss", XED_IFORM_RSQRTSS_XMMss_MEMss},
{"RSQRTSS_XMMss_XMMss", XED_IFORM_RSQRTSS_XMMss_XMMss},
{"RSTORSSP_MEMu64", XED_IFORM_RSTORSSP_MEMu64},
{"SAHF", XED_IFORM_SAHF},
{"SALC", XED_IFORM_SALC},
{"SAR_GPR8_CL", XED_IFORM_SAR_GPR8_CL},
{"SAR_GPR8_IMMb", XED_IFORM_SAR_GPR8_IMMb},
{"SAR_GPR8_ONE", XED_IFORM_SAR_GPR8_ONE},
{"SAR_GPRv_CL", XED_IFORM_SAR_GPRv_CL},
{"SAR_GPRv_IMMb", XED_IFORM_SAR_GPRv_IMMb},
{"SAR_GPRv_ONE", XED_IFORM_SAR_GPRv_ONE},
{"SAR_MEMb_CL", XED_IFORM_SAR_MEMb_CL},
{"SAR_MEMb_IMMb", XED_IFORM_SAR_MEMb_IMMb},
{"SAR_MEMb_ONE", XED_IFORM_SAR_MEMb_ONE},
{"SAR_MEMv_CL", XED_IFORM_SAR_MEMv_CL},
{"SAR_MEMv_IMMb", XED_IFORM_SAR_MEMv_IMMb},
{"SAR_MEMv_ONE", XED_IFORM_SAR_MEMv_ONE},
{"SARX_VGPR32d_MEMd_VGPR32d", XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d},
{"SARX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d},
{"SARX_VGPR64q_MEMq_VGPR64q", XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q},
{"SARX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q},
{"SAVEPREVSSP", XED_IFORM_SAVEPREVSSP},
{"SBB_AL_IMMb", XED_IFORM_SBB_AL_IMMb},
{"SBB_GPR8_GPR8_18", XED_IFORM_SBB_GPR8_GPR8_18},
{"SBB_GPR8_GPR8_1A", XED_IFORM_SBB_GPR8_GPR8_1A},
{"SBB_GPR8_IMMb_80r3", XED_IFORM_SBB_GPR8_IMMb_80r3},
{"SBB_GPR8_IMMb_82r3", XED_IFORM_SBB_GPR8_IMMb_82r3},
{"SBB_GPR8_MEMb", XED_IFORM_SBB_GPR8_MEMb},
{"SBB_GPRv_GPRv_19", XED_IFORM_SBB_GPRv_GPRv_19},
{"SBB_GPRv_GPRv_1B", XED_IFORM_SBB_GPRv_GPRv_1B},
{"SBB_GPRv_IMMb", XED_IFORM_SBB_GPRv_IMMb},
{"SBB_GPRv_IMMz", XED_IFORM_SBB_GPRv_IMMz},
{"SBB_GPRv_MEMv", XED_IFORM_SBB_GPRv_MEMv},
{"SBB_MEMb_GPR8", XED_IFORM_SBB_MEMb_GPR8},
{"SBB_MEMb_IMMb_80r3", XED_IFORM_SBB_MEMb_IMMb_80r3},
{"SBB_MEMb_IMMb_82r3", XED_IFORM_SBB_MEMb_IMMb_82r3},
{"SBB_MEMv_GPRv", XED_IFORM_SBB_MEMv_GPRv},
{"SBB_MEMv_IMMb", XED_IFORM_SBB_MEMv_IMMb},
{"SBB_MEMv_IMMz", XED_IFORM_SBB_MEMv_IMMz},
{"SBB_OrAX_IMMz", XED_IFORM_SBB_OrAX_IMMz},
{"SBB_LOCK_MEMb_GPR8", XED_IFORM_SBB_LOCK_MEMb_GPR8},
{"SBB_LOCK_MEMb_IMMb_80r3", XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3},
{"SBB_LOCK_MEMb_IMMb_82r3", XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3},
{"SBB_LOCK_MEMv_GPRv", XED_IFORM_SBB_LOCK_MEMv_GPRv},
{"SBB_LOCK_MEMv_IMMb", XED_IFORM_SBB_LOCK_MEMv_IMMb},
{"SBB_LOCK_MEMv_IMMz", XED_IFORM_SBB_LOCK_MEMv_IMMz},
{"SCASB", XED_IFORM_SCASB},
{"SCASD", XED_IFORM_SCASD},
{"SCASQ", XED_IFORM_SCASQ},
{"SCASW", XED_IFORM_SCASW},
{"SEAMCALL", XED_IFORM_SEAMCALL},
{"SEAMOPS", XED_IFORM_SEAMOPS},
{"SEAMRET", XED_IFORM_SEAMRET},
{"SENDUIPI_GPR32u32", XED_IFORM_SENDUIPI_GPR32u32},
{"SERIALIZE", XED_IFORM_SERIALIZE},
{"SETB_GPR8", XED_IFORM_SETB_GPR8},
{"SETB_MEMb", XED_IFORM_SETB_MEMb},
{"SETBE_GPR8", XED_IFORM_SETBE_GPR8},
{"SETBE_MEMb", XED_IFORM_SETBE_MEMb},
{"SETL_GPR8", XED_IFORM_SETL_GPR8},
{"SETL_MEMb", XED_IFORM_SETL_MEMb},
{"SETLE_GPR8", XED_IFORM_SETLE_GPR8},
{"SETLE_MEMb", XED_IFORM_SETLE_MEMb},
{"SETNB_GPR8", XED_IFORM_SETNB_GPR8},
{"SETNB_MEMb", XED_IFORM_SETNB_MEMb},
{"SETNBE_GPR8", XED_IFORM_SETNBE_GPR8},
{"SETNBE_MEMb", XED_IFORM_SETNBE_MEMb},
{"SETNL_GPR8", XED_IFORM_SETNL_GPR8},
{"SETNL_MEMb", XED_IFORM_SETNL_MEMb},
{"SETNLE_GPR8", XED_IFORM_SETNLE_GPR8},
{"SETNLE_MEMb", XED_IFORM_SETNLE_MEMb},
{"SETNO_GPR8", XED_IFORM_SETNO_GPR8},
{"SETNO_MEMb", XED_IFORM_SETNO_MEMb},
{"SETNP_GPR8", XED_IFORM_SETNP_GPR8},
{"SETNP_MEMb", XED_IFORM_SETNP_MEMb},
{"SETNS_GPR8", XED_IFORM_SETNS_GPR8},
{"SETNS_MEMb", XED_IFORM_SETNS_MEMb},
{"SETNZ_GPR8", XED_IFORM_SETNZ_GPR8},
{"SETNZ_MEMb", XED_IFORM_SETNZ_MEMb},
{"SETO_GPR8", XED_IFORM_SETO_GPR8},
{"SETO_MEMb", XED_IFORM_SETO_MEMb},
{"SETP_GPR8", XED_IFORM_SETP_GPR8},
{"SETP_MEMb", XED_IFORM_SETP_MEMb},
{"SETS_GPR8", XED_IFORM_SETS_GPR8},
{"SETS_MEMb", XED_IFORM_SETS_MEMb},
{"SETSSBSY", XED_IFORM_SETSSBSY},
{"SETZ_GPR8", XED_IFORM_SETZ_GPR8},
{"SETZ_MEMb", XED_IFORM_SETZ_MEMb},
{"SFENCE", XED_IFORM_SFENCE},
{"SGDT_MEMs", XED_IFORM_SGDT_MEMs},
{"SGDT_MEMs64", XED_IFORM_SGDT_MEMs64},
{"SHA1MSG1_XMMi32_MEMi32_SHA", XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA},
{"SHA1MSG1_XMMi32_XMMi32_SHA", XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA},
{"SHA1MSG2_XMMi32_MEMi32_SHA", XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA},
{"SHA1MSG2_XMMi32_XMMi32_SHA", XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA},
{"SHA1NEXTE_XMMi32_MEMi32_SHA", XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA},
{"SHA1NEXTE_XMMi32_XMMi32_SHA", XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA},
{"SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA", XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA},
{"SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA", XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA},
{"SHA256MSG1_XMMi32_MEMi32_SHA", XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA},
{"SHA256MSG1_XMMi32_XMMi32_SHA", XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA},
{"SHA256MSG2_XMMi32_MEMi32_SHA", XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA},
{"SHA256MSG2_XMMi32_XMMi32_SHA", XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA},
{"SHA256RNDS2_XMMi32_MEMi32_SHA", XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA},
{"SHA256RNDS2_XMMi32_XMMi32_SHA", XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA},
{"SHL_GPR8_CL_D2r4", XED_IFORM_SHL_GPR8_CL_D2r4},
{"SHL_GPR8_CL_D2r6", XED_IFORM_SHL_GPR8_CL_D2r6},
{"SHL_GPR8_IMMb_C0r4", XED_IFORM_SHL_GPR8_IMMb_C0r4},
{"SHL_GPR8_IMMb_C0r6", XED_IFORM_SHL_GPR8_IMMb_C0r6},
{"SHL_GPR8_ONE_D0r4", XED_IFORM_SHL_GPR8_ONE_D0r4},
{"SHL_GPR8_ONE_D0r6", XED_IFORM_SHL_GPR8_ONE_D0r6},
{"SHL_GPRv_CL_D3r4", XED_IFORM_SHL_GPRv_CL_D3r4},
{"SHL_GPRv_CL_D3r6", XED_IFORM_SHL_GPRv_CL_D3r6},
{"SHL_GPRv_IMMb_C1r4", XED_IFORM_SHL_GPRv_IMMb_C1r4},
{"SHL_GPRv_IMMb_C1r6", XED_IFORM_SHL_GPRv_IMMb_C1r6},
{"SHL_GPRv_ONE_D1r4", XED_IFORM_SHL_GPRv_ONE_D1r4},
{"SHL_GPRv_ONE_D1r6", XED_IFORM_SHL_GPRv_ONE_D1r6},
{"SHL_MEMb_CL_D2r4", XED_IFORM_SHL_MEMb_CL_D2r4},
{"SHL_MEMb_CL_D2r6", XED_IFORM_SHL_MEMb_CL_D2r6},
{"SHL_MEMb_IMMb_C0r4", XED_IFORM_SHL_MEMb_IMMb_C0r4},
{"SHL_MEMb_IMMb_C0r6", XED_IFORM_SHL_MEMb_IMMb_C0r6},
{"SHL_MEMb_ONE_D0r4", XED_IFORM_SHL_MEMb_ONE_D0r4},
{"SHL_MEMb_ONE_D0r6", XED_IFORM_SHL_MEMb_ONE_D0r6},
{"SHL_MEMv_CL_D3r4", XED_IFORM_SHL_MEMv_CL_D3r4},
{"SHL_MEMv_CL_D3r6", XED_IFORM_SHL_MEMv_CL_D3r6},
{"SHL_MEMv_IMMb_C1r4", XED_IFORM_SHL_MEMv_IMMb_C1r4},
{"SHL_MEMv_IMMb_C1r6", XED_IFORM_SHL_MEMv_IMMb_C1r6},
{"SHL_MEMv_ONE_D1r4", XED_IFORM_SHL_MEMv_ONE_D1r4},
{"SHL_MEMv_ONE_D1r6", XED_IFORM_SHL_MEMv_ONE_D1r6},
{"SHLD_GPRv_GPRv_CL", XED_IFORM_SHLD_GPRv_GPRv_CL},
{"SHLD_GPRv_GPRv_IMMb", XED_IFORM_SHLD_GPRv_GPRv_IMMb},
{"SHLD_MEMv_GPRv_CL", XED_IFORM_SHLD_MEMv_GPRv_CL},
{"SHLD_MEMv_GPRv_IMMb", XED_IFORM_SHLD_MEMv_GPRv_IMMb},
{"SHLX_VGPR32d_MEMd_VGPR32d", XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d},
{"SHLX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d},
{"SHLX_VGPR64q_MEMq_VGPR64q", XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q},
{"SHLX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q},
{"SHR_GPR8_CL", XED_IFORM_SHR_GPR8_CL},
{"SHR_GPR8_IMMb", XED_IFORM_SHR_GPR8_IMMb},
{"SHR_GPR8_ONE", XED_IFORM_SHR_GPR8_ONE},
{"SHR_GPRv_CL", XED_IFORM_SHR_GPRv_CL},
{"SHR_GPRv_IMMb", XED_IFORM_SHR_GPRv_IMMb},
{"SHR_GPRv_ONE", XED_IFORM_SHR_GPRv_ONE},
{"SHR_MEMb_CL", XED_IFORM_SHR_MEMb_CL},
{"SHR_MEMb_IMMb", XED_IFORM_SHR_MEMb_IMMb},
{"SHR_MEMb_ONE", XED_IFORM_SHR_MEMb_ONE},
{"SHR_MEMv_CL", XED_IFORM_SHR_MEMv_CL},
{"SHR_MEMv_IMMb", XED_IFORM_SHR_MEMv_IMMb},
{"SHR_MEMv_ONE", XED_IFORM_SHR_MEMv_ONE},
{"SHRD_GPRv_GPRv_CL", XED_IFORM_SHRD_GPRv_GPRv_CL},
{"SHRD_GPRv_GPRv_IMMb", XED_IFORM_SHRD_GPRv_GPRv_IMMb},
{"SHRD_MEMv_GPRv_CL", XED_IFORM_SHRD_MEMv_GPRv_CL},
{"SHRD_MEMv_GPRv_IMMb", XED_IFORM_SHRD_MEMv_GPRv_IMMb},
{"SHRX_VGPR32d_MEMd_VGPR32d", XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d},
{"SHRX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d},
{"SHRX_VGPR64q_MEMq_VGPR64q", XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q},
{"SHRX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q},
{"SHUFPD_XMMpd_MEMpd_IMMb", XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb},
{"SHUFPD_XMMpd_XMMpd_IMMb", XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb},
{"SHUFPS_XMMps_MEMps_IMMb", XED_IFORM_SHUFPS_XMMps_MEMps_IMMb},
{"SHUFPS_XMMps_XMMps_IMMb", XED_IFORM_SHUFPS_XMMps_XMMps_IMMb},
{"SIDT_MEMs", XED_IFORM_SIDT_MEMs},
{"SIDT_MEMs64", XED_IFORM_SIDT_MEMs64},
{"SKINIT_EAX", XED_IFORM_SKINIT_EAX},
{"SLDT_GPRv", XED_IFORM_SLDT_GPRv},
{"SLDT_MEMw", XED_IFORM_SLDT_MEMw},
{"SLWPCB_VGPRyy", XED_IFORM_SLWPCB_VGPRyy},
{"SMSW_GPRv", XED_IFORM_SMSW_GPRv},
{"SMSW_MEMw", XED_IFORM_SMSW_MEMw},
{"SQRTPD_XMMpd_MEMpd", XED_IFORM_SQRTPD_XMMpd_MEMpd},
{"SQRTPD_XMMpd_XMMpd", XED_IFORM_SQRTPD_XMMpd_XMMpd},
{"SQRTPS_XMMps_MEMps", XED_IFORM_SQRTPS_XMMps_MEMps},
{"SQRTPS_XMMps_XMMps", XED_IFORM_SQRTPS_XMMps_XMMps},
{"SQRTSD_XMMsd_MEMsd", XED_IFORM_SQRTSD_XMMsd_MEMsd},
{"SQRTSD_XMMsd_XMMsd", XED_IFORM_SQRTSD_XMMsd_XMMsd},
{"SQRTSS_XMMss_MEMss", XED_IFORM_SQRTSS_XMMss_MEMss},
{"SQRTSS_XMMss_XMMss", XED_IFORM_SQRTSS_XMMss_XMMss},
{"STAC", XED_IFORM_STAC},
{"STC", XED_IFORM_STC},
{"STD", XED_IFORM_STD},
{"STGI", XED_IFORM_STGI},
{"STI", XED_IFORM_STI},
{"STMXCSR_MEMd", XED_IFORM_STMXCSR_MEMd},
{"STOSB", XED_IFORM_STOSB},
{"STOSD", XED_IFORM_STOSD},
{"STOSQ", XED_IFORM_STOSQ},
{"STOSW", XED_IFORM_STOSW},
{"STR_GPRv", XED_IFORM_STR_GPRv},
{"STR_MEMw", XED_IFORM_STR_MEMw},
{"STTILECFG_MEM", XED_IFORM_STTILECFG_MEM},
{"STUI", XED_IFORM_STUI},
{"SUB_AL_IMMb", XED_IFORM_SUB_AL_IMMb},
{"SUB_GPR8_GPR8_28", XED_IFORM_SUB_GPR8_GPR8_28},
{"SUB_GPR8_GPR8_2A", XED_IFORM_SUB_GPR8_GPR8_2A},
{"SUB_GPR8_IMMb_80r5", XED_IFORM_SUB_GPR8_IMMb_80r5},
{"SUB_GPR8_IMMb_82r5", XED_IFORM_SUB_GPR8_IMMb_82r5},
{"SUB_GPR8_MEMb", XED_IFORM_SUB_GPR8_MEMb},
{"SUB_GPRv_GPRv_29", XED_IFORM_SUB_GPRv_GPRv_29},
{"SUB_GPRv_GPRv_2B", XED_IFORM_SUB_GPRv_GPRv_2B},
{"SUB_GPRv_IMMb", XED_IFORM_SUB_GPRv_IMMb},
{"SUB_GPRv_IMMz", XED_IFORM_SUB_GPRv_IMMz},
{"SUB_GPRv_MEMv", XED_IFORM_SUB_GPRv_MEMv},
{"SUB_MEMb_GPR8", XED_IFORM_SUB_MEMb_GPR8},
{"SUB_MEMb_IMMb_80r5", XED_IFORM_SUB_MEMb_IMMb_80r5},
{"SUB_MEMb_IMMb_82r5", XED_IFORM_SUB_MEMb_IMMb_82r5},
{"SUB_MEMv_GPRv", XED_IFORM_SUB_MEMv_GPRv},
{"SUB_MEMv_IMMb", XED_IFORM_SUB_MEMv_IMMb},
{"SUB_MEMv_IMMz", XED_IFORM_SUB_MEMv_IMMz},
{"SUB_OrAX_IMMz", XED_IFORM_SUB_OrAX_IMMz},
{"SUBPD_XMMpd_MEMpd", XED_IFORM_SUBPD_XMMpd_MEMpd},
{"SUBPD_XMMpd_XMMpd", XED_IFORM_SUBPD_XMMpd_XMMpd},
{"SUBPS_XMMps_MEMps", XED_IFORM_SUBPS_XMMps_MEMps},
{"SUBPS_XMMps_XMMps", XED_IFORM_SUBPS_XMMps_XMMps},
{"SUBSD_XMMsd_MEMsd", XED_IFORM_SUBSD_XMMsd_MEMsd},
{"SUBSD_XMMsd_XMMsd", XED_IFORM_SUBSD_XMMsd_XMMsd},
{"SUBSS_XMMss_MEMss", XED_IFORM_SUBSS_XMMss_MEMss},
{"SUBSS_XMMss_XMMss", XED_IFORM_SUBSS_XMMss_XMMss},
{"SUB_LOCK_MEMb_GPR8", XED_IFORM_SUB_LOCK_MEMb_GPR8},
{"SUB_LOCK_MEMb_IMMb_80r5", XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5},
{"SUB_LOCK_MEMb_IMMb_82r5", XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5},
{"SUB_LOCK_MEMv_GPRv", XED_IFORM_SUB_LOCK_MEMv_GPRv},
{"SUB_LOCK_MEMv_IMMb", XED_IFORM_SUB_LOCK_MEMv_IMMb},
{"SUB_LOCK_MEMv_IMMz", XED_IFORM_SUB_LOCK_MEMv_IMMz},
{"SWAPGS", XED_IFORM_SWAPGS},
{"SYSCALL", XED_IFORM_SYSCALL},
{"SYSCALL_AMD", XED_IFORM_SYSCALL_AMD},
{"SYSENTER", XED_IFORM_SYSENTER},
{"SYSEXIT", XED_IFORM_SYSEXIT},
{"SYSRET", XED_IFORM_SYSRET},
{"SYSRET64", XED_IFORM_SYSRET64},
{"SYSRET_AMD", XED_IFORM_SYSRET_AMD},
{"T1MSKC_VGPR32d_MEMd", XED_IFORM_T1MSKC_VGPR32d_MEMd},
{"T1MSKC_VGPR32d_VGPR32d", XED_IFORM_T1MSKC_VGPR32d_VGPR32d},
{"T1MSKC_VGPRyy_MEMy", XED_IFORM_T1MSKC_VGPRyy_MEMy},
{"T1MSKC_VGPRyy_VGPRyy", XED_IFORM_T1MSKC_VGPRyy_VGPRyy},
{"TDCALL", XED_IFORM_TDCALL},
{"TDPBF16PS_TMMf32_TMMu32_TMMu32", XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32},
{"TDPBSSD_TMMi32_TMMu32_TMMu32", XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32},
{"TDPBSUD_TMMi32_TMMu32_TMMu32", XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32},
{"TDPBUSD_TMMi32_TMMu32_TMMu32", XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32},
{"TDPBUUD_TMMu32_TMMu32_TMMu32", XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32},
{"TEST_AL_IMMb", XED_IFORM_TEST_AL_IMMb},
{"TEST_GPR8_GPR8", XED_IFORM_TEST_GPR8_GPR8},
{"TEST_GPR8_IMMb_F6r0", XED_IFORM_TEST_GPR8_IMMb_F6r0},
{"TEST_GPR8_IMMb_F6r1", XED_IFORM_TEST_GPR8_IMMb_F6r1},
{"TEST_GPRv_GPRv", XED_IFORM_TEST_GPRv_GPRv},
{"TEST_GPRv_IMMz_F7r0", XED_IFORM_TEST_GPRv_IMMz_F7r0},
{"TEST_GPRv_IMMz_F7r1", XED_IFORM_TEST_GPRv_IMMz_F7r1},
{"TEST_MEMb_GPR8", XED_IFORM_TEST_MEMb_GPR8},
{"TEST_MEMb_IMMb_F6r0", XED_IFORM_TEST_MEMb_IMMb_F6r0},
{"TEST_MEMb_IMMb_F6r1", XED_IFORM_TEST_MEMb_IMMb_F6r1},
{"TEST_MEMv_GPRv", XED_IFORM_TEST_MEMv_GPRv},
{"TEST_MEMv_IMMz_F7r0", XED_IFORM_TEST_MEMv_IMMz_F7r0},
{"TEST_MEMv_IMMz_F7r1", XED_IFORM_TEST_MEMv_IMMz_F7r1},
{"TEST_OrAX_IMMz", XED_IFORM_TEST_OrAX_IMMz},
{"TESTUI", XED_IFORM_TESTUI},
{"TILELOADD_TMMu32_MEMu32", XED_IFORM_TILELOADD_TMMu32_MEMu32},
{"TILELOADDT1_TMMu32_MEMu32", XED_IFORM_TILELOADDT1_TMMu32_MEMu32},
{"TILERELEASE", XED_IFORM_TILERELEASE},
{"TILESTORED_MEMu32_TMMu32", XED_IFORM_TILESTORED_MEMu32_TMMu32},
{"TILEZERO_TMMu32", XED_IFORM_TILEZERO_TMMu32},
{"TLBSYNC", XED_IFORM_TLBSYNC},
{"TPAUSE_GPR32u32", XED_IFORM_TPAUSE_GPR32u32},
{"TZCNT_GPRv_GPRv", XED_IFORM_TZCNT_GPRv_GPRv},
{"TZCNT_GPRv_MEMv", XED_IFORM_TZCNT_GPRv_MEMv},
{"TZMSK_VGPR32d_MEMd", XED_IFORM_TZMSK_VGPR32d_MEMd},
{"TZMSK_VGPR32d_VGPR32d", XED_IFORM_TZMSK_VGPR32d_VGPR32d},
{"TZMSK_VGPRyy_MEMy", XED_IFORM_TZMSK_VGPRyy_MEMy},
{"TZMSK_VGPRyy_VGPRyy", XED_IFORM_TZMSK_VGPRyy_VGPRyy},
{"UCOMISD_XMMsd_MEMsd", XED_IFORM_UCOMISD_XMMsd_MEMsd},
{"UCOMISD_XMMsd_XMMsd", XED_IFORM_UCOMISD_XMMsd_XMMsd},
{"UCOMISS_XMMss_MEMss", XED_IFORM_UCOMISS_XMMss_MEMss},
{"UCOMISS_XMMss_XMMss", XED_IFORM_UCOMISS_XMMss_XMMss},
{"UD0", XED_IFORM_UD0},
{"UD0_GPR32_GPR32", XED_IFORM_UD0_GPR32_GPR32},
{"UD0_GPR32_MEMd", XED_IFORM_UD0_GPR32_MEMd},
{"UD1_GPR32_GPR32", XED_IFORM_UD1_GPR32_GPR32},
{"UD1_GPR32_MEMd", XED_IFORM_UD1_GPR32_MEMd},
{"UD2", XED_IFORM_UD2},
{"UIRET", XED_IFORM_UIRET},
{"UMONITOR_GPRa", XED_IFORM_UMONITOR_GPRa},
{"UMWAIT_GPR32", XED_IFORM_UMWAIT_GPR32},
{"UNPCKHPD_XMMpd_MEMdq", XED_IFORM_UNPCKHPD_XMMpd_MEMdq},
{"UNPCKHPD_XMMpd_XMMq", XED_IFORM_UNPCKHPD_XMMpd_XMMq},
{"UNPCKHPS_XMMps_MEMdq", XED_IFORM_UNPCKHPS_XMMps_MEMdq},
{"UNPCKHPS_XMMps_XMMdq", XED_IFORM_UNPCKHPS_XMMps_XMMdq},
{"UNPCKLPD_XMMpd_MEMdq", XED_IFORM_UNPCKLPD_XMMpd_MEMdq},
{"UNPCKLPD_XMMpd_XMMq", XED_IFORM_UNPCKLPD_XMMpd_XMMq},
{"UNPCKLPS_XMMps_MEMdq", XED_IFORM_UNPCKLPS_XMMps_MEMdq},
{"UNPCKLPS_XMMps_XMMq", XED_IFORM_UNPCKLPS_XMMps_XMMq},
{"V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VADDPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq},
{"VADDPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq},
{"VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VADDPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq},
{"VADDPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq},
{"VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VADDPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq},
{"VADDPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq},
{"VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VADDPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq},
{"VADDPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq},
{"VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VADDSD_XMMdq_XMMdq_MEMq", XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq},
{"VADDSD_XMMdq_XMMdq_XMMq", XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq},
{"VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VADDSS_XMMdq_XMMdq_MEMd", XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd},
{"VADDSS_XMMdq_XMMdq_XMMd", XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd},
{"VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VADDSUBPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq},
{"VADDSUBPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq},
{"VADDSUBPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq},
{"VADDSUBPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq},
{"VADDSUBPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq},
{"VADDSUBPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq},
{"VADDSUBPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq},
{"VADDSUBPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq},
{"VAESDEC_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq},
{"VAESDEC_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq},
{"VAESDEC_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512},
{"VAESDEC_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512},
{"VAESDEC_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128},
{"VAESDEC_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512},
{"VAESDEC_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128},
{"VAESDEC_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512},
{"VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512},
{"VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512},
{"VAESDECLAST_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq},
{"VAESDECLAST_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq},
{"VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512},
{"VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512},
{"VAESDECLAST_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128},
{"VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512},
{"VAESDECLAST_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128},
{"VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512},
{"VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512},
{"VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512},
{"VAESENC_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq},
{"VAESENC_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq},
{"VAESENC_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512},
{"VAESENC_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512},
{"VAESENC_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128},
{"VAESENC_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512},
{"VAESENC_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128},
{"VAESENC_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512},
{"VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512},
{"VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512},
{"VAESENCLAST_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq},
{"VAESENCLAST_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq},
{"VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512},
{"VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512},
{"VAESENCLAST_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128},
{"VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512},
{"VAESENCLAST_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128},
{"VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512},
{"VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512},
{"VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512},
{"VAESIMC_XMMdq_MEMdq", XED_IFORM_VAESIMC_XMMdq_MEMdq},
{"VAESIMC_XMMdq_XMMdq", XED_IFORM_VAESIMC_XMMdq_XMMdq},
{"VAESKEYGENASSIST_XMMdq_MEMdq_IMMb", XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb},
{"VAESKEYGENASSIST_XMMdq_XMMdq_IMMb", XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb},
{"VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512},
{"VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512},
{"VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512},
{"VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512},
{"VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512},
{"VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512},
{"VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512},
{"VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512},
{"VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512},
{"VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512},
{"VANDNPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq},
{"VANDNPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq},
{"VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VANDNPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq},
{"VANDNPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq},
{"VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VANDNPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq},
{"VANDNPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq},
{"VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VANDNPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq},
{"VANDNPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq},
{"VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VANDPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq},
{"VANDPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq},
{"VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VANDPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq},
{"VANDPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq},
{"VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VANDPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq},
{"VANDPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq},
{"VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VANDPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq},
{"VANDPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq},
{"VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb},
{"VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb},
{"VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb},
{"VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb},
{"VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb},
{"VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb},
{"VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb},
{"VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb},
{"VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq},
{"VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq},
{"VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq},
{"VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq},
{"VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq},
{"VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq},
{"VBROADCASTF128_YMMqq_MEMdq", XED_IFORM_VBROADCASTF128_YMMqq_MEMdq},
{"VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512},
{"VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512},
{"VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512},
{"VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VBROADCASTI128_YMMqq_MEMdq", XED_IFORM_VBROADCASTI128_YMMqq_MEMdq},
{"VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512},
{"VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512},
{"VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512},
{"VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512},
{"VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512},
{"VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512},
{"VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512},
{"VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512},
{"VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512},
{"VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512},
{"VBROADCASTSD_YMMqq_MEMq", XED_IFORM_VBROADCASTSD_YMMqq_MEMq},
{"VBROADCASTSD_YMMqq_XMMdq", XED_IFORM_VBROADCASTSD_YMMqq_XMMdq},
{"VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512},
{"VBROADCASTSS_XMMdq_MEMd", XED_IFORM_VBROADCASTSS_XMMdq_MEMd},
{"VBROADCASTSS_XMMdq_XMMdq", XED_IFORM_VBROADCASTSS_XMMdq_XMMdq},
{"VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512},
{"VBROADCASTSS_YMMqq_MEMd", XED_IFORM_VBROADCASTSS_YMMqq_MEMd},
{"VBROADCASTSS_YMMqq_XMMdq", XED_IFORM_VBROADCASTSS_YMMqq_XMMdq},
{"VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512},
{"VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512},
{"VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512},
{"VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512},
{"VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512},
{"VCMPPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb},
{"VCMPPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb},
{"VCMPPD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb},
{"VCMPPD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb},
{"VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512},
{"VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512},
{"VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512},
{"VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512},
{"VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512},
{"VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512},
{"VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512},
{"VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512},
{"VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512},
{"VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512},
{"VCMPPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb},
{"VCMPPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb},
{"VCMPPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb},
{"VCMPPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb},
{"VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VCMPSD_XMMdq_XMMdq_MEMq_IMMb", XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb},
{"VCMPSD_XMMdq_XMMdq_XMMq_IMMb", XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb},
{"VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512},
{"VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512},
{"VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VCMPSS_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb},
{"VCMPSS_XMMdq_XMMdq_XMMd_IMMb", XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb},
{"VCOMISD_XMMf64_MEMf64_AVX512", XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512},
{"VCOMISD_XMMf64_XMMf64_AVX512", XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512},
{"VCOMISD_XMMq_MEMq", XED_IFORM_VCOMISD_XMMq_MEMq},
{"VCOMISD_XMMq_XMMq", XED_IFORM_VCOMISD_XMMq_XMMq},
{"VCOMISH_XMMf16_MEMf16_AVX512", XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512},
{"VCOMISH_XMMf16_XMMf16_AVX512", XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512},
{"VCOMISS_XMMd_MEMd", XED_IFORM_VCOMISS_XMMd_MEMd},
{"VCOMISS_XMMd_XMMd", XED_IFORM_VCOMISS_XMMd_XMMd},
{"VCOMISS_XMMf32_MEMf32_AVX512", XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512},
{"VCOMISS_XMMf32_XMMf32_AVX512", XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512},
{"VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512},
{"VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512},
{"VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512},
{"VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512},
{"VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512},
{"VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512},
{"VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VCVTDQ2PD_XMMdq_MEMq", XED_IFORM_VCVTDQ2PD_XMMdq_MEMq},
{"VCVTDQ2PD_XMMdq_XMMq", XED_IFORM_VCVTDQ2PD_XMMdq_XMMq},
{"VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512},
{"VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512},
{"VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512},
{"VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512},
{"VCVTDQ2PD_YMMqq_MEMdq", XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq},
{"VCVTDQ2PD_YMMqq_XMMdq", XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq},
{"VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512},
{"VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512", XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512},
{"VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128},
{"VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256},
{"VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512},
{"VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512},
{"VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512},
{"VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512", XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512},
{"VCVTDQ2PS_XMMdq_MEMdq", XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq},
{"VCVTDQ2PS_XMMdq_XMMdq", XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq},
{"VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512},
{"VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512},
{"VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512},
{"VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512", XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512},
{"VCVTDQ2PS_YMMqq_MEMqq", XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq},
{"VCVTDQ2PS_YMMqq_YMMqq", XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq},
{"VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512},
{"VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512", XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512},
{"VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128", XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128},
{"VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512},
{"VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256", XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256},
{"VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512},
{"VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512", XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512},
{"VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128},
{"VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256},
{"VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512},
{"VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512},
{"VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512},
{"VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512},
{"VCVTPD2DQ_XMMdq_MEMdq", XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq},
{"VCVTPD2DQ_XMMdq_MEMqq", XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq},
{"VCVTPD2DQ_XMMdq_XMMdq", XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq},
{"VCVTPD2DQ_XMMdq_YMMqq", XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq},
{"VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128},
{"VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256},
{"VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128},
{"VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256},
{"VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512},
{"VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512},
{"VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128},
{"VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256},
{"VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512},
{"VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512},
{"VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512},
{"VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512},
{"VCVTPD2PS_XMMdq_MEMdq", XED_IFORM_VCVTPD2PS_XMMdq_MEMdq},
{"VCVTPD2PS_XMMdq_MEMqq", XED_IFORM_VCVTPD2PS_XMMdq_MEMqq},
{"VCVTPD2PS_XMMdq_XMMdq", XED_IFORM_VCVTPD2PS_XMMdq_XMMdq},
{"VCVTPD2PS_XMMdq_YMMqq", XED_IFORM_VCVTPD2PS_XMMdq_YMMqq},
{"VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128},
{"VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256},
{"VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128},
{"VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256},
{"VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512},
{"VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512},
{"VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512},
{"VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512},
{"VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512},
{"VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128},
{"VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256},
{"VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128},
{"VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256},
{"VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512},
{"VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512},
{"VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512},
{"VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512},
{"VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512},
{"VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512},
{"VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512},
{"VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512},
{"VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512},
{"VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2PS_XMMdq_MEMq", XED_IFORM_VCVTPH2PS_XMMdq_MEMq},
{"VCVTPH2PS_XMMdq_XMMq", XED_IFORM_VCVTPH2PS_XMMdq_XMMq},
{"VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2PS_YMMqq_MEMdq", XED_IFORM_VCVTPH2PS_YMMqq_MEMdq},
{"VCVTPH2PS_YMMqq_XMMdq", XED_IFORM_VCVTPH2PS_YMMqq_XMMdq},
{"VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512},
{"VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512},
{"VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512},
{"VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512},
{"VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512},
{"VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512},
{"VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512},
{"VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512},
{"VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512},
{"VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512},
{"VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512},
{"VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512},
{"VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512},
{"VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512},
{"VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512},
{"VCVTPS2DQ_XMMdq_MEMdq", XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq},
{"VCVTPS2DQ_XMMdq_XMMdq", XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq},
{"VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512},
{"VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512},
{"VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512},
{"VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512},
{"VCVTPS2DQ_YMMqq_MEMqq", XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq},
{"VCVTPS2DQ_YMMqq_YMMqq", XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq},
{"VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512},
{"VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512},
{"VCVTPS2PD_XMMdq_MEMq", XED_IFORM_VCVTPS2PD_XMMdq_MEMq},
{"VCVTPS2PD_XMMdq_XMMq", XED_IFORM_VCVTPS2PD_XMMdq_XMMq},
{"VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512},
{"VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512},
{"VCVTPS2PD_YMMqq_MEMdq", XED_IFORM_VCVTPS2PD_YMMqq_MEMdq},
{"VCVTPS2PD_YMMqq_XMMdq", XED_IFORM_VCVTPS2PD_YMMqq_XMMdq},
{"VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512},
{"VCVTPS2PH_MEMdq_YMMqq_IMMb", XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb},
{"VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512},
{"VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512},
{"VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512},
{"VCVTPS2PH_MEMq_XMMdq_IMMb", XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb},
{"VCVTPS2PH_XMMdq_YMMqq_IMMb", XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb},
{"VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512},
{"VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512},
{"VCVTPS2PH_XMMq_XMMdq_IMMb", XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb},
{"VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512},
{"VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128},
{"VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256},
{"VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512},
{"VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512},
{"VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512},
{"VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512},
{"VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512},
{"VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512},
{"VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512},
{"VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512},
{"VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512},
{"VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512},
{"VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512},
{"VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512},
{"VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512},
{"VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512},
{"VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512},
{"VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512},
{"VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512},
{"VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512},
{"VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512},
{"VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512},
{"VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128},
{"VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256},
{"VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512},
{"VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512},
{"VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512},
{"VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512},
{"VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128},
{"VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256},
{"VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128},
{"VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256},
{"VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512},
{"VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512},
{"VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512},
{"VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512},
{"VCVTSD2SI_GPR32d_MEMq", XED_IFORM_VCVTSD2SI_GPR32d_MEMq},
{"VCVTSD2SI_GPR32d_XMMq", XED_IFORM_VCVTSD2SI_GPR32d_XMMq},
{"VCVTSD2SI_GPR32i32_MEMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512},
{"VCVTSD2SI_GPR32i32_XMMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512},
{"VCVTSD2SI_GPR64i64_MEMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512},
{"VCVTSD2SI_GPR64i64_XMMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512},
{"VCVTSD2SI_GPR64q_MEMq", XED_IFORM_VCVTSD2SI_GPR64q_MEMq},
{"VCVTSD2SI_GPR64q_XMMq", XED_IFORM_VCVTSD2SI_GPR64q_XMMq},
{"VCVTSD2SS_XMMdq_XMMdq_MEMq", XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq},
{"VCVTSD2SS_XMMdq_XMMdq_XMMq", XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq},
{"VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512},
{"VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512},
{"VCVTSD2USI_GPR32u32_MEMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512},
{"VCVTSD2USI_GPR32u32_XMMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512},
{"VCVTSD2USI_GPR64u64_MEMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512},
{"VCVTSD2USI_GPR64u64_XMMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512},
{"VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512", XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512},
{"VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512", XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512},
{"VCVTSH2SI_GPR32i32_MEMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512},
{"VCVTSH2SI_GPR32i32_XMMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512},
{"VCVTSH2SI_GPR64i64_MEMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512},
{"VCVTSH2SI_GPR64i64_XMMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512},
{"VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512", XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512},
{"VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512", XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512},
{"VCVTSH2USI_GPR32u32_MEMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512},
{"VCVTSH2USI_GPR32u32_XMMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512},
{"VCVTSH2USI_GPR64u64_MEMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512},
{"VCVTSH2USI_GPR64u64_XMMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512},
{"VCVTSI2SD_XMMdq_XMMdq_GPR32d", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d},
{"VCVTSI2SD_XMMdq_XMMdq_GPR64q", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q},
{"VCVTSI2SD_XMMdq_XMMdq_MEMd", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd},
{"VCVTSI2SD_XMMdq_XMMdq_MEMq", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq},
{"VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512},
{"VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512},
{"VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512},
{"VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512},
{"VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512},
{"VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512},
{"VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512},
{"VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512},
{"VCVTSI2SS_XMMdq_XMMdq_GPR32d", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d},
{"VCVTSI2SS_XMMdq_XMMdq_GPR64q", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q},
{"VCVTSI2SS_XMMdq_XMMdq_MEMd", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd},
{"VCVTSI2SS_XMMdq_XMMdq_MEMq", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq},
{"VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512},
{"VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512},
{"VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512},
{"VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512},
{"VCVTSS2SD_XMMdq_XMMdq_MEMd", XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd},
{"VCVTSS2SD_XMMdq_XMMdq_XMMd", XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd},
{"VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512},
{"VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512},
{"VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512", XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512},
{"VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512", XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512},
{"VCVTSS2SI_GPR32d_MEMd", XED_IFORM_VCVTSS2SI_GPR32d_MEMd},
{"VCVTSS2SI_GPR32d_XMMd", XED_IFORM_VCVTSS2SI_GPR32d_XMMd},
{"VCVTSS2SI_GPR32i32_MEMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512},
{"VCVTSS2SI_GPR32i32_XMMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512},
{"VCVTSS2SI_GPR64i64_MEMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512},
{"VCVTSS2SI_GPR64i64_XMMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512},
{"VCVTSS2SI_GPR64q_MEMd", XED_IFORM_VCVTSS2SI_GPR64q_MEMd},
{"VCVTSS2SI_GPR64q_XMMd", XED_IFORM_VCVTSS2SI_GPR64q_XMMd},
{"VCVTSS2USI_GPR32u32_MEMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512},
{"VCVTSS2USI_GPR32u32_XMMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512},
{"VCVTSS2USI_GPR64u64_MEMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512},
{"VCVTSS2USI_GPR64u64_XMMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512},
{"VCVTTPD2DQ_XMMdq_MEMdq", XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq},
{"VCVTTPD2DQ_XMMdq_MEMqq", XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq},
{"VCVTTPD2DQ_XMMdq_XMMdq", XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq},
{"VCVTTPD2DQ_XMMdq_YMMqq", XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq},
{"VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128},
{"VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256},
{"VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128},
{"VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256},
{"VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512},
{"VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512},
{"VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512},
{"VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512},
{"VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512},
{"VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512},
{"VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128},
{"VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256},
{"VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128},
{"VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256},
{"VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512},
{"VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512},
{"VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512},
{"VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512},
{"VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512},
{"VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512},
{"VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512},
{"VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512},
{"VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512},
{"VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512},
{"VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512},
{"VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512},
{"VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512},
{"VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512},
{"VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512},
{"VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512},
{"VCVTTPS2DQ_XMMdq_MEMdq", XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq},
{"VCVTTPS2DQ_XMMdq_XMMdq", XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq},
{"VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512},
{"VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512},
{"VCVTTPS2DQ_YMMqq_MEMqq", XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq},
{"VCVTTPS2DQ_YMMqq_YMMqq", XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq},
{"VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512},
{"VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512},
{"VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512},
{"VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512},
{"VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512},
{"VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512},
{"VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512},
{"VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512},
{"VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512},
{"VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512},
{"VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512},
{"VCVTTSD2SI_GPR32d_MEMq", XED_IFORM_VCVTTSD2SI_GPR32d_MEMq},
{"VCVTTSD2SI_GPR32d_XMMq", XED_IFORM_VCVTTSD2SI_GPR32d_XMMq},
{"VCVTTSD2SI_GPR32i32_MEMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512},
{"VCVTTSD2SI_GPR32i32_XMMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512},
{"VCVTTSD2SI_GPR64i64_MEMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512},
{"VCVTTSD2SI_GPR64i64_XMMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512},
{"VCVTTSD2SI_GPR64q_MEMq", XED_IFORM_VCVTTSD2SI_GPR64q_MEMq},
{"VCVTTSD2SI_GPR64q_XMMq", XED_IFORM_VCVTTSD2SI_GPR64q_XMMq},
{"VCVTTSD2USI_GPR32u32_MEMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512},
{"VCVTTSD2USI_GPR32u32_XMMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512},
{"VCVTTSD2USI_GPR64u64_MEMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512},
{"VCVTTSD2USI_GPR64u64_XMMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512},
{"VCVTTSH2SI_GPR32i32_MEMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512},
{"VCVTTSH2SI_GPR32i32_XMMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512},
{"VCVTTSH2SI_GPR64i64_MEMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512},
{"VCVTTSH2SI_GPR64i64_XMMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512},
{"VCVTTSH2USI_GPR32u32_MEMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512},
{"VCVTTSH2USI_GPR32u32_XMMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512},
{"VCVTTSH2USI_GPR64u64_MEMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512},
{"VCVTTSH2USI_GPR64u64_XMMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512},
{"VCVTTSS2SI_GPR32d_MEMd", XED_IFORM_VCVTTSS2SI_GPR32d_MEMd},
{"VCVTTSS2SI_GPR32d_XMMd", XED_IFORM_VCVTTSS2SI_GPR32d_XMMd},
{"VCVTTSS2SI_GPR32i32_MEMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512},
{"VCVTTSS2SI_GPR32i32_XMMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512},
{"VCVTTSS2SI_GPR64i64_MEMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512},
{"VCVTTSS2SI_GPR64i64_XMMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512},
{"VCVTTSS2SI_GPR64q_MEMd", XED_IFORM_VCVTTSS2SI_GPR64q_MEMd},
{"VCVTTSS2SI_GPR64q_XMMd", XED_IFORM_VCVTTSS2SI_GPR64q_XMMd},
{"VCVTTSS2USI_GPR32u32_MEMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512},
{"VCVTTSS2USI_GPR32u32_XMMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512},
{"VCVTTSS2USI_GPR64u64_MEMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512},
{"VCVTTSS2USI_GPR64u64_XMMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512},
{"VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512},
{"VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512},
{"VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512},
{"VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512},
{"VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512},
{"VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512", XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512},
{"VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128},
{"VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256},
{"VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512},
{"VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512},
{"VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512},
{"VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512},
{"VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512},
{"VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512},
{"VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512},
{"VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512", XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512},
{"VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512},
{"VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512},
{"VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512", XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512},
{"VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512", XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512},
{"VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512", XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512},
{"VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512", XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512},
{"VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512", XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512},
{"VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512},
{"VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128},
{"VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256},
{"VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512},
{"VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512},
{"VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512},
{"VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512},
{"VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128},
{"VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256},
{"VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128},
{"VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256},
{"VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512},
{"VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512},
{"VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512},
{"VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512},
{"VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512},
{"VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512},
{"VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512},
{"VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512},
{"VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512},
{"VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512},
{"VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512},
{"VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512},
{"VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512},
{"VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512},
{"VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512", XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512},
{"VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512", XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512},
{"VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512", XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512},
{"VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512", XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512},
{"VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512", XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512},
{"VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512},
{"VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512", XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512},
{"VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512", XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512},
{"VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512", XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512},
{"VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512", XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512},
{"VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512", XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512},
{"VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512", XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512},
{"VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512},
{"VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512},
{"VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512},
{"VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512},
{"VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512},
{"VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512},
{"VDIVPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq},
{"VDIVPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq},
{"VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VDIVPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq},
{"VDIVPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq},
{"VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VDIVPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq},
{"VDIVPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq},
{"VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VDIVPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq},
{"VDIVPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq},
{"VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VDIVSD_XMMdq_XMMdq_MEMq", XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq},
{"VDIVSD_XMMdq_XMMdq_XMMq", XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq},
{"VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VDIVSS_XMMdq_XMMdq_MEMd", XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd},
{"VDIVSS_XMMdq_XMMdq_XMMd", XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd},
{"VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VDPPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb},
{"VDPPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb},
{"VDPPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb},
{"VDPPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb},
{"VDPPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb},
{"VDPPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb},
{"VERR_GPR16", XED_IFORM_VERR_GPR16},
{"VERR_MEMw", XED_IFORM_VERR_MEMw},
{"VERW_GPR16", XED_IFORM_VERW_GPR16},
{"VERW_MEMw", XED_IFORM_VERW_MEMw},
{"VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER", XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER},
{"VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER", XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER},
{"VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER", XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER},
{"VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER", XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER},
{"VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VEXTRACTF128_MEMdq_YMMdq_IMMb", XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb},
{"VEXTRACTF128_XMMdq_YMMdq_IMMb", XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb},
{"VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512},
{"VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512},
{"VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512},
{"VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512},
{"VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VEXTRACTI128_MEMdq_YMMqq_IMMb", XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb},
{"VEXTRACTI128_XMMdq_YMMqq_IMMb", XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb},
{"VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VEXTRACTPS_GPR32_XMMdq_IMMb", XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb},
{"VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512},
{"VEXTRACTPS_MEMd_XMMdq_IMMb", XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb},
{"VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512},
{"VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512},
{"VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512},
{"VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512},
{"VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512},
{"VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512},
{"VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512},
{"VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512},
{"VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512},
{"VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512},
{"VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512},
{"VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512},
{"VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512},
{"VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512},
{"VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512},
{"VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512},
{"VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512},
{"VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VFMADD132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq},
{"VFMADD132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq},
{"VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMADD132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq},
{"VFMADD132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq},
{"VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMADD132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq},
{"VFMADD132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq},
{"VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMADD132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq},
{"VFMADD132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq},
{"VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMADD132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq},
{"VFMADD132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq},
{"VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADD132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd},
{"VFMADD132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd},
{"VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADD213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq},
{"VFMADD213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq},
{"VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMADD213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq},
{"VFMADD213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq},
{"VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMADD213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq},
{"VFMADD213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq},
{"VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMADD213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq},
{"VFMADD213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq},
{"VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMADD213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq},
{"VFMADD213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq},
{"VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADD213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd},
{"VFMADD213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd},
{"VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADD231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq},
{"VFMADD231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq},
{"VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMADD231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq},
{"VFMADD231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq},
{"VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMADD231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq},
{"VFMADD231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq},
{"VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMADD231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq},
{"VFMADD231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq},
{"VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMADD231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq},
{"VFMADD231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq},
{"VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADD231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd},
{"VFMADD231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd},
{"VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512},
{"VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512},
{"VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512},
{"VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512},
{"VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMADDSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq},
{"VFMADDSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq},
{"VFMADDSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq},
{"VFMADDSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd},
{"VFMADDSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd},
{"VFMADDSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd},
{"VFMADDSUB132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq},
{"VFMADDSUB132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq},
{"VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMADDSUB132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq},
{"VFMADDSUB132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq},
{"VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMADDSUB132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq},
{"VFMADDSUB132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq},
{"VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMADDSUB132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq},
{"VFMADDSUB132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq},
{"VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMADDSUB213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq},
{"VFMADDSUB213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq},
{"VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMADDSUB213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq},
{"VFMADDSUB213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq},
{"VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMADDSUB213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq},
{"VFMADDSUB213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq},
{"VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMADDSUB213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq},
{"VFMADDSUB213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq},
{"VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMADDSUB231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq},
{"VFMADDSUB231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq},
{"VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMADDSUB231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq},
{"VFMADDSUB231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq},
{"VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMADDSUB231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq},
{"VFMADDSUB231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq},
{"VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMADDSUB231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq},
{"VFMADDSUB231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq},
{"VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMSUB132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq},
{"VFMSUB132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq},
{"VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMSUB132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq},
{"VFMSUB132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq},
{"VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMSUB132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq},
{"VFMSUB132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq},
{"VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMSUB132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq},
{"VFMSUB132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq},
{"VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMSUB132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq},
{"VFMSUB132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq},
{"VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUB132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd},
{"VFMSUB132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd},
{"VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUB213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq},
{"VFMSUB213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq},
{"VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMSUB213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq},
{"VFMSUB213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq},
{"VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMSUB213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq},
{"VFMSUB213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq},
{"VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMSUB213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq},
{"VFMSUB213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq},
{"VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMSUB213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq},
{"VFMSUB213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq},
{"VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUB213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd},
{"VFMSUB213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd},
{"VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUB231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq},
{"VFMSUB231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq},
{"VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMSUB231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq},
{"VFMSUB231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq},
{"VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMSUB231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq},
{"VFMSUB231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq},
{"VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMSUB231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq},
{"VFMSUB231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq},
{"VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMSUB231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq},
{"VFMSUB231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq},
{"VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUB231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd},
{"VFMSUB231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd},
{"VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUBADD132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq},
{"VFMSUBADD132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq},
{"VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMSUBADD132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq},
{"VFMSUBADD132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq},
{"VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMSUBADD132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq},
{"VFMSUBADD132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq},
{"VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMSUBADD132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq},
{"VFMSUBADD132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq},
{"VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMSUBADD213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq},
{"VFMSUBADD213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq},
{"VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMSUBADD213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq},
{"VFMSUBADD213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq},
{"VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMSUBADD213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq},
{"VFMSUBADD213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq},
{"VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMSUBADD213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq},
{"VFMSUBADD213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq},
{"VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMSUBADD231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq},
{"VFMSUBADD231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq},
{"VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFMSUBADD231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq},
{"VFMSUBADD231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq},
{"VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFMSUBADD231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq},
{"VFMSUBADD231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq},
{"VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFMSUBADD231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq},
{"VFMSUBADD231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq},
{"VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFMSUBSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq},
{"VFMSUBSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq},
{"VFMSUBSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq},
{"VFMSUBSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd},
{"VFMSUBSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd},
{"VFMSUBSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd},
{"VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512},
{"VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512},
{"VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512},
{"VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512},
{"VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512},
{"VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512},
{"VFNMADD132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq},
{"VFNMADD132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq},
{"VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFNMADD132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq},
{"VFNMADD132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq},
{"VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFNMADD132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq},
{"VFNMADD132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq},
{"VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFNMADD132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq},
{"VFNMADD132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq},
{"VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFNMADD132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq},
{"VFNMADD132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq},
{"VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMADD132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd},
{"VFNMADD132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd},
{"VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMADD213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq},
{"VFNMADD213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq},
{"VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFNMADD213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq},
{"VFNMADD213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq},
{"VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFNMADD213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq},
{"VFNMADD213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq},
{"VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFNMADD213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq},
{"VFNMADD213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq},
{"VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFNMADD213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq},
{"VFNMADD213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq},
{"VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMADD213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd},
{"VFNMADD213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd},
{"VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMADD231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq},
{"VFNMADD231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq},
{"VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFNMADD231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq},
{"VFNMADD231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq},
{"VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFNMADD231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq},
{"VFNMADD231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq},
{"VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFNMADD231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq},
{"VFNMADD231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq},
{"VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFNMADD231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq},
{"VFNMADD231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq},
{"VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMADD231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd},
{"VFNMADD231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd},
{"VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFNMADDSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq},
{"VFNMADDSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq},
{"VFNMADDSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq},
{"VFNMADDSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd},
{"VFNMADDSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd},
{"VFNMADDSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd},
{"VFNMSUB132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq},
{"VFNMSUB132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq},
{"VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFNMSUB132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq},
{"VFNMSUB132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq},
{"VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFNMSUB132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq},
{"VFNMSUB132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq},
{"VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFNMSUB132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq},
{"VFNMSUB132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq},
{"VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFNMSUB132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq},
{"VFNMSUB132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq},
{"VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMSUB132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd},
{"VFNMSUB132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd},
{"VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMSUB213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq},
{"VFNMSUB213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq},
{"VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFNMSUB213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq},
{"VFNMSUB213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq},
{"VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFNMSUB213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq},
{"VFNMSUB213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq},
{"VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFNMSUB213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq},
{"VFNMSUB213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq},
{"VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFNMSUB213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq},
{"VFNMSUB213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq},
{"VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMSUB213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd},
{"VFNMSUB213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd},
{"VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMSUB231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq},
{"VFNMSUB231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq},
{"VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VFNMSUB231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq},
{"VFNMSUB231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq},
{"VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VFNMSUB231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq},
{"VFNMSUB231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq},
{"VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VFNMSUB231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq},
{"VFNMSUB231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq},
{"VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VFNMSUB231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq},
{"VFNMSUB231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq},
{"VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VFNMSUB231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd},
{"VFNMSUB231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd},
{"VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq},
{"VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq},
{"VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq},
{"VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq},
{"VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq},
{"VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq},
{"VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq},
{"VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq},
{"VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq},
{"VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd},
{"VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd},
{"VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd},
{"VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128},
{"VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256},
{"VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512},
{"VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512},
{"VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512},
{"VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512},
{"VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128},
{"VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256},
{"VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512},
{"VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512},
{"VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512},
{"VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512},
{"VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128},
{"VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256},
{"VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512},
{"VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512},
{"VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512},
{"VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512},
{"VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512},
{"VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512},
{"VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512},
{"VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512},
{"VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512},
{"VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512},
{"VFRCZPD_XMMdq_MEMdq", XED_IFORM_VFRCZPD_XMMdq_MEMdq},
{"VFRCZPD_XMMdq_XMMdq", XED_IFORM_VFRCZPD_XMMdq_XMMdq},
{"VFRCZPD_YMMqq_MEMqq", XED_IFORM_VFRCZPD_YMMqq_MEMqq},
{"VFRCZPD_YMMqq_YMMqq", XED_IFORM_VFRCZPD_YMMqq_YMMqq},
{"VFRCZPS_XMMdq_MEMdq", XED_IFORM_VFRCZPS_XMMdq_MEMdq},
{"VFRCZPS_XMMdq_XMMdq", XED_IFORM_VFRCZPS_XMMdq_XMMdq},
{"VFRCZPS_YMMqq_MEMqq", XED_IFORM_VFRCZPS_YMMqq_MEMqq},
{"VFRCZPS_YMMqq_YMMqq", XED_IFORM_VFRCZPS_YMMqq_YMMqq},
{"VFRCZSD_XMMdq_MEMq", XED_IFORM_VFRCZSD_XMMdq_MEMq},
{"VFRCZSD_XMMdq_XMMq", XED_IFORM_VFRCZSD_XMMdq_XMMq},
{"VFRCZSS_XMMdq_MEMd", XED_IFORM_VFRCZSS_XMMdq_MEMd},
{"VFRCZSS_XMMdq_XMMd", XED_IFORM_VFRCZSS_XMMdq_XMMd},
{"VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128},
{"VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128", XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128},
{"VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256},
{"VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256", XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256},
{"VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512},
{"VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128},
{"VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128", XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128},
{"VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256},
{"VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256", XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256},
{"VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512},
{"VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128},
{"VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128", XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128},
{"VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256},
{"VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256", XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256},
{"VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512},
{"VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128},
{"VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256},
{"VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128", XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128},
{"VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256", XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256},
{"VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512},
{"VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512},
{"VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512},
{"VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512},
{"VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512},
{"VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512},
{"VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512},
{"VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512},
{"VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512},
{"VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512},
{"VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512},
{"VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512},
{"VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512},
{"VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512},
{"VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512},
{"VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512},
{"VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512},
{"VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512},
{"VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8},
{"VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8},
{"VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512},
{"VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512},
{"VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8},
{"VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8},
{"VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512},
{"VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512},
{"VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512},
{"VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512},
{"VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8},
{"VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8},
{"VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512},
{"VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512},
{"VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8},
{"VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8},
{"VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512},
{"VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512},
{"VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VGF2P8MULB_XMMu8_XMMu8_MEMu8", XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8},
{"VGF2P8MULB_XMMu8_XMMu8_XMMu8", XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8},
{"VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VGF2P8MULB_YMMu8_YMMu8_MEMu8", XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8},
{"VGF2P8MULB_YMMu8_YMMu8_YMMu8", XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8},
{"VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VHADDPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq},
{"VHADDPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq},
{"VHADDPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq},
{"VHADDPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq},
{"VHADDPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq},
{"VHADDPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq},
{"VHADDPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq},
{"VHADDPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq},
{"VHSUBPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq},
{"VHSUBPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq},
{"VHSUBPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq},
{"VHSUBPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq},
{"VHSUBPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq},
{"VHSUBPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq},
{"VHSUBPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq},
{"VHSUBPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq},
{"VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb", XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb},
{"VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb", XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb},
{"VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512},
{"VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512},
{"VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512},
{"VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512},
{"VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512},
{"VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512},
{"VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512},
{"VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512},
{"VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512},
{"VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512},
{"VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512},
{"VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512},
{"VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb", XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb},
{"VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb", XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb},
{"VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512},
{"VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512},
{"VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512},
{"VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512},
{"VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512},
{"VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512},
{"VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512},
{"VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512},
{"VINSERTPS_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb},
{"VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb},
{"VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512},
{"VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512},
{"VLDDQU_XMMdq_MEMdq", XED_IFORM_VLDDQU_XMMdq_MEMdq},
{"VLDDQU_YMMqq_MEMqq", XED_IFORM_VLDDQU_YMMqq_MEMqq},
{"VLDMXCSR_MEMd", XED_IFORM_VLDMXCSR_MEMd},
{"VMASKMOVDQU_XMMdq_XMMdq", XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq},
{"VMASKMOVPD_MEMdq_XMMdq_XMMdq", XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq},
{"VMASKMOVPD_MEMqq_YMMqq_YMMqq", XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq},
{"VMASKMOVPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq},
{"VMASKMOVPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq},
{"VMASKMOVPS_MEMdq_XMMdq_XMMdq", XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq},
{"VMASKMOVPS_MEMqq_YMMqq_YMMqq", XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq},
{"VMASKMOVPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq},
{"VMASKMOVPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq},
{"VMAXPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq},
{"VMAXPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq},
{"VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VMAXPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq},
{"VMAXPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq},
{"VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VMAXPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq},
{"VMAXPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq},
{"VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VMAXPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq},
{"VMAXPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq},
{"VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VMAXSD_XMMdq_XMMdq_MEMq", XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq},
{"VMAXSD_XMMdq_XMMdq_XMMq", XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq},
{"VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VMAXSS_XMMdq_XMMdq_MEMd", XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd},
{"VMAXSS_XMMdq_XMMdq_XMMd", XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd},
{"VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VMCALL", XED_IFORM_VMCALL},
{"VMCLEAR_MEMq", XED_IFORM_VMCLEAR_MEMq},
{"VMFUNC", XED_IFORM_VMFUNC},
{"VMINPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq},
{"VMINPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq},
{"VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VMINPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq},
{"VMINPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq},
{"VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VMINPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq},
{"VMINPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq},
{"VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VMINPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq},
{"VMINPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq},
{"VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VMINSD_XMMdq_XMMdq_MEMq", XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq},
{"VMINSD_XMMdq_XMMdq_XMMq", XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq},
{"VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VMINSS_XMMdq_XMMdq_MEMd", XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd},
{"VMINSS_XMMdq_XMMdq_XMMd", XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd},
{"VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VMLAUNCH", XED_IFORM_VMLAUNCH},
{"VMLOAD_ArAX", XED_IFORM_VMLOAD_ArAX},
{"VMMCALL", XED_IFORM_VMMCALL},
{"VMOVAPD_MEMdq_XMMdq", XED_IFORM_VMOVAPD_MEMdq_XMMdq},
{"VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512},
{"VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512},
{"VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512},
{"VMOVAPD_MEMqq_YMMqq", XED_IFORM_VMOVAPD_MEMqq_YMMqq},
{"VMOVAPD_XMMdq_MEMdq", XED_IFORM_VMOVAPD_XMMdq_MEMdq},
{"VMOVAPD_XMMdq_XMMdq_28", XED_IFORM_VMOVAPD_XMMdq_XMMdq_28},
{"VMOVAPD_XMMdq_XMMdq_29", XED_IFORM_VMOVAPD_XMMdq_XMMdq_29},
{"VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VMOVAPD_YMMqq_MEMqq", XED_IFORM_VMOVAPD_YMMqq_MEMqq},
{"VMOVAPD_YMMqq_YMMqq_28", XED_IFORM_VMOVAPD_YMMqq_YMMqq_28},
{"VMOVAPD_YMMqq_YMMqq_29", XED_IFORM_VMOVAPD_YMMqq_YMMqq_29},
{"VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VMOVAPS_MEMdq_XMMdq", XED_IFORM_VMOVAPS_MEMdq_XMMdq},
{"VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512},
{"VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512},
{"VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512},
{"VMOVAPS_MEMqq_YMMqq", XED_IFORM_VMOVAPS_MEMqq_YMMqq},
{"VMOVAPS_XMMdq_MEMdq", XED_IFORM_VMOVAPS_XMMdq_MEMdq},
{"VMOVAPS_XMMdq_XMMdq_28", XED_IFORM_VMOVAPS_XMMdq_XMMdq_28},
{"VMOVAPS_XMMdq_XMMdq_29", XED_IFORM_VMOVAPS_XMMdq_XMMdq_29},
{"VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VMOVAPS_YMMqq_MEMqq", XED_IFORM_VMOVAPS_YMMqq_MEMqq},
{"VMOVAPS_YMMqq_YMMqq_28", XED_IFORM_VMOVAPS_YMMqq_YMMqq_28},
{"VMOVAPS_YMMqq_YMMqq_29", XED_IFORM_VMOVAPS_YMMqq_YMMqq_29},
{"VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VMOVD_GPR32d_XMMd", XED_IFORM_VMOVD_GPR32d_XMMd},
{"VMOVD_GPR32u32_XMMu32_AVX512", XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512},
{"VMOVD_MEMd_XMMd", XED_IFORM_VMOVD_MEMd_XMMd},
{"VMOVD_MEMu32_XMMu32_AVX512", XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512},
{"VMOVD_XMMdq_GPR32d", XED_IFORM_VMOVD_XMMdq_GPR32d},
{"VMOVD_XMMdq_MEMd", XED_IFORM_VMOVD_XMMdq_MEMd},
{"VMOVD_XMMu32_GPR32u32_AVX512", XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512},
{"VMOVD_XMMu32_MEMu32_AVX512", XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512},
{"VMOVDDUP_XMMdq_MEMq", XED_IFORM_VMOVDDUP_XMMdq_MEMq},
{"VMOVDDUP_XMMdq_XMMq", XED_IFORM_VMOVDDUP_XMMdq_XMMq},
{"VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512},
{"VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512},
{"VMOVDDUP_YMMqq_MEMqq", XED_IFORM_VMOVDDUP_YMMqq_MEMqq},
{"VMOVDDUP_YMMqq_YMMqq", XED_IFORM_VMOVDDUP_YMMqq_YMMqq},
{"VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VMOVDQA_MEMdq_XMMdq", XED_IFORM_VMOVDQA_MEMdq_XMMdq},
{"VMOVDQA_MEMqq_YMMqq", XED_IFORM_VMOVDQA_MEMqq_YMMqq},
{"VMOVDQA_XMMdq_MEMdq", XED_IFORM_VMOVDQA_XMMdq_MEMdq},
{"VMOVDQA_XMMdq_XMMdq_6F", XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F},
{"VMOVDQA_XMMdq_XMMdq_7F", XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F},
{"VMOVDQA_YMMqq_MEMqq", XED_IFORM_VMOVDQA_YMMqq_MEMqq},
{"VMOVDQA_YMMqq_YMMqq_6F", XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F},
{"VMOVDQA_YMMqq_YMMqq_7F", XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F},
{"VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512},
{"VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512},
{"VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512},
{"VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512},
{"VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512},
{"VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512},
{"VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512},
{"VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512},
{"VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512},
{"VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512},
{"VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512},
{"VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512},
{"VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512},
{"VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512},
{"VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512},
{"VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512},
{"VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512},
{"VMOVDQU_MEMdq_XMMdq", XED_IFORM_VMOVDQU_MEMdq_XMMdq},
{"VMOVDQU_MEMqq_YMMqq", XED_IFORM_VMOVDQU_MEMqq_YMMqq},
{"VMOVDQU_XMMdq_MEMdq", XED_IFORM_VMOVDQU_XMMdq_MEMdq},
{"VMOVDQU_XMMdq_XMMdq_6F", XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F},
{"VMOVDQU_XMMdq_XMMdq_7F", XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F},
{"VMOVDQU_YMMqq_MEMqq", XED_IFORM_VMOVDQU_YMMqq_MEMqq},
{"VMOVDQU_YMMqq_YMMqq_6F", XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F},
{"VMOVDQU_YMMqq_YMMqq_7F", XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F},
{"VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512},
{"VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512},
{"VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512},
{"VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512},
{"VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512},
{"VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512},
{"VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512},
{"VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512},
{"VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512},
{"VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512},
{"VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512},
{"VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512},
{"VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512},
{"VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512},
{"VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512},
{"VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512},
{"VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512},
{"VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512},
{"VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512},
{"VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512},
{"VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512},
{"VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512},
{"VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512},
{"VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512},
{"VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512},
{"VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512},
{"VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512},
{"VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512},
{"VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512},
{"VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512},
{"VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512},
{"VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512},
{"VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512},
{"VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512},
{"VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512},
{"VMOVHLPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq},
{"VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512", XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512},
{"VMOVHPD_MEMf64_XMMf64_AVX512", XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512},
{"VMOVHPD_MEMq_XMMdq", XED_IFORM_VMOVHPD_MEMq_XMMdq},
{"VMOVHPD_XMMdq_XMMq_MEMq", XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq},
{"VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512", XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512},
{"VMOVHPS_MEMf32_XMMf32_AVX512", XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512},
{"VMOVHPS_MEMq_XMMdq", XED_IFORM_VMOVHPS_MEMq_XMMdq},
{"VMOVHPS_XMMdq_XMMq_MEMq", XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq},
{"VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512", XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512},
{"VMOVLHPS_XMMdq_XMMq_XMMq", XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq},
{"VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512", XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512},
{"VMOVLPD_MEMf64_XMMf64_AVX512", XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512},
{"VMOVLPD_MEMq_XMMq", XED_IFORM_VMOVLPD_MEMq_XMMq},
{"VMOVLPD_XMMdq_XMMdq_MEMq", XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq},
{"VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512", XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512},
{"VMOVLPS_MEMf32_XMMf32_AVX512", XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512},
{"VMOVLPS_MEMq_XMMq", XED_IFORM_VMOVLPS_MEMq_XMMq},
{"VMOVLPS_XMMdq_XMMdq_MEMq", XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq},
{"VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512", XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512},
{"VMOVMSKPD_GPR32d_XMMdq", XED_IFORM_VMOVMSKPD_GPR32d_XMMdq},
{"VMOVMSKPD_GPR32d_YMMqq", XED_IFORM_VMOVMSKPD_GPR32d_YMMqq},
{"VMOVMSKPS_GPR32d_XMMdq", XED_IFORM_VMOVMSKPS_GPR32d_XMMdq},
{"VMOVMSKPS_GPR32d_YMMqq", XED_IFORM_VMOVMSKPS_GPR32d_YMMqq},
{"VMOVNTDQ_MEMdq_XMMdq", XED_IFORM_VMOVNTDQ_MEMdq_XMMdq},
{"VMOVNTDQ_MEMqq_YMMqq", XED_IFORM_VMOVNTDQ_MEMqq_YMMqq},
{"VMOVNTDQ_MEMu32_XMMu32_AVX512", XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512},
{"VMOVNTDQ_MEMu32_YMMu32_AVX512", XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512},
{"VMOVNTDQ_MEMu32_ZMMu32_AVX512", XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512},
{"VMOVNTDQA_XMMdq_MEMdq", XED_IFORM_VMOVNTDQA_XMMdq_MEMdq},
{"VMOVNTDQA_XMMu32_MEMu32_AVX512", XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512},
{"VMOVNTDQA_YMMqq_MEMqq", XED_IFORM_VMOVNTDQA_YMMqq_MEMqq},
{"VMOVNTDQA_YMMu32_MEMu32_AVX512", XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512},
{"VMOVNTDQA_ZMMu32_MEMu32_AVX512", XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512},
{"VMOVNTPD_MEMdq_XMMdq", XED_IFORM_VMOVNTPD_MEMdq_XMMdq},
{"VMOVNTPD_MEMf64_XMMf64_AVX512", XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512},
{"VMOVNTPD_MEMf64_YMMf64_AVX512", XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512},
{"VMOVNTPD_MEMf64_ZMMf64_AVX512", XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512},
{"VMOVNTPD_MEMqq_YMMqq", XED_IFORM_VMOVNTPD_MEMqq_YMMqq},
{"VMOVNTPS_MEMdq_XMMdq", XED_IFORM_VMOVNTPS_MEMdq_XMMdq},
{"VMOVNTPS_MEMf32_XMMf32_AVX512", XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512},
{"VMOVNTPS_MEMf32_YMMf32_AVX512", XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512},
{"VMOVNTPS_MEMf32_ZMMf32_AVX512", XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512},
{"VMOVNTPS_MEMqq_YMMqq", XED_IFORM_VMOVNTPS_MEMqq_YMMqq},
{"VMOVQ_GPR64q_XMMq", XED_IFORM_VMOVQ_GPR64q_XMMq},
{"VMOVQ_GPR64u64_XMMu64_AVX512", XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512},
{"VMOVQ_MEMq_XMMq_7E", XED_IFORM_VMOVQ_MEMq_XMMq_7E},
{"VMOVQ_MEMq_XMMq_D6", XED_IFORM_VMOVQ_MEMq_XMMq_D6},
{"VMOVQ_MEMu64_XMMu64_AVX512", XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512},
{"VMOVQ_XMMdq_GPR64q", XED_IFORM_VMOVQ_XMMdq_GPR64q},
{"VMOVQ_XMMdq_MEMq_6E", XED_IFORM_VMOVQ_XMMdq_MEMq_6E},
{"VMOVQ_XMMdq_MEMq_7E", XED_IFORM_VMOVQ_XMMdq_MEMq_7E},
{"VMOVQ_XMMdq_XMMq_7E", XED_IFORM_VMOVQ_XMMdq_XMMq_7E},
{"VMOVQ_XMMdq_XMMq_D6", XED_IFORM_VMOVQ_XMMdq_XMMq_D6},
{"VMOVQ_XMMu64_GPR64u64_AVX512", XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512},
{"VMOVQ_XMMu64_MEMu64_AVX512", XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512},
{"VMOVQ_XMMu64_XMMu64_AVX512", XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512},
{"VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512},
{"VMOVSD_MEMq_XMMq", XED_IFORM_VMOVSD_MEMq_XMMq},
{"VMOVSD_XMMdq_MEMq", XED_IFORM_VMOVSD_XMMdq_MEMq},
{"VMOVSD_XMMdq_XMMdq_XMMq_10", XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10},
{"VMOVSD_XMMdq_XMMdq_XMMq_11", XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11},
{"VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512},
{"VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512},
{"VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VMOVSHDUP_XMMdq_MEMdq", XED_IFORM_VMOVSHDUP_XMMdq_MEMdq},
{"VMOVSHDUP_XMMdq_XMMdq", XED_IFORM_VMOVSHDUP_XMMdq_XMMdq},
{"VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512},
{"VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512},
{"VMOVSHDUP_YMMqq_MEMqq", XED_IFORM_VMOVSHDUP_YMMqq_MEMqq},
{"VMOVSHDUP_YMMqq_YMMqq", XED_IFORM_VMOVSHDUP_YMMqq_YMMqq},
{"VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VMOVSLDUP_XMMdq_MEMdq", XED_IFORM_VMOVSLDUP_XMMdq_MEMdq},
{"VMOVSLDUP_XMMdq_XMMdq", XED_IFORM_VMOVSLDUP_XMMdq_XMMdq},
{"VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512},
{"VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512},
{"VMOVSLDUP_YMMqq_MEMqq", XED_IFORM_VMOVSLDUP_YMMqq_MEMqq},
{"VMOVSLDUP_YMMqq_YMMqq", XED_IFORM_VMOVSLDUP_YMMqq_YMMqq},
{"VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VMOVSS_MEMd_XMMd", XED_IFORM_VMOVSS_MEMd_XMMd},
{"VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512},
{"VMOVSS_XMMdq_MEMd", XED_IFORM_VMOVSS_XMMdq_MEMd},
{"VMOVSS_XMMdq_XMMdq_XMMd_10", XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10},
{"VMOVSS_XMMdq_XMMdq_XMMd_11", XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11},
{"VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VMOVUPD_MEMdq_XMMdq", XED_IFORM_VMOVUPD_MEMdq_XMMdq},
{"VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512},
{"VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512},
{"VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512},
{"VMOVUPD_MEMqq_YMMqq", XED_IFORM_VMOVUPD_MEMqq_YMMqq},
{"VMOVUPD_XMMdq_MEMdq", XED_IFORM_VMOVUPD_XMMdq_MEMdq},
{"VMOVUPD_XMMdq_XMMdq_10", XED_IFORM_VMOVUPD_XMMdq_XMMdq_10},
{"VMOVUPD_XMMdq_XMMdq_11", XED_IFORM_VMOVUPD_XMMdq_XMMdq_11},
{"VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VMOVUPD_YMMqq_MEMqq", XED_IFORM_VMOVUPD_YMMqq_MEMqq},
{"VMOVUPD_YMMqq_YMMqq_10", XED_IFORM_VMOVUPD_YMMqq_YMMqq_10},
{"VMOVUPD_YMMqq_YMMqq_11", XED_IFORM_VMOVUPD_YMMqq_YMMqq_11},
{"VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VMOVUPS_MEMdq_XMMdq", XED_IFORM_VMOVUPS_MEMdq_XMMdq},
{"VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512},
{"VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512},
{"VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512},
{"VMOVUPS_MEMqq_YMMqq", XED_IFORM_VMOVUPS_MEMqq_YMMqq},
{"VMOVUPS_XMMdq_MEMdq", XED_IFORM_VMOVUPS_XMMdq_MEMdq},
{"VMOVUPS_XMMdq_XMMdq_10", XED_IFORM_VMOVUPS_XMMdq_XMMdq_10},
{"VMOVUPS_XMMdq_XMMdq_11", XED_IFORM_VMOVUPS_XMMdq_XMMdq_11},
{"VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VMOVUPS_YMMqq_MEMqq", XED_IFORM_VMOVUPS_YMMqq_MEMqq},
{"VMOVUPS_YMMqq_YMMqq_10", XED_IFORM_VMOVUPS_YMMqq_YMMqq_10},
{"VMOVUPS_YMMqq_YMMqq_11", XED_IFORM_VMOVUPS_YMMqq_YMMqq_11},
{"VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VMOVW_GPR32f16_XMMf16_AVX512", XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512},
{"VMOVW_MEMf16_XMMf16_AVX512", XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512},
{"VMOVW_XMMf16_GPR32f16_AVX512", XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512},
{"VMOVW_XMMf16_MEMf16_AVX512", XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512},
{"VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb},
{"VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb},
{"VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb},
{"VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb},
{"VMPTRLD_MEMq", XED_IFORM_VMPTRLD_MEMq},
{"VMPTRST_MEMq", XED_IFORM_VMPTRST_MEMq},
{"VMREAD_GPR32_GPR32", XED_IFORM_VMREAD_GPR32_GPR32},
{"VMREAD_GPR64_GPR64", XED_IFORM_VMREAD_GPR64_GPR64},
{"VMREAD_MEMd_GPR32", XED_IFORM_VMREAD_MEMd_GPR32},
{"VMREAD_MEMq_GPR64", XED_IFORM_VMREAD_MEMq_GPR64},
{"VMRESUME", XED_IFORM_VMRESUME},
{"VMRUN_ArAX", XED_IFORM_VMRUN_ArAX},
{"VMSAVE", XED_IFORM_VMSAVE},
{"VMULPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq},
{"VMULPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq},
{"VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VMULPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq},
{"VMULPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq},
{"VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VMULPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq},
{"VMULPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq},
{"VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VMULPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq},
{"VMULPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq},
{"VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VMULSD_XMMdq_XMMdq_MEMq", XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq},
{"VMULSD_XMMdq_XMMdq_XMMq", XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq},
{"VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VMULSS_XMMdq_XMMdq_MEMd", XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd},
{"VMULSS_XMMdq_XMMdq_XMMd", XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd},
{"VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VMWRITE_GPR32_GPR32", XED_IFORM_VMWRITE_GPR32_GPR32},
{"VMWRITE_GPR32_MEMd", XED_IFORM_VMWRITE_GPR32_MEMd},
{"VMWRITE_GPR64_GPR64", XED_IFORM_VMWRITE_GPR64_GPR64},
{"VMWRITE_GPR64_MEMq", XED_IFORM_VMWRITE_GPR64_MEMq},
{"VMXOFF", XED_IFORM_VMXOFF},
{"VMXON_MEMq", XED_IFORM_VMXON_MEMq},
{"VORPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq},
{"VORPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq},
{"VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VORPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq},
{"VORPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq},
{"VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VORPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq},
{"VORPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq},
{"VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VORPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq},
{"VORPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq},
{"VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512},
{"VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512},
{"VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512},
{"VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512},
{"VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512},
{"VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512},
{"VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512},
{"VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512},
{"VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512},
{"VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512},
{"VPABSB_XMMdq_MEMdq", XED_IFORM_VPABSB_XMMdq_MEMdq},
{"VPABSB_XMMdq_XMMdq", XED_IFORM_VPABSB_XMMdq_XMMdq},
{"VPABSB_XMMi8_MASKmskw_MEMi8_AVX512", XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512},
{"VPABSB_XMMi8_MASKmskw_XMMi8_AVX512", XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512},
{"VPABSB_YMMi8_MASKmskw_MEMi8_AVX512", XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512},
{"VPABSB_YMMi8_MASKmskw_YMMi8_AVX512", XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512},
{"VPABSB_YMMqq_MEMqq", XED_IFORM_VPABSB_YMMqq_MEMqq},
{"VPABSB_YMMqq_YMMqq", XED_IFORM_VPABSB_YMMqq_YMMqq},
{"VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512", XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512},
{"VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512", XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512},
{"VPABSD_XMMdq_MEMdq", XED_IFORM_VPABSD_XMMdq_MEMdq},
{"VPABSD_XMMdq_XMMdq", XED_IFORM_VPABSD_XMMdq_XMMdq},
{"VPABSD_XMMi32_MASKmskw_MEMi32_AVX512", XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512},
{"VPABSD_XMMi32_MASKmskw_XMMi32_AVX512", XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512},
{"VPABSD_YMMi32_MASKmskw_MEMi32_AVX512", XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512},
{"VPABSD_YMMi32_MASKmskw_YMMi32_AVX512", XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512},
{"VPABSD_YMMqq_MEMqq", XED_IFORM_VPABSD_YMMqq_MEMqq},
{"VPABSD_YMMqq_YMMqq", XED_IFORM_VPABSD_YMMqq_YMMqq},
{"VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512", XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512},
{"VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512},
{"VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512", XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512},
{"VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512", XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512},
{"VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512", XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512},
{"VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512", XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512},
{"VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512", XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512},
{"VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512},
{"VPABSW_XMMdq_MEMdq", XED_IFORM_VPABSW_XMMdq_MEMdq},
{"VPABSW_XMMdq_XMMdq", XED_IFORM_VPABSW_XMMdq_XMMdq},
{"VPABSW_XMMi16_MASKmskw_MEMi16_AVX512", XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512},
{"VPABSW_XMMi16_MASKmskw_XMMi16_AVX512", XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512},
{"VPABSW_YMMi16_MASKmskw_MEMi16_AVX512", XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512},
{"VPABSW_YMMi16_MASKmskw_YMMi16_AVX512", XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512},
{"VPABSW_YMMqq_MEMqq", XED_IFORM_VPABSW_YMMqq_MEMqq},
{"VPABSW_YMMqq_YMMqq", XED_IFORM_VPABSW_YMMqq_YMMqq},
{"VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512", XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512},
{"VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512", XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512},
{"VPACKSSDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq},
{"VPACKSSDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq},
{"VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512},
{"VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512},
{"VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512},
{"VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512},
{"VPACKSSDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq},
{"VPACKSSDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq},
{"VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512},
{"VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512},
{"VPACKSSWB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq},
{"VPACKSSWB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq},
{"VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPACKSSWB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq},
{"VPACKSSWB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq},
{"VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPACKUSDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq},
{"VPACKUSDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq},
{"VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPACKUSDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq},
{"VPACKUSDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq},
{"VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPACKUSWB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq},
{"VPACKUSWB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq},
{"VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPACKUSWB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq},
{"VPACKUSWB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq},
{"VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPADDB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq},
{"VPADDB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq},
{"VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPADDB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq},
{"VPADDB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq},
{"VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPADDD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq},
{"VPADDD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq},
{"VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPADDD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq},
{"VPADDD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq},
{"VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPADDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq},
{"VPADDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq},
{"VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPADDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq},
{"VPADDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq},
{"VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPADDSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq},
{"VPADDSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq},
{"VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512},
{"VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512},
{"VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512},
{"VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512},
{"VPADDSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq},
{"VPADDSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq},
{"VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512},
{"VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512},
{"VPADDSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq},
{"VPADDSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq},
{"VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPADDSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq},
{"VPADDSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq},
{"VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPADDUSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq},
{"VPADDUSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq},
{"VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPADDUSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq},
{"VPADDUSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq},
{"VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPADDUSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq},
{"VPADDUSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq},
{"VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPADDUSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq},
{"VPADDUSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq},
{"VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPADDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq},
{"VPADDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq},
{"VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPADDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq},
{"VPADDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq},
{"VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb},
{"VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb},
{"VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512},
{"VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512},
{"VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb},
{"VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb},
{"VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512},
{"VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512},
{"VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512},
{"VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512},
{"VPAND_XMMdq_XMMdq_MEMdq", XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq},
{"VPAND_XMMdq_XMMdq_XMMdq", XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq},
{"VPAND_YMMqq_YMMqq_MEMqq", XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq},
{"VPAND_YMMqq_YMMqq_YMMqq", XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq},
{"VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPANDN_XMMdq_XMMdq_MEMdq", XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq},
{"VPANDN_XMMdq_XMMdq_XMMdq", XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq},
{"VPANDN_YMMqq_YMMqq_MEMqq", XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq},
{"VPANDN_YMMqq_YMMqq_YMMqq", XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq},
{"VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPAVGB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq},
{"VPAVGB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq},
{"VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPAVGB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq},
{"VPAVGB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq},
{"VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPAVGW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq},
{"VPAVGW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq},
{"VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPAVGW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq},
{"VPAVGW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq},
{"VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb},
{"VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb},
{"VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb},
{"VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb},
{"VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq},
{"VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq},
{"VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb},
{"VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb},
{"VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb},
{"VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb},
{"VPBROADCASTB_XMMdq_MEMb", XED_IFORM_VPBROADCASTB_XMMdq_MEMb},
{"VPBROADCASTB_XMMdq_XMMb", XED_IFORM_VPBROADCASTB_XMMdq_XMMb},
{"VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512", XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512},
{"VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512},
{"VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512},
{"VPBROADCASTB_YMMqq_MEMb", XED_IFORM_VPBROADCASTB_YMMqq_MEMb},
{"VPBROADCASTB_YMMqq_XMMb", XED_IFORM_VPBROADCASTB_YMMqq_XMMb},
{"VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512", XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512},
{"VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512},
{"VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512},
{"VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512", XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512},
{"VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512},
{"VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512},
{"VPBROADCASTD_XMMdq_MEMd", XED_IFORM_VPBROADCASTD_XMMdq_MEMd},
{"VPBROADCASTD_XMMdq_XMMd", XED_IFORM_VPBROADCASTD_XMMdq_XMMd},
{"VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512", XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512},
{"VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512},
{"VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512},
{"VPBROADCASTD_YMMqq_MEMd", XED_IFORM_VPBROADCASTD_YMMqq_MEMd},
{"VPBROADCASTD_YMMqq_XMMd", XED_IFORM_VPBROADCASTD_YMMqq_XMMd},
{"VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512", XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512},
{"VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512},
{"VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512},
{"VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512", XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512},
{"VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512},
{"VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512", XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512},
{"VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512", XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512},
{"VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD", XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD},
{"VPBROADCASTMW2D_XMMu32_MASKu32_AVX512", XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512},
{"VPBROADCASTMW2D_YMMu32_MASKu32_AVX512", XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512},
{"VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD", XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD},
{"VPBROADCASTQ_XMMdq_MEMq", XED_IFORM_VPBROADCASTQ_XMMdq_MEMq},
{"VPBROADCASTQ_XMMdq_XMMq", XED_IFORM_VPBROADCASTQ_XMMdq_XMMq},
{"VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512", XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512},
{"VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512},
{"VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512},
{"VPBROADCASTQ_YMMqq_MEMq", XED_IFORM_VPBROADCASTQ_YMMqq_MEMq},
{"VPBROADCASTQ_YMMqq_XMMq", XED_IFORM_VPBROADCASTQ_YMMqq_XMMq},
{"VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512", XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512},
{"VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512},
{"VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512},
{"VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512", XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512},
{"VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512},
{"VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512},
{"VPBROADCASTW_XMMdq_MEMw", XED_IFORM_VPBROADCASTW_XMMdq_MEMw},
{"VPBROADCASTW_XMMdq_XMMw", XED_IFORM_VPBROADCASTW_XMMdq_XMMw},
{"VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512", XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512},
{"VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512},
{"VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512},
{"VPBROADCASTW_YMMqq_MEMw", XED_IFORM_VPBROADCASTW_YMMqq_MEMw},
{"VPBROADCASTW_YMMqq_XMMw", XED_IFORM_VPBROADCASTW_YMMqq_XMMw},
{"VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512", XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512},
{"VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512},
{"VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512},
{"VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512", XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512},
{"VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512},
{"VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512},
{"VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512},
{"VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512},
{"VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8},
{"VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512},
{"VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8},
{"VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512},
{"VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512},
{"VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512},
{"VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq},
{"VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq},
{"VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq},
{"VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq},
{"VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512},
{"VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512},
{"VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512},
{"VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512},
{"VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512},
{"VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512},
{"VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512},
{"VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512},
{"VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512},
{"VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512},
{"VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512},
{"VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512},
{"VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPCMPEQB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq},
{"VPCMPEQB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq},
{"VPCMPEQB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq},
{"VPCMPEQB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq},
{"VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPCMPEQD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq},
{"VPCMPEQD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq},
{"VPCMPEQD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq},
{"VPCMPEQD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq},
{"VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPCMPEQQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq},
{"VPCMPEQQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq},
{"VPCMPEQQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq},
{"VPCMPEQQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq},
{"VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPCMPEQW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq},
{"VPCMPEQW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq},
{"VPCMPEQW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq},
{"VPCMPEQW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq},
{"VPCMPESTRI_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb},
{"VPCMPESTRI_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb},
{"VPCMPESTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb},
{"VPCMPESTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb},
{"VPCMPESTRM_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb},
{"VPCMPESTRM_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb},
{"VPCMPESTRM64_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb},
{"VPCMPESTRM64_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb},
{"VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPCMPGTB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq},
{"VPCMPGTB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq},
{"VPCMPGTB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq},
{"VPCMPGTB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq},
{"VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512},
{"VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512},
{"VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512},
{"VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512},
{"VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512},
{"VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512},
{"VPCMPGTD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq},
{"VPCMPGTD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq},
{"VPCMPGTD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq},
{"VPCMPGTD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq},
{"VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512},
{"VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512},
{"VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512},
{"VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512},
{"VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512},
{"VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512},
{"VPCMPGTQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq},
{"VPCMPGTQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq},
{"VPCMPGTQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq},
{"VPCMPGTQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq},
{"VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPCMPGTW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq},
{"VPCMPGTW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq},
{"VPCMPGTW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq},
{"VPCMPGTW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq},
{"VPCMPISTRI_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb},
{"VPCMPISTRI_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb},
{"VPCMPISTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb},
{"VPCMPISTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb},
{"VPCMPISTRM_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb},
{"VPCMPISTRM_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb},
{"VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512},
{"VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512},
{"VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512},
{"VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512},
{"VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512},
{"VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512},
{"VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512},
{"VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512},
{"VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512},
{"VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512},
{"VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512},
{"VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512},
{"VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512},
{"VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512},
{"VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512},
{"VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512},
{"VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512},
{"VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512},
{"VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512},
{"VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512},
{"VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512},
{"VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512},
{"VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512},
{"VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512},
{"VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512},
{"VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512},
{"VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512},
{"VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512},
{"VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512},
{"VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512},
{"VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512},
{"VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512},
{"VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512},
{"VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512},
{"VPCOMB_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMB_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCOMD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512},
{"VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512},
{"VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512},
{"VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512},
{"VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512},
{"VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512},
{"VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512},
{"VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512},
{"VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512},
{"VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512},
{"VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512},
{"VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512},
{"VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512},
{"VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512},
{"VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512},
{"VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512},
{"VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512},
{"VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512},
{"VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512},
{"VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512},
{"VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512},
{"VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512},
{"VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512},
{"VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512},
{"VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCOMW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb},
{"VPCOMW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb},
{"VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512},
{"VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512},
{"VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512},
{"VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512},
{"VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD", XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD},
{"VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD", XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD},
{"VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512},
{"VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512},
{"VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512},
{"VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512},
{"VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD", XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD},
{"VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD", XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD},
{"VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512},
{"VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512", XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512},
{"VPDPBUSD_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32},
{"VPDPBUSD_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32},
{"VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512},
{"VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512", XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512},
{"VPDPBUSD_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32},
{"VPDPBUSD_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32},
{"VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512},
{"VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512", XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512},
{"VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512},
{"VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512", XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512},
{"VPDPBUSDS_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32},
{"VPDPBUSDS_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32},
{"VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512},
{"VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512", XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512},
{"VPDPBUSDS_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32},
{"VPDPBUSDS_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32},
{"VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512},
{"VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512", XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512},
{"VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512},
{"VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512", XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512},
{"VPDPWSSD_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32},
{"VPDPWSSD_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32},
{"VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512},
{"VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512", XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512},
{"VPDPWSSD_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32},
{"VPDPWSSD_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32},
{"VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512},
{"VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512", XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512},
{"VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512},
{"VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512", XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512},
{"VPDPWSSDS_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32},
{"VPDPWSSDS_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32},
{"VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512},
{"VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512", XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512},
{"VPDPWSSDS_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32},
{"VPDPWSSDS_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32},
{"VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512},
{"VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512", XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512},
{"VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb},
{"VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb},
{"VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb},
{"VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb},
{"VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPERMD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq},
{"VPERMD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq},
{"VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb},
{"VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb},
{"VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb},
{"VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb},
{"VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb},
{"VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb},
{"VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb},
{"VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb},
{"VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb},
{"VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb},
{"VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb},
{"VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb},
{"VPERMILPD_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb},
{"VPERMILPD_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb},
{"VPERMILPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq},
{"VPERMILPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq},
{"VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512},
{"VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512},
{"VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VPERMILPD_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb},
{"VPERMILPD_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb},
{"VPERMILPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq},
{"VPERMILPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq},
{"VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VPERMILPS_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb},
{"VPERMILPS_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb},
{"VPERMILPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq},
{"VPERMILPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq},
{"VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512},
{"VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512},
{"VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VPERMILPS_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb},
{"VPERMILPS_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb},
{"VPERMILPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq},
{"VPERMILPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq},
{"VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512},
{"VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VPERMPD_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb},
{"VPERMPD_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb},
{"VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VPERMPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq},
{"VPERMPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq},
{"VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VPERMQ_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb},
{"VPERMQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb},
{"VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512},
{"VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512},
{"VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512},
{"VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512},
{"VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512},
{"VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512},
{"VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512},
{"VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512},
{"VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512},
{"VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512},
{"VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512},
{"VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512},
{"VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512},
{"VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512},
{"VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512},
{"VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512},
{"VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512},
{"VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512},
{"VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512},
{"VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512},
{"VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512},
{"VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512},
{"VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512},
{"VPEXTRB_GPR32d_XMMdq_IMMb", XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb},
{"VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512", XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512},
{"VPEXTRB_MEMb_XMMdq_IMMb", XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb},
{"VPEXTRB_MEMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512},
{"VPEXTRD_GPR32d_XMMdq_IMMb", XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb},
{"VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512", XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512},
{"VPEXTRD_MEMd_XMMdq_IMMb", XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb},
{"VPEXTRD_MEMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512},
{"VPEXTRQ_GPR64q_XMMdq_IMMb", XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb},
{"VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512", XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512},
{"VPEXTRQ_MEMq_XMMdq_IMMb", XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb},
{"VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512},
{"VPEXTRW_GPR32d_XMMdq_IMMb_15", XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15},
{"VPEXTRW_GPR32d_XMMdq_IMMb_C5", XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5},
{"VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512", XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512},
{"VPEXTRW_MEMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512},
{"VPEXTRW_MEMw_XMMdq_IMMb", XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb},
{"VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5", XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5},
{"VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128", XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128},
{"VPGATHERDD_XMMu32_MEMd_XMMi32_VL128", XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128},
{"VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256", XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256},
{"VPGATHERDD_YMMu32_MEMd_YMMi32_VL256", XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256},
{"VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512", XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512},
{"VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128},
{"VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128", XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128},
{"VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256},
{"VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256", XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256},
{"VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512},
{"VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128", XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128},
{"VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256", XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256},
{"VPGATHERQD_XMMu32_MEMd_XMMi32_VL128", XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128},
{"VPGATHERQD_XMMu32_MEMd_XMMi32_VL256", XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256},
{"VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512", XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512},
{"VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128},
{"VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128", XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128},
{"VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256},
{"VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256", XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256},
{"VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512},
{"VPHADDBD_XMMdq_MEMdq", XED_IFORM_VPHADDBD_XMMdq_MEMdq},
{"VPHADDBD_XMMdq_XMMdq", XED_IFORM_VPHADDBD_XMMdq_XMMdq},
{"VPHADDBQ_XMMdq_MEMdq", XED_IFORM_VPHADDBQ_XMMdq_MEMdq},
{"VPHADDBQ_XMMdq_XMMdq", XED_IFORM_VPHADDBQ_XMMdq_XMMdq},
{"VPHADDBW_XMMdq_MEMdq", XED_IFORM_VPHADDBW_XMMdq_MEMdq},
{"VPHADDBW_XMMdq_XMMdq", XED_IFORM_VPHADDBW_XMMdq_XMMdq},
{"VPHADDD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq},
{"VPHADDD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq},
{"VPHADDD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq},
{"VPHADDD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq},
{"VPHADDDQ_XMMdq_MEMdq", XED_IFORM_VPHADDDQ_XMMdq_MEMdq},
{"VPHADDDQ_XMMdq_XMMdq", XED_IFORM_VPHADDDQ_XMMdq_XMMdq},
{"VPHADDSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq},
{"VPHADDSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq},
{"VPHADDSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq},
{"VPHADDSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq},
{"VPHADDUBD_XMMdq_MEMdq", XED_IFORM_VPHADDUBD_XMMdq_MEMdq},
{"VPHADDUBD_XMMdq_XMMdq", XED_IFORM_VPHADDUBD_XMMdq_XMMdq},
{"VPHADDUBQ_XMMdq_MEMdq", XED_IFORM_VPHADDUBQ_XMMdq_MEMdq},
{"VPHADDUBQ_XMMdq_XMMdq", XED_IFORM_VPHADDUBQ_XMMdq_XMMdq},
{"VPHADDUBW_XMMdq_MEMdq", XED_IFORM_VPHADDUBW_XMMdq_MEMdq},
{"VPHADDUBW_XMMdq_XMMdq", XED_IFORM_VPHADDUBW_XMMdq_XMMdq},
{"VPHADDUDQ_XMMdq_MEMdq", XED_IFORM_VPHADDUDQ_XMMdq_MEMdq},
{"VPHADDUDQ_XMMdq_XMMdq", XED_IFORM_VPHADDUDQ_XMMdq_XMMdq},
{"VPHADDUWD_XMMdq_MEMdq", XED_IFORM_VPHADDUWD_XMMdq_MEMdq},
{"VPHADDUWD_XMMdq_XMMdq", XED_IFORM_VPHADDUWD_XMMdq_XMMdq},
{"VPHADDUWQ_XMMdq_MEMdq", XED_IFORM_VPHADDUWQ_XMMdq_MEMdq},
{"VPHADDUWQ_XMMdq_XMMdq", XED_IFORM_VPHADDUWQ_XMMdq_XMMdq},
{"VPHADDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq},
{"VPHADDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq},
{"VPHADDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq},
{"VPHADDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq},
{"VPHADDWD_XMMdq_MEMdq", XED_IFORM_VPHADDWD_XMMdq_MEMdq},
{"VPHADDWD_XMMdq_XMMdq", XED_IFORM_VPHADDWD_XMMdq_XMMdq},
{"VPHADDWQ_XMMdq_MEMdq", XED_IFORM_VPHADDWQ_XMMdq_MEMdq},
{"VPHADDWQ_XMMdq_XMMdq", XED_IFORM_VPHADDWQ_XMMdq_XMMdq},
{"VPHMINPOSUW_XMMdq_MEMdq", XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq},
{"VPHMINPOSUW_XMMdq_XMMdq", XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq},
{"VPHSUBBW_XMMdq_MEMdq", XED_IFORM_VPHSUBBW_XMMdq_MEMdq},
{"VPHSUBBW_XMMdq_XMMdq", XED_IFORM_VPHSUBBW_XMMdq_XMMdq},
{"VPHSUBD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq},
{"VPHSUBD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq},
{"VPHSUBD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq},
{"VPHSUBD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq},
{"VPHSUBDQ_XMMdq_MEMdq", XED_IFORM_VPHSUBDQ_XMMdq_MEMdq},
{"VPHSUBDQ_XMMdq_XMMdq", XED_IFORM_VPHSUBDQ_XMMdq_XMMdq},
{"VPHSUBSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq},
{"VPHSUBSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq},
{"VPHSUBSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq},
{"VPHSUBSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq},
{"VPHSUBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq},
{"VPHSUBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq},
{"VPHSUBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq},
{"VPHSUBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq},
{"VPHSUBWD_XMMdq_MEMdq", XED_IFORM_VPHSUBWD_XMMdq_MEMdq},
{"VPHSUBWD_XMMdq_XMMdq", XED_IFORM_VPHSUBWD_XMMdq_XMMdq},
{"VPINSRB_XMMdq_XMMdq_GPR32d_IMMb", XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb},
{"VPINSRB_XMMdq_XMMdq_MEMb_IMMb", XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb},
{"VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512", XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512},
{"VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512},
{"VPINSRD_XMMdq_XMMdq_GPR32d_IMMb", XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb},
{"VPINSRD_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb},
{"VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512", XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512},
{"VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512},
{"VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb", XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb},
{"VPINSRQ_XMMdq_XMMdq_MEMq_IMMb", XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb},
{"VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512", XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512},
{"VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512},
{"VPINSRW_XMMdq_XMMdq_GPR32d_IMMb", XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb},
{"VPINSRW_XMMdq_XMMdq_MEMw_IMMb", XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb},
{"VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512", XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512},
{"VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512},
{"VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512},
{"VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512},
{"VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512},
{"VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512},
{"VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD", XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD},
{"VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD", XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD},
{"VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512},
{"VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512},
{"VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512},
{"VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512},
{"VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD", XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD},
{"VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD", XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD},
{"VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPMADDUBSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq},
{"VPMADDUBSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq},
{"VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPMADDUBSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq},
{"VPMADDUBSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq},
{"VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPMADDWD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq},
{"VPMADDWD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq},
{"VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPMADDWD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq},
{"VPMADDWD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq},
{"VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPMASKMOVD_MEMdq_XMMdq_XMMdq", XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq},
{"VPMASKMOVD_MEMqq_YMMqq_YMMqq", XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq},
{"VPMASKMOVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq},
{"VPMASKMOVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq},
{"VPMASKMOVQ_MEMdq_XMMdq_XMMdq", XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq},
{"VPMASKMOVQ_MEMqq_YMMqq_YMMqq", XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq},
{"VPMASKMOVQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq},
{"VPMASKMOVQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq},
{"VPMAXSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq},
{"VPMAXSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq},
{"VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512},
{"VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512},
{"VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512},
{"VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512},
{"VPMAXSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq},
{"VPMAXSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq},
{"VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512},
{"VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512},
{"VPMAXSD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq},
{"VPMAXSD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq},
{"VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512},
{"VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512},
{"VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512},
{"VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512},
{"VPMAXSD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq},
{"VPMAXSD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq},
{"VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512},
{"VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512},
{"VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512", XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512},
{"VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512", XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512},
{"VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512", XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512},
{"VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512", XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512},
{"VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512", XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512},
{"VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512", XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512},
{"VPMAXSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq},
{"VPMAXSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq},
{"VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPMAXSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq},
{"VPMAXSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq},
{"VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPMAXUB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq},
{"VPMAXUB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq},
{"VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPMAXUB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq},
{"VPMAXUB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq},
{"VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPMAXUD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq},
{"VPMAXUD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq},
{"VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPMAXUD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq},
{"VPMAXUD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq},
{"VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPMAXUW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq},
{"VPMAXUW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq},
{"VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPMAXUW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq},
{"VPMAXUW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq},
{"VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPMINSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq},
{"VPMINSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq},
{"VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512},
{"VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512},
{"VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512},
{"VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512},
{"VPMINSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq},
{"VPMINSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq},
{"VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512},
{"VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512},
{"VPMINSD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq},
{"VPMINSD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq},
{"VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512},
{"VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512},
{"VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512},
{"VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512},
{"VPMINSD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq},
{"VPMINSD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq},
{"VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512},
{"VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512},
{"VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512", XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512},
{"VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512", XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512},
{"VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512", XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512},
{"VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512", XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512},
{"VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512", XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512},
{"VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512", XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512},
{"VPMINSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq},
{"VPMINSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq},
{"VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPMINSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq},
{"VPMINSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq},
{"VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPMINUB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq},
{"VPMINUB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq},
{"VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPMINUB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq},
{"VPMINUB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq},
{"VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPMINUD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq},
{"VPMINUD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq},
{"VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPMINUD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq},
{"VPMINUD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq},
{"VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPMINUW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq},
{"VPMINUW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq},
{"VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPMINUW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq},
{"VPMINUW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq},
{"VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPMOVB2M_MASKmskw_XMMu8_AVX512", XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512},
{"VPMOVB2M_MASKmskw_YMMu8_AVX512", XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512},
{"VPMOVB2M_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512},
{"VPMOVD2M_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512},
{"VPMOVD2M_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512},
{"VPMOVD2M_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512},
{"VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512},
{"VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512},
{"VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512},
{"VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512},
{"VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512},
{"VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512},
{"VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512},
{"VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512},
{"VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512},
{"VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512},
{"VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512},
{"VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512},
{"VPMOVM2B_XMMu8_MASKmskw_AVX512", XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512},
{"VPMOVM2B_YMMu8_MASKmskw_AVX512", XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512},
{"VPMOVM2B_ZMMu8_MASKmskw_AVX512", XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512},
{"VPMOVM2D_XMMu32_MASKmskw_AVX512", XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512},
{"VPMOVM2D_YMMu32_MASKmskw_AVX512", XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512},
{"VPMOVM2D_ZMMu32_MASKmskw_AVX512", XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512},
{"VPMOVM2Q_XMMu64_MASKmskw_AVX512", XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512},
{"VPMOVM2Q_YMMu64_MASKmskw_AVX512", XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512},
{"VPMOVM2Q_ZMMu64_MASKmskw_AVX512", XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512},
{"VPMOVM2W_XMMu16_MASKmskw_AVX512", XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512},
{"VPMOVM2W_YMMu16_MASKmskw_AVX512", XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512},
{"VPMOVM2W_ZMMu16_MASKmskw_AVX512", XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512},
{"VPMOVMSKB_GPR32d_XMMdq", XED_IFORM_VPMOVMSKB_GPR32d_XMMdq},
{"VPMOVMSKB_GPR32d_YMMqq", XED_IFORM_VPMOVMSKB_GPR32d_YMMqq},
{"VPMOVQ2M_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512},
{"VPMOVQ2M_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512},
{"VPMOVQ2M_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512},
{"VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512},
{"VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512},
{"VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512},
{"VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512},
{"VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512},
{"VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512},
{"VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512},
{"VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512},
{"VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512},
{"VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512},
{"VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512},
{"VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512},
{"VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512},
{"VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512},
{"VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512},
{"VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512},
{"VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512},
{"VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512},
{"VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512},
{"VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512},
{"VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512},
{"VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512},
{"VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512},
{"VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512},
{"VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512},
{"VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512},
{"VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512},
{"VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512},
{"VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512},
{"VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512},
{"VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512},
{"VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512},
{"VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512},
{"VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512},
{"VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512},
{"VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512},
{"VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512},
{"VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512},
{"VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512},
{"VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512},
{"VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512},
{"VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512},
{"VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512},
{"VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512},
{"VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512},
{"VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512},
{"VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512},
{"VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512},
{"VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512},
{"VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512},
{"VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512", XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512},
{"VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512},
{"VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512},
{"VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512", XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512},
{"VPMOVSXBD_XMMdq_MEMd", XED_IFORM_VPMOVSXBD_XMMdq_MEMd},
{"VPMOVSXBD_XMMdq_XMMd", XED_IFORM_VPMOVSXBD_XMMdq_XMMd},
{"VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBD_YMMqq_MEMq", XED_IFORM_VPMOVSXBD_YMMqq_MEMq},
{"VPMOVSXBD_YMMqq_XMMq", XED_IFORM_VPMOVSXBD_YMMqq_XMMq},
{"VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBQ_XMMdq_MEMw", XED_IFORM_VPMOVSXBQ_XMMdq_MEMw},
{"VPMOVSXBQ_XMMdq_XMMw", XED_IFORM_VPMOVSXBQ_XMMdq_XMMw},
{"VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBQ_YMMqq_MEMd", XED_IFORM_VPMOVSXBQ_YMMqq_MEMd},
{"VPMOVSXBQ_YMMqq_XMMd", XED_IFORM_VPMOVSXBQ_YMMqq_XMMd},
{"VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBW_XMMdq_MEMq", XED_IFORM_VPMOVSXBW_XMMdq_MEMq},
{"VPMOVSXBW_XMMdq_XMMq", XED_IFORM_VPMOVSXBW_XMMdq_XMMq},
{"VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512},
{"VPMOVSXBW_YMMqq_MEMdq", XED_IFORM_VPMOVSXBW_YMMqq_MEMdq},
{"VPMOVSXBW_YMMqq_XMMdq", XED_IFORM_VPMOVSXBW_YMMqq_XMMdq},
{"VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512},
{"VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512", XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512},
{"VPMOVSXDQ_XMMdq_MEMq", XED_IFORM_VPMOVSXDQ_XMMdq_MEMq},
{"VPMOVSXDQ_XMMdq_XMMq", XED_IFORM_VPMOVSXDQ_XMMdq_XMMq},
{"VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512},
{"VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512},
{"VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512},
{"VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512},
{"VPMOVSXDQ_YMMqq_MEMdq", XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq},
{"VPMOVSXDQ_YMMqq_XMMdq", XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq},
{"VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512},
{"VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512},
{"VPMOVSXWD_XMMdq_MEMq", XED_IFORM_VPMOVSXWD_XMMdq_MEMq},
{"VPMOVSXWD_XMMdq_XMMq", XED_IFORM_VPMOVSXWD_XMMdq_XMMq},
{"VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512},
{"VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512},
{"VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512},
{"VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512},
{"VPMOVSXWD_YMMqq_MEMdq", XED_IFORM_VPMOVSXWD_YMMqq_MEMdq},
{"VPMOVSXWD_YMMqq_XMMdq", XED_IFORM_VPMOVSXWD_YMMqq_XMMdq},
{"VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512},
{"VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512},
{"VPMOVSXWQ_XMMdq_MEMd", XED_IFORM_VPMOVSXWQ_XMMdq_MEMd},
{"VPMOVSXWQ_XMMdq_XMMd", XED_IFORM_VPMOVSXWQ_XMMdq_XMMd},
{"VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512},
{"VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512},
{"VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512},
{"VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512},
{"VPMOVSXWQ_YMMqq_MEMq", XED_IFORM_VPMOVSXWQ_YMMqq_MEMq},
{"VPMOVSXWQ_YMMqq_XMMq", XED_IFORM_VPMOVSXWQ_YMMqq_XMMq},
{"VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512},
{"VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512},
{"VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512},
{"VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512},
{"VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512},
{"VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512},
{"VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512},
{"VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512},
{"VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512},
{"VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512},
{"VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512},
{"VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512},
{"VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512},
{"VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512},
{"VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512},
{"VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512},
{"VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512},
{"VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512},
{"VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512},
{"VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512},
{"VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512},
{"VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512},
{"VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512},
{"VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512},
{"VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512},
{"VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512},
{"VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512},
{"VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512},
{"VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512},
{"VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512},
{"VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512},
{"VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512},
{"VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512},
{"VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512},
{"VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512},
{"VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512},
{"VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512},
{"VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512},
{"VPMOVW2M_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512},
{"VPMOVW2M_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512},
{"VPMOVW2M_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512},
{"VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512},
{"VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512},
{"VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512},
{"VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512},
{"VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512},
{"VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512},
{"VPMOVZXBD_XMMdq_MEMd", XED_IFORM_VPMOVZXBD_XMMdq_MEMd},
{"VPMOVZXBD_XMMdq_XMMd", XED_IFORM_VPMOVZXBD_XMMdq_XMMd},
{"VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBD_YMMqq_MEMq", XED_IFORM_VPMOVZXBD_YMMqq_MEMq},
{"VPMOVZXBD_YMMqq_XMMq", XED_IFORM_VPMOVZXBD_YMMqq_XMMq},
{"VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBQ_XMMdq_MEMw", XED_IFORM_VPMOVZXBQ_XMMdq_MEMw},
{"VPMOVZXBQ_XMMdq_XMMw", XED_IFORM_VPMOVZXBQ_XMMdq_XMMw},
{"VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBQ_YMMqq_MEMd", XED_IFORM_VPMOVZXBQ_YMMqq_MEMd},
{"VPMOVZXBQ_YMMqq_XMMd", XED_IFORM_VPMOVZXBQ_YMMqq_XMMd},
{"VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBW_XMMdq_MEMq", XED_IFORM_VPMOVZXBW_XMMdq_MEMq},
{"VPMOVZXBW_XMMdq_XMMq", XED_IFORM_VPMOVZXBW_XMMdq_XMMq},
{"VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512},
{"VPMOVZXBW_YMMqq_MEMdq", XED_IFORM_VPMOVZXBW_YMMqq_MEMdq},
{"VPMOVZXBW_YMMqq_XMMdq", XED_IFORM_VPMOVZXBW_YMMqq_XMMdq},
{"VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512},
{"VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512", XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512},
{"VPMOVZXDQ_XMMdq_MEMq", XED_IFORM_VPMOVZXDQ_XMMdq_MEMq},
{"VPMOVZXDQ_XMMdq_XMMq", XED_IFORM_VPMOVZXDQ_XMMdq_XMMq},
{"VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512},
{"VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512},
{"VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512},
{"VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512},
{"VPMOVZXDQ_YMMqq_MEMdq", XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq},
{"VPMOVZXDQ_YMMqq_XMMdq", XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq},
{"VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512},
{"VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512},
{"VPMOVZXWD_XMMdq_MEMq", XED_IFORM_VPMOVZXWD_XMMdq_MEMq},
{"VPMOVZXWD_XMMdq_XMMq", XED_IFORM_VPMOVZXWD_XMMdq_XMMq},
{"VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512},
{"VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512},
{"VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512},
{"VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512},
{"VPMOVZXWD_YMMqq_MEMdq", XED_IFORM_VPMOVZXWD_YMMqq_MEMdq},
{"VPMOVZXWD_YMMqq_XMMdq", XED_IFORM_VPMOVZXWD_YMMqq_XMMdq},
{"VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512},
{"VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512},
{"VPMOVZXWQ_XMMdq_MEMd", XED_IFORM_VPMOVZXWQ_XMMdq_MEMd},
{"VPMOVZXWQ_XMMdq_XMMd", XED_IFORM_VPMOVZXWQ_XMMdq_XMMd},
{"VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512},
{"VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512},
{"VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512},
{"VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512},
{"VPMOVZXWQ_YMMqq_MEMq", XED_IFORM_VPMOVZXWQ_YMMqq_MEMq},
{"VPMOVZXWQ_YMMqq_XMMq", XED_IFORM_VPMOVZXWQ_YMMqq_XMMq},
{"VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512},
{"VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512},
{"VPMULDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq},
{"VPMULDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq},
{"VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512},
{"VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512},
{"VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512},
{"VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512},
{"VPMULDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq},
{"VPMULDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq},
{"VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512},
{"VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512},
{"VPMULHRSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq},
{"VPMULHRSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq},
{"VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPMULHRSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq},
{"VPMULHRSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq},
{"VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPMULHUW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq},
{"VPMULHUW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq},
{"VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPMULHUW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq},
{"VPMULHUW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq},
{"VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPMULHW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq},
{"VPMULHW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq},
{"VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPMULHW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq},
{"VPMULHW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq},
{"VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPMULLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq},
{"VPMULLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq},
{"VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPMULLD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq},
{"VPMULLD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq},
{"VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPMULLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq},
{"VPMULLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq},
{"VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPMULLW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq},
{"VPMULLW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq},
{"VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512},
{"VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512},
{"VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512},
{"VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512},
{"VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512},
{"VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512},
{"VPMULUDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq},
{"VPMULUDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq},
{"VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPMULUDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq},
{"VPMULUDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq},
{"VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512},
{"VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512},
{"VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512},
{"VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512},
{"VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512},
{"VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512},
{"VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512},
{"VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512},
{"VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512},
{"VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512},
{"VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512},
{"VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512},
{"VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512},
{"VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512},
{"VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512},
{"VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512},
{"VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512},
{"VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512},
{"VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512},
{"VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512},
{"VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512},
{"VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512},
{"VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512},
{"VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512},
{"VPOR_XMMdq_XMMdq_MEMdq", XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq},
{"VPOR_XMMdq_XMMdq_XMMdq", XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq},
{"VPOR_YMMqq_YMMqq_MEMqq", XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq},
{"VPOR_YMMqq_YMMqq_YMMqq", XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq},
{"VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPPERM_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq},
{"VPPERM_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq},
{"VPPERM_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq},
{"VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512},
{"VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512},
{"VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512},
{"VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512},
{"VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPROTB_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb},
{"VPROTB_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq},
{"VPROTB_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb},
{"VPROTB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq},
{"VPROTB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq},
{"VPROTD_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb},
{"VPROTD_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq},
{"VPROTD_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb},
{"VPROTD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq},
{"VPROTD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq},
{"VPROTQ_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb},
{"VPROTQ_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq},
{"VPROTQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb},
{"VPROTQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq},
{"VPROTQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq},
{"VPROTW_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb},
{"VPROTW_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq},
{"VPROTW_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb},
{"VPROTW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq},
{"VPROTW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq},
{"VPSADBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq},
{"VPSADBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq},
{"VPSADBW_XMMu16_XMMu8_MEMu8_AVX512", XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512},
{"VPSADBW_XMMu16_XMMu8_XMMu8_AVX512", XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512},
{"VPSADBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq},
{"VPSADBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq},
{"VPSADBW_YMMu16_YMMu8_MEMu8_AVX512", XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512},
{"VPSADBW_YMMu16_YMMu8_YMMu8_AVX512", XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512},
{"VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512},
{"VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512},
{"VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128", XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128},
{"VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256", XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256},
{"VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512", XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512},
{"VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128},
{"VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256},
{"VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512},
{"VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128", XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128},
{"VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256", XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256},
{"VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512", XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512},
{"VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128},
{"VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256},
{"VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512},
{"VPSHAB_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq},
{"VPSHAB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq},
{"VPSHAB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq},
{"VPSHAD_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq},
{"VPSHAD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq},
{"VPSHAD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq},
{"VPSHAQ_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq},
{"VPSHAQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq},
{"VPSHAQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq},
{"VPSHAW_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq},
{"VPSHAW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq},
{"VPSHAW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq},
{"VPSHLB_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq},
{"VPSHLB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq},
{"VPSHLB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq},
{"VPSHLD_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq},
{"VPSHLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq},
{"VPSHLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq},
{"VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512},
{"VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512},
{"VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512},
{"VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512},
{"VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512},
{"VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512},
{"VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512},
{"VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512},
{"VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512},
{"VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512},
{"VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512},
{"VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512},
{"VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512},
{"VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512},
{"VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512},
{"VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512},
{"VPSHLQ_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq},
{"VPSHLQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq},
{"VPSHLQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq},
{"VPSHLW_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq},
{"VPSHLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq},
{"VPSHLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq},
{"VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512},
{"VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512},
{"VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512},
{"VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512},
{"VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512},
{"VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512},
{"VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512},
{"VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512},
{"VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512},
{"VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512},
{"VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512},
{"VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512},
{"VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512},
{"VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512},
{"VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512},
{"VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512},
{"VPSHUFB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq},
{"VPSHUFB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq},
{"VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPSHUFB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq},
{"VPSHUFB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq},
{"VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512},
{"VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512},
{"VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512},
{"VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512},
{"VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512},
{"VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512},
{"VPSHUFD_XMMdq_MEMdq_IMMb", XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb},
{"VPSHUFD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb},
{"VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512},
{"VPSHUFD_YMMqq_MEMqq_IMMb", XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb},
{"VPSHUFD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb},
{"VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VPSHUFHW_XMMdq_MEMdq_IMMb", XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb},
{"VPSHUFHW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb},
{"VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512},
{"VPSHUFHW_YMMqq_MEMqq_IMMb", XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb},
{"VPSHUFHW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb},
{"VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512},
{"VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512},
{"VPSHUFLW_XMMdq_MEMdq_IMMb", XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb},
{"VPSHUFLW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb},
{"VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512},
{"VPSHUFLW_YMMqq_MEMqq_IMMb", XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb},
{"VPSHUFLW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb},
{"VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512},
{"VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512},
{"VPSIGNB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq},
{"VPSIGNB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq},
{"VPSIGNB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq},
{"VPSIGNB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq},
{"VPSIGND_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq},
{"VPSIGND_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq},
{"VPSIGND_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq},
{"VPSIGND_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq},
{"VPSIGNW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq},
{"VPSIGNW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq},
{"VPSIGNW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq},
{"VPSIGNW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq},
{"VPSLLD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb},
{"VPSLLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq},
{"VPSLLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq},
{"VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512},
{"VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSLLD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb},
{"VPSLLD_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq},
{"VPSLLD_YMMqq_YMMqq_XMMq", XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq},
{"VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512},
{"VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512},
{"VPSLLDQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb},
{"VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512},
{"VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512},
{"VPSLLDQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb},
{"VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512},
{"VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512},
{"VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512},
{"VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512},
{"VPSLLQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb},
{"VPSLLQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq},
{"VPSLLQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq},
{"VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512},
{"VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSLLQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb},
{"VPSLLQ_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq},
{"VPSLLQ_YMMqq_YMMqq_XMMq", XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq},
{"VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512},
{"VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512},
{"VPSLLVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq},
{"VPSLLVD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq},
{"VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSLLVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq},
{"VPSLLVD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq},
{"VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPSLLVQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq},
{"VPSLLVQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq},
{"VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSLLVQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq},
{"VPSLLVQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq},
{"VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPSLLW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb},
{"VPSLLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq},
{"VPSLLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq},
{"VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512},
{"VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSLLW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb},
{"VPSLLW_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq},
{"VPSLLW_YMMqq_YMMqq_XMMq", XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq},
{"VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512},
{"VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512},
{"VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512},
{"VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512},
{"VPSRAD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb},
{"VPSRAD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq},
{"VPSRAD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq},
{"VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512},
{"VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSRAD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb},
{"VPSRAD_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq},
{"VPSRAD_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq},
{"VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512},
{"VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512},
{"VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512},
{"VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512},
{"VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512},
{"VPSRAVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq},
{"VPSRAVD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq},
{"VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSRAVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq},
{"VPSRAVD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq},
{"VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPSRAW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb},
{"VPSRAW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq},
{"VPSRAW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq},
{"VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512},
{"VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSRAW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb},
{"VPSRAW_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq},
{"VPSRAW_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq},
{"VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512},
{"VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512},
{"VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512},
{"VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512},
{"VPSRLD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb},
{"VPSRLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq},
{"VPSRLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq},
{"VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512},
{"VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSRLD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb},
{"VPSRLD_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq},
{"VPSRLD_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq},
{"VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512},
{"VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512},
{"VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512},
{"VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512},
{"VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512},
{"VPSRLDQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb},
{"VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512},
{"VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512},
{"VPSRLDQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb},
{"VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512},
{"VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512},
{"VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512},
{"VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512},
{"VPSRLQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb},
{"VPSRLQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq},
{"VPSRLQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq},
{"VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512},
{"VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSRLQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb},
{"VPSRLQ_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq},
{"VPSRLQ_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq},
{"VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512},
{"VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512},
{"VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512},
{"VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512},
{"VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512},
{"VPSRLVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq},
{"VPSRLVD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq},
{"VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSRLVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq},
{"VPSRLVD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq},
{"VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPSRLVQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq},
{"VPSRLVQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq},
{"VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSRLVQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq},
{"VPSRLVQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq},
{"VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPSRLW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb},
{"VPSRLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq},
{"VPSRLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq},
{"VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512},
{"VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSRLW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb},
{"VPSRLW_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq},
{"VPSRLW_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq},
{"VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512},
{"VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512},
{"VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512},
{"VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512},
{"VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512},
{"VPSUBB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq},
{"VPSUBB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq},
{"VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPSUBB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq},
{"VPSUBB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq},
{"VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPSUBD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq},
{"VPSUBD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq},
{"VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPSUBD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq},
{"VPSUBD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq},
{"VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPSUBQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq},
{"VPSUBQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq},
{"VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPSUBQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq},
{"VPSUBQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq},
{"VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPSUBSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq},
{"VPSUBSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq},
{"VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512},
{"VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512},
{"VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512},
{"VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512},
{"VPSUBSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq},
{"VPSUBSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq},
{"VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512},
{"VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512},
{"VPSUBSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq},
{"VPSUBSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq},
{"VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512},
{"VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512},
{"VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512},
{"VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512},
{"VPSUBSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq},
{"VPSUBSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq},
{"VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512},
{"VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512},
{"VPSUBUSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq},
{"VPSUBUSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq},
{"VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPSUBUSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq},
{"VPSUBUSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq},
{"VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPSUBUSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq},
{"VPSUBUSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq},
{"VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSUBUSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq},
{"VPSUBUSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq},
{"VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPSUBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq},
{"VPSUBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq},
{"VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPSUBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq},
{"VPSUBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq},
{"VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512},
{"VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512},
{"VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512},
{"VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512},
{"VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512},
{"VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512},
{"VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512},
{"VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512},
{"VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512},
{"VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512},
{"VPTEST_XMMdq_MEMdq", XED_IFORM_VPTEST_XMMdq_MEMdq},
{"VPTEST_XMMdq_XMMdq", XED_IFORM_VPTEST_XMMdq_XMMdq},
{"VPTEST_YMMqq_MEMqq", XED_IFORM_VPTEST_YMMqq_MEMqq},
{"VPTEST_YMMqq_YMMqq", XED_IFORM_VPTEST_YMMqq_YMMqq},
{"VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPUNPCKHBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq},
{"VPUNPCKHBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq},
{"VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPUNPCKHBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq},
{"VPUNPCKHBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq},
{"VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPUNPCKHDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq},
{"VPUNPCKHDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq},
{"VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPUNPCKHDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq},
{"VPUNPCKHDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq},
{"VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq},
{"VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq},
{"VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq},
{"VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq},
{"VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPUNPCKHWD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq},
{"VPUNPCKHWD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq},
{"VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPUNPCKHWD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq},
{"VPUNPCKHWD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq},
{"VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPUNPCKLBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq},
{"VPUNPCKLBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq},
{"VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512},
{"VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512},
{"VPUNPCKLBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq},
{"VPUNPCKLBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq},
{"VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512},
{"VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512},
{"VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512},
{"VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512},
{"VPUNPCKLDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq},
{"VPUNPCKLDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq},
{"VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPUNPCKLDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq},
{"VPUNPCKLDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq},
{"VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq},
{"VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq},
{"VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq},
{"VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq},
{"VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VPUNPCKLWD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq},
{"VPUNPCKLWD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq},
{"VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512},
{"VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512},
{"VPUNPCKLWD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq},
{"VPUNPCKLWD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq},
{"VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512},
{"VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512},
{"VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512},
{"VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512},
{"VPXOR_XMMdq_XMMdq_MEMdq", XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq},
{"VPXOR_XMMdq_XMMdq_XMMdq", XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq},
{"VPXOR_YMMqq_YMMqq_MEMqq", XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq},
{"VPXOR_YMMqq_YMMqq_YMMqq", XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq},
{"VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512},
{"VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512},
{"VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512},
{"VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512},
{"VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512},
{"VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512},
{"VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512},
{"VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512},
{"VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER", XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER},
{"VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER", XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER},
{"VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER", XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER},
{"VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER", XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER},
{"VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER", XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER},
{"VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER", XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER},
{"VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER", XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER},
{"VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER", XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER},
{"VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512},
{"VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512},
{"VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512},
{"VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512},
{"VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512},
{"VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512},
{"VRCPPS_XMMdq_MEMdq", XED_IFORM_VRCPPS_XMMdq_MEMdq},
{"VRCPPS_XMMdq_XMMdq", XED_IFORM_VRCPPS_XMMdq_XMMdq},
{"VRCPPS_YMMqq_MEMqq", XED_IFORM_VRCPPS_YMMqq_MEMqq},
{"VRCPPS_YMMqq_YMMqq", XED_IFORM_VRCPPS_YMMqq_YMMqq},
{"VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VRCPSS_XMMdq_XMMdq_MEMd", XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd},
{"VRCPSS_XMMdq_XMMdq_XMMd", XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd},
{"VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512},
{"VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512},
{"VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512},
{"VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512},
{"VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512},
{"VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512},
{"VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512},
{"VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512},
{"VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512},
{"VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512},
{"VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512},
{"VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512},
{"VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512},
{"VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512},
{"VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512},
{"VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512},
{"VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512},
{"VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512},
{"VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512},
{"VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512},
{"VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512},
{"VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512},
{"VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512},
{"VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VROUNDPD_XMMdq_MEMdq_IMMb", XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb},
{"VROUNDPD_XMMdq_XMMdq_IMMb", XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb},
{"VROUNDPD_YMMqq_MEMqq_IMMb", XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb},
{"VROUNDPD_YMMqq_YMMqq_IMMb", XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb},
{"VROUNDPS_XMMdq_MEMdq_IMMb", XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb},
{"VROUNDPS_XMMdq_XMMdq_IMMb", XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb},
{"VROUNDPS_YMMqq_MEMqq_IMMb", XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb},
{"VROUNDPS_YMMqq_YMMqq_IMMb", XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb},
{"VROUNDSD_XMMdq_XMMdq_MEMq_IMMb", XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb},
{"VROUNDSD_XMMdq_XMMdq_XMMq_IMMb", XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb},
{"VROUNDSS_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb},
{"VROUNDSS_XMMdq_XMMdq_XMMd_IMMb", XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb},
{"VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER", XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER},
{"VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER", XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER},
{"VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER", XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER},
{"VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER", XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER},
{"VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER", XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER},
{"VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER", XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER},
{"VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER", XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER},
{"VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER", XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER},
{"VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512},
{"VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512},
{"VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512},
{"VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512},
{"VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512},
{"VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512},
{"VRSQRTPS_XMMdq_MEMdq", XED_IFORM_VRSQRTPS_XMMdq_MEMdq},
{"VRSQRTPS_XMMdq_XMMdq", XED_IFORM_VRSQRTPS_XMMdq_XMMdq},
{"VRSQRTPS_YMMqq_MEMqq", XED_IFORM_VRSQRTPS_YMMqq_MEMqq},
{"VRSQRTPS_YMMqq_YMMqq", XED_IFORM_VRSQRTPS_YMMqq_YMMqq},
{"VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VRSQRTSS_XMMdq_XMMdq_MEMd", XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd},
{"VRSQRTSS_XMMdq_XMMdq_XMMd", XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd},
{"VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128},
{"VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256},
{"VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512},
{"VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128", XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128},
{"VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256", XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256},
{"VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512", XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512},
{"VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512},
{"VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512},
{"VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128},
{"VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256},
{"VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512},
{"VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128", XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128},
{"VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256", XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256},
{"VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512", XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512},
{"VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512},
{"VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512},
{"VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512},
{"VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512},
{"VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512},
{"VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512},
{"VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512},
{"VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512},
{"VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512},
{"VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512},
{"VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512},
{"VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512},
{"VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512},
{"VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512},
{"VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512},
{"VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512},
{"VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb},
{"VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb},
{"VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512},
{"VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512},
{"VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512},
{"VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512},
{"VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb},
{"VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb},
{"VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512},
{"VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512},
{"VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb},
{"VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb},
{"VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512},
{"VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512},
{"VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512},
{"VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512},
{"VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb},
{"VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb},
{"VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512},
{"VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512},
{"VSQRTPD_XMMdq_MEMdq", XED_IFORM_VSQRTPD_XMMdq_MEMdq},
{"VSQRTPD_XMMdq_XMMdq", XED_IFORM_VSQRTPD_XMMdq_XMMdq},
{"VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512},
{"VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512},
{"VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512},
{"VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512},
{"VSQRTPD_YMMqq_MEMqq", XED_IFORM_VSQRTPD_YMMqq_MEMqq},
{"VSQRTPD_YMMqq_YMMqq", XED_IFORM_VSQRTPD_YMMqq_YMMqq},
{"VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512},
{"VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512},
{"VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512},
{"VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512},
{"VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512},
{"VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512},
{"VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512},
{"VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512},
{"VSQRTPS_XMMdq_MEMdq", XED_IFORM_VSQRTPS_XMMdq_MEMdq},
{"VSQRTPS_XMMdq_XMMdq", XED_IFORM_VSQRTPS_XMMdq_XMMdq},
{"VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512},
{"VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512},
{"VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512},
{"VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512},
{"VSQRTPS_YMMqq_MEMqq", XED_IFORM_VSQRTPS_YMMqq_MEMqq},
{"VSQRTPS_YMMqq_YMMqq", XED_IFORM_VSQRTPS_YMMqq_YMMqq},
{"VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512},
{"VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512},
{"VSQRTSD_XMMdq_XMMdq_MEMq", XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq},
{"VSQRTSD_XMMdq_XMMdq_XMMq", XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq},
{"VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VSQRTSS_XMMdq_XMMdq_MEMd", XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd},
{"VSQRTSS_XMMdq_XMMdq_XMMd", XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd},
{"VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VSTMXCSR_MEMd", XED_IFORM_VSTMXCSR_MEMd},
{"VSUBPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq},
{"VSUBPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq},
{"VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VSUBPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq},
{"VSUBPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq},
{"VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512},
{"VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512},
{"VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512},
{"VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512},
{"VSUBPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq},
{"VSUBPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq},
{"VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VSUBPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq},
{"VSUBPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq},
{"VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VSUBSD_XMMdq_XMMdq_MEMq", XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq},
{"VSUBSD_XMMdq_XMMdq_XMMq", XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq},
{"VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512},
{"VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512},
{"VSUBSS_XMMdq_XMMdq_MEMd", XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd},
{"VSUBSS_XMMdq_XMMdq_XMMd", XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd},
{"VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VTESTPD_XMMdq_MEMdq", XED_IFORM_VTESTPD_XMMdq_MEMdq},
{"VTESTPD_XMMdq_XMMdq", XED_IFORM_VTESTPD_XMMdq_XMMdq},
{"VTESTPD_YMMqq_MEMqq", XED_IFORM_VTESTPD_YMMqq_MEMqq},
{"VTESTPD_YMMqq_YMMqq", XED_IFORM_VTESTPD_YMMqq_YMMqq},
{"VTESTPS_XMMdq_MEMdq", XED_IFORM_VTESTPS_XMMdq_MEMdq},
{"VTESTPS_XMMdq_XMMdq", XED_IFORM_VTESTPS_XMMdq_XMMdq},
{"VTESTPS_YMMqq_MEMqq", XED_IFORM_VTESTPS_YMMqq_MEMqq},
{"VTESTPS_YMMqq_YMMqq", XED_IFORM_VTESTPS_YMMqq_YMMqq},
{"VUCOMISD_XMMdq_MEMq", XED_IFORM_VUCOMISD_XMMdq_MEMq},
{"VUCOMISD_XMMdq_XMMq", XED_IFORM_VUCOMISD_XMMdq_XMMq},
{"VUCOMISD_XMMf64_MEMf64_AVX512", XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512},
{"VUCOMISD_XMMf64_XMMf64_AVX512", XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512},
{"VUCOMISH_XMMf16_MEMf16_AVX512", XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512},
{"VUCOMISH_XMMf16_XMMf16_AVX512", XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512},
{"VUCOMISS_XMMdq_MEMd", XED_IFORM_VUCOMISS_XMMdq_MEMd},
{"VUCOMISS_XMMdq_XMMd", XED_IFORM_VUCOMISS_XMMdq_XMMd},
{"VUCOMISS_XMMf32_MEMf32_AVX512", XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512},
{"VUCOMISS_XMMf32_XMMf32_AVX512", XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512},
{"VUNPCKHPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq},
{"VUNPCKHPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq},
{"VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VUNPCKHPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq},
{"VUNPCKHPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq},
{"VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VUNPCKHPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq},
{"VUNPCKHPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq},
{"VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VUNPCKHPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq},
{"VUNPCKHPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq},
{"VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VUNPCKLPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq},
{"VUNPCKLPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq},
{"VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512},
{"VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512},
{"VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512},
{"VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512},
{"VUNPCKLPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq},
{"VUNPCKLPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq},
{"VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512},
{"VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512},
{"VUNPCKLPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq},
{"VUNPCKLPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq},
{"VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512},
{"VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512},
{"VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512},
{"VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512},
{"VUNPCKLPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq},
{"VUNPCKLPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq},
{"VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512},
{"VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512},
{"VXORPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq},
{"VXORPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq},
{"VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512},
{"VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512},
{"VXORPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq},
{"VXORPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq},
{"VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512},
{"VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512},
{"VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512},
{"VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512},
{"VXORPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq},
{"VXORPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq},
{"VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512},
{"VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512},
{"VXORPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq},
{"VXORPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq},
{"VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512},
{"VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512},
{"VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512},
{"VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512},
{"VZEROALL", XED_IFORM_VZEROALL},
{"VZEROUPPER", XED_IFORM_VZEROUPPER},
{"WBINVD", XED_IFORM_WBINVD},
{"WBNOINVD", XED_IFORM_WBNOINVD},
{"WRFSBASE_GPRy", XED_IFORM_WRFSBASE_GPRy},
{"WRGSBASE_GPRy", XED_IFORM_WRGSBASE_GPRy},
{"WRMSR", XED_IFORM_WRMSR},
{"WRPKRU", XED_IFORM_WRPKRU},
{"WRSSD_MEMu32_GPR32u32", XED_IFORM_WRSSD_MEMu32_GPR32u32},
{"WRSSQ_MEMu64_GPR64u64", XED_IFORM_WRSSQ_MEMu64_GPR64u64},
{"WRUSSD_MEMu32_GPR32u32", XED_IFORM_WRUSSD_MEMu32_GPR32u32},
{"WRUSSQ_MEMu64_GPR64u64", XED_IFORM_WRUSSQ_MEMu64_GPR64u64},
{"XABORT_IMMb", XED_IFORM_XABORT_IMMb},
{"XADD_GPR8_GPR8", XED_IFORM_XADD_GPR8_GPR8},
{"XADD_GPRv_GPRv", XED_IFORM_XADD_GPRv_GPRv},
{"XADD_MEMb_GPR8", XED_IFORM_XADD_MEMb_GPR8},
{"XADD_MEMv_GPRv", XED_IFORM_XADD_MEMv_GPRv},
{"XADD_LOCK_MEMb_GPR8", XED_IFORM_XADD_LOCK_MEMb_GPR8},
{"XADD_LOCK_MEMv_GPRv", XED_IFORM_XADD_LOCK_MEMv_GPRv},
{"XBEGIN_RELBRz", XED_IFORM_XBEGIN_RELBRz},
{"XCHG_GPR8_GPR8", XED_IFORM_XCHG_GPR8_GPR8},
{"XCHG_GPRv_GPRv", XED_IFORM_XCHG_GPRv_GPRv},
{"XCHG_GPRv_OrAX", XED_IFORM_XCHG_GPRv_OrAX},
{"XCHG_MEMb_GPR8", XED_IFORM_XCHG_MEMb_GPR8},
{"XCHG_MEMv_GPRv", XED_IFORM_XCHG_MEMv_GPRv},
{"XEND", XED_IFORM_XEND},
{"XGETBV", XED_IFORM_XGETBV},
{"XLAT", XED_IFORM_XLAT},
{"XOR_AL_IMMb", XED_IFORM_XOR_AL_IMMb},
{"XOR_GPR8_GPR8_30", XED_IFORM_XOR_GPR8_GPR8_30},
{"XOR_GPR8_GPR8_32", XED_IFORM_XOR_GPR8_GPR8_32},
{"XOR_GPR8_IMMb_80r6", XED_IFORM_XOR_GPR8_IMMb_80r6},
{"XOR_GPR8_IMMb_82r6", XED_IFORM_XOR_GPR8_IMMb_82r6},
{"XOR_GPR8_MEMb", XED_IFORM_XOR_GPR8_MEMb},
{"XOR_GPRv_GPRv_31", XED_IFORM_XOR_GPRv_GPRv_31},
{"XOR_GPRv_GPRv_33", XED_IFORM_XOR_GPRv_GPRv_33},
{"XOR_GPRv_IMMb", XED_IFORM_XOR_GPRv_IMMb},
{"XOR_GPRv_IMMz", XED_IFORM_XOR_GPRv_IMMz},
{"XOR_GPRv_MEMv", XED_IFORM_XOR_GPRv_MEMv},
{"XOR_MEMb_GPR8", XED_IFORM_XOR_MEMb_GPR8},
{"XOR_MEMb_IMMb_80r6", XED_IFORM_XOR_MEMb_IMMb_80r6},
{"XOR_MEMb_IMMb_82r6", XED_IFORM_XOR_MEMb_IMMb_82r6},
{"XOR_MEMv_GPRv", XED_IFORM_XOR_MEMv_GPRv},
{"XOR_MEMv_IMMb", XED_IFORM_XOR_MEMv_IMMb},
{"XOR_MEMv_IMMz", XED_IFORM_XOR_MEMv_IMMz},
{"XOR_OrAX_IMMz", XED_IFORM_XOR_OrAX_IMMz},
{"XORPD_XMMxuq_MEMxuq", XED_IFORM_XORPD_XMMxuq_MEMxuq},
{"XORPD_XMMxuq_XMMxuq", XED_IFORM_XORPD_XMMxuq_XMMxuq},
{"XORPS_XMMxud_MEMxud", XED_IFORM_XORPS_XMMxud_MEMxud},
{"XORPS_XMMxud_XMMxud", XED_IFORM_XORPS_XMMxud_XMMxud},
{"XOR_LOCK_MEMb_GPR8", XED_IFORM_XOR_LOCK_MEMb_GPR8},
{"XOR_LOCK_MEMb_IMMb_80r6", XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6},
{"XOR_LOCK_MEMb_IMMb_82r6", XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6},
{"XOR_LOCK_MEMv_GPRv", XED_IFORM_XOR_LOCK_MEMv_GPRv},
{"XOR_LOCK_MEMv_IMMb", XED_IFORM_XOR_LOCK_MEMv_IMMb},
{"XOR_LOCK_MEMv_IMMz", XED_IFORM_XOR_LOCK_MEMv_IMMz},
{"XRESLDTRK", XED_IFORM_XRESLDTRK},
{"XRSTOR_MEMmxsave", XED_IFORM_XRSTOR_MEMmxsave},
{"XRSTOR64_MEMmxsave", XED_IFORM_XRSTOR64_MEMmxsave},
{"XRSTORS_MEMmxsave", XED_IFORM_XRSTORS_MEMmxsave},
{"XRSTORS64_MEMmxsave", XED_IFORM_XRSTORS64_MEMmxsave},
{"XSAVE_MEMmxsave", XED_IFORM_XSAVE_MEMmxsave},
{"XSAVE64_MEMmxsave", XED_IFORM_XSAVE64_MEMmxsave},
{"XSAVEC_MEMmxsave", XED_IFORM_XSAVEC_MEMmxsave},
{"XSAVEC64_MEMmxsave", XED_IFORM_XSAVEC64_MEMmxsave},
{"XSAVEOPT_MEMmxsave", XED_IFORM_XSAVEOPT_MEMmxsave},
{"XSAVEOPT64_MEMmxsave", XED_IFORM_XSAVEOPT64_MEMmxsave},
{"XSAVES_MEMmxsave", XED_IFORM_XSAVES_MEMmxsave},
{"XSAVES64_MEMmxsave", XED_IFORM_XSAVES64_MEMmxsave},
{"XSETBV", XED_IFORM_XSETBV},
{"XSTORE", XED_IFORM_XSTORE},
{"XSUSLDTRK", XED_IFORM_XSUSLDTRK},
{"XTEST", XED_IFORM_XTEST},
{"LAST", XED_IFORM_LAST},
{0, XED_IFORM_LAST},
};

        
xed_iform_enum_t str2xed_iform_enum_t(const char* s)
{
   const name_table_xed_iform_enum_t* p = name_array_xed_iform_enum_t;
   while( p->name ) {
     if (strcmp(p->name,s) == 0) {
      return p->value;
     }
     p++;
   }
        

   return XED_IFORM_INVALID;
}


const char* xed_iform_enum_t2str(const xed_iform_enum_t p)
{
   xed_iform_enum_t type_idx = p;
   if ( p > XED_IFORM_LAST) type_idx = XED_IFORM_LAST;
   return name_array_xed_iform_enum_t[type_idx].name;
}

xed_iform_enum_t xed_iform_enum_t_last(void) {
    return XED_IFORM_LAST;
}
       
/*

Here is a skeleton switch statement embedded in a comment


  switch(p) {
  case XED_IFORM_INVALID:
  case XED_IFORM_AAA:
  case XED_IFORM_AAD_IMMb:
  case XED_IFORM_AAM_IMMb:
  case XED_IFORM_AAS:
  case XED_IFORM_ADC_AL_IMMb:
  case XED_IFORM_ADC_GPR8_GPR8_10:
  case XED_IFORM_ADC_GPR8_GPR8_12:
  case XED_IFORM_ADC_GPR8_IMMb_80r2:
  case XED_IFORM_ADC_GPR8_IMMb_82r2:
  case XED_IFORM_ADC_GPR8_MEMb:
  case XED_IFORM_ADC_GPRv_GPRv_11:
  case XED_IFORM_ADC_GPRv_GPRv_13:
  case XED_IFORM_ADC_GPRv_IMMb:
  case XED_IFORM_ADC_GPRv_IMMz:
  case XED_IFORM_ADC_GPRv_MEMv:
  case XED_IFORM_ADC_MEMb_GPR8:
  case XED_IFORM_ADC_MEMb_IMMb_80r2:
  case XED_IFORM_ADC_MEMb_IMMb_82r2:
  case XED_IFORM_ADC_MEMv_GPRv:
  case XED_IFORM_ADC_MEMv_IMMb:
  case XED_IFORM_ADC_MEMv_IMMz:
  case XED_IFORM_ADC_OrAX_IMMz:
  case XED_IFORM_ADCX_GPR32d_GPR32d:
  case XED_IFORM_ADCX_GPR32d_MEMd:
  case XED_IFORM_ADCX_GPR64q_GPR64q:
  case XED_IFORM_ADCX_GPR64q_MEMq:
  case XED_IFORM_ADC_LOCK_MEMb_GPR8:
  case XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2:
  case XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2:
  case XED_IFORM_ADC_LOCK_MEMv_GPRv:
  case XED_IFORM_ADC_LOCK_MEMv_IMMb:
  case XED_IFORM_ADC_LOCK_MEMv_IMMz:
  case XED_IFORM_ADD_AL_IMMb:
  case XED_IFORM_ADD_GPR8_GPR8_00:
  case XED_IFORM_ADD_GPR8_GPR8_02:
  case XED_IFORM_ADD_GPR8_IMMb_80r0:
  case XED_IFORM_ADD_GPR8_IMMb_82r0:
  case XED_IFORM_ADD_GPR8_MEMb:
  case XED_IFORM_ADD_GPRv_GPRv_01:
  case XED_IFORM_ADD_GPRv_GPRv_03:
  case XED_IFORM_ADD_GPRv_IMMb:
  case XED_IFORM_ADD_GPRv_IMMz:
  case XED_IFORM_ADD_GPRv_MEMv:
  case XED_IFORM_ADD_MEMb_GPR8:
  case XED_IFORM_ADD_MEMb_IMMb_80r0:
  case XED_IFORM_ADD_MEMb_IMMb_82r0:
  case XED_IFORM_ADD_MEMv_GPRv:
  case XED_IFORM_ADD_MEMv_IMMb:
  case XED_IFORM_ADD_MEMv_IMMz:
  case XED_IFORM_ADD_OrAX_IMMz:
  case XED_IFORM_ADDPD_XMMpd_MEMpd:
  case XED_IFORM_ADDPD_XMMpd_XMMpd:
  case XED_IFORM_ADDPS_XMMps_MEMps:
  case XED_IFORM_ADDPS_XMMps_XMMps:
  case XED_IFORM_ADDSD_XMMsd_MEMsd:
  case XED_IFORM_ADDSD_XMMsd_XMMsd:
  case XED_IFORM_ADDSS_XMMss_MEMss:
  case XED_IFORM_ADDSS_XMMss_XMMss:
  case XED_IFORM_ADDSUBPD_XMMpd_MEMpd:
  case XED_IFORM_ADDSUBPD_XMMpd_XMMpd:
  case XED_IFORM_ADDSUBPS_XMMps_MEMps:
  case XED_IFORM_ADDSUBPS_XMMps_XMMps:
  case XED_IFORM_ADD_LOCK_MEMb_GPR8:
  case XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0:
  case XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0:
  case XED_IFORM_ADD_LOCK_MEMv_GPRv:
  case XED_IFORM_ADD_LOCK_MEMv_IMMb:
  case XED_IFORM_ADD_LOCK_MEMv_IMMz:
  case XED_IFORM_ADOX_GPR32d_GPR32d:
  case XED_IFORM_ADOX_GPR32d_MEMd:
  case XED_IFORM_ADOX_GPR64q_GPR64q:
  case XED_IFORM_ADOX_GPR64q_MEMq:
  case XED_IFORM_AESDEC_XMMdq_MEMdq:
  case XED_IFORM_AESDEC_XMMdq_XMMdq:
  case XED_IFORM_AESDEC128KL_XMMu8_MEMu8:
  case XED_IFORM_AESDEC256KL_XMMu8_MEMu8:
  case XED_IFORM_AESDECLAST_XMMdq_MEMdq:
  case XED_IFORM_AESDECLAST_XMMdq_XMMdq:
  case XED_IFORM_AESDECWIDE128KL_MEMu8:
  case XED_IFORM_AESDECWIDE256KL_MEMu8:
  case XED_IFORM_AESENC_XMMdq_MEMdq:
  case XED_IFORM_AESENC_XMMdq_XMMdq:
  case XED_IFORM_AESENC128KL_XMMu8_MEMu8:
  case XED_IFORM_AESENC256KL_XMMu8_MEMu8:
  case XED_IFORM_AESENCLAST_XMMdq_MEMdq:
  case XED_IFORM_AESENCLAST_XMMdq_XMMdq:
  case XED_IFORM_AESENCWIDE128KL_MEMu8:
  case XED_IFORM_AESENCWIDE256KL_MEMu8:
  case XED_IFORM_AESIMC_XMMdq_MEMdq:
  case XED_IFORM_AESIMC_XMMdq_XMMdq:
  case XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb:
  case XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb:
  case XED_IFORM_AND_AL_IMMb:
  case XED_IFORM_AND_GPR8_GPR8_20:
  case XED_IFORM_AND_GPR8_GPR8_22:
  case XED_IFORM_AND_GPR8_IMMb_80r4:
  case XED_IFORM_AND_GPR8_IMMb_82r4:
  case XED_IFORM_AND_GPR8_MEMb:
  case XED_IFORM_AND_GPRv_GPRv_21:
  case XED_IFORM_AND_GPRv_GPRv_23:
  case XED_IFORM_AND_GPRv_IMMb:
  case XED_IFORM_AND_GPRv_IMMz:
  case XED_IFORM_AND_GPRv_MEMv:
  case XED_IFORM_AND_MEMb_GPR8:
  case XED_IFORM_AND_MEMb_IMMb_80r4:
  case XED_IFORM_AND_MEMb_IMMb_82r4:
  case XED_IFORM_AND_MEMv_GPRv:
  case XED_IFORM_AND_MEMv_IMMb:
  case XED_IFORM_AND_MEMv_IMMz:
  case XED_IFORM_AND_OrAX_IMMz:
  case XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd:
  case XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq:
  case XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_ANDNPD_XMMxuq_MEMxuq:
  case XED_IFORM_ANDNPD_XMMxuq_XMMxuq:
  case XED_IFORM_ANDNPS_XMMxud_MEMxud:
  case XED_IFORM_ANDNPS_XMMxud_XMMxud:
  case XED_IFORM_ANDPD_XMMxuq_MEMxuq:
  case XED_IFORM_ANDPD_XMMxuq_XMMxuq:
  case XED_IFORM_ANDPS_XMMxud_MEMxud:
  case XED_IFORM_ANDPS_XMMxud_XMMxud:
  case XED_IFORM_AND_LOCK_MEMb_GPR8:
  case XED_IFORM_AND_LOCK_MEMb_IMMb_80r4:
  case XED_IFORM_AND_LOCK_MEMb_IMMb_82r4:
  case XED_IFORM_AND_LOCK_MEMv_GPRv:
  case XED_IFORM_AND_LOCK_MEMv_IMMb:
  case XED_IFORM_AND_LOCK_MEMv_IMMz:
  case XED_IFORM_ARPL_GPR16_GPR16:
  case XED_IFORM_ARPL_MEMw_GPR16:
  case XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d:
  case XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q:
  case XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd:
  case XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd:
  case XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd:
  case XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd:
  case XED_IFORM_BLCFILL_VGPR32d_MEMd:
  case XED_IFORM_BLCFILL_VGPR32d_VGPR32d:
  case XED_IFORM_BLCFILL_VGPRyy_MEMy:
  case XED_IFORM_BLCFILL_VGPRyy_VGPRyy:
  case XED_IFORM_BLCI_VGPR32d_MEMd:
  case XED_IFORM_BLCI_VGPR32d_VGPR32d:
  case XED_IFORM_BLCI_VGPRyy_MEMy:
  case XED_IFORM_BLCI_VGPRyy_VGPRyy:
  case XED_IFORM_BLCIC_VGPR32d_MEMd:
  case XED_IFORM_BLCIC_VGPR32d_VGPR32d:
  case XED_IFORM_BLCIC_VGPRyy_MEMy:
  case XED_IFORM_BLCIC_VGPRyy_VGPRyy:
  case XED_IFORM_BLCMSK_VGPR32d_MEMd:
  case XED_IFORM_BLCMSK_VGPR32d_VGPR32d:
  case XED_IFORM_BLCMSK_VGPRyy_MEMy:
  case XED_IFORM_BLCMSK_VGPRyy_VGPRyy:
  case XED_IFORM_BLCS_VGPR32d_MEMd:
  case XED_IFORM_BLCS_VGPR32d_VGPR32d:
  case XED_IFORM_BLCS_VGPRyy_MEMy:
  case XED_IFORM_BLCS_VGPRyy_VGPRyy:
  case XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb:
  case XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb:
  case XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb:
  case XED_IFORM_BLENDVPD_XMMdq_MEMdq:
  case XED_IFORM_BLENDVPD_XMMdq_XMMdq:
  case XED_IFORM_BLENDVPS_XMMdq_MEMdq:
  case XED_IFORM_BLENDVPS_XMMdq_XMMdq:
  case XED_IFORM_BLSFILL_VGPR32d_MEMd:
  case XED_IFORM_BLSFILL_VGPR32d_VGPR32d:
  case XED_IFORM_BLSFILL_VGPRyy_MEMy:
  case XED_IFORM_BLSFILL_VGPRyy_VGPRyy:
  case XED_IFORM_BLSI_VGPR32d_MEMd:
  case XED_IFORM_BLSI_VGPR32d_VGPR32d:
  case XED_IFORM_BLSI_VGPR64q_MEMq:
  case XED_IFORM_BLSI_VGPR64q_VGPR64q:
  case XED_IFORM_BLSIC_VGPR32d_MEMd:
  case XED_IFORM_BLSIC_VGPR32d_VGPR32d:
  case XED_IFORM_BLSIC_VGPRyy_MEMy:
  case XED_IFORM_BLSIC_VGPRyy_VGPRyy:
  case XED_IFORM_BLSMSK_VGPR32d_MEMd:
  case XED_IFORM_BLSMSK_VGPR32d_VGPR32d:
  case XED_IFORM_BLSMSK_VGPR64q_MEMq:
  case XED_IFORM_BLSMSK_VGPR64q_VGPR64q:
  case XED_IFORM_BLSR_VGPR32d_MEMd:
  case XED_IFORM_BLSR_VGPR32d_VGPR32d:
  case XED_IFORM_BLSR_VGPR64q_MEMq:
  case XED_IFORM_BLSR_VGPR64q_VGPR64q:
  case XED_IFORM_BNDCL_BND_AGEN:
  case XED_IFORM_BNDCL_BND_GPR32:
  case XED_IFORM_BNDCL_BND_GPR64:
  case XED_IFORM_BNDCN_BND_AGEN:
  case XED_IFORM_BNDCN_BND_GPR32:
  case XED_IFORM_BNDCN_BND_GPR64:
  case XED_IFORM_BNDCU_BND_AGEN:
  case XED_IFORM_BNDCU_BND_GPR32:
  case XED_IFORM_BNDCU_BND_GPR64:
  case XED_IFORM_BNDLDX_BND_MEMbnd32:
  case XED_IFORM_BNDLDX_BND_MEMbnd64:
  case XED_IFORM_BNDMK_BND_AGEN:
  case XED_IFORM_BNDMOV_BND_BND:
  case XED_IFORM_BNDMOV_BND_MEMdq:
  case XED_IFORM_BNDMOV_BND_MEMq:
  case XED_IFORM_BNDMOV_MEMdq_BND:
  case XED_IFORM_BNDMOV_MEMq_BND:
  case XED_IFORM_BNDSTX_MEMbnd32_BND:
  case XED_IFORM_BNDSTX_MEMbnd64_BND:
  case XED_IFORM_BOUND_GPRv_MEMa16:
  case XED_IFORM_BOUND_GPRv_MEMa32:
  case XED_IFORM_BSF_GPRv_GPRv:
  case XED_IFORM_BSF_GPRv_MEMv:
  case XED_IFORM_BSR_GPRv_GPRv:
  case XED_IFORM_BSR_GPRv_MEMv:
  case XED_IFORM_BSWAP_GPRv:
  case XED_IFORM_BT_GPRv_GPRv:
  case XED_IFORM_BT_GPRv_IMMb:
  case XED_IFORM_BT_MEMv_GPRv:
  case XED_IFORM_BT_MEMv_IMMb:
  case XED_IFORM_BTC_GPRv_GPRv:
  case XED_IFORM_BTC_GPRv_IMMb:
  case XED_IFORM_BTC_MEMv_GPRv:
  case XED_IFORM_BTC_MEMv_IMMb:
  case XED_IFORM_BTC_LOCK_MEMv_GPRv:
  case XED_IFORM_BTC_LOCK_MEMv_IMMb:
  case XED_IFORM_BTR_GPRv_GPRv:
  case XED_IFORM_BTR_GPRv_IMMb:
  case XED_IFORM_BTR_MEMv_GPRv:
  case XED_IFORM_BTR_MEMv_IMMb:
  case XED_IFORM_BTR_LOCK_MEMv_GPRv:
  case XED_IFORM_BTR_LOCK_MEMv_IMMb:
  case XED_IFORM_BTS_GPRv_GPRv:
  case XED_IFORM_BTS_GPRv_IMMb:
  case XED_IFORM_BTS_MEMv_GPRv:
  case XED_IFORM_BTS_MEMv_IMMb:
  case XED_IFORM_BTS_LOCK_MEMv_GPRv:
  case XED_IFORM_BTS_LOCK_MEMv_IMMb:
  case XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d:
  case XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q:
  case XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_CALL_FAR_MEMp2:
  case XED_IFORM_CALL_FAR_PTRp_IMMw:
  case XED_IFORM_CALL_NEAR_GPRv:
  case XED_IFORM_CALL_NEAR_MEMv:
  case XED_IFORM_CALL_NEAR_RELBRd:
  case XED_IFORM_CALL_NEAR_RELBRz:
  case XED_IFORM_CBW:
  case XED_IFORM_CDQ:
  case XED_IFORM_CDQE:
  case XED_IFORM_CLAC:
  case XED_IFORM_CLC:
  case XED_IFORM_CLD:
  case XED_IFORM_CLDEMOTE_MEMu8:
  case XED_IFORM_CLFLUSH_MEMmprefetch:
  case XED_IFORM_CLFLUSHOPT_MEMmprefetch:
  case XED_IFORM_CLGI:
  case XED_IFORM_CLI:
  case XED_IFORM_CLRSSBSY_MEMu64:
  case XED_IFORM_CLTS:
  case XED_IFORM_CLUI:
  case XED_IFORM_CLWB_MEMmprefetch:
  case XED_IFORM_CLZERO:
  case XED_IFORM_CMC:
  case XED_IFORM_CMOVB_GPRv_GPRv:
  case XED_IFORM_CMOVB_GPRv_MEMv:
  case XED_IFORM_CMOVBE_GPRv_GPRv:
  case XED_IFORM_CMOVBE_GPRv_MEMv:
  case XED_IFORM_CMOVL_GPRv_GPRv:
  case XED_IFORM_CMOVL_GPRv_MEMv:
  case XED_IFORM_CMOVLE_GPRv_GPRv:
  case XED_IFORM_CMOVLE_GPRv_MEMv:
  case XED_IFORM_CMOVNB_GPRv_GPRv:
  case XED_IFORM_CMOVNB_GPRv_MEMv:
  case XED_IFORM_CMOVNBE_GPRv_GPRv:
  case XED_IFORM_CMOVNBE_GPRv_MEMv:
  case XED_IFORM_CMOVNL_GPRv_GPRv:
  case XED_IFORM_CMOVNL_GPRv_MEMv:
  case XED_IFORM_CMOVNLE_GPRv_GPRv:
  case XED_IFORM_CMOVNLE_GPRv_MEMv:
  case XED_IFORM_CMOVNO_GPRv_GPRv:
  case XED_IFORM_CMOVNO_GPRv_MEMv:
  case XED_IFORM_CMOVNP_GPRv_GPRv:
  case XED_IFORM_CMOVNP_GPRv_MEMv:
  case XED_IFORM_CMOVNS_GPRv_GPRv:
  case XED_IFORM_CMOVNS_GPRv_MEMv:
  case XED_IFORM_CMOVNZ_GPRv_GPRv:
  case XED_IFORM_CMOVNZ_GPRv_MEMv:
  case XED_IFORM_CMOVO_GPRv_GPRv:
  case XED_IFORM_CMOVO_GPRv_MEMv:
  case XED_IFORM_CMOVP_GPRv_GPRv:
  case XED_IFORM_CMOVP_GPRv_MEMv:
  case XED_IFORM_CMOVS_GPRv_GPRv:
  case XED_IFORM_CMOVS_GPRv_MEMv:
  case XED_IFORM_CMOVZ_GPRv_GPRv:
  case XED_IFORM_CMOVZ_GPRv_MEMv:
  case XED_IFORM_CMP_AL_IMMb:
  case XED_IFORM_CMP_GPR8_GPR8_38:
  case XED_IFORM_CMP_GPR8_GPR8_3A:
  case XED_IFORM_CMP_GPR8_IMMb_80r7:
  case XED_IFORM_CMP_GPR8_IMMb_82r7:
  case XED_IFORM_CMP_GPR8_MEMb:
  case XED_IFORM_CMP_GPRv_GPRv_39:
  case XED_IFORM_CMP_GPRv_GPRv_3B:
  case XED_IFORM_CMP_GPRv_IMMb:
  case XED_IFORM_CMP_GPRv_IMMz:
  case XED_IFORM_CMP_GPRv_MEMv:
  case XED_IFORM_CMP_MEMb_GPR8:
  case XED_IFORM_CMP_MEMb_IMMb_80r7:
  case XED_IFORM_CMP_MEMb_IMMb_82r7:
  case XED_IFORM_CMP_MEMv_GPRv:
  case XED_IFORM_CMP_MEMv_IMMb:
  case XED_IFORM_CMP_MEMv_IMMz:
  case XED_IFORM_CMP_OrAX_IMMz:
  case XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb:
  case XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb:
  case XED_IFORM_CMPPS_XMMps_MEMps_IMMb:
  case XED_IFORM_CMPPS_XMMps_XMMps_IMMb:
  case XED_IFORM_CMPSB:
  case XED_IFORM_CMPSD:
  case XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb:
  case XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb:
  case XED_IFORM_CMPSQ:
  case XED_IFORM_CMPSS_XMMss_MEMss_IMMb:
  case XED_IFORM_CMPSS_XMMss_XMMss_IMMb:
  case XED_IFORM_CMPSW:
  case XED_IFORM_CMPXCHG_GPR8_GPR8:
  case XED_IFORM_CMPXCHG_GPRv_GPRv:
  case XED_IFORM_CMPXCHG_MEMb_GPR8:
  case XED_IFORM_CMPXCHG_MEMv_GPRv:
  case XED_IFORM_CMPXCHG16B_MEMdq:
  case XED_IFORM_CMPXCHG16B_LOCK_MEMdq:
  case XED_IFORM_CMPXCHG8B_MEMq:
  case XED_IFORM_CMPXCHG8B_LOCK_MEMq:
  case XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8:
  case XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv:
  case XED_IFORM_COMISD_XMMsd_MEMsd:
  case XED_IFORM_COMISD_XMMsd_XMMsd:
  case XED_IFORM_COMISS_XMMss_MEMss:
  case XED_IFORM_COMISS_XMMss_XMMss:
  case XED_IFORM_CPUID:
  case XED_IFORM_CQO:
  case XED_IFORM_CRC32_GPRyy_GPR8b:
  case XED_IFORM_CRC32_GPRyy_GPRv:
  case XED_IFORM_CRC32_GPRyy_MEMb:
  case XED_IFORM_CRC32_GPRyy_MEMv:
  case XED_IFORM_CVTDQ2PD_XMMpd_MEMq:
  case XED_IFORM_CVTDQ2PD_XMMpd_XMMq:
  case XED_IFORM_CVTDQ2PS_XMMps_MEMdq:
  case XED_IFORM_CVTDQ2PS_XMMps_XMMdq:
  case XED_IFORM_CVTPD2DQ_XMMdq_MEMpd:
  case XED_IFORM_CVTPD2DQ_XMMdq_XMMpd:
  case XED_IFORM_CVTPD2PI_MMXq_MEMpd:
  case XED_IFORM_CVTPD2PI_MMXq_XMMpd:
  case XED_IFORM_CVTPD2PS_XMMps_MEMpd:
  case XED_IFORM_CVTPD2PS_XMMps_XMMpd:
  case XED_IFORM_CVTPI2PD_XMMpd_MEMq:
  case XED_IFORM_CVTPI2PD_XMMpd_MMXq:
  case XED_IFORM_CVTPI2PS_XMMq_MEMq:
  case XED_IFORM_CVTPI2PS_XMMq_MMXq:
  case XED_IFORM_CVTPS2DQ_XMMdq_MEMps:
  case XED_IFORM_CVTPS2DQ_XMMdq_XMMps:
  case XED_IFORM_CVTPS2PD_XMMpd_MEMq:
  case XED_IFORM_CVTPS2PD_XMMpd_XMMq:
  case XED_IFORM_CVTPS2PI_MMXq_MEMq:
  case XED_IFORM_CVTPS2PI_MMXq_XMMq:
  case XED_IFORM_CVTSD2SI_GPR32d_MEMsd:
  case XED_IFORM_CVTSD2SI_GPR32d_XMMsd:
  case XED_IFORM_CVTSD2SI_GPR64q_MEMsd:
  case XED_IFORM_CVTSD2SI_GPR64q_XMMsd:
  case XED_IFORM_CVTSD2SS_XMMss_MEMsd:
  case XED_IFORM_CVTSD2SS_XMMss_XMMsd:
  case XED_IFORM_CVTSI2SD_XMMsd_GPR32d:
  case XED_IFORM_CVTSI2SD_XMMsd_GPR64q:
  case XED_IFORM_CVTSI2SD_XMMsd_MEMd:
  case XED_IFORM_CVTSI2SD_XMMsd_MEMq:
  case XED_IFORM_CVTSI2SS_XMMss_GPR32d:
  case XED_IFORM_CVTSI2SS_XMMss_GPR64q:
  case XED_IFORM_CVTSI2SS_XMMss_MEMd:
  case XED_IFORM_CVTSI2SS_XMMss_MEMq:
  case XED_IFORM_CVTSS2SD_XMMsd_MEMss:
  case XED_IFORM_CVTSS2SD_XMMsd_XMMss:
  case XED_IFORM_CVTSS2SI_GPR32d_MEMss:
  case XED_IFORM_CVTSS2SI_GPR32d_XMMss:
  case XED_IFORM_CVTSS2SI_GPR64q_MEMss:
  case XED_IFORM_CVTSS2SI_GPR64q_XMMss:
  case XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd:
  case XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd:
  case XED_IFORM_CVTTPD2PI_MMXq_MEMpd:
  case XED_IFORM_CVTTPD2PI_MMXq_XMMpd:
  case XED_IFORM_CVTTPS2DQ_XMMdq_MEMps:
  case XED_IFORM_CVTTPS2DQ_XMMdq_XMMps:
  case XED_IFORM_CVTTPS2PI_MMXq_MEMq:
  case XED_IFORM_CVTTPS2PI_MMXq_XMMq:
  case XED_IFORM_CVTTSD2SI_GPR32d_MEMsd:
  case XED_IFORM_CVTTSD2SI_GPR32d_XMMsd:
  case XED_IFORM_CVTTSD2SI_GPR64q_MEMsd:
  case XED_IFORM_CVTTSD2SI_GPR64q_XMMsd:
  case XED_IFORM_CVTTSS2SI_GPR32d_MEMss:
  case XED_IFORM_CVTTSS2SI_GPR32d_XMMss:
  case XED_IFORM_CVTTSS2SI_GPR64q_MEMss:
  case XED_IFORM_CVTTSS2SI_GPR64q_XMMss:
  case XED_IFORM_CWD:
  case XED_IFORM_CWDE:
  case XED_IFORM_DAA:
  case XED_IFORM_DAS:
  case XED_IFORM_DEC_GPR8:
  case XED_IFORM_DEC_GPRv_48:
  case XED_IFORM_DEC_GPRv_FFr1:
  case XED_IFORM_DEC_MEMb:
  case XED_IFORM_DEC_MEMv:
  case XED_IFORM_DEC_LOCK_MEMb:
  case XED_IFORM_DEC_LOCK_MEMv:
  case XED_IFORM_DIV_GPR8:
  case XED_IFORM_DIV_GPRv:
  case XED_IFORM_DIV_MEMb:
  case XED_IFORM_DIV_MEMv:
  case XED_IFORM_DIVPD_XMMpd_MEMpd:
  case XED_IFORM_DIVPD_XMMpd_XMMpd:
  case XED_IFORM_DIVPS_XMMps_MEMps:
  case XED_IFORM_DIVPS_XMMps_XMMps:
  case XED_IFORM_DIVSD_XMMsd_MEMsd:
  case XED_IFORM_DIVSD_XMMsd_XMMsd:
  case XED_IFORM_DIVSS_XMMss_MEMss:
  case XED_IFORM_DIVSS_XMMss_XMMss:
  case XED_IFORM_DPPD_XMMdq_MEMdq_IMMb:
  case XED_IFORM_DPPD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_DPPS_XMMdq_MEMdq_IMMb:
  case XED_IFORM_DPPS_XMMdq_XMMdq_IMMb:
  case XED_IFORM_EMMS:
  case XED_IFORM_ENCLS:
  case XED_IFORM_ENCLU:
  case XED_IFORM_ENCLV:
  case XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8:
  case XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8:
  case XED_IFORM_ENDBR32:
  case XED_IFORM_ENDBR64:
  case XED_IFORM_ENQCMD_GPRa_MEMu32:
  case XED_IFORM_ENQCMDS_GPRa_MEMu32:
  case XED_IFORM_ENTER_IMMw_IMMb:
  case XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb:
  case XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb:
  case XED_IFORM_EXTRQ_XMMq_IMMb_IMMb:
  case XED_IFORM_EXTRQ_XMMq_XMMdq:
  case XED_IFORM_F2XM1:
  case XED_IFORM_FABS:
  case XED_IFORM_FADD_ST0_MEMm64real:
  case XED_IFORM_FADD_ST0_MEMmem32real:
  case XED_IFORM_FADD_ST0_X87:
  case XED_IFORM_FADD_X87_ST0:
  case XED_IFORM_FADDP_X87_ST0:
  case XED_IFORM_FBLD_ST0_MEMmem80dec:
  case XED_IFORM_FBSTP_MEMmem80dec_ST0:
  case XED_IFORM_FCHS:
  case XED_IFORM_FCMOVB_ST0_X87:
  case XED_IFORM_FCMOVBE_ST0_X87:
  case XED_IFORM_FCMOVE_ST0_X87:
  case XED_IFORM_FCMOVNB_ST0_X87:
  case XED_IFORM_FCMOVNBE_ST0_X87:
  case XED_IFORM_FCMOVNE_ST0_X87:
  case XED_IFORM_FCMOVNU_ST0_X87:
  case XED_IFORM_FCMOVU_ST0_X87:
  case XED_IFORM_FCOM_ST0_MEMm64real:
  case XED_IFORM_FCOM_ST0_MEMmem32real:
  case XED_IFORM_FCOM_ST0_X87:
  case XED_IFORM_FCOM_ST0_X87_DCD0:
  case XED_IFORM_FCOMI_ST0_X87:
  case XED_IFORM_FCOMIP_ST0_X87:
  case XED_IFORM_FCOMP_ST0_MEMm64real:
  case XED_IFORM_FCOMP_ST0_MEMmem32real:
  case XED_IFORM_FCOMP_ST0_X87:
  case XED_IFORM_FCOMP_ST0_X87_DCD1:
  case XED_IFORM_FCOMP_ST0_X87_DED0:
  case XED_IFORM_FCOMPP:
  case XED_IFORM_FCOS:
  case XED_IFORM_FDECSTP:
  case XED_IFORM_FDISI8087_NOP:
  case XED_IFORM_FDIV_ST0_MEMm64real:
  case XED_IFORM_FDIV_ST0_MEMmem32real:
  case XED_IFORM_FDIV_ST0_X87:
  case XED_IFORM_FDIV_X87_ST0:
  case XED_IFORM_FDIVP_X87_ST0:
  case XED_IFORM_FDIVR_ST0_MEMm64real:
  case XED_IFORM_FDIVR_ST0_MEMmem32real:
  case XED_IFORM_FDIVR_ST0_X87:
  case XED_IFORM_FDIVR_X87_ST0:
  case XED_IFORM_FDIVRP_X87_ST0:
  case XED_IFORM_FEMMS:
  case XED_IFORM_FENI8087_NOP:
  case XED_IFORM_FFREE_X87:
  case XED_IFORM_FFREEP_X87:
  case XED_IFORM_FIADD_ST0_MEMmem16int:
  case XED_IFORM_FIADD_ST0_MEMmem32int:
  case XED_IFORM_FICOM_ST0_MEMmem16int:
  case XED_IFORM_FICOM_ST0_MEMmem32int:
  case XED_IFORM_FICOMP_ST0_MEMmem16int:
  case XED_IFORM_FICOMP_ST0_MEMmem32int:
  case XED_IFORM_FIDIV_ST0_MEMmem16int:
  case XED_IFORM_FIDIV_ST0_MEMmem32int:
  case XED_IFORM_FIDIVR_ST0_MEMmem16int:
  case XED_IFORM_FIDIVR_ST0_MEMmem32int:
  case XED_IFORM_FILD_ST0_MEMm64int:
  case XED_IFORM_FILD_ST0_MEMmem16int:
  case XED_IFORM_FILD_ST0_MEMmem32int:
  case XED_IFORM_FIMUL_ST0_MEMmem16int:
  case XED_IFORM_FIMUL_ST0_MEMmem32int:
  case XED_IFORM_FINCSTP:
  case XED_IFORM_FIST_MEMmem16int_ST0:
  case XED_IFORM_FIST_MEMmem32int_ST0:
  case XED_IFORM_FISTP_MEMm64int_ST0:
  case XED_IFORM_FISTP_MEMmem16int_ST0:
  case XED_IFORM_FISTP_MEMmem32int_ST0:
  case XED_IFORM_FISTTP_MEMm64int_ST0:
  case XED_IFORM_FISTTP_MEMmem16int_ST0:
  case XED_IFORM_FISTTP_MEMmem32int_ST0:
  case XED_IFORM_FISUB_ST0_MEMmem16int:
  case XED_IFORM_FISUB_ST0_MEMmem32int:
  case XED_IFORM_FISUBR_ST0_MEMmem16int:
  case XED_IFORM_FISUBR_ST0_MEMmem32int:
  case XED_IFORM_FLD_ST0_MEMm64real:
  case XED_IFORM_FLD_ST0_MEMmem32real:
  case XED_IFORM_FLD_ST0_MEMmem80real:
  case XED_IFORM_FLD_ST0_X87:
  case XED_IFORM_FLD1:
  case XED_IFORM_FLDCW_MEMmem16:
  case XED_IFORM_FLDENV_MEMmem14:
  case XED_IFORM_FLDENV_MEMmem28:
  case XED_IFORM_FLDL2E:
  case XED_IFORM_FLDL2T:
  case XED_IFORM_FLDLG2:
  case XED_IFORM_FLDLN2:
  case XED_IFORM_FLDPI:
  case XED_IFORM_FLDZ:
  case XED_IFORM_FMUL_ST0_MEMm64real:
  case XED_IFORM_FMUL_ST0_MEMmem32real:
  case XED_IFORM_FMUL_ST0_X87:
  case XED_IFORM_FMUL_X87_ST0:
  case XED_IFORM_FMULP_X87_ST0:
  case XED_IFORM_FNCLEX:
  case XED_IFORM_FNINIT:
  case XED_IFORM_FNOP:
  case XED_IFORM_FNSAVE_MEMmem108:
  case XED_IFORM_FNSAVE_MEMmem94:
  case XED_IFORM_FNSTCW_MEMmem16:
  case XED_IFORM_FNSTENV_MEMmem14:
  case XED_IFORM_FNSTENV_MEMmem28:
  case XED_IFORM_FNSTSW_AX:
  case XED_IFORM_FNSTSW_MEMmem16:
  case XED_IFORM_FPATAN:
  case XED_IFORM_FPREM:
  case XED_IFORM_FPREM1:
  case XED_IFORM_FPTAN:
  case XED_IFORM_FRNDINT:
  case XED_IFORM_FRSTOR_MEMmem108:
  case XED_IFORM_FRSTOR_MEMmem94:
  case XED_IFORM_FSCALE:
  case XED_IFORM_FSETPM287_NOP:
  case XED_IFORM_FSIN:
  case XED_IFORM_FSINCOS:
  case XED_IFORM_FSQRT:
  case XED_IFORM_FST_MEMm64real_ST0:
  case XED_IFORM_FST_MEMmem32real_ST0:
  case XED_IFORM_FST_X87_ST0:
  case XED_IFORM_FSTP_MEMm64real_ST0:
  case XED_IFORM_FSTP_MEMmem32real_ST0:
  case XED_IFORM_FSTP_MEMmem80real_ST0:
  case XED_IFORM_FSTP_X87_ST0:
  case XED_IFORM_FSTP_X87_ST0_DFD0:
  case XED_IFORM_FSTP_X87_ST0_DFD1:
  case XED_IFORM_FSTPNCE_X87_ST0:
  case XED_IFORM_FSUB_ST0_MEMm64real:
  case XED_IFORM_FSUB_ST0_MEMmem32real:
  case XED_IFORM_FSUB_ST0_X87:
  case XED_IFORM_FSUB_X87_ST0:
  case XED_IFORM_FSUBP_X87_ST0:
  case XED_IFORM_FSUBR_ST0_MEMm64real:
  case XED_IFORM_FSUBR_ST0_MEMmem32real:
  case XED_IFORM_FSUBR_ST0_X87:
  case XED_IFORM_FSUBR_X87_ST0:
  case XED_IFORM_FSUBRP_X87_ST0:
  case XED_IFORM_FTST:
  case XED_IFORM_FUCOM_ST0_X87:
  case XED_IFORM_FUCOMI_ST0_X87:
  case XED_IFORM_FUCOMIP_ST0_X87:
  case XED_IFORM_FUCOMP_ST0_X87:
  case XED_IFORM_FUCOMPP:
  case XED_IFORM_FWAIT:
  case XED_IFORM_FXAM:
  case XED_IFORM_FXCH_ST0_X87:
  case XED_IFORM_FXCH_ST0_X87_DDC1:
  case XED_IFORM_FXCH_ST0_X87_DFC1:
  case XED_IFORM_FXRSTOR_MEMmfpxenv:
  case XED_IFORM_FXRSTOR64_MEMmfpxenv:
  case XED_IFORM_FXSAVE_MEMmfpxenv:
  case XED_IFORM_FXSAVE64_MEMmfpxenv:
  case XED_IFORM_FXTRACT:
  case XED_IFORM_FYL2X:
  case XED_IFORM_FYL2XP1:
  case XED_IFORM_GETSEC:
  case XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8:
  case XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8:
  case XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8:
  case XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8:
  case XED_IFORM_GF2P8MULB_XMMu8_MEMu8:
  case XED_IFORM_GF2P8MULB_XMMu8_XMMu8:
  case XED_IFORM_HADDPD_XMMpd_MEMpd:
  case XED_IFORM_HADDPD_XMMpd_XMMpd:
  case XED_IFORM_HADDPS_XMMps_MEMps:
  case XED_IFORM_HADDPS_XMMps_XMMps:
  case XED_IFORM_HLT:
  case XED_IFORM_HRESET_IMM8:
  case XED_IFORM_HSUBPD_XMMpd_MEMpd:
  case XED_IFORM_HSUBPD_XMMpd_XMMpd:
  case XED_IFORM_HSUBPS_XMMps_MEMps:
  case XED_IFORM_HSUBPS_XMMps_XMMps:
  case XED_IFORM_IDIV_GPR8:
  case XED_IFORM_IDIV_GPRv:
  case XED_IFORM_IDIV_MEMb:
  case XED_IFORM_IDIV_MEMv:
  case XED_IFORM_IMUL_GPR8:
  case XED_IFORM_IMUL_GPRv:
  case XED_IFORM_IMUL_GPRv_GPRv:
  case XED_IFORM_IMUL_GPRv_GPRv_IMMb:
  case XED_IFORM_IMUL_GPRv_GPRv_IMMz:
  case XED_IFORM_IMUL_GPRv_MEMv:
  case XED_IFORM_IMUL_GPRv_MEMv_IMMb:
  case XED_IFORM_IMUL_GPRv_MEMv_IMMz:
  case XED_IFORM_IMUL_MEMb:
  case XED_IFORM_IMUL_MEMv:
  case XED_IFORM_IN_AL_DX:
  case XED_IFORM_IN_AL_IMMb:
  case XED_IFORM_IN_OeAX_DX:
  case XED_IFORM_IN_OeAX_IMMb:
  case XED_IFORM_INC_GPR8:
  case XED_IFORM_INC_GPRv_40:
  case XED_IFORM_INC_GPRv_FFr0:
  case XED_IFORM_INC_MEMb:
  case XED_IFORM_INC_MEMv:
  case XED_IFORM_INCSSPD_GPR32u8:
  case XED_IFORM_INCSSPQ_GPR64u8:
  case XED_IFORM_INC_LOCK_MEMb:
  case XED_IFORM_INC_LOCK_MEMv:
  case XED_IFORM_INSB:
  case XED_IFORM_INSD:
  case XED_IFORM_INSERTPS_XMMps_MEMd_IMMb:
  case XED_IFORM_INSERTPS_XMMps_XMMps_IMMb:
  case XED_IFORM_INSERTQ_XMMq_XMMdq:
  case XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb:
  case XED_IFORM_INSW:
  case XED_IFORM_INT_IMMb:
  case XED_IFORM_INT1:
  case XED_IFORM_INT3:
  case XED_IFORM_INTO:
  case XED_IFORM_INVD:
  case XED_IFORM_INVEPT_GPR32_MEMdq:
  case XED_IFORM_INVEPT_GPR64_MEMdq:
  case XED_IFORM_INVLPG_MEMb:
  case XED_IFORM_INVLPGA_ArAX_ECX:
  case XED_IFORM_INVLPGB_EAX_EDX_ECX:
  case XED_IFORM_INVLPGB_RAX_EDX_ECX:
  case XED_IFORM_INVPCID_GPR32_MEMdq:
  case XED_IFORM_INVPCID_GPR64_MEMdq:
  case XED_IFORM_INVVPID_GPR32_MEMdq:
  case XED_IFORM_INVVPID_GPR64_MEMdq:
  case XED_IFORM_IRET:
  case XED_IFORM_IRETD:
  case XED_IFORM_IRETQ:
  case XED_IFORM_JB_RELBRb:
  case XED_IFORM_JB_RELBRd:
  case XED_IFORM_JB_RELBRz:
  case XED_IFORM_JBE_RELBRb:
  case XED_IFORM_JBE_RELBRd:
  case XED_IFORM_JBE_RELBRz:
  case XED_IFORM_JCXZ_RELBRb:
  case XED_IFORM_JECXZ_RELBRb:
  case XED_IFORM_JL_RELBRb:
  case XED_IFORM_JL_RELBRd:
  case XED_IFORM_JL_RELBRz:
  case XED_IFORM_JLE_RELBRb:
  case XED_IFORM_JLE_RELBRd:
  case XED_IFORM_JLE_RELBRz:
  case XED_IFORM_JMP_GPRv:
  case XED_IFORM_JMP_MEMv:
  case XED_IFORM_JMP_RELBRb:
  case XED_IFORM_JMP_RELBRd:
  case XED_IFORM_JMP_RELBRz:
  case XED_IFORM_JMP_FAR_MEMp2:
  case XED_IFORM_JMP_FAR_PTRp_IMMw:
  case XED_IFORM_JNB_RELBRb:
  case XED_IFORM_JNB_RELBRd:
  case XED_IFORM_JNB_RELBRz:
  case XED_IFORM_JNBE_RELBRb:
  case XED_IFORM_JNBE_RELBRd:
  case XED_IFORM_JNBE_RELBRz:
  case XED_IFORM_JNL_RELBRb:
  case XED_IFORM_JNL_RELBRd:
  case XED_IFORM_JNL_RELBRz:
  case XED_IFORM_JNLE_RELBRb:
  case XED_IFORM_JNLE_RELBRd:
  case XED_IFORM_JNLE_RELBRz:
  case XED_IFORM_JNO_RELBRb:
  case XED_IFORM_JNO_RELBRd:
  case XED_IFORM_JNO_RELBRz:
  case XED_IFORM_JNP_RELBRb:
  case XED_IFORM_JNP_RELBRd:
  case XED_IFORM_JNP_RELBRz:
  case XED_IFORM_JNS_RELBRb:
  case XED_IFORM_JNS_RELBRd:
  case XED_IFORM_JNS_RELBRz:
  case XED_IFORM_JNZ_RELBRb:
  case XED_IFORM_JNZ_RELBRd:
  case XED_IFORM_JNZ_RELBRz:
  case XED_IFORM_JO_RELBRb:
  case XED_IFORM_JO_RELBRd:
  case XED_IFORM_JO_RELBRz:
  case XED_IFORM_JP_RELBRb:
  case XED_IFORM_JP_RELBRd:
  case XED_IFORM_JP_RELBRz:
  case XED_IFORM_JRCXZ_RELBRb:
  case XED_IFORM_JS_RELBRb:
  case XED_IFORM_JS_RELBRd:
  case XED_IFORM_JS_RELBRz:
  case XED_IFORM_JZ_RELBRb:
  case XED_IFORM_JZ_RELBRd:
  case XED_IFORM_JZ_RELBRz:
  case XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512:
  case XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512:
  case XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512:
  case XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512:
  case XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512:
  case XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512:
  case XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512:
  case XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512:
  case XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512:
  case XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512:
  case XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512:
  case XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512:
  case XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512:
  case XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512:
  case XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512:
  case XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512:
  case XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512:
  case XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512:
  case XED_IFORM_LAHF:
  case XED_IFORM_LAR_GPRv_GPRv:
  case XED_IFORM_LAR_GPRv_MEMw:
  case XED_IFORM_LDDQU_XMMpd_MEMdq:
  case XED_IFORM_LDMXCSR_MEMd:
  case XED_IFORM_LDS_GPRz_MEMp:
  case XED_IFORM_LDTILECFG_MEM:
  case XED_IFORM_LEA_GPRv_AGEN:
  case XED_IFORM_LEAVE:
  case XED_IFORM_LES_GPRz_MEMp:
  case XED_IFORM_LFENCE:
  case XED_IFORM_LFS_GPRv_MEMp2:
  case XED_IFORM_LGDT_MEMs:
  case XED_IFORM_LGDT_MEMs64:
  case XED_IFORM_LGS_GPRv_MEMp2:
  case XED_IFORM_LIDT_MEMs:
  case XED_IFORM_LIDT_MEMs64:
  case XED_IFORM_LLDT_GPR16:
  case XED_IFORM_LLDT_MEMw:
  case XED_IFORM_LLWPCB_VGPRyy:
  case XED_IFORM_LMSW_GPR16:
  case XED_IFORM_LMSW_MEMw:
  case XED_IFORM_LOADIWKEY_XMMu8_XMMu8:
  case XED_IFORM_LODSB:
  case XED_IFORM_LODSD:
  case XED_IFORM_LODSQ:
  case XED_IFORM_LODSW:
  case XED_IFORM_LOOP_RELBRb:
  case XED_IFORM_LOOPE_RELBRb:
  case XED_IFORM_LOOPNE_RELBRb:
  case XED_IFORM_LSL_GPRv_GPRz:
  case XED_IFORM_LSL_GPRv_MEMw:
  case XED_IFORM_LSS_GPRv_MEMp2:
  case XED_IFORM_LTR_GPR16:
  case XED_IFORM_LTR_MEMw:
  case XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd:
  case XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd:
  case XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd:
  case XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd:
  case XED_IFORM_LZCNT_GPRv_GPRv:
  case XED_IFORM_LZCNT_GPRv_MEMv:
  case XED_IFORM_MASKMOVDQU_XMMdq_XMMdq:
  case XED_IFORM_MASKMOVQ_MMXq_MMXq:
  case XED_IFORM_MAXPD_XMMpd_MEMpd:
  case XED_IFORM_MAXPD_XMMpd_XMMpd:
  case XED_IFORM_MAXPS_XMMps_MEMps:
  case XED_IFORM_MAXPS_XMMps_XMMps:
  case XED_IFORM_MAXSD_XMMsd_MEMsd:
  case XED_IFORM_MAXSD_XMMsd_XMMsd:
  case XED_IFORM_MAXSS_XMMss_MEMss:
  case XED_IFORM_MAXSS_XMMss_XMMss:
  case XED_IFORM_MCOMMIT:
  case XED_IFORM_MFENCE:
  case XED_IFORM_MINPD_XMMpd_MEMpd:
  case XED_IFORM_MINPD_XMMpd_XMMpd:
  case XED_IFORM_MINPS_XMMps_MEMps:
  case XED_IFORM_MINPS_XMMps_XMMps:
  case XED_IFORM_MINSD_XMMsd_MEMsd:
  case XED_IFORM_MINSD_XMMsd_XMMsd:
  case XED_IFORM_MINSS_XMMss_MEMss:
  case XED_IFORM_MINSS_XMMss_XMMss:
  case XED_IFORM_MONITOR:
  case XED_IFORM_MONITORX:
  case XED_IFORM_MOV_AL_MEMb:
  case XED_IFORM_MOV_GPR8_GPR8_88:
  case XED_IFORM_MOV_GPR8_GPR8_8A:
  case XED_IFORM_MOV_GPR8_IMMb_B0:
  case XED_IFORM_MOV_GPR8_IMMb_C6r0:
  case XED_IFORM_MOV_GPR8_MEMb:
  case XED_IFORM_MOV_GPRv_GPRv_89:
  case XED_IFORM_MOV_GPRv_GPRv_8B:
  case XED_IFORM_MOV_GPRv_IMMv:
  case XED_IFORM_MOV_GPRv_IMMz:
  case XED_IFORM_MOV_GPRv_MEMv:
  case XED_IFORM_MOV_GPRv_SEG:
  case XED_IFORM_MOV_MEMb_AL:
  case XED_IFORM_MOV_MEMb_GPR8:
  case XED_IFORM_MOV_MEMb_IMMb:
  case XED_IFORM_MOV_MEMv_GPRv:
  case XED_IFORM_MOV_MEMv_IMMz:
  case XED_IFORM_MOV_MEMv_OrAX:
  case XED_IFORM_MOV_MEMw_SEG:
  case XED_IFORM_MOV_OrAX_MEMv:
  case XED_IFORM_MOV_SEG_GPR16:
  case XED_IFORM_MOV_SEG_MEMw:
  case XED_IFORM_MOVAPD_MEMpd_XMMpd:
  case XED_IFORM_MOVAPD_XMMpd_MEMpd:
  case XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28:
  case XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29:
  case XED_IFORM_MOVAPS_MEMps_XMMps:
  case XED_IFORM_MOVAPS_XMMps_MEMps:
  case XED_IFORM_MOVAPS_XMMps_XMMps_0F28:
  case XED_IFORM_MOVAPS_XMMps_XMMps_0F29:
  case XED_IFORM_MOVBE_GPRv_MEMv:
  case XED_IFORM_MOVBE_MEMv_GPRv:
  case XED_IFORM_MOVD_GPR32_MMXd:
  case XED_IFORM_MOVD_GPR32_XMMd:
  case XED_IFORM_MOVD_MEMd_MMXd:
  case XED_IFORM_MOVD_MEMd_XMMd:
  case XED_IFORM_MOVD_MMXq_GPR32:
  case XED_IFORM_MOVD_MMXq_MEMd:
  case XED_IFORM_MOVD_XMMdq_GPR32:
  case XED_IFORM_MOVD_XMMdq_MEMd:
  case XED_IFORM_MOVDDUP_XMMdq_MEMq:
  case XED_IFORM_MOVDDUP_XMMdq_XMMq:
  case XED_IFORM_MOVDIR64B_GPRa_MEM:
  case XED_IFORM_MOVDIRI_MEMu32_GPR32u32:
  case XED_IFORM_MOVDIRI_MEMu64_GPR64u64:
  case XED_IFORM_MOVDQ2Q_MMXq_XMMq:
  case XED_IFORM_MOVDQA_MEMdq_XMMdq:
  case XED_IFORM_MOVDQA_XMMdq_MEMdq:
  case XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F:
  case XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F:
  case XED_IFORM_MOVDQU_MEMdq_XMMdq:
  case XED_IFORM_MOVDQU_XMMdq_MEMdq:
  case XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F:
  case XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F:
  case XED_IFORM_MOVHLPS_XMMq_XMMq:
  case XED_IFORM_MOVHPD_MEMq_XMMsd:
  case XED_IFORM_MOVHPD_XMMsd_MEMq:
  case XED_IFORM_MOVHPS_MEMq_XMMps:
  case XED_IFORM_MOVHPS_XMMq_MEMq:
  case XED_IFORM_MOVLHPS_XMMq_XMMq:
  case XED_IFORM_MOVLPD_MEMq_XMMsd:
  case XED_IFORM_MOVLPD_XMMsd_MEMq:
  case XED_IFORM_MOVLPS_MEMq_XMMq:
  case XED_IFORM_MOVLPS_XMMq_MEMq:
  case XED_IFORM_MOVMSKPD_GPR32_XMMpd:
  case XED_IFORM_MOVMSKPS_GPR32_XMMps:
  case XED_IFORM_MOVNTDQ_MEMdq_XMMdq:
  case XED_IFORM_MOVNTDQA_XMMdq_MEMdq:
  case XED_IFORM_MOVNTI_MEMd_GPR32:
  case XED_IFORM_MOVNTI_MEMq_GPR64:
  case XED_IFORM_MOVNTPD_MEMdq_XMMpd:
  case XED_IFORM_MOVNTPS_MEMdq_XMMps:
  case XED_IFORM_MOVNTQ_MEMq_MMXq:
  case XED_IFORM_MOVNTSD_MEMq_XMMq:
  case XED_IFORM_MOVNTSS_MEMd_XMMd:
  case XED_IFORM_MOVQ_GPR64_MMXq:
  case XED_IFORM_MOVQ_GPR64_XMMq:
  case XED_IFORM_MOVQ_MEMq_MMXq_0F7E:
  case XED_IFORM_MOVQ_MEMq_MMXq_0F7F:
  case XED_IFORM_MOVQ_MEMq_XMMq_0F7E:
  case XED_IFORM_MOVQ_MEMq_XMMq_0FD6:
  case XED_IFORM_MOVQ_MMXq_GPR64:
  case XED_IFORM_MOVQ_MMXq_MEMq_0F6E:
  case XED_IFORM_MOVQ_MMXq_MEMq_0F6F:
  case XED_IFORM_MOVQ_MMXq_MMXq_0F6F:
  case XED_IFORM_MOVQ_MMXq_MMXq_0F7F:
  case XED_IFORM_MOVQ_XMMdq_GPR64:
  case XED_IFORM_MOVQ_XMMdq_MEMq_0F6E:
  case XED_IFORM_MOVQ_XMMdq_MEMq_0F7E:
  case XED_IFORM_MOVQ_XMMdq_XMMq_0F7E:
  case XED_IFORM_MOVQ_XMMdq_XMMq_0FD6:
  case XED_IFORM_MOVQ2DQ_XMMdq_MMXq:
  case XED_IFORM_MOVSB:
  case XED_IFORM_MOVSD:
  case XED_IFORM_MOVSD_XMM_MEMsd_XMMsd:
  case XED_IFORM_MOVSD_XMM_XMMdq_MEMsd:
  case XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10:
  case XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11:
  case XED_IFORM_MOVSHDUP_XMMps_MEMps:
  case XED_IFORM_MOVSHDUP_XMMps_XMMps:
  case XED_IFORM_MOVSLDUP_XMMps_MEMps:
  case XED_IFORM_MOVSLDUP_XMMps_XMMps:
  case XED_IFORM_MOVSQ:
  case XED_IFORM_MOVSS_MEMss_XMMss:
  case XED_IFORM_MOVSS_XMMdq_MEMss:
  case XED_IFORM_MOVSS_XMMss_XMMss_0F10:
  case XED_IFORM_MOVSS_XMMss_XMMss_0F11:
  case XED_IFORM_MOVSW:
  case XED_IFORM_MOVSX_GPRv_GPR16:
  case XED_IFORM_MOVSX_GPRv_GPR8:
  case XED_IFORM_MOVSX_GPRv_MEMb:
  case XED_IFORM_MOVSX_GPRv_MEMw:
  case XED_IFORM_MOVSXD_GPRv_GPRz:
  case XED_IFORM_MOVSXD_GPRv_MEMz:
  case XED_IFORM_MOVUPD_MEMpd_XMMpd:
  case XED_IFORM_MOVUPD_XMMpd_MEMpd:
  case XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10:
  case XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11:
  case XED_IFORM_MOVUPS_MEMps_XMMps:
  case XED_IFORM_MOVUPS_XMMps_MEMps:
  case XED_IFORM_MOVUPS_XMMps_XMMps_0F10:
  case XED_IFORM_MOVUPS_XMMps_XMMps_0F11:
  case XED_IFORM_MOVZX_GPRv_GPR16:
  case XED_IFORM_MOVZX_GPRv_GPR8:
  case XED_IFORM_MOVZX_GPRv_MEMb:
  case XED_IFORM_MOVZX_GPRv_MEMw:
  case XED_IFORM_MOV_CR_CR_GPR32:
  case XED_IFORM_MOV_CR_CR_GPR64:
  case XED_IFORM_MOV_CR_GPR32_CR:
  case XED_IFORM_MOV_CR_GPR64_CR:
  case XED_IFORM_MOV_DR_DR_GPR32:
  case XED_IFORM_MOV_DR_DR_GPR64:
  case XED_IFORM_MOV_DR_GPR32_DR:
  case XED_IFORM_MOV_DR_GPR64_DR:
  case XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb:
  case XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_MUL_GPR8:
  case XED_IFORM_MUL_GPRv:
  case XED_IFORM_MUL_MEMb:
  case XED_IFORM_MUL_MEMv:
  case XED_IFORM_MULPD_XMMpd_MEMpd:
  case XED_IFORM_MULPD_XMMpd_XMMpd:
  case XED_IFORM_MULPS_XMMps_MEMps:
  case XED_IFORM_MULPS_XMMps_XMMps:
  case XED_IFORM_MULSD_XMMsd_MEMsd:
  case XED_IFORM_MULSD_XMMsd_XMMsd:
  case XED_IFORM_MULSS_XMMss_MEMss:
  case XED_IFORM_MULSS_XMMss_XMMss:
  case XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd:
  case XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq:
  case XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_MWAIT:
  case XED_IFORM_MWAITX:
  case XED_IFORM_NEG_GPR8:
  case XED_IFORM_NEG_GPRv:
  case XED_IFORM_NEG_MEMb:
  case XED_IFORM_NEG_MEMv:
  case XED_IFORM_NEG_LOCK_MEMb:
  case XED_IFORM_NEG_LOCK_MEMv:
  case XED_IFORM_NOP_90:
  case XED_IFORM_NOP_GPRv_0F18r0:
  case XED_IFORM_NOP_GPRv_0F18r1:
  case XED_IFORM_NOP_GPRv_0F18r2:
  case XED_IFORM_NOP_GPRv_0F18r3:
  case XED_IFORM_NOP_GPRv_0F18r4:
  case XED_IFORM_NOP_GPRv_0F18r5:
  case XED_IFORM_NOP_GPRv_0F18r6:
  case XED_IFORM_NOP_GPRv_0F18r7:
  case XED_IFORM_NOP_GPRv_GPRv_0F0D:
  case XED_IFORM_NOP_GPRv_GPRv_0F19:
  case XED_IFORM_NOP_GPRv_GPRv_0F1A:
  case XED_IFORM_NOP_GPRv_GPRv_0F1B:
  case XED_IFORM_NOP_GPRv_GPRv_0F1C:
  case XED_IFORM_NOP_GPRv_GPRv_0F1D:
  case XED_IFORM_NOP_GPRv_GPRv_0F1E:
  case XED_IFORM_NOP_GPRv_GPRv_0F1F:
  case XED_IFORM_NOP_GPRv_MEM_0F1B:
  case XED_IFORM_NOP_GPRv_MEMv_0F1A:
  case XED_IFORM_NOP_MEMv_0F18r4:
  case XED_IFORM_NOP_MEMv_0F18r5:
  case XED_IFORM_NOP_MEMv_0F18r6:
  case XED_IFORM_NOP_MEMv_0F18r7:
  case XED_IFORM_NOP_MEMv_GPRv_0F19:
  case XED_IFORM_NOP_MEMv_GPRv_0F1C:
  case XED_IFORM_NOP_MEMv_GPRv_0F1D:
  case XED_IFORM_NOP_MEMv_GPRv_0F1E:
  case XED_IFORM_NOP_MEMv_GPRv_0F1F:
  case XED_IFORM_NOT_GPR8:
  case XED_IFORM_NOT_GPRv:
  case XED_IFORM_NOT_MEMb:
  case XED_IFORM_NOT_MEMv:
  case XED_IFORM_NOT_LOCK_MEMb:
  case XED_IFORM_NOT_LOCK_MEMv:
  case XED_IFORM_OR_AL_IMMb:
  case XED_IFORM_OR_GPR8_GPR8_08:
  case XED_IFORM_OR_GPR8_GPR8_0A:
  case XED_IFORM_OR_GPR8_IMMb_80r1:
  case XED_IFORM_OR_GPR8_IMMb_82r1:
  case XED_IFORM_OR_GPR8_MEMb:
  case XED_IFORM_OR_GPRv_GPRv_09:
  case XED_IFORM_OR_GPRv_GPRv_0B:
  case XED_IFORM_OR_GPRv_IMMb:
  case XED_IFORM_OR_GPRv_IMMz:
  case XED_IFORM_OR_GPRv_MEMv:
  case XED_IFORM_OR_MEMb_GPR8:
  case XED_IFORM_OR_MEMb_IMMb_80r1:
  case XED_IFORM_OR_MEMb_IMMb_82r1:
  case XED_IFORM_OR_MEMv_GPRv:
  case XED_IFORM_OR_MEMv_IMMb:
  case XED_IFORM_OR_MEMv_IMMz:
  case XED_IFORM_OR_OrAX_IMMz:
  case XED_IFORM_ORPD_XMMxuq_MEMxuq:
  case XED_IFORM_ORPD_XMMxuq_XMMxuq:
  case XED_IFORM_ORPS_XMMxud_MEMxud:
  case XED_IFORM_ORPS_XMMxud_XMMxud:
  case XED_IFORM_OR_LOCK_MEMb_GPR8:
  case XED_IFORM_OR_LOCK_MEMb_IMMb_80r1:
  case XED_IFORM_OR_LOCK_MEMb_IMMb_82r1:
  case XED_IFORM_OR_LOCK_MEMv_GPRv:
  case XED_IFORM_OR_LOCK_MEMv_IMMb:
  case XED_IFORM_OR_LOCK_MEMv_IMMz:
  case XED_IFORM_OUT_DX_AL:
  case XED_IFORM_OUT_DX_OeAX:
  case XED_IFORM_OUT_IMMb_AL:
  case XED_IFORM_OUT_IMMb_OeAX:
  case XED_IFORM_OUTSB:
  case XED_IFORM_OUTSD:
  case XED_IFORM_OUTSW:
  case XED_IFORM_PABSB_MMXq_MEMq:
  case XED_IFORM_PABSB_MMXq_MMXq:
  case XED_IFORM_PABSB_XMMdq_MEMdq:
  case XED_IFORM_PABSB_XMMdq_XMMdq:
  case XED_IFORM_PABSD_MMXq_MEMq:
  case XED_IFORM_PABSD_MMXq_MMXq:
  case XED_IFORM_PABSD_XMMdq_MEMdq:
  case XED_IFORM_PABSD_XMMdq_XMMdq:
  case XED_IFORM_PABSW_MMXq_MEMq:
  case XED_IFORM_PABSW_MMXq_MMXq:
  case XED_IFORM_PABSW_XMMdq_MEMdq:
  case XED_IFORM_PABSW_XMMdq_XMMdq:
  case XED_IFORM_PACKSSDW_MMXq_MEMq:
  case XED_IFORM_PACKSSDW_MMXq_MMXq:
  case XED_IFORM_PACKSSDW_XMMdq_MEMdq:
  case XED_IFORM_PACKSSDW_XMMdq_XMMdq:
  case XED_IFORM_PACKSSWB_MMXq_MEMq:
  case XED_IFORM_PACKSSWB_MMXq_MMXq:
  case XED_IFORM_PACKSSWB_XMMdq_MEMdq:
  case XED_IFORM_PACKSSWB_XMMdq_XMMdq:
  case XED_IFORM_PACKUSDW_XMMdq_MEMdq:
  case XED_IFORM_PACKUSDW_XMMdq_XMMdq:
  case XED_IFORM_PACKUSWB_MMXq_MEMq:
  case XED_IFORM_PACKUSWB_MMXq_MMXq:
  case XED_IFORM_PACKUSWB_XMMdq_MEMdq:
  case XED_IFORM_PACKUSWB_XMMdq_XMMdq:
  case XED_IFORM_PADDB_MMXq_MEMq:
  case XED_IFORM_PADDB_MMXq_MMXq:
  case XED_IFORM_PADDB_XMMdq_MEMdq:
  case XED_IFORM_PADDB_XMMdq_XMMdq:
  case XED_IFORM_PADDD_MMXq_MEMq:
  case XED_IFORM_PADDD_MMXq_MMXq:
  case XED_IFORM_PADDD_XMMdq_MEMdq:
  case XED_IFORM_PADDD_XMMdq_XMMdq:
  case XED_IFORM_PADDQ_MMXq_MEMq:
  case XED_IFORM_PADDQ_MMXq_MMXq:
  case XED_IFORM_PADDQ_XMMdq_MEMdq:
  case XED_IFORM_PADDQ_XMMdq_XMMdq:
  case XED_IFORM_PADDSB_MMXq_MEMq:
  case XED_IFORM_PADDSB_MMXq_MMXq:
  case XED_IFORM_PADDSB_XMMdq_MEMdq:
  case XED_IFORM_PADDSB_XMMdq_XMMdq:
  case XED_IFORM_PADDSW_MMXq_MEMq:
  case XED_IFORM_PADDSW_MMXq_MMXq:
  case XED_IFORM_PADDSW_XMMdq_MEMdq:
  case XED_IFORM_PADDSW_XMMdq_XMMdq:
  case XED_IFORM_PADDUSB_MMXq_MEMq:
  case XED_IFORM_PADDUSB_MMXq_MMXq:
  case XED_IFORM_PADDUSB_XMMdq_MEMdq:
  case XED_IFORM_PADDUSB_XMMdq_XMMdq:
  case XED_IFORM_PADDUSW_MMXq_MEMq:
  case XED_IFORM_PADDUSW_MMXq_MMXq:
  case XED_IFORM_PADDUSW_XMMdq_MEMdq:
  case XED_IFORM_PADDUSW_XMMdq_XMMdq:
  case XED_IFORM_PADDW_MMXq_MEMq:
  case XED_IFORM_PADDW_MMXq_MMXq:
  case XED_IFORM_PADDW_XMMdq_MEMdq:
  case XED_IFORM_PADDW_XMMdq_XMMdq:
  case XED_IFORM_PALIGNR_MMXq_MEMq_IMMb:
  case XED_IFORM_PALIGNR_MMXq_MMXq_IMMb:
  case XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PAND_MMXq_MEMq:
  case XED_IFORM_PAND_MMXq_MMXq:
  case XED_IFORM_PAND_XMMdq_MEMdq:
  case XED_IFORM_PAND_XMMdq_XMMdq:
  case XED_IFORM_PANDN_MMXq_MEMq:
  case XED_IFORM_PANDN_MMXq_MMXq:
  case XED_IFORM_PANDN_XMMdq_MEMdq:
  case XED_IFORM_PANDN_XMMdq_XMMdq:
  case XED_IFORM_PAUSE:
  case XED_IFORM_PAVGB_MMXq_MEMq:
  case XED_IFORM_PAVGB_MMXq_MMXq:
  case XED_IFORM_PAVGB_XMMdq_MEMdq:
  case XED_IFORM_PAVGB_XMMdq_XMMdq:
  case XED_IFORM_PAVGUSB_MMXq_MEMq:
  case XED_IFORM_PAVGUSB_MMXq_MMXq:
  case XED_IFORM_PAVGW_MMXq_MEMq:
  case XED_IFORM_PAVGW_MMXq_MMXq:
  case XED_IFORM_PAVGW_XMMdq_MEMdq:
  case XED_IFORM_PAVGW_XMMdq_XMMdq:
  case XED_IFORM_PBLENDVB_XMMdq_MEMdq:
  case XED_IFORM_PBLENDVB_XMMdq_XMMdq:
  case XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCMPEQB_MMXq_MEMq:
  case XED_IFORM_PCMPEQB_MMXq_MMXq:
  case XED_IFORM_PCMPEQB_XMMdq_MEMdq:
  case XED_IFORM_PCMPEQB_XMMdq_XMMdq:
  case XED_IFORM_PCMPEQD_MMXq_MEMq:
  case XED_IFORM_PCMPEQD_MMXq_MMXq:
  case XED_IFORM_PCMPEQD_XMMdq_MEMdq:
  case XED_IFORM_PCMPEQD_XMMdq_XMMdq:
  case XED_IFORM_PCMPEQQ_XMMdq_MEMdq:
  case XED_IFORM_PCMPEQQ_XMMdq_XMMdq:
  case XED_IFORM_PCMPEQW_MMXq_MEMq:
  case XED_IFORM_PCMPEQW_MMXq_MMXq:
  case XED_IFORM_PCMPEQW_XMMdq_MEMdq:
  case XED_IFORM_PCMPEQW_XMMdq_XMMdq:
  case XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCMPGTB_MMXq_MEMq:
  case XED_IFORM_PCMPGTB_MMXq_MMXq:
  case XED_IFORM_PCMPGTB_XMMdq_MEMdq:
  case XED_IFORM_PCMPGTB_XMMdq_XMMdq:
  case XED_IFORM_PCMPGTD_MMXq_MEMq:
  case XED_IFORM_PCMPGTD_MMXq_MMXq:
  case XED_IFORM_PCMPGTD_XMMdq_MEMdq:
  case XED_IFORM_PCMPGTD_XMMdq_XMMdq:
  case XED_IFORM_PCMPGTQ_XMMdq_MEMdq:
  case XED_IFORM_PCMPGTQ_XMMdq_XMMdq:
  case XED_IFORM_PCMPGTW_MMXq_MEMq:
  case XED_IFORM_PCMPGTW_MMXq_MMXq:
  case XED_IFORM_PCMPGTW_XMMdq_MEMdq:
  case XED_IFORM_PCMPGTW_XMMdq_XMMdq:
  case XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PCONFIG:
  case XED_IFORM_PCONFIG64:
  case XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd:
  case XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq:
  case XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd:
  case XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq:
  case XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb:
  case XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb:
  case XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb:
  case XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb:
  case XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb:
  case XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb:
  case XED_IFORM_PEXTRW_GPR32_MMXq_IMMb:
  case XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb:
  case XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb:
  case XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb:
  case XED_IFORM_PF2ID_MMXq_MEMq:
  case XED_IFORM_PF2ID_MMXq_MMXq:
  case XED_IFORM_PF2IW_MMXq_MEMq:
  case XED_IFORM_PF2IW_MMXq_MMXq:
  case XED_IFORM_PFACC_MMXq_MEMq:
  case XED_IFORM_PFACC_MMXq_MMXq:
  case XED_IFORM_PFADD_MMXq_MEMq:
  case XED_IFORM_PFADD_MMXq_MMXq:
  case XED_IFORM_PFCMPEQ_MMXq_MEMq:
  case XED_IFORM_PFCMPEQ_MMXq_MMXq:
  case XED_IFORM_PFCMPGE_MMXq_MEMq:
  case XED_IFORM_PFCMPGE_MMXq_MMXq:
  case XED_IFORM_PFCMPGT_MMXq_MEMq:
  case XED_IFORM_PFCMPGT_MMXq_MMXq:
  case XED_IFORM_PFMAX_MMXq_MEMq:
  case XED_IFORM_PFMAX_MMXq_MMXq:
  case XED_IFORM_PFMIN_MMXq_MEMq:
  case XED_IFORM_PFMIN_MMXq_MMXq:
  case XED_IFORM_PFMUL_MMXq_MEMq:
  case XED_IFORM_PFMUL_MMXq_MMXq:
  case XED_IFORM_PFNACC_MMXq_MEMq:
  case XED_IFORM_PFNACC_MMXq_MMXq:
  case XED_IFORM_PFPNACC_MMXq_MEMq:
  case XED_IFORM_PFPNACC_MMXq_MMXq:
  case XED_IFORM_PFRCP_MMXq_MEMq:
  case XED_IFORM_PFRCP_MMXq_MMXq:
  case XED_IFORM_PFRCPIT1_MMXq_MEMq:
  case XED_IFORM_PFRCPIT1_MMXq_MMXq:
  case XED_IFORM_PFRCPIT2_MMXq_MEMq:
  case XED_IFORM_PFRCPIT2_MMXq_MMXq:
  case XED_IFORM_PFRSQIT1_MMXq_MEMq:
  case XED_IFORM_PFRSQIT1_MMXq_MMXq:
  case XED_IFORM_PFRSQRT_MMXq_MEMq:
  case XED_IFORM_PFRSQRT_MMXq_MMXq:
  case XED_IFORM_PFSUB_MMXq_MEMq:
  case XED_IFORM_PFSUB_MMXq_MMXq:
  case XED_IFORM_PFSUBR_MMXq_MEMq:
  case XED_IFORM_PFSUBR_MMXq_MMXq:
  case XED_IFORM_PHADDD_MMXq_MEMq:
  case XED_IFORM_PHADDD_MMXq_MMXq:
  case XED_IFORM_PHADDD_XMMdq_MEMdq:
  case XED_IFORM_PHADDD_XMMdq_XMMdq:
  case XED_IFORM_PHADDSW_MMXq_MEMq:
  case XED_IFORM_PHADDSW_MMXq_MMXq:
  case XED_IFORM_PHADDSW_XMMdq_MEMdq:
  case XED_IFORM_PHADDSW_XMMdq_XMMdq:
  case XED_IFORM_PHADDW_MMXq_MEMq:
  case XED_IFORM_PHADDW_MMXq_MMXq:
  case XED_IFORM_PHADDW_XMMdq_MEMdq:
  case XED_IFORM_PHADDW_XMMdq_XMMdq:
  case XED_IFORM_PHMINPOSUW_XMMdq_MEMdq:
  case XED_IFORM_PHMINPOSUW_XMMdq_XMMdq:
  case XED_IFORM_PHSUBD_MMXq_MEMq:
  case XED_IFORM_PHSUBD_MMXq_MMXq:
  case XED_IFORM_PHSUBD_XMMdq_MEMdq:
  case XED_IFORM_PHSUBD_XMMdq_XMMdq:
  case XED_IFORM_PHSUBSW_MMXq_MEMq:
  case XED_IFORM_PHSUBSW_MMXq_MMXq:
  case XED_IFORM_PHSUBSW_XMMdq_MEMdq:
  case XED_IFORM_PHSUBSW_XMMdq_XMMdq:
  case XED_IFORM_PHSUBW_MMXq_MEMq:
  case XED_IFORM_PHSUBW_MMXq_MMXq:
  case XED_IFORM_PHSUBW_XMMdq_MEMdq:
  case XED_IFORM_PHSUBW_XMMdq_XMMdq:
  case XED_IFORM_PI2FD_MMXq_MEMq:
  case XED_IFORM_PI2FD_MMXq_MMXq:
  case XED_IFORM_PI2FW_MMXq_MEMq:
  case XED_IFORM_PI2FW_MMXq_MMXq:
  case XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb:
  case XED_IFORM_PINSRB_XMMdq_MEMb_IMMb:
  case XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb:
  case XED_IFORM_PINSRD_XMMdq_MEMd_IMMb:
  case XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb:
  case XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb:
  case XED_IFORM_PINSRW_MMXq_GPR32_IMMb:
  case XED_IFORM_PINSRW_MMXq_MEMw_IMMb:
  case XED_IFORM_PINSRW_XMMdq_GPR32_IMMb:
  case XED_IFORM_PINSRW_XMMdq_MEMw_IMMb:
  case XED_IFORM_PMADDUBSW_MMXq_MEMq:
  case XED_IFORM_PMADDUBSW_MMXq_MMXq:
  case XED_IFORM_PMADDUBSW_XMMdq_MEMdq:
  case XED_IFORM_PMADDUBSW_XMMdq_XMMdq:
  case XED_IFORM_PMADDWD_MMXq_MEMq:
  case XED_IFORM_PMADDWD_MMXq_MMXq:
  case XED_IFORM_PMADDWD_XMMdq_MEMdq:
  case XED_IFORM_PMADDWD_XMMdq_XMMdq:
  case XED_IFORM_PMAXSB_XMMdq_MEMdq:
  case XED_IFORM_PMAXSB_XMMdq_XMMdq:
  case XED_IFORM_PMAXSD_XMMdq_MEMdq:
  case XED_IFORM_PMAXSD_XMMdq_XMMdq:
  case XED_IFORM_PMAXSW_MMXq_MEMq:
  case XED_IFORM_PMAXSW_MMXq_MMXq:
  case XED_IFORM_PMAXSW_XMMdq_MEMdq:
  case XED_IFORM_PMAXSW_XMMdq_XMMdq:
  case XED_IFORM_PMAXUB_MMXq_MEMq:
  case XED_IFORM_PMAXUB_MMXq_MMXq:
  case XED_IFORM_PMAXUB_XMMdq_MEMdq:
  case XED_IFORM_PMAXUB_XMMdq_XMMdq:
  case XED_IFORM_PMAXUD_XMMdq_MEMdq:
  case XED_IFORM_PMAXUD_XMMdq_XMMdq:
  case XED_IFORM_PMAXUW_XMMdq_MEMdq:
  case XED_IFORM_PMAXUW_XMMdq_XMMdq:
  case XED_IFORM_PMINSB_XMMdq_MEMdq:
  case XED_IFORM_PMINSB_XMMdq_XMMdq:
  case XED_IFORM_PMINSD_XMMdq_MEMdq:
  case XED_IFORM_PMINSD_XMMdq_XMMdq:
  case XED_IFORM_PMINSW_MMXq_MEMq:
  case XED_IFORM_PMINSW_MMXq_MMXq:
  case XED_IFORM_PMINSW_XMMdq_MEMdq:
  case XED_IFORM_PMINSW_XMMdq_XMMdq:
  case XED_IFORM_PMINUB_MMXq_MEMq:
  case XED_IFORM_PMINUB_MMXq_MMXq:
  case XED_IFORM_PMINUB_XMMdq_MEMdq:
  case XED_IFORM_PMINUB_XMMdq_XMMdq:
  case XED_IFORM_PMINUD_XMMdq_MEMdq:
  case XED_IFORM_PMINUD_XMMdq_XMMdq:
  case XED_IFORM_PMINUW_XMMdq_MEMdq:
  case XED_IFORM_PMINUW_XMMdq_XMMdq:
  case XED_IFORM_PMOVMSKB_GPR32_MMXq:
  case XED_IFORM_PMOVMSKB_GPR32_XMMdq:
  case XED_IFORM_PMOVSXBD_XMMdq_MEMd:
  case XED_IFORM_PMOVSXBD_XMMdq_XMMd:
  case XED_IFORM_PMOVSXBQ_XMMdq_MEMw:
  case XED_IFORM_PMOVSXBQ_XMMdq_XMMw:
  case XED_IFORM_PMOVSXBW_XMMdq_MEMq:
  case XED_IFORM_PMOVSXBW_XMMdq_XMMq:
  case XED_IFORM_PMOVSXDQ_XMMdq_MEMq:
  case XED_IFORM_PMOVSXDQ_XMMdq_XMMq:
  case XED_IFORM_PMOVSXWD_XMMdq_MEMq:
  case XED_IFORM_PMOVSXWD_XMMdq_XMMq:
  case XED_IFORM_PMOVSXWQ_XMMdq_MEMd:
  case XED_IFORM_PMOVSXWQ_XMMdq_XMMd:
  case XED_IFORM_PMOVZXBD_XMMdq_MEMd:
  case XED_IFORM_PMOVZXBD_XMMdq_XMMd:
  case XED_IFORM_PMOVZXBQ_XMMdq_MEMw:
  case XED_IFORM_PMOVZXBQ_XMMdq_XMMw:
  case XED_IFORM_PMOVZXBW_XMMdq_MEMq:
  case XED_IFORM_PMOVZXBW_XMMdq_XMMq:
  case XED_IFORM_PMOVZXDQ_XMMdq_MEMq:
  case XED_IFORM_PMOVZXDQ_XMMdq_XMMq:
  case XED_IFORM_PMOVZXWD_XMMdq_MEMq:
  case XED_IFORM_PMOVZXWD_XMMdq_XMMq:
  case XED_IFORM_PMOVZXWQ_XMMdq_MEMd:
  case XED_IFORM_PMOVZXWQ_XMMdq_XMMd:
  case XED_IFORM_PMULDQ_XMMdq_MEMdq:
  case XED_IFORM_PMULDQ_XMMdq_XMMdq:
  case XED_IFORM_PMULHRSW_MMXq_MEMq:
  case XED_IFORM_PMULHRSW_MMXq_MMXq:
  case XED_IFORM_PMULHRSW_XMMdq_MEMdq:
  case XED_IFORM_PMULHRSW_XMMdq_XMMdq:
  case XED_IFORM_PMULHRW_MMXq_MEMq:
  case XED_IFORM_PMULHRW_MMXq_MMXq:
  case XED_IFORM_PMULHUW_MMXq_MEMq:
  case XED_IFORM_PMULHUW_MMXq_MMXq:
  case XED_IFORM_PMULHUW_XMMdq_MEMdq:
  case XED_IFORM_PMULHUW_XMMdq_XMMdq:
  case XED_IFORM_PMULHW_MMXq_MEMq:
  case XED_IFORM_PMULHW_MMXq_MMXq:
  case XED_IFORM_PMULHW_XMMdq_MEMdq:
  case XED_IFORM_PMULHW_XMMdq_XMMdq:
  case XED_IFORM_PMULLD_XMMdq_MEMdq:
  case XED_IFORM_PMULLD_XMMdq_XMMdq:
  case XED_IFORM_PMULLW_MMXq_MEMq:
  case XED_IFORM_PMULLW_MMXq_MMXq:
  case XED_IFORM_PMULLW_XMMdq_MEMdq:
  case XED_IFORM_PMULLW_XMMdq_XMMdq:
  case XED_IFORM_PMULUDQ_MMXq_MEMq:
  case XED_IFORM_PMULUDQ_MMXq_MMXq:
  case XED_IFORM_PMULUDQ_XMMdq_MEMdq:
  case XED_IFORM_PMULUDQ_XMMdq_XMMdq:
  case XED_IFORM_POP_DS:
  case XED_IFORM_POP_ES:
  case XED_IFORM_POP_FS:
  case XED_IFORM_POP_GPRv_58:
  case XED_IFORM_POP_GPRv_8F:
  case XED_IFORM_POP_GS:
  case XED_IFORM_POP_MEMv:
  case XED_IFORM_POP_SS:
  case XED_IFORM_POPA:
  case XED_IFORM_POPAD:
  case XED_IFORM_POPCNT_GPRv_GPRv:
  case XED_IFORM_POPCNT_GPRv_MEMv:
  case XED_IFORM_POPF:
  case XED_IFORM_POPFD:
  case XED_IFORM_POPFQ:
  case XED_IFORM_POR_MMXq_MEMq:
  case XED_IFORM_POR_MMXq_MMXq:
  case XED_IFORM_POR_XMMdq_MEMdq:
  case XED_IFORM_POR_XMMdq_XMMdq:
  case XED_IFORM_PREFETCHNTA_MEMmprefetch:
  case XED_IFORM_PREFETCHT0_MEMmprefetch:
  case XED_IFORM_PREFETCHT1_MEMmprefetch:
  case XED_IFORM_PREFETCHT2_MEMmprefetch:
  case XED_IFORM_PREFETCHW_0F0Dr1:
  case XED_IFORM_PREFETCHW_0F0Dr3:
  case XED_IFORM_PREFETCHWT1_MEMu8:
  case XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch:
  case XED_IFORM_PREFETCH_RESERVED_0F0Dr4:
  case XED_IFORM_PREFETCH_RESERVED_0F0Dr5:
  case XED_IFORM_PREFETCH_RESERVED_0F0Dr6:
  case XED_IFORM_PREFETCH_RESERVED_0F0Dr7:
  case XED_IFORM_PSADBW_MMXq_MEMq:
  case XED_IFORM_PSADBW_MMXq_MMXq:
  case XED_IFORM_PSADBW_XMMdq_MEMdq:
  case XED_IFORM_PSADBW_XMMdq_XMMdq:
  case XED_IFORM_PSHUFB_MMXq_MEMq:
  case XED_IFORM_PSHUFB_MMXq_MMXq:
  case XED_IFORM_PSHUFB_XMMdq_MEMdq:
  case XED_IFORM_PSHUFB_XMMdq_XMMdq:
  case XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb:
  case XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_PSHUFW_MMXq_MEMq_IMMb:
  case XED_IFORM_PSHUFW_MMXq_MMXq_IMMb:
  case XED_IFORM_PSIGNB_MMXq_MEMq:
  case XED_IFORM_PSIGNB_MMXq_MMXq:
  case XED_IFORM_PSIGNB_XMMdq_MEMdq:
  case XED_IFORM_PSIGNB_XMMdq_XMMdq:
  case XED_IFORM_PSIGND_MMXq_MEMq:
  case XED_IFORM_PSIGND_MMXq_MMXq:
  case XED_IFORM_PSIGND_XMMdq_MEMdq:
  case XED_IFORM_PSIGND_XMMdq_XMMdq:
  case XED_IFORM_PSIGNW_MMXq_MEMq:
  case XED_IFORM_PSIGNW_MMXq_MMXq:
  case XED_IFORM_PSIGNW_XMMdq_MEMdq:
  case XED_IFORM_PSIGNW_XMMdq_XMMdq:
  case XED_IFORM_PSLLD_MMXq_IMMb:
  case XED_IFORM_PSLLD_MMXq_MEMq:
  case XED_IFORM_PSLLD_MMXq_MMXq:
  case XED_IFORM_PSLLD_XMMdq_IMMb:
  case XED_IFORM_PSLLD_XMMdq_MEMdq:
  case XED_IFORM_PSLLD_XMMdq_XMMdq:
  case XED_IFORM_PSLLDQ_XMMdq_IMMb:
  case XED_IFORM_PSLLQ_MMXq_IMMb:
  case XED_IFORM_PSLLQ_MMXq_MEMq:
  case XED_IFORM_PSLLQ_MMXq_MMXq:
  case XED_IFORM_PSLLQ_XMMdq_IMMb:
  case XED_IFORM_PSLLQ_XMMdq_MEMdq:
  case XED_IFORM_PSLLQ_XMMdq_XMMdq:
  case XED_IFORM_PSLLW_MMXq_IMMb:
  case XED_IFORM_PSLLW_MMXq_MEMq:
  case XED_IFORM_PSLLW_MMXq_MMXq:
  case XED_IFORM_PSLLW_XMMdq_IMMb:
  case XED_IFORM_PSLLW_XMMdq_MEMdq:
  case XED_IFORM_PSLLW_XMMdq_XMMdq:
  case XED_IFORM_PSMASH_RAX:
  case XED_IFORM_PSRAD_MMXq_IMMb:
  case XED_IFORM_PSRAD_MMXq_MEMq:
  case XED_IFORM_PSRAD_MMXq_MMXq:
  case XED_IFORM_PSRAD_XMMdq_IMMb:
  case XED_IFORM_PSRAD_XMMdq_MEMdq:
  case XED_IFORM_PSRAD_XMMdq_XMMdq:
  case XED_IFORM_PSRAW_MMXq_IMMb:
  case XED_IFORM_PSRAW_MMXq_MEMq:
  case XED_IFORM_PSRAW_MMXq_MMXq:
  case XED_IFORM_PSRAW_XMMdq_IMMb:
  case XED_IFORM_PSRAW_XMMdq_MEMdq:
  case XED_IFORM_PSRAW_XMMdq_XMMdq:
  case XED_IFORM_PSRLD_MMXq_IMMb:
  case XED_IFORM_PSRLD_MMXq_MEMq:
  case XED_IFORM_PSRLD_MMXq_MMXq:
  case XED_IFORM_PSRLD_XMMdq_IMMb:
  case XED_IFORM_PSRLD_XMMdq_MEMdq:
  case XED_IFORM_PSRLD_XMMdq_XMMdq:
  case XED_IFORM_PSRLDQ_XMMdq_IMMb:
  case XED_IFORM_PSRLQ_MMXq_IMMb:
  case XED_IFORM_PSRLQ_MMXq_MEMq:
  case XED_IFORM_PSRLQ_MMXq_MMXq:
  case XED_IFORM_PSRLQ_XMMdq_IMMb:
  case XED_IFORM_PSRLQ_XMMdq_MEMdq:
  case XED_IFORM_PSRLQ_XMMdq_XMMdq:
  case XED_IFORM_PSRLW_MMXq_IMMb:
  case XED_IFORM_PSRLW_MMXq_MEMq:
  case XED_IFORM_PSRLW_MMXq_MMXq:
  case XED_IFORM_PSRLW_XMMdq_IMMb:
  case XED_IFORM_PSRLW_XMMdq_MEMdq:
  case XED_IFORM_PSRLW_XMMdq_XMMdq:
  case XED_IFORM_PSUBB_MMXq_MEMq:
  case XED_IFORM_PSUBB_MMXq_MMXq:
  case XED_IFORM_PSUBB_XMMdq_MEMdq:
  case XED_IFORM_PSUBB_XMMdq_XMMdq:
  case XED_IFORM_PSUBD_MMXq_MEMq:
  case XED_IFORM_PSUBD_MMXq_MMXq:
  case XED_IFORM_PSUBD_XMMdq_MEMdq:
  case XED_IFORM_PSUBD_XMMdq_XMMdq:
  case XED_IFORM_PSUBQ_MMXq_MEMq:
  case XED_IFORM_PSUBQ_MMXq_MMXq:
  case XED_IFORM_PSUBQ_XMMdq_MEMdq:
  case XED_IFORM_PSUBQ_XMMdq_XMMdq:
  case XED_IFORM_PSUBSB_MMXq_MEMq:
  case XED_IFORM_PSUBSB_MMXq_MMXq:
  case XED_IFORM_PSUBSB_XMMdq_MEMdq:
  case XED_IFORM_PSUBSB_XMMdq_XMMdq:
  case XED_IFORM_PSUBSW_MMXq_MEMq:
  case XED_IFORM_PSUBSW_MMXq_MMXq:
  case XED_IFORM_PSUBSW_XMMdq_MEMdq:
  case XED_IFORM_PSUBSW_XMMdq_XMMdq:
  case XED_IFORM_PSUBUSB_MMXq_MEMq:
  case XED_IFORM_PSUBUSB_MMXq_MMXq:
  case XED_IFORM_PSUBUSB_XMMdq_MEMdq:
  case XED_IFORM_PSUBUSB_XMMdq_XMMdq:
  case XED_IFORM_PSUBUSW_MMXq_MEMq:
  case XED_IFORM_PSUBUSW_MMXq_MMXq:
  case XED_IFORM_PSUBUSW_XMMdq_MEMdq:
  case XED_IFORM_PSUBUSW_XMMdq_XMMdq:
  case XED_IFORM_PSUBW_MMXq_MEMq:
  case XED_IFORM_PSUBW_MMXq_MMXq:
  case XED_IFORM_PSUBW_XMMdq_MEMdq:
  case XED_IFORM_PSUBW_XMMdq_XMMdq:
  case XED_IFORM_PSWAPD_MMXq_MEMq:
  case XED_IFORM_PSWAPD_MMXq_MMXq:
  case XED_IFORM_PTEST_XMMdq_MEMdq:
  case XED_IFORM_PTEST_XMMdq_XMMdq:
  case XED_IFORM_PTWRITE_GPRy:
  case XED_IFORM_PTWRITE_MEMy:
  case XED_IFORM_PUNPCKHBW_MMXq_MEMq:
  case XED_IFORM_PUNPCKHBW_MMXq_MMXd:
  case XED_IFORM_PUNPCKHBW_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKHBW_XMMdq_XMMq:
  case XED_IFORM_PUNPCKHDQ_MMXq_MEMq:
  case XED_IFORM_PUNPCKHDQ_MMXq_MMXd:
  case XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKHDQ_XMMdq_XMMq:
  case XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq:
  case XED_IFORM_PUNPCKHWD_MMXq_MEMq:
  case XED_IFORM_PUNPCKHWD_MMXq_MMXd:
  case XED_IFORM_PUNPCKHWD_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKHWD_XMMdq_XMMq:
  case XED_IFORM_PUNPCKLBW_MMXq_MEMd:
  case XED_IFORM_PUNPCKLBW_MMXq_MMXd:
  case XED_IFORM_PUNPCKLBW_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKLBW_XMMdq_XMMq:
  case XED_IFORM_PUNPCKLDQ_MMXq_MEMd:
  case XED_IFORM_PUNPCKLDQ_MMXq_MMXd:
  case XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKLDQ_XMMdq_XMMq:
  case XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq:
  case XED_IFORM_PUNPCKLWD_MMXq_MEMd:
  case XED_IFORM_PUNPCKLWD_MMXq_MMXd:
  case XED_IFORM_PUNPCKLWD_XMMdq_MEMdq:
  case XED_IFORM_PUNPCKLWD_XMMdq_XMMq:
  case XED_IFORM_PUSH_CS:
  case XED_IFORM_PUSH_DS:
  case XED_IFORM_PUSH_ES:
  case XED_IFORM_PUSH_FS:
  case XED_IFORM_PUSH_GPRv_50:
  case XED_IFORM_PUSH_GPRv_FFr6:
  case XED_IFORM_PUSH_GS:
  case XED_IFORM_PUSH_IMMb:
  case XED_IFORM_PUSH_IMMz:
  case XED_IFORM_PUSH_MEMv:
  case XED_IFORM_PUSH_SS:
  case XED_IFORM_PUSHA:
  case XED_IFORM_PUSHAD:
  case XED_IFORM_PUSHF:
  case XED_IFORM_PUSHFD:
  case XED_IFORM_PUSHFQ:
  case XED_IFORM_PVALIDATE_RAX_ECX_EDX:
  case XED_IFORM_PXOR_MMXq_MEMq:
  case XED_IFORM_PXOR_MMXq_MMXq:
  case XED_IFORM_PXOR_XMMdq_MEMdq:
  case XED_IFORM_PXOR_XMMdq_XMMdq:
  case XED_IFORM_RCL_GPR8_CL:
  case XED_IFORM_RCL_GPR8_IMMb:
  case XED_IFORM_RCL_GPR8_ONE:
  case XED_IFORM_RCL_GPRv_CL:
  case XED_IFORM_RCL_GPRv_IMMb:
  case XED_IFORM_RCL_GPRv_ONE:
  case XED_IFORM_RCL_MEMb_CL:
  case XED_IFORM_RCL_MEMb_IMMb:
  case XED_IFORM_RCL_MEMb_ONE:
  case XED_IFORM_RCL_MEMv_CL:
  case XED_IFORM_RCL_MEMv_IMMb:
  case XED_IFORM_RCL_MEMv_ONE:
  case XED_IFORM_RCPPS_XMMps_MEMps:
  case XED_IFORM_RCPPS_XMMps_XMMps:
  case XED_IFORM_RCPSS_XMMss_MEMss:
  case XED_IFORM_RCPSS_XMMss_XMMss:
  case XED_IFORM_RCR_GPR8_CL:
  case XED_IFORM_RCR_GPR8_IMMb:
  case XED_IFORM_RCR_GPR8_ONE:
  case XED_IFORM_RCR_GPRv_CL:
  case XED_IFORM_RCR_GPRv_IMMb:
  case XED_IFORM_RCR_GPRv_ONE:
  case XED_IFORM_RCR_MEMb_CL:
  case XED_IFORM_RCR_MEMb_IMMb:
  case XED_IFORM_RCR_MEMb_ONE:
  case XED_IFORM_RCR_MEMv_CL:
  case XED_IFORM_RCR_MEMv_IMMb:
  case XED_IFORM_RCR_MEMv_ONE:
  case XED_IFORM_RDFSBASE_GPRy:
  case XED_IFORM_RDGSBASE_GPRy:
  case XED_IFORM_RDMSR:
  case XED_IFORM_RDPID_GPR32u32:
  case XED_IFORM_RDPID_GPR64u64:
  case XED_IFORM_RDPKRU:
  case XED_IFORM_RDPMC:
  case XED_IFORM_RDPRU:
  case XED_IFORM_RDRAND_GPRv:
  case XED_IFORM_RDSEED_GPRv:
  case XED_IFORM_RDSSPD_GPR32u32:
  case XED_IFORM_RDSSPQ_GPR64u64:
  case XED_IFORM_RDTSC:
  case XED_IFORM_RDTSCP:
  case XED_IFORM_REPE_CMPSB:
  case XED_IFORM_REPE_CMPSD:
  case XED_IFORM_REPE_CMPSQ:
  case XED_IFORM_REPE_CMPSW:
  case XED_IFORM_REPE_SCASB:
  case XED_IFORM_REPE_SCASD:
  case XED_IFORM_REPE_SCASQ:
  case XED_IFORM_REPE_SCASW:
  case XED_IFORM_REPNE_CMPSB:
  case XED_IFORM_REPNE_CMPSD:
  case XED_IFORM_REPNE_CMPSQ:
  case XED_IFORM_REPNE_CMPSW:
  case XED_IFORM_REPNE_SCASB:
  case XED_IFORM_REPNE_SCASD:
  case XED_IFORM_REPNE_SCASQ:
  case XED_IFORM_REPNE_SCASW:
  case XED_IFORM_REP_INSB:
  case XED_IFORM_REP_INSD:
  case XED_IFORM_REP_INSW:
  case XED_IFORM_REP_LODSB:
  case XED_IFORM_REP_LODSD:
  case XED_IFORM_REP_LODSQ:
  case XED_IFORM_REP_LODSW:
  case XED_IFORM_REP_MONTMUL:
  case XED_IFORM_REP_MOVSB:
  case XED_IFORM_REP_MOVSD:
  case XED_IFORM_REP_MOVSQ:
  case XED_IFORM_REP_MOVSW:
  case XED_IFORM_REP_OUTSB:
  case XED_IFORM_REP_OUTSD:
  case XED_IFORM_REP_OUTSW:
  case XED_IFORM_REP_STOSB:
  case XED_IFORM_REP_STOSD:
  case XED_IFORM_REP_STOSQ:
  case XED_IFORM_REP_STOSW:
  case XED_IFORM_REP_XCRYPTCBC:
  case XED_IFORM_REP_XCRYPTCFB:
  case XED_IFORM_REP_XCRYPTCTR:
  case XED_IFORM_REP_XCRYPTECB:
  case XED_IFORM_REP_XCRYPTOFB:
  case XED_IFORM_REP_XSHA1:
  case XED_IFORM_REP_XSHA256:
  case XED_IFORM_REP_XSTORE:
  case XED_IFORM_RET_FAR:
  case XED_IFORM_RET_FAR_IMMw:
  case XED_IFORM_RET_NEAR:
  case XED_IFORM_RET_NEAR_IMMw:
  case XED_IFORM_RMPADJUST_RAX_RCX_RDX:
  case XED_IFORM_RMPUPDATE_RAX_RCX:
  case XED_IFORM_ROL_GPR8_CL:
  case XED_IFORM_ROL_GPR8_IMMb:
  case XED_IFORM_ROL_GPR8_ONE:
  case XED_IFORM_ROL_GPRv_CL:
  case XED_IFORM_ROL_GPRv_IMMb:
  case XED_IFORM_ROL_GPRv_ONE:
  case XED_IFORM_ROL_MEMb_CL:
  case XED_IFORM_ROL_MEMb_IMMb:
  case XED_IFORM_ROL_MEMb_ONE:
  case XED_IFORM_ROL_MEMv_CL:
  case XED_IFORM_ROL_MEMv_IMMb:
  case XED_IFORM_ROL_MEMv_ONE:
  case XED_IFORM_ROR_GPR8_CL:
  case XED_IFORM_ROR_GPR8_IMMb:
  case XED_IFORM_ROR_GPR8_ONE:
  case XED_IFORM_ROR_GPRv_CL:
  case XED_IFORM_ROR_GPRv_IMMb:
  case XED_IFORM_ROR_GPRv_ONE:
  case XED_IFORM_ROR_MEMb_CL:
  case XED_IFORM_ROR_MEMb_IMMb:
  case XED_IFORM_ROR_MEMb_ONE:
  case XED_IFORM_ROR_MEMv_CL:
  case XED_IFORM_ROR_MEMv_IMMb:
  case XED_IFORM_ROR_MEMv_ONE:
  case XED_IFORM_RORX_VGPR32d_MEMd_IMMb:
  case XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb:
  case XED_IFORM_RORX_VGPR64q_MEMq_IMMb:
  case XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb:
  case XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb:
  case XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb:
  case XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb:
  case XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb:
  case XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb:
  case XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb:
  case XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb:
  case XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb:
  case XED_IFORM_RSM:
  case XED_IFORM_RSQRTPS_XMMps_MEMps:
  case XED_IFORM_RSQRTPS_XMMps_XMMps:
  case XED_IFORM_RSQRTSS_XMMss_MEMss:
  case XED_IFORM_RSQRTSS_XMMss_XMMss:
  case XED_IFORM_RSTORSSP_MEMu64:
  case XED_IFORM_SAHF:
  case XED_IFORM_SALC:
  case XED_IFORM_SAR_GPR8_CL:
  case XED_IFORM_SAR_GPR8_IMMb:
  case XED_IFORM_SAR_GPR8_ONE:
  case XED_IFORM_SAR_GPRv_CL:
  case XED_IFORM_SAR_GPRv_IMMb:
  case XED_IFORM_SAR_GPRv_ONE:
  case XED_IFORM_SAR_MEMb_CL:
  case XED_IFORM_SAR_MEMb_IMMb:
  case XED_IFORM_SAR_MEMb_ONE:
  case XED_IFORM_SAR_MEMv_CL:
  case XED_IFORM_SAR_MEMv_IMMb:
  case XED_IFORM_SAR_MEMv_ONE:
  case XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d:
  case XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q:
  case XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_SAVEPREVSSP:
  case XED_IFORM_SBB_AL_IMMb:
  case XED_IFORM_SBB_GPR8_GPR8_18:
  case XED_IFORM_SBB_GPR8_GPR8_1A:
  case XED_IFORM_SBB_GPR8_IMMb_80r3:
  case XED_IFORM_SBB_GPR8_IMMb_82r3:
  case XED_IFORM_SBB_GPR8_MEMb:
  case XED_IFORM_SBB_GPRv_GPRv_19:
  case XED_IFORM_SBB_GPRv_GPRv_1B:
  case XED_IFORM_SBB_GPRv_IMMb:
  case XED_IFORM_SBB_GPRv_IMMz:
  case XED_IFORM_SBB_GPRv_MEMv:
  case XED_IFORM_SBB_MEMb_GPR8:
  case XED_IFORM_SBB_MEMb_IMMb_80r3:
  case XED_IFORM_SBB_MEMb_IMMb_82r3:
  case XED_IFORM_SBB_MEMv_GPRv:
  case XED_IFORM_SBB_MEMv_IMMb:
  case XED_IFORM_SBB_MEMv_IMMz:
  case XED_IFORM_SBB_OrAX_IMMz:
  case XED_IFORM_SBB_LOCK_MEMb_GPR8:
  case XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3:
  case XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3:
  case XED_IFORM_SBB_LOCK_MEMv_GPRv:
  case XED_IFORM_SBB_LOCK_MEMv_IMMb:
  case XED_IFORM_SBB_LOCK_MEMv_IMMz:
  case XED_IFORM_SCASB:
  case XED_IFORM_SCASD:
  case XED_IFORM_SCASQ:
  case XED_IFORM_SCASW:
  case XED_IFORM_SEAMCALL:
  case XED_IFORM_SEAMOPS:
  case XED_IFORM_SEAMRET:
  case XED_IFORM_SENDUIPI_GPR32u32:
  case XED_IFORM_SERIALIZE:
  case XED_IFORM_SETB_GPR8:
  case XED_IFORM_SETB_MEMb:
  case XED_IFORM_SETBE_GPR8:
  case XED_IFORM_SETBE_MEMb:
  case XED_IFORM_SETL_GPR8:
  case XED_IFORM_SETL_MEMb:
  case XED_IFORM_SETLE_GPR8:
  case XED_IFORM_SETLE_MEMb:
  case XED_IFORM_SETNB_GPR8:
  case XED_IFORM_SETNB_MEMb:
  case XED_IFORM_SETNBE_GPR8:
  case XED_IFORM_SETNBE_MEMb:
  case XED_IFORM_SETNL_GPR8:
  case XED_IFORM_SETNL_MEMb:
  case XED_IFORM_SETNLE_GPR8:
  case XED_IFORM_SETNLE_MEMb:
  case XED_IFORM_SETNO_GPR8:
  case XED_IFORM_SETNO_MEMb:
  case XED_IFORM_SETNP_GPR8:
  case XED_IFORM_SETNP_MEMb:
  case XED_IFORM_SETNS_GPR8:
  case XED_IFORM_SETNS_MEMb:
  case XED_IFORM_SETNZ_GPR8:
  case XED_IFORM_SETNZ_MEMb:
  case XED_IFORM_SETO_GPR8:
  case XED_IFORM_SETO_MEMb:
  case XED_IFORM_SETP_GPR8:
  case XED_IFORM_SETP_MEMb:
  case XED_IFORM_SETS_GPR8:
  case XED_IFORM_SETS_MEMb:
  case XED_IFORM_SETSSBSY:
  case XED_IFORM_SETZ_GPR8:
  case XED_IFORM_SETZ_MEMb:
  case XED_IFORM_SFENCE:
  case XED_IFORM_SGDT_MEMs:
  case XED_IFORM_SGDT_MEMs64:
  case XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA:
  case XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA:
  case XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA:
  case XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA:
  case XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA:
  case XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA:
  case XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA:
  case XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA:
  case XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA:
  case XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA:
  case XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA:
  case XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA:
  case XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA:
  case XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA:
  case XED_IFORM_SHL_GPR8_CL_D2r4:
  case XED_IFORM_SHL_GPR8_CL_D2r6:
  case XED_IFORM_SHL_GPR8_IMMb_C0r4:
  case XED_IFORM_SHL_GPR8_IMMb_C0r6:
  case XED_IFORM_SHL_GPR8_ONE_D0r4:
  case XED_IFORM_SHL_GPR8_ONE_D0r6:
  case XED_IFORM_SHL_GPRv_CL_D3r4:
  case XED_IFORM_SHL_GPRv_CL_D3r6:
  case XED_IFORM_SHL_GPRv_IMMb_C1r4:
  case XED_IFORM_SHL_GPRv_IMMb_C1r6:
  case XED_IFORM_SHL_GPRv_ONE_D1r4:
  case XED_IFORM_SHL_GPRv_ONE_D1r6:
  case XED_IFORM_SHL_MEMb_CL_D2r4:
  case XED_IFORM_SHL_MEMb_CL_D2r6:
  case XED_IFORM_SHL_MEMb_IMMb_C0r4:
  case XED_IFORM_SHL_MEMb_IMMb_C0r6:
  case XED_IFORM_SHL_MEMb_ONE_D0r4:
  case XED_IFORM_SHL_MEMb_ONE_D0r6:
  case XED_IFORM_SHL_MEMv_CL_D3r4:
  case XED_IFORM_SHL_MEMv_CL_D3r6:
  case XED_IFORM_SHL_MEMv_IMMb_C1r4:
  case XED_IFORM_SHL_MEMv_IMMb_C1r6:
  case XED_IFORM_SHL_MEMv_ONE_D1r4:
  case XED_IFORM_SHL_MEMv_ONE_D1r6:
  case XED_IFORM_SHLD_GPRv_GPRv_CL:
  case XED_IFORM_SHLD_GPRv_GPRv_IMMb:
  case XED_IFORM_SHLD_MEMv_GPRv_CL:
  case XED_IFORM_SHLD_MEMv_GPRv_IMMb:
  case XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d:
  case XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q:
  case XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_SHR_GPR8_CL:
  case XED_IFORM_SHR_GPR8_IMMb:
  case XED_IFORM_SHR_GPR8_ONE:
  case XED_IFORM_SHR_GPRv_CL:
  case XED_IFORM_SHR_GPRv_IMMb:
  case XED_IFORM_SHR_GPRv_ONE:
  case XED_IFORM_SHR_MEMb_CL:
  case XED_IFORM_SHR_MEMb_IMMb:
  case XED_IFORM_SHR_MEMb_ONE:
  case XED_IFORM_SHR_MEMv_CL:
  case XED_IFORM_SHR_MEMv_IMMb:
  case XED_IFORM_SHR_MEMv_ONE:
  case XED_IFORM_SHRD_GPRv_GPRv_CL:
  case XED_IFORM_SHRD_GPRv_GPRv_IMMb:
  case XED_IFORM_SHRD_MEMv_GPRv_CL:
  case XED_IFORM_SHRD_MEMv_GPRv_IMMb:
  case XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d:
  case XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d:
  case XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q:
  case XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q:
  case XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb:
  case XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb:
  case XED_IFORM_SHUFPS_XMMps_MEMps_IMMb:
  case XED_IFORM_SHUFPS_XMMps_XMMps_IMMb:
  case XED_IFORM_SIDT_MEMs:
  case XED_IFORM_SIDT_MEMs64:
  case XED_IFORM_SKINIT_EAX:
  case XED_IFORM_SLDT_GPRv:
  case XED_IFORM_SLDT_MEMw:
  case XED_IFORM_SLWPCB_VGPRyy:
  case XED_IFORM_SMSW_GPRv:
  case XED_IFORM_SMSW_MEMw:
  case XED_IFORM_SQRTPD_XMMpd_MEMpd:
  case XED_IFORM_SQRTPD_XMMpd_XMMpd:
  case XED_IFORM_SQRTPS_XMMps_MEMps:
  case XED_IFORM_SQRTPS_XMMps_XMMps:
  case XED_IFORM_SQRTSD_XMMsd_MEMsd:
  case XED_IFORM_SQRTSD_XMMsd_XMMsd:
  case XED_IFORM_SQRTSS_XMMss_MEMss:
  case XED_IFORM_SQRTSS_XMMss_XMMss:
  case XED_IFORM_STAC:
  case XED_IFORM_STC:
  case XED_IFORM_STD:
  case XED_IFORM_STGI:
  case XED_IFORM_STI:
  case XED_IFORM_STMXCSR_MEMd:
  case XED_IFORM_STOSB:
  case XED_IFORM_STOSD:
  case XED_IFORM_STOSQ:
  case XED_IFORM_STOSW:
  case XED_IFORM_STR_GPRv:
  case XED_IFORM_STR_MEMw:
  case XED_IFORM_STTILECFG_MEM:
  case XED_IFORM_STUI:
  case XED_IFORM_SUB_AL_IMMb:
  case XED_IFORM_SUB_GPR8_GPR8_28:
  case XED_IFORM_SUB_GPR8_GPR8_2A:
  case XED_IFORM_SUB_GPR8_IMMb_80r5:
  case XED_IFORM_SUB_GPR8_IMMb_82r5:
  case XED_IFORM_SUB_GPR8_MEMb:
  case XED_IFORM_SUB_GPRv_GPRv_29:
  case XED_IFORM_SUB_GPRv_GPRv_2B:
  case XED_IFORM_SUB_GPRv_IMMb:
  case XED_IFORM_SUB_GPRv_IMMz:
  case XED_IFORM_SUB_GPRv_MEMv:
  case XED_IFORM_SUB_MEMb_GPR8:
  case XED_IFORM_SUB_MEMb_IMMb_80r5:
  case XED_IFORM_SUB_MEMb_IMMb_82r5:
  case XED_IFORM_SUB_MEMv_GPRv:
  case XED_IFORM_SUB_MEMv_IMMb:
  case XED_IFORM_SUB_MEMv_IMMz:
  case XED_IFORM_SUB_OrAX_IMMz:
  case XED_IFORM_SUBPD_XMMpd_MEMpd:
  case XED_IFORM_SUBPD_XMMpd_XMMpd:
  case XED_IFORM_SUBPS_XMMps_MEMps:
  case XED_IFORM_SUBPS_XMMps_XMMps:
  case XED_IFORM_SUBSD_XMMsd_MEMsd:
  case XED_IFORM_SUBSD_XMMsd_XMMsd:
  case XED_IFORM_SUBSS_XMMss_MEMss:
  case XED_IFORM_SUBSS_XMMss_XMMss:
  case XED_IFORM_SUB_LOCK_MEMb_GPR8:
  case XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5:
  case XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5:
  case XED_IFORM_SUB_LOCK_MEMv_GPRv:
  case XED_IFORM_SUB_LOCK_MEMv_IMMb:
  case XED_IFORM_SUB_LOCK_MEMv_IMMz:
  case XED_IFORM_SWAPGS:
  case XED_IFORM_SYSCALL:
  case XED_IFORM_SYSCALL_AMD:
  case XED_IFORM_SYSENTER:
  case XED_IFORM_SYSEXIT:
  case XED_IFORM_SYSRET:
  case XED_IFORM_SYSRET64:
  case XED_IFORM_SYSRET_AMD:
  case XED_IFORM_T1MSKC_VGPR32d_MEMd:
  case XED_IFORM_T1MSKC_VGPR32d_VGPR32d:
  case XED_IFORM_T1MSKC_VGPRyy_MEMy:
  case XED_IFORM_T1MSKC_VGPRyy_VGPRyy:
  case XED_IFORM_TDCALL:
  case XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32:
  case XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32:
  case XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32:
  case XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32:
  case XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32:
  case XED_IFORM_TEST_AL_IMMb:
  case XED_IFORM_TEST_GPR8_GPR8:
  case XED_IFORM_TEST_GPR8_IMMb_F6r0:
  case XED_IFORM_TEST_GPR8_IMMb_F6r1:
  case XED_IFORM_TEST_GPRv_GPRv:
  case XED_IFORM_TEST_GPRv_IMMz_F7r0:
  case XED_IFORM_TEST_GPRv_IMMz_F7r1:
  case XED_IFORM_TEST_MEMb_GPR8:
  case XED_IFORM_TEST_MEMb_IMMb_F6r0:
  case XED_IFORM_TEST_MEMb_IMMb_F6r1:
  case XED_IFORM_TEST_MEMv_GPRv:
  case XED_IFORM_TEST_MEMv_IMMz_F7r0:
  case XED_IFORM_TEST_MEMv_IMMz_F7r1:
  case XED_IFORM_TEST_OrAX_IMMz:
  case XED_IFORM_TESTUI:
  case XED_IFORM_TILELOADD_TMMu32_MEMu32:
  case XED_IFORM_TILELOADDT1_TMMu32_MEMu32:
  case XED_IFORM_TILERELEASE:
  case XED_IFORM_TILESTORED_MEMu32_TMMu32:
  case XED_IFORM_TILEZERO_TMMu32:
  case XED_IFORM_TLBSYNC:
  case XED_IFORM_TPAUSE_GPR32u32:
  case XED_IFORM_TZCNT_GPRv_GPRv:
  case XED_IFORM_TZCNT_GPRv_MEMv:
  case XED_IFORM_TZMSK_VGPR32d_MEMd:
  case XED_IFORM_TZMSK_VGPR32d_VGPR32d:
  case XED_IFORM_TZMSK_VGPRyy_MEMy:
  case XED_IFORM_TZMSK_VGPRyy_VGPRyy:
  case XED_IFORM_UCOMISD_XMMsd_MEMsd:
  case XED_IFORM_UCOMISD_XMMsd_XMMsd:
  case XED_IFORM_UCOMISS_XMMss_MEMss:
  case XED_IFORM_UCOMISS_XMMss_XMMss:
  case XED_IFORM_UD0:
  case XED_IFORM_UD0_GPR32_GPR32:
  case XED_IFORM_UD0_GPR32_MEMd:
  case XED_IFORM_UD1_GPR32_GPR32:
  case XED_IFORM_UD1_GPR32_MEMd:
  case XED_IFORM_UD2:
  case XED_IFORM_UIRET:
  case XED_IFORM_UMONITOR_GPRa:
  case XED_IFORM_UMWAIT_GPR32:
  case XED_IFORM_UNPCKHPD_XMMpd_MEMdq:
  case XED_IFORM_UNPCKHPD_XMMpd_XMMq:
  case XED_IFORM_UNPCKHPS_XMMps_MEMdq:
  case XED_IFORM_UNPCKHPS_XMMps_XMMdq:
  case XED_IFORM_UNPCKLPD_XMMpd_MEMdq:
  case XED_IFORM_UNPCKLPD_XMMpd_XMMq:
  case XED_IFORM_UNPCKLPS_XMMps_MEMdq:
  case XED_IFORM_UNPCKLPS_XMMps_XMMq:
  case XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512:
  case XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128:
  case XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128:
  case XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512:
  case XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512:
  case XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512:
  case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128:
  case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128:
  case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512:
  case XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512:
  case XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512:
  case XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128:
  case XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128:
  case XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512:
  case XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512:
  case XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512:
  case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128:
  case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128:
  case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512:
  case XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512:
  case XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512:
  case XED_IFORM_VAESIMC_XMMdq_MEMdq:
  case XED_IFORM_VAESIMC_XMMdq_XMMdq:
  case XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512:
  case XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VBROADCASTF128_YMMqq_MEMdq:
  case XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VBROADCASTI128_YMMqq_MEMdq:
  case XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VBROADCASTSD_YMMqq_MEMq:
  case XED_IFORM_VBROADCASTSD_YMMqq_XMMdq:
  case XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VBROADCASTSS_XMMdq_MEMd:
  case XED_IFORM_VBROADCASTSS_XMMdq_XMMdq:
  case XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VBROADCASTSS_YMMqq_MEMd:
  case XED_IFORM_VBROADCASTSS_YMMqq_XMMdq:
  case XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512:
  case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512:
  case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512:
  case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512:
  case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512:
  case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512:
  case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512:
  case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512:
  case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb:
  case XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb:
  case XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512:
  case XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512:
  case XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb:
  case XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb:
  case XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VCOMISD_XMMq_MEMq:
  case XED_IFORM_VCOMISD_XMMq_XMMq:
  case XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VCOMISS_XMMd_MEMd:
  case XED_IFORM_VCOMISS_XMMd_XMMd:
  case XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCVTDQ2PD_XMMdq_MEMq:
  case XED_IFORM_VCVTDQ2PD_XMMdq_XMMq:
  case XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq:
  case XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq:
  case XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128:
  case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256:
  case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq:
  case XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq:
  case XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq:
  case XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq:
  case XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512:
  case XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128:
  case XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256:
  case XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512:
  case XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128:
  case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256:
  case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512:
  case XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq:
  case XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq:
  case XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq:
  case XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq:
  case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128:
  case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256:
  case XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512:
  case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCVTPD2PS_XMMdq_MEMdq:
  case XED_IFORM_VCVTPD2PS_XMMdq_MEMqq:
  case XED_IFORM_VCVTPD2PS_XMMdq_XMMdq:
  case XED_IFORM_VCVTPD2PS_XMMdq_YMMqq:
  case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128:
  case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256:
  case XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512:
  case XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128:
  case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256:
  case XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512:
  case XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2PS_XMMdq_MEMq:
  case XED_IFORM_VCVTPH2PS_XMMdq_XMMq:
  case XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2PS_YMMqq_MEMdq:
  case XED_IFORM_VCVTPH2PS_YMMqq_XMMdq:
  case XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq:
  case XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq:
  case XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq:
  case XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq:
  case XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCVTPS2PD_XMMdq_MEMq:
  case XED_IFORM_VCVTPS2PD_XMMdq_XMMq:
  case XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2PD_YMMqq_MEMdq:
  case XED_IFORM_VCVTPS2PD_YMMqq_XMMdq:
  case XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb:
  case XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb:
  case XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb:
  case XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb:
  case XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128:
  case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256:
  case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512:
  case XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128:
  case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256:
  case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512:
  case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128:
  case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256:
  case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128:
  case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256:
  case XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512:
  case XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512:
  case XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VCVTSD2SI_GPR32d_MEMq:
  case XED_IFORM_VCVTSD2SI_GPR32d_XMMq:
  case XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512:
  case XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512:
  case XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512:
  case XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512:
  case XED_IFORM_VCVTSD2SI_GPR64q_MEMq:
  case XED_IFORM_VCVTSD2SI_GPR64q_XMMq:
  case XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512:
  case XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512:
  case XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512:
  case XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512:
  case XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512:
  case XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512:
  case XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512:
  case XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512:
  case XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512:
  case XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512:
  case XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512:
  case XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512:
  case XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512:
  case XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512:
  case XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512:
  case XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512:
  case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d:
  case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q:
  case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512:
  case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512:
  case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512:
  case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512:
  case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512:
  case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512:
  case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512:
  case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512:
  case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d:
  case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q:
  case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512:
  case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512:
  case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512:
  case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512:
  case XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512:
  case XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512:
  case XED_IFORM_VCVTSS2SI_GPR32d_MEMd:
  case XED_IFORM_VCVTSS2SI_GPR32d_XMMd:
  case XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512:
  case XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512:
  case XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512:
  case XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512:
  case XED_IFORM_VCVTSS2SI_GPR64q_MEMd:
  case XED_IFORM_VCVTSS2SI_GPR64q_XMMd:
  case XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512:
  case XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512:
  case XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512:
  case XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512:
  case XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq:
  case XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq:
  case XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq:
  case XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq:
  case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128:
  case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256:
  case XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512:
  case XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128:
  case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256:
  case XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512:
  case XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq:
  case XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq:
  case XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq:
  case XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq:
  case XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VCVTTSD2SI_GPR32d_MEMq:
  case XED_IFORM_VCVTTSD2SI_GPR32d_XMMq:
  case XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512:
  case XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512:
  case XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512:
  case XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512:
  case XED_IFORM_VCVTTSD2SI_GPR64q_MEMq:
  case XED_IFORM_VCVTTSD2SI_GPR64q_XMMq:
  case XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512:
  case XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512:
  case XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512:
  case XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512:
  case XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512:
  case XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512:
  case XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512:
  case XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512:
  case XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512:
  case XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512:
  case XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512:
  case XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512:
  case XED_IFORM_VCVTTSS2SI_GPR32d_MEMd:
  case XED_IFORM_VCVTTSS2SI_GPR32d_XMMd:
  case XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512:
  case XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512:
  case XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512:
  case XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512:
  case XED_IFORM_VCVTTSS2SI_GPR64q_MEMd:
  case XED_IFORM_VCVTTSS2SI_GPR64q_XMMd:
  case XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512:
  case XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512:
  case XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512:
  case XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512:
  case XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128:
  case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256:
  case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128:
  case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256:
  case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512:
  case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128:
  case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256:
  case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128:
  case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256:
  case XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512:
  case XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512:
  case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512:
  case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512:
  case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512:
  case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512:
  case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512:
  case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512:
  case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512:
  case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512:
  case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512:
  case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512:
  case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512:
  case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512:
  case XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512:
  case XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512:
  case XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512:
  case XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512:
  case XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512:
  case XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VERR_GPR16:
  case XED_IFORM_VERR_MEMw:
  case XED_IFORM_VERW_GPR16:
  case XED_IFORM_VERW_MEMw:
  case XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER:
  case XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER:
  case XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER:
  case XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER:
  case XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb:
  case XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb:
  case XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb:
  case XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb:
  case XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb:
  case XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb:
  case XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512:
  case XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512:
  case XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512:
  case XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512:
  case XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512:
  case XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512:
  case XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq:
  case XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq:
  case XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq:
  case XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd:
  case XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd:
  case XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd:
  case XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq:
  case XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq:
  case XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq:
  case XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd:
  case XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd:
  case XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd:
  case XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512:
  case XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512:
  case XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512:
  case XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512:
  case XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq:
  case XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq:
  case XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq:
  case XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd:
  case XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd:
  case XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd:
  case XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq:
  case XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd:
  case XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd:
  case XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq:
  case XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq:
  case XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq:
  case XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd:
  case XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd:
  case XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd:
  case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128:
  case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256:
  case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512:
  case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128:
  case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256:
  case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512:
  case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128:
  case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256:
  case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512:
  case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512:
  case XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512:
  case XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VFRCZPD_XMMdq_MEMdq:
  case XED_IFORM_VFRCZPD_XMMdq_XMMdq:
  case XED_IFORM_VFRCZPD_YMMqq_MEMqq:
  case XED_IFORM_VFRCZPD_YMMqq_YMMqq:
  case XED_IFORM_VFRCZPS_XMMdq_MEMdq:
  case XED_IFORM_VFRCZPS_XMMdq_XMMdq:
  case XED_IFORM_VFRCZPS_YMMqq_MEMqq:
  case XED_IFORM_VFRCZPS_YMMqq_YMMqq:
  case XED_IFORM_VFRCZSD_XMMdq_MEMq:
  case XED_IFORM_VFRCZSD_XMMdq_XMMq:
  case XED_IFORM_VFRCZSS_XMMdq_MEMd:
  case XED_IFORM_VFRCZSS_XMMdq_XMMd:
  case XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128:
  case XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256:
  case XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128:
  case XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128:
  case XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256:
  case XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256:
  case XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512:
  case XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128:
  case XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128:
  case XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256:
  case XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256:
  case XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512:
  case XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128:
  case XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256:
  case XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128:
  case XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256:
  case XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512:
  case XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512:
  case XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8:
  case XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8:
  case XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8:
  case XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8:
  case XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8:
  case XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb:
  case XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb:
  case XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512:
  case XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512:
  case XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb:
  case XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb:
  case XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512:
  case XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb:
  case XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VLDDQU_XMMdq_MEMdq:
  case XED_IFORM_VLDDQU_YMMqq_MEMqq:
  case XED_IFORM_VLDMXCSR_MEMd:
  case XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq:
  case XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq:
  case XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq:
  case XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq:
  case XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq:
  case XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMCALL:
  case XED_IFORM_VMCLEAR_MEMq:
  case XED_IFORM_VMFUNC:
  case XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMLAUNCH:
  case XED_IFORM_VMLOAD_ArAX:
  case XED_IFORM_VMMCALL:
  case XED_IFORM_VMOVAPD_MEMdq_XMMdq:
  case XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VMOVAPD_MEMqq_YMMqq:
  case XED_IFORM_VMOVAPD_XMMdq_MEMdq:
  case XED_IFORM_VMOVAPD_XMMdq_XMMdq_28:
  case XED_IFORM_VMOVAPD_XMMdq_XMMdq_29:
  case XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VMOVAPD_YMMqq_MEMqq:
  case XED_IFORM_VMOVAPD_YMMqq_YMMqq_28:
  case XED_IFORM_VMOVAPD_YMMqq_YMMqq_29:
  case XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VMOVAPS_MEMdq_XMMdq:
  case XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VMOVAPS_MEMqq_YMMqq:
  case XED_IFORM_VMOVAPS_XMMdq_MEMdq:
  case XED_IFORM_VMOVAPS_XMMdq_XMMdq_28:
  case XED_IFORM_VMOVAPS_XMMdq_XMMdq_29:
  case XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VMOVAPS_YMMqq_MEMqq:
  case XED_IFORM_VMOVAPS_YMMqq_YMMqq_28:
  case XED_IFORM_VMOVAPS_YMMqq_YMMqq_29:
  case XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VMOVD_GPR32d_XMMd:
  case XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512:
  case XED_IFORM_VMOVD_MEMd_XMMd:
  case XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512:
  case XED_IFORM_VMOVD_XMMdq_GPR32d:
  case XED_IFORM_VMOVD_XMMdq_MEMd:
  case XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512:
  case XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VMOVDDUP_XMMdq_MEMq:
  case XED_IFORM_VMOVDDUP_XMMdq_XMMq:
  case XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VMOVDDUP_YMMqq_MEMqq:
  case XED_IFORM_VMOVDDUP_YMMqq_YMMqq:
  case XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VMOVDQA_MEMdq_XMMdq:
  case XED_IFORM_VMOVDQA_MEMqq_YMMqq:
  case XED_IFORM_VMOVDQA_XMMdq_MEMdq:
  case XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F:
  case XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F:
  case XED_IFORM_VMOVDQA_YMMqq_MEMqq:
  case XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F:
  case XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F:
  case XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VMOVDQU_MEMdq_XMMdq:
  case XED_IFORM_VMOVDQU_MEMqq_YMMqq:
  case XED_IFORM_VMOVDQU_XMMdq_MEMdq:
  case XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F:
  case XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F:
  case XED_IFORM_VMOVDQU_YMMqq_MEMqq:
  case XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F:
  case XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F:
  case XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512:
  case XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512:
  case XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512:
  case XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512:
  case XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512:
  case XED_IFORM_VMOVHPD_MEMq_XMMdq:
  case XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq:
  case XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512:
  case XED_IFORM_VMOVHPS_MEMq_XMMdq:
  case XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq:
  case XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq:
  case XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512:
  case XED_IFORM_VMOVLPD_MEMq_XMMq:
  case XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512:
  case XED_IFORM_VMOVLPS_MEMq_XMMq:
  case XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMOVMSKPD_GPR32d_XMMdq:
  case XED_IFORM_VMOVMSKPD_GPR32d_YMMqq:
  case XED_IFORM_VMOVMSKPS_GPR32d_XMMdq:
  case XED_IFORM_VMOVMSKPS_GPR32d_YMMqq:
  case XED_IFORM_VMOVNTDQ_MEMdq_XMMdq:
  case XED_IFORM_VMOVNTDQ_MEMqq_YMMqq:
  case XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512:
  case XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512:
  case XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512:
  case XED_IFORM_VMOVNTDQA_XMMdq_MEMdq:
  case XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VMOVNTDQA_YMMqq_MEMqq:
  case XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VMOVNTPD_MEMdq_XMMdq:
  case XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512:
  case XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512:
  case XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512:
  case XED_IFORM_VMOVNTPD_MEMqq_YMMqq:
  case XED_IFORM_VMOVNTPS_MEMdq_XMMdq:
  case XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512:
  case XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512:
  case XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512:
  case XED_IFORM_VMOVNTPS_MEMqq_YMMqq:
  case XED_IFORM_VMOVQ_GPR64q_XMMq:
  case XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512:
  case XED_IFORM_VMOVQ_MEMq_XMMq_7E:
  case XED_IFORM_VMOVQ_MEMq_XMMq_D6:
  case XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512:
  case XED_IFORM_VMOVQ_XMMdq_GPR64q:
  case XED_IFORM_VMOVQ_XMMdq_MEMq_6E:
  case XED_IFORM_VMOVQ_XMMdq_MEMq_7E:
  case XED_IFORM_VMOVQ_XMMdq_XMMq_7E:
  case XED_IFORM_VMOVQ_XMMdq_XMMq_D6:
  case XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512:
  case XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VMOVSD_MEMq_XMMq:
  case XED_IFORM_VMOVSD_XMMdq_MEMq:
  case XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10:
  case XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11:
  case XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VMOVSHDUP_XMMdq_MEMdq:
  case XED_IFORM_VMOVSHDUP_XMMdq_XMMdq:
  case XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VMOVSHDUP_YMMqq_MEMqq:
  case XED_IFORM_VMOVSHDUP_YMMqq_YMMqq:
  case XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VMOVSLDUP_XMMdq_MEMdq:
  case XED_IFORM_VMOVSLDUP_XMMdq_XMMdq:
  case XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VMOVSLDUP_YMMqq_MEMqq:
  case XED_IFORM_VMOVSLDUP_YMMqq_YMMqq:
  case XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VMOVSS_MEMd_XMMd:
  case XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VMOVSS_XMMdq_MEMd:
  case XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10:
  case XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11:
  case XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMOVUPD_MEMdq_XMMdq:
  case XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VMOVUPD_MEMqq_YMMqq:
  case XED_IFORM_VMOVUPD_XMMdq_MEMdq:
  case XED_IFORM_VMOVUPD_XMMdq_XMMdq_10:
  case XED_IFORM_VMOVUPD_XMMdq_XMMdq_11:
  case XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VMOVUPD_YMMqq_MEMqq:
  case XED_IFORM_VMOVUPD_YMMqq_YMMqq_10:
  case XED_IFORM_VMOVUPD_YMMqq_YMMqq_11:
  case XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VMOVUPS_MEMdq_XMMdq:
  case XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VMOVUPS_MEMqq_YMMqq:
  case XED_IFORM_VMOVUPS_XMMdq_MEMdq:
  case XED_IFORM_VMOVUPS_XMMdq_XMMdq_10:
  case XED_IFORM_VMOVUPS_XMMdq_XMMdq_11:
  case XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VMOVUPS_YMMqq_MEMqq:
  case XED_IFORM_VMOVUPS_YMMqq_YMMqq_10:
  case XED_IFORM_VMOVUPS_YMMqq_YMMqq_11:
  case XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512:
  case XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512:
  case XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512:
  case XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VMPTRLD_MEMq:
  case XED_IFORM_VMPTRST_MEMq:
  case XED_IFORM_VMREAD_GPR32_GPR32:
  case XED_IFORM_VMREAD_GPR64_GPR64:
  case XED_IFORM_VMREAD_MEMd_GPR32:
  case XED_IFORM_VMREAD_MEMq_GPR64:
  case XED_IFORM_VMRESUME:
  case XED_IFORM_VMRUN_ArAX:
  case XED_IFORM_VMSAVE:
  case XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VMWRITE_GPR32_GPR32:
  case XED_IFORM_VMWRITE_GPR32_MEMd:
  case XED_IFORM_VMWRITE_GPR64_GPR64:
  case XED_IFORM_VMWRITE_GPR64_MEMq:
  case XED_IFORM_VMXOFF:
  case XED_IFORM_VMXON_MEMq:
  case XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512:
  case XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512:
  case XED_IFORM_VPABSB_XMMdq_MEMdq:
  case XED_IFORM_VPABSB_XMMdq_XMMdq:
  case XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512:
  case XED_IFORM_VPABSB_YMMqq_MEMqq:
  case XED_IFORM_VPABSB_YMMqq_YMMqq:
  case XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512:
  case XED_IFORM_VPABSD_XMMdq_MEMdq:
  case XED_IFORM_VPABSD_XMMdq_XMMdq:
  case XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VPABSD_YMMqq_MEMqq:
  case XED_IFORM_VPABSD_YMMqq_YMMqq:
  case XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512:
  case XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512:
  case XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512:
  case XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512:
  case XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512:
  case XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512:
  case XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512:
  case XED_IFORM_VPABSW_XMMdq_MEMdq:
  case XED_IFORM_VPABSW_XMMdq_XMMdq:
  case XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512:
  case XED_IFORM_VPABSW_YMMqq_MEMqq:
  case XED_IFORM_VPABSW_YMMqq_YMMqq:
  case XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512:
  case XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512:
  case XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512:
  case XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512:
  case XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512:
  case XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512:
  case XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512:
  case XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512:
  case XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512:
  case XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512:
  case XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512:
  case XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512:
  case XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512:
  case XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512:
  case XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512:
  case XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512:
  case XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPBROADCASTB_XMMdq_MEMb:
  case XED_IFORM_VPBROADCASTB_XMMdq_XMMb:
  case XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512:
  case XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPBROADCASTB_YMMqq_MEMb:
  case XED_IFORM_VPBROADCASTB_YMMqq_XMMb:
  case XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512:
  case XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512:
  case XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPBROADCASTD_XMMdq_MEMd:
  case XED_IFORM_VPBROADCASTD_XMMdq_XMMd:
  case XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512:
  case XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPBROADCASTD_YMMqq_MEMd:
  case XED_IFORM_VPBROADCASTD_YMMqq_XMMd:
  case XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512:
  case XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512:
  case XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512:
  case XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512:
  case XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD:
  case XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512:
  case XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512:
  case XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD:
  case XED_IFORM_VPBROADCASTQ_XMMdq_MEMq:
  case XED_IFORM_VPBROADCASTQ_XMMdq_XMMq:
  case XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512:
  case XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPBROADCASTQ_YMMqq_MEMq:
  case XED_IFORM_VPBROADCASTQ_YMMqq_XMMq:
  case XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512:
  case XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512:
  case XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPBROADCASTW_XMMdq_MEMw:
  case XED_IFORM_VPBROADCASTW_XMMdq_XMMw:
  case XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512:
  case XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPBROADCASTW_YMMqq_MEMw:
  case XED_IFORM_VPBROADCASTW_YMMqq_XMMw:
  case XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512:
  case XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512:
  case XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8:
  case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8:
  case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq:
  case XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512:
  case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512:
  case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512:
  case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512:
  case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512:
  case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512:
  case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512:
  case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512:
  case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512:
  case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512:
  case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512:
  case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512:
  case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512:
  case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512:
  case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512:
  case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512:
  case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512:
  case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512:
  case XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512:
  case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512:
  case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512:
  case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512:
  case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512:
  case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512:
  case XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512:
  case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512:
  case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512:
  case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512:
  case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512:
  case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512:
  case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512:
  case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512:
  case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512:
  case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512:
  case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512:
  case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512:
  case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512:
  case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512:
  case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512:
  case XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512:
  case XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512:
  case XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512:
  case XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512:
  case XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD:
  case XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD:
  case XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD:
  case XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD:
  case XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512:
  case XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512:
  case XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32:
  case XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32:
  case XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512:
  case XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512:
  case XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32:
  case XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32:
  case XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512:
  case XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512:
  case XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512:
  case XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512:
  case XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32:
  case XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32:
  case XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512:
  case XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512:
  case XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32:
  case XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32:
  case XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512:
  case XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512:
  case XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512:
  case XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512:
  case XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32:
  case XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32:
  case XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512:
  case XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512:
  case XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32:
  case XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32:
  case XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512:
  case XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512:
  case XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512:
  case XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512:
  case XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32:
  case XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32:
  case XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512:
  case XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512:
  case XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32:
  case XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32:
  case XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512:
  case XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512:
  case XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb:
  case XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb:
  case XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512:
  case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512:
  case XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512:
  case XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb:
  case XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512:
  case XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb:
  case XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512:
  case XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb:
  case XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb:
  case XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb:
  case XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb:
  case XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15:
  case XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5:
  case XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb:
  case XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5:
  case XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128:
  case XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128:
  case XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256:
  case XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256:
  case XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512:
  case XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128:
  case XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128:
  case XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256:
  case XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256:
  case XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512:
  case XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128:
  case XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256:
  case XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128:
  case XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256:
  case XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512:
  case XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128:
  case XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128:
  case XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256:
  case XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256:
  case XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512:
  case XED_IFORM_VPHADDBD_XMMdq_MEMdq:
  case XED_IFORM_VPHADDBD_XMMdq_XMMdq:
  case XED_IFORM_VPHADDBQ_XMMdq_MEMdq:
  case XED_IFORM_VPHADDBQ_XMMdq_XMMdq:
  case XED_IFORM_VPHADDBW_XMMdq_MEMdq:
  case XED_IFORM_VPHADDBW_XMMdq_XMMdq:
  case XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPHADDDQ_XMMdq_MEMdq:
  case XED_IFORM_VPHADDDQ_XMMdq_XMMdq:
  case XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPHADDUBD_XMMdq_MEMdq:
  case XED_IFORM_VPHADDUBD_XMMdq_XMMdq:
  case XED_IFORM_VPHADDUBQ_XMMdq_MEMdq:
  case XED_IFORM_VPHADDUBQ_XMMdq_XMMdq:
  case XED_IFORM_VPHADDUBW_XMMdq_MEMdq:
  case XED_IFORM_VPHADDUBW_XMMdq_XMMdq:
  case XED_IFORM_VPHADDUDQ_XMMdq_MEMdq:
  case XED_IFORM_VPHADDUDQ_XMMdq_XMMdq:
  case XED_IFORM_VPHADDUWD_XMMdq_MEMdq:
  case XED_IFORM_VPHADDUWD_XMMdq_XMMdq:
  case XED_IFORM_VPHADDUWQ_XMMdq_MEMdq:
  case XED_IFORM_VPHADDUWQ_XMMdq_XMMdq:
  case XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPHADDWD_XMMdq_MEMdq:
  case XED_IFORM_VPHADDWD_XMMdq_XMMdq:
  case XED_IFORM_VPHADDWQ_XMMdq_MEMdq:
  case XED_IFORM_VPHADDWQ_XMMdq_XMMdq:
  case XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq:
  case XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq:
  case XED_IFORM_VPHSUBBW_XMMdq_MEMdq:
  case XED_IFORM_VPHSUBBW_XMMdq_XMMdq:
  case XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPHSUBDQ_XMMdq_MEMdq:
  case XED_IFORM_VPHSUBDQ_XMMdq_XMMdq:
  case XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPHSUBWD_XMMdq_MEMdq:
  case XED_IFORM_VPHSUBWD_XMMdq_XMMdq:
  case XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb:
  case XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb:
  case XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512:
  case XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb:
  case XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb:
  case XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512:
  case XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb:
  case XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb:
  case XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512:
  case XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb:
  case XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb:
  case XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512:
  case XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD:
  case XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD:
  case XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD:
  case XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD:
  case XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512:
  case XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512:
  case XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512:
  case XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512:
  case XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512:
  case XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512:
  case XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512:
  case XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512:
  case XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512:
  case XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512:
  case XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512:
  case XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512:
  case XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512:
  case XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512:
  case XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512:
  case XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512:
  case XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512:
  case XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512:
  case XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512:
  case XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512:
  case XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512:
  case XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512:
  case XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512:
  case XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512:
  case XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512:
  case XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512:
  case XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512:
  case XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512:
  case XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512:
  case XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512:
  case XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512:
  case XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512:
  case XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512:
  case XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512:
  case XED_IFORM_VPMOVMSKB_GPR32d_XMMdq:
  case XED_IFORM_VPMOVMSKB_GPR32d_YMMqq:
  case XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512:
  case XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512:
  case XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512:
  case XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512:
  case XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512:
  case XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512:
  case XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512:
  case XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512:
  case XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512:
  case XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512:
  case XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512:
  case XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512:
  case XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512:
  case XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512:
  case XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512:
  case XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512:
  case XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512:
  case XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512:
  case XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512:
  case XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512:
  case XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512:
  case XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512:
  case XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512:
  case XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512:
  case XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512:
  case XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512:
  case XED_IFORM_VPMOVSXBD_XMMdq_MEMd:
  case XED_IFORM_VPMOVSXBD_XMMdq_XMMd:
  case XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBD_YMMqq_MEMq:
  case XED_IFORM_VPMOVSXBD_YMMqq_XMMq:
  case XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBQ_XMMdq_MEMw:
  case XED_IFORM_VPMOVSXBQ_XMMdq_XMMw:
  case XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBQ_YMMqq_MEMd:
  case XED_IFORM_VPMOVSXBQ_YMMqq_XMMd:
  case XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBW_XMMdq_MEMq:
  case XED_IFORM_VPMOVSXBW_XMMdq_XMMq:
  case XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVSXBW_YMMqq_MEMdq:
  case XED_IFORM_VPMOVSXBW_YMMqq_XMMdq:
  case XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512:
  case XED_IFORM_VPMOVSXDQ_XMMdq_MEMq:
  case XED_IFORM_VPMOVSXDQ_XMMdq_XMMq:
  case XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq:
  case XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq:
  case XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VPMOVSXWD_XMMdq_MEMq:
  case XED_IFORM_VPMOVSXWD_XMMdq_XMMq:
  case XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVSXWD_YMMqq_MEMdq:
  case XED_IFORM_VPMOVSXWD_YMMqq_XMMdq:
  case XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512:
  case XED_IFORM_VPMOVSXWQ_XMMdq_MEMd:
  case XED_IFORM_VPMOVSXWQ_XMMdq_XMMd:
  case XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVSXWQ_YMMqq_MEMq:
  case XED_IFORM_VPMOVSXWQ_YMMqq_XMMq:
  case XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPMOVZXBD_XMMdq_MEMd:
  case XED_IFORM_VPMOVZXBD_XMMdq_XMMd:
  case XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBD_YMMqq_MEMq:
  case XED_IFORM_VPMOVZXBD_YMMqq_XMMq:
  case XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBQ_XMMdq_MEMw:
  case XED_IFORM_VPMOVZXBQ_XMMdq_XMMw:
  case XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBQ_YMMqq_MEMd:
  case XED_IFORM_VPMOVZXBQ_YMMqq_XMMd:
  case XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBW_XMMdq_MEMq:
  case XED_IFORM_VPMOVZXBW_XMMdq_XMMq:
  case XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512:
  case XED_IFORM_VPMOVZXBW_YMMqq_MEMdq:
  case XED_IFORM_VPMOVZXBW_YMMqq_XMMdq:
  case XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512:
  case XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512:
  case XED_IFORM_VPMOVZXDQ_XMMdq_MEMq:
  case XED_IFORM_VPMOVZXDQ_XMMdq_XMMq:
  case XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512:
  case XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq:
  case XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq:
  case XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512:
  case XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512:
  case XED_IFORM_VPMOVZXWD_XMMdq_MEMq:
  case XED_IFORM_VPMOVZXWD_XMMdq_XMMq:
  case XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVZXWD_YMMqq_MEMdq:
  case XED_IFORM_VPMOVZXWD_YMMqq_XMMdq:
  case XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512:
  case XED_IFORM_VPMOVZXWQ_XMMdq_MEMd:
  case XED_IFORM_VPMOVZXWQ_XMMdq_XMMd:
  case XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMOVZXWQ_YMMqq_MEMq:
  case XED_IFORM_VPMOVZXWQ_YMMqq_XMMq:
  case XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512:
  case XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512:
  case XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512:
  case XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512:
  case XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512:
  case XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512:
  case XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512:
  case XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512:
  case XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512:
  case XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512:
  case XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512:
  case XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512:
  case XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512:
  case XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512:
  case XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512:
  case XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512:
  case XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512:
  case XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512:
  case XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512:
  case XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512:
  case XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512:
  case XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512:
  case XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512:
  case XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512:
  case XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512:
  case XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512:
  case XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512:
  case XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512:
  case XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128:
  case XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256:
  case XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512:
  case XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128:
  case XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256:
  case XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512:
  case XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128:
  case XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256:
  case XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512:
  case XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128:
  case XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256:
  case XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512:
  case XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq:
  case XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512:
  case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512:
  case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512:
  case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512:
  case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512:
  case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512:
  case XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512:
  case XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512:
  case XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512:
  case XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512:
  case XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512:
  case XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512:
  case XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512:
  case XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512:
  case XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq:
  case XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq:
  case XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512:
  case XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512:
  case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512:
  case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512:
  case XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512:
  case XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512:
  case XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512:
  case XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512:
  case XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512:
  case XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512:
  case XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512:
  case XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512:
  case XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512:
  case XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512:
  case XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512:
  case XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VPTEST_XMMdq_MEMdq:
  case XED_IFORM_VPTEST_XMMdq_XMMdq:
  case XED_IFORM_VPTEST_YMMqq_MEMqq:
  case XED_IFORM_VPTEST_YMMqq_YMMqq:
  case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512:
  case XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512:
  case XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512:
  case XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512:
  case XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512:
  case XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512:
  case XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512:
  case XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512:
  case XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512:
  case XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512:
  case XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512:
  case XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512:
  case XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512:
  case XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512:
  case XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER:
  case XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER:
  case XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER:
  case XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER:
  case XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER:
  case XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER:
  case XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER:
  case XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER:
  case XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VRCPPS_XMMdq_MEMdq:
  case XED_IFORM_VRCPPS_XMMdq_XMMdq:
  case XED_IFORM_VRCPPS_YMMqq_MEMqq:
  case XED_IFORM_VRCPPS_YMMqq_YMMqq:
  case XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512:
  case XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512:
  case XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb:
  case XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb:
  case XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb:
  case XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb:
  case XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER:
  case XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER:
  case XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER:
  case XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER:
  case XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER:
  case XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER:
  case XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER:
  case XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER:
  case XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VRSQRTPS_XMMdq_MEMdq:
  case XED_IFORM_VRSQRTPS_XMMdq_XMMdq:
  case XED_IFORM_VRSQRTPS_YMMqq_MEMqq:
  case XED_IFORM_VRSQRTPS_YMMqq_YMMqq:
  case XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128:
  case XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256:
  case XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512:
  case XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128:
  case XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256:
  case XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512:
  case XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512:
  case XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128:
  case XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256:
  case XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512:
  case XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128:
  case XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256:
  case XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512:
  case XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512:
  case XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512:
  case XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512:
  case XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512:
  case XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512:
  case XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512:
  case XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512:
  case XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb:
  case XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb:
  case XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb:
  case XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb:
  case XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512:
  case XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512:
  case XED_IFORM_VSQRTPD_XMMdq_MEMdq:
  case XED_IFORM_VSQRTPD_XMMdq_XMMdq:
  case XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512:
  case XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512:
  case XED_IFORM_VSQRTPD_YMMqq_MEMqq:
  case XED_IFORM_VSQRTPD_YMMqq_YMMqq:
  case XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512:
  case XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512:
  case XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512:
  case XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512:
  case XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512:
  case XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512:
  case XED_IFORM_VSQRTPS_XMMdq_MEMdq:
  case XED_IFORM_VSQRTPS_XMMdq_XMMdq:
  case XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512:
  case XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512:
  case XED_IFORM_VSQRTPS_YMMqq_MEMqq:
  case XED_IFORM_VSQRTPS_YMMqq_YMMqq:
  case XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512:
  case XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512:
  case XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VSTMXCSR_MEMd:
  case XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512:
  case XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512:
  case XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512:
  case XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512:
  case XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq:
  case XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq:
  case XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd:
  case XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd:
  case XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VTESTPD_XMMdq_MEMdq:
  case XED_IFORM_VTESTPD_XMMdq_XMMdq:
  case XED_IFORM_VTESTPD_YMMqq_MEMqq:
  case XED_IFORM_VTESTPD_YMMqq_YMMqq:
  case XED_IFORM_VTESTPS_XMMdq_MEMdq:
  case XED_IFORM_VTESTPS_XMMdq_XMMdq:
  case XED_IFORM_VTESTPS_YMMqq_MEMqq:
  case XED_IFORM_VTESTPS_YMMqq_YMMqq:
  case XED_IFORM_VUCOMISD_XMMdq_MEMq:
  case XED_IFORM_VUCOMISD_XMMdq_XMMq:
  case XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512:
  case XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512:
  case XED_IFORM_VUCOMISS_XMMdq_MEMd:
  case XED_IFORM_VUCOMISS_XMMdq_XMMd:
  case XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512:
  case XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512:
  case XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512:
  case XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512:
  case XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512:
  case XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512:
  case XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512:
  case XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512:
  case XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512:
  case XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512:
  case XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512:
  case XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512:
  case XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512:
  case XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512:
  case XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512:
  case XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512:
  case XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512:
  case XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512:
  case XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq:
  case XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq:
  case XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512:
  case XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512:
  case XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq:
  case XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq:
  case XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512:
  case XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512:
  case XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512:
  case XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512:
  case XED_IFORM_VZEROALL:
  case XED_IFORM_VZEROUPPER:
  case XED_IFORM_WBINVD:
  case XED_IFORM_WBNOINVD:
  case XED_IFORM_WRFSBASE_GPRy:
  case XED_IFORM_WRGSBASE_GPRy:
  case XED_IFORM_WRMSR:
  case XED_IFORM_WRPKRU:
  case XED_IFORM_WRSSD_MEMu32_GPR32u32:
  case XED_IFORM_WRSSQ_MEMu64_GPR64u64:
  case XED_IFORM_WRUSSD_MEMu32_GPR32u32:
  case XED_IFORM_WRUSSQ_MEMu64_GPR64u64:
  case XED_IFORM_XABORT_IMMb:
  case XED_IFORM_XADD_GPR8_GPR8:
  case XED_IFORM_XADD_GPRv_GPRv:
  case XED_IFORM_XADD_MEMb_GPR8:
  case XED_IFORM_XADD_MEMv_GPRv:
  case XED_IFORM_XADD_LOCK_MEMb_GPR8:
  case XED_IFORM_XADD_LOCK_MEMv_GPRv:
  case XED_IFORM_XBEGIN_RELBRz:
  case XED_IFORM_XCHG_GPR8_GPR8:
  case XED_IFORM_XCHG_GPRv_GPRv:
  case XED_IFORM_XCHG_GPRv_OrAX:
  case XED_IFORM_XCHG_MEMb_GPR8:
  case XED_IFORM_XCHG_MEMv_GPRv:
  case XED_IFORM_XEND:
  case XED_IFORM_XGETBV:
  case XED_IFORM_XLAT:
  case XED_IFORM_XOR_AL_IMMb:
  case XED_IFORM_XOR_GPR8_GPR8_30:
  case XED_IFORM_XOR_GPR8_GPR8_32:
  case XED_IFORM_XOR_GPR8_IMMb_80r6:
  case XED_IFORM_XOR_GPR8_IMMb_82r6:
  case XED_IFORM_XOR_GPR8_MEMb:
  case XED_IFORM_XOR_GPRv_GPRv_31:
  case XED_IFORM_XOR_GPRv_GPRv_33:
  case XED_IFORM_XOR_GPRv_IMMb:
  case XED_IFORM_XOR_GPRv_IMMz:
  case XED_IFORM_XOR_GPRv_MEMv:
  case XED_IFORM_XOR_MEMb_GPR8:
  case XED_IFORM_XOR_MEMb_IMMb_80r6:
  case XED_IFORM_XOR_MEMb_IMMb_82r6:
  case XED_IFORM_XOR_MEMv_GPRv:
  case XED_IFORM_XOR_MEMv_IMMb:
  case XED_IFORM_XOR_MEMv_IMMz:
  case XED_IFORM_XOR_OrAX_IMMz:
  case XED_IFORM_XORPD_XMMxuq_MEMxuq:
  case XED_IFORM_XORPD_XMMxuq_XMMxuq:
  case XED_IFORM_XORPS_XMMxud_MEMxud:
  case XED_IFORM_XORPS_XMMxud_XMMxud:
  case XED_IFORM_XOR_LOCK_MEMb_GPR8:
  case XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6:
  case XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6:
  case XED_IFORM_XOR_LOCK_MEMv_GPRv:
  case XED_IFORM_XOR_LOCK_MEMv_IMMb:
  case XED_IFORM_XOR_LOCK_MEMv_IMMz:
  case XED_IFORM_XRESLDTRK:
  case XED_IFORM_XRSTOR_MEMmxsave:
  case XED_IFORM_XRSTOR64_MEMmxsave:
  case XED_IFORM_XRSTORS_MEMmxsave:
  case XED_IFORM_XRSTORS64_MEMmxsave:
  case XED_IFORM_XSAVE_MEMmxsave:
  case XED_IFORM_XSAVE64_MEMmxsave:
  case XED_IFORM_XSAVEC_MEMmxsave:
  case XED_IFORM_XSAVEC64_MEMmxsave:
  case XED_IFORM_XSAVEOPT_MEMmxsave:
  case XED_IFORM_XSAVEOPT64_MEMmxsave:
  case XED_IFORM_XSAVES_MEMmxsave:
  case XED_IFORM_XSAVES64_MEMmxsave:
  case XED_IFORM_XSETBV:
  case XED_IFORM_XSTORE:
  case XED_IFORM_XSUSLDTRK:
  case XED_IFORM_XTEST:
  case XED_IFORM_LAST:
  default:
     xed_assert(0);
  }
*/