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273 lines
14 KiB
273 lines
14 KiB
#include "VirtualMachine.h"
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XED_REG_ENUM VmOperandSizeToRegEnumBase(VM_OPERAND_SIZE_ENUM OperandSize)
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{
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switch (OperandSize)
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{
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case VM_OPSIZE_8: return XED_REG_GPR8_FIRST;
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case VM_OPSIZE_16: return XED_REG_GPR16_FIRST;
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case VM_OPSIZE_32: return XED_REG_GPR32_FIRST;
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case VM_OPSIZE_64: return XED_REG_GPR64_FIRST;
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}
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return XED_REG_INVALID;
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}
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XED_REG_ENUM VmGetRegOfSize(XED_REG_ENUM Reg, VM_OPERAND_SIZE_ENUM OperandSize)
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{
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if (Reg >= XED_REG_GPR8_FIRST && Reg <= XED_REG_GPR8_LAST)
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return (XED_REG_ENUM)(VmOperandSizeToRegEnumBase(OperandSize) + (Reg - XED_REG_GPR8_FIRST));
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else if (Reg >= XED_REG_GPR16_FIRST && Reg <= XED_REG_GPR16_LAST)
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return (XED_REG_ENUM)(VmOperandSizeToRegEnumBase(OperandSize) + (Reg - XED_REG_GPR16_FIRST));
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else if (Reg >= XED_REG_GPR32_FIRST && Reg <= XED_REG_GPR32_LAST)
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return (XED_REG_ENUM)(VmOperandSizeToRegEnumBase(OperandSize) + (Reg - XED_REG_GPR32_FIRST));
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else if (Reg >= XED_REG_GPR64_FIRST && Reg <= XED_REG_GPR64_LAST)
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return (XED_REG_ENUM)(VmOperandSizeToRegEnumBase(OperandSize) + (Reg - XED_REG_GPR64_FIRST));
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return XED_REG_INVALID;
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}
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VM_OPERAND_SIZE_ENUM VmXRegToOpSize(XED_REG_ENUM Reg)
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{
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if (Reg >= XED_REG_GPR8_FIRST && Reg <= XED_REG_GPR8_LAST)
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return VM_OPSIZE_8;
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else if (Reg >= XED_REG_GPR16_FIRST && Reg <= XED_REG_GPR16_LAST)
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return VM_OPSIZE_16;
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else if (Reg >= XED_REG_GPR32_FIRST && Reg <= XED_REG_GPR32_LAST)
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return VM_OPSIZE_32;
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else if (Reg >= XED_REG_GPR64_FIRST && Reg <= XED_REG_GPR64_LAST)
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return VM_OPSIZE_64;
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return VM_OPSIZE_COUNT;
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}
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XED_REG_ENUM VmIRegToXReg(VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize)
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{
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switch (IReg)
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{
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case VM_IREG_1: return VmGetRegOfSize(XED_REG_RAX, OperandSize);
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case VM_IREG_2: return VmGetRegOfSize(XED_REG_RBX, OperandSize);
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case VM_IREG_3: return VmGetRegOfSize(XED_REG_RCX, OperandSize);
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}
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return XED_REG_INVALID;
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//Less portable version.
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/*if (OperandSize == VM_OPSIZE_8)
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{
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return (XED_REG_ENUM)(XED_REG_AL + IReg);
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}
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return (XED_REG_ENUM)(XED_REG_AX + (16 * (OperandSize - 1)) + IReg);*/
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}
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VM_REG_ENUM VmXRegToVRegId(XED_REG_ENUM Reg)
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{
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return (VM_REG_ENUM)(VmGetRegOfSize(Reg, VM_OPSIZE_64) - XED_REG_RAX);
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}
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CONST CHAR* VmIClassToString(VM_ICLASS_ENUM IClass)
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{
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if (IClass >= VM_ICLASS_COUNT)
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return "VM_ICLASS_INVALID";
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else if (IClass == VM_ICLASS_EXIT)
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return "VM_ICLASS_EXIT";
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else if (IClass >= VM_ICLASS_LD_IREG_MEM_START && IClass <= VM_ICLASS_LD_IREG_MEM_END)
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return "VM_ICLASS_LD_IREG_MEM";
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else if (IClass >= VM_ICLASS_ST_IREG_MEM_START && IClass <= VM_ICLASS_ST_IREG_MEM_END)
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return "VM_ICLASS_ST_IREG_MEM";
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else if (IClass >= VM_ICLASS_LD_IREG_MEM_START && IClass <= VM_ICLASS_LD_IREG_REG_END)
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return "VM_ICLASS_LD_IREG_REG";
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else if (IClass >= VM_ICLASS_ST_IREG_REG_START && IClass <= VM_ICLASS_ST_IREG_REG_END)
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return "VM_ICLASS_ST_IREG_REG";
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else if (IClass >= VM_ICLASS_LD_IREG_IMM_START && IClass <= VM_ICLASS_LD_IREG_IMM_END)
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return "VM_ICLASS_LD_IREG_IMM";
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}
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PUCHAR VmHandlerEpilogue(UINT InstructionSize, PUINT OutSize, XED_REG_ENUM Vip, XED_REG_ENUM HandlerTableReg)
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{
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// add rdx, InstructionSize + Prologue Size
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// movzx r8,byte ptr[rdx]
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// jmp qword ptr[rsi+r8*8h]
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XED_ENCODER_INSTRUCTION InstList[3];
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InstructionSize += VM_HANDLER_EPILOGUE_SIZE;
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_ADD, 64, XedReg(Vip), XedImm0(InstructionSize, 32));
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOVZX, 64, XedReg(XED_REG_R8), XedMemB(Vip, 16));
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XedInst1(&InstList[2], XedGlobalMachineState, XED_ICLASS_JMP, 64, XedMemBISD(HandlerTableReg, XED_REG_R8, 8, XedDisp(0, 0), 64));
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PUCHAR Ret = XedEncodeInstructions(InstList, 3, OutSize);
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if (*OutSize == VM_HANDLER_EPILOGUE_SIZE)
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return Ret;
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delete[] Ret;
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InstructionSize -= VM_HANDLER_EPILOGUE_SIZE;
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InstructionSize += *OutSize;
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_ADD, 64, XedReg(Vip), XedImm0(InstructionSize, 32));
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOVZX, 64, XedReg(XED_REG_R8), XedMemB(Vip, 16));
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XedInst1(&InstList[2], XedGlobalMachineState, XED_ICLASS_JMP, 64, XedMemBISD(HandlerTableReg, XED_REG_R8, 8, XedDisp(0, 0), 64));
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return XedEncodeInstructions(InstList, 3, OutSize);
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}
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PUCHAR VmHandlerEnter(PUINT OutSize)
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{
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}
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PUCHAR VmHandlerExit(PUINT OutSize)
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{
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}
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PUCHAR VmHandlerIRegMem_B(VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize, BOOL Load, PUINT OutSize, XED_REG_ENUM XReg1)
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{
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/*
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* movzx r8,byte ptr[rdx+2]
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* mov r8, qword ptr[rbp+r8*8]
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* mov (ireg), (size) ptr[r8]
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*/
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UINT OpSizeBits = VmOpSizeToBits(OperandSize);
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XED_ENCODER_INSTRUCTION InstList[3];
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_MOVZX, 64, XedReg(XReg1), XedMemBD(XED_REG_RDX, XedDisp(2, 8), 8));
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOV, 64, XedReg(XReg1), XedMemBISD(XED_REG_RBP, XReg1, 8, XedDisp(0,0), 64));
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if (Load)
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XedInst2(&InstList[2], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedReg(VmIRegToXReg(IReg, OperandSize)), XedMemB(XReg1, OpSizeBits));
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else
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XedInst2(&InstList[2], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedMemB(XReg1, OpSizeBits), XedReg(VmIRegToXReg(IReg, OperandSize)));
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return XedEncodeInstructions(InstList, 3, OutSize);
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}
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PUCHAR VmHandlerIRegMem_BD(VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize, BOOL Load, PUINT OutSize, XED_REG_ENUM XReg1, XED_REG_ENUM XReg2)
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{
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/*
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* movzx r8,byte ptr[rdx+2]
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* mov r8, qword ptr[rbp+r8*8]
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* mov r9, dword ptr[rdx+3]
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* mov (ireg), (size) ptr[r8+r9]
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*/
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UINT OpSizeBits = VmOpSizeToBits(OperandSize);
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XED_ENCODER_INSTRUCTION InstList[4];
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_MOVZX, 64, XedReg(XReg1), XedMemBD(XED_REG_RDX, XedDisp(2, 8), 8));
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOV, 64, XedReg(XReg1), XedMemBISD(XED_REG_RBP, XReg1, 8, XedDisp(0, 0), 64));
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XedInst2(&InstList[2], XedGlobalMachineState, XED_ICLASS_MOVSXD, 64, XedReg(XReg2), XedMemBD(XED_REG_RDX, XedDisp(3, 8), 32));
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if (Load)
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XedInst2(&InstList[3], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedReg(VmIRegToXReg(IReg, OperandSize)), XedMemBISD(XReg1, XReg2, 1, XedDisp(0, 0), OpSizeBits));
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else
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XedInst2(&InstList[3], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedMemBISD(XReg1, XReg2, 1, XedDisp(0, 0), OpSizeBits), XedReg(VmIRegToXReg(IReg, OperandSize)));
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return XedEncodeInstructions(InstList, 4, OutSize);
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}
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PUCHAR VmHandlerIRegMem_BIS(VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize, BOOL Load, PUINT OutSize, XED_REG_ENUM XReg1, XED_REG_ENUM XReg2, XED_REG_ENUM XReg3)
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{
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/*
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* movzx r8,byte ptr[rdx+2]
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* mov r8, qword ptr[rbp+r8*8]
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* movzx r9, byte ptr[rdx+3]
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* movzx r10, byte ptr[rdx+4] ;load scale value(unsigned)
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* imul r10, qword ptr[rbp+r9*8]
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* mov (ireg), (size) ptr[r8+r10]
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*/
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UINT OpSizeBits = VmOpSizeToBits(OperandSize);
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XED_ENCODER_INSTRUCTION InstList[6];
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_MOVZX, 64, XedReg(XReg1), XedMemBD(XED_REG_RDX, XedDisp(2, 8), 8));
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOV, 64, XedReg(XReg1), XedMemBISD(XED_REG_RBP, XReg1, 8, XedDisp(0, 0), 64));
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XedInst2(&InstList[2], XedGlobalMachineState, XED_ICLASS_MOVSX, 64, XedReg(XReg2), XedMemBD(XED_REG_RDX, XedDisp(3, 8), 8));
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XedInst2(&InstList[3], XedGlobalMachineState, XED_ICLASS_MOVSX, 64, XedReg(XReg3), XedMemBD(XED_REG_RDX, XedDisp(4, 8), 8));
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XedInst2(&InstList[4], XedGlobalMachineState, XED_ICLASS_IMUL, 64, XedReg(XReg3), XedMemBISD(XED_REG_RBP, XReg2, 8, XedDisp(0, 0), 64));
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if (Load)
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XedInst2(&InstList[5], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedReg(VmIRegToXReg(IReg, OperandSize)), XedMemBISD(XReg1, XReg3, 1, XedDisp(0, 0), OpSizeBits));
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else
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XedInst2(&InstList[5], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedMemBISD(XReg1, XReg3, 1, XedDisp(0, 0), OpSizeBits), XedReg(VmIRegToXReg(IReg, OperandSize)));
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return XedEncodeInstructions(InstList, 6, OutSize);
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}
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PUCHAR VmHandlerIRegMem_BISD(VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize, BOOL Load, PUINT OutSize, XED_REG_ENUM XReg1, XED_REG_ENUM XReg2, XED_REG_ENUM XReg3)
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{
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/*
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* movzx r8, byte ptr[rdx+2]
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* mov r8, qword ptr[rbp+r8*8]
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* movzx r9, byte ptr[rdx+3]
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* movzx r10, byte ptr[rdx+4] ;load scale value(unsigned)
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* imul r10, qword ptr[rbp+r9*8]
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* movsxd r9, dword ptr[rdx+5] ;load immediate displacement
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* add r10, r9 ;add immediate displacement
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* mov (ireg), (size) ptr[r8+r10]
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*/
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UINT OpSizeBits = VmOpSizeToBits(OperandSize);
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XED_ENCODER_INSTRUCTION InstList[8];
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_MOVZX, 64, XedReg(XReg1), XedMemBD(XED_REG_RDX, XedDisp(2, 8), 8));
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOV, 64, XedReg(XReg1), XedMemBISD(XED_REG_RBP, XReg1, 8, XedDisp(0, 0), 64));
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XedInst2(&InstList[2], XedGlobalMachineState, XED_ICLASS_MOVSX, 64, XedReg(XReg2), XedMemBD(XED_REG_RDX, XedDisp(3, 8), 8));
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XedInst2(&InstList[3], XedGlobalMachineState, XED_ICLASS_MOVSX, 64, XedReg(XReg3), XedMemBD(XED_REG_RDX, XedDisp(4, 8), 8));
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XedInst2(&InstList[4], XedGlobalMachineState, XED_ICLASS_IMUL, 64, XedReg(XReg3), XedMemBISD(XED_REG_RBP, XReg2, 8, XedDisp(0, 0), 64));
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XedInst2(&InstList[5], XedGlobalMachineState, XED_ICLASS_MOVSXD, 64, XedReg(XReg2), XedMemBD(XED_REG_RDX, XedDisp(5, 8), 32));
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XedInst2(&InstList[6], XedGlobalMachineState, XED_ICLASS_ADD, 64, XedReg(XReg3), XedReg(XReg2));
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if (Load)
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XedInst2(&InstList[7], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedReg(VmIRegToXReg(IReg, OperandSize)), XedMemBISD(XReg1, XReg3, 1, XedDisp(0, 0), OpSizeBits));
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else
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XedInst2(&InstList[7], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedMemBISD(XReg1, XReg3, 1, XedDisp(0, 0), OpSizeBits), XedReg(VmIRegToXReg(IReg, OperandSize)));
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return XedEncodeInstructions(InstList, 8, OutSize);
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}
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PUCHAR VmHandlerIRegMem(VM_MEMOP_TYPE_ENUM MemOpType, VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize, BOOL Load, PUINT OutSize, XED_REG_ENUM XReg1, XED_REG_ENUM XReg2, XED_REG_ENUM XReg3)
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{
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switch (MemOpType)
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{
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case VM_MEMOP_B: return VmHandlerIRegMem_B(IReg, OperandSize, Load, OutSize, XReg1);
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case VM_MEMOP_BD: return VmHandlerIRegMem_BD(IReg, OperandSize, Load, OutSize, XReg1, XReg2);
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case VM_MEMOP_BIS: return VmHandlerIRegMem_BIS(IReg, OperandSize, Load, OutSize, XReg1, XReg2, XReg3);
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case VM_MEMOP_BISD: return VmHandlerIRegMem_BISD(IReg, OperandSize, Load, OutSize, XReg1, XReg2, XReg3);
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}
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return NULL;
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}
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PUCHAR VmHandlerIRegReg(VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize, BOOL Load, PUINT OutSize, XED_REG_ENUM XReg1)
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{
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/*
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* movzx r8,byte ptr[rdx+2]
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* mov (ireg), (size) ptr[rbp+r8*8]
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*/
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UINT OpSizeBits = VmOpSizeToBits(OperandSize);
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XED_ENCODER_INSTRUCTION InstList[2];
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_MOVZX, 64, XedReg(XReg1), XedMemBD(XED_REG_RDX, XedDisp(2, 8), 8));
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if (Load)
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedReg(VmIRegToXReg(IReg, OperandSize)), XedMemBISD(XED_REG_RBP, XReg1, 8, XedDisp(0, 0), OpSizeBits));
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else
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XedInst2(&InstList[1], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedMemBISD(XED_REG_RBP, XReg1, 8, XedDisp(0, 0), OpSizeBits), XedReg(VmIRegToXReg(IReg, OperandSize)));
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return XedEncodeInstructions(InstList, 2, OutSize);
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}
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PUCHAR VmHandlerIRegImm(VM_IREG_ENUM IReg, VM_OPERAND_SIZE_ENUM OperandSize, PUINT OutSize)
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{
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/*
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* mov (ireg), size ptr[rdx+2]
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*/
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UINT OpSizeBits = VmOpSizeToBits(OperandSize);
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XED_ENCODER_INSTRUCTION InstList[1];
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XedInst2(&InstList[0], XedGlobalMachineState, XED_ICLASS_MOV, OpSizeBits, XedReg(VmIRegToXReg(IReg, OperandSize)), XedMemBD(XED_REG_RDX, XedDisp(2, 8), OpSizeBits));
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return XedEncodeInstructions(InstList, 1, OutSize);
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}
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PUCHAR VmHandlerEncode0(XED_ICLASS_ENUM IClass, VM_OPERAND_SIZE_ENUM OperandSize, PUINT OutSize)
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{
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XED_ENCODER_INSTRUCTION InstList[3];
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XedInst0(&InstList[0], XedGlobalMachineState, XED_ICLASS_POPFQ, 64);
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XedInst0(&InstList[1], XedGlobalMachineState, IClass, VmOpSizeToBits(OperandSize));
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XedInst0(&InstList[2], XedGlobalMachineState, XED_ICLASS_PUSHFQ, 64);
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return XedEncodeInstructions(InstList, 3, OutSize);
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}
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PUCHAR VmHandlerEncode1(XED_ICLASS_ENUM IClass, VM_OPERAND_SIZE_ENUM OperandSize, PUINT OutSize)
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{
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XED_ENCODER_INSTRUCTION InstList[3];
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XedInst0(&InstList[0], XedGlobalMachineState, XED_ICLASS_POPFQ, 64);
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XedInst1(&InstList[1], XedGlobalMachineState, IClass, VmOpSizeToBits(OperandSize), XedReg(VmIRegToXReg(VM_IREG_1, OperandSize)));
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XedInst0(&InstList[2], XedGlobalMachineState, XED_ICLASS_PUSHFQ, 64);
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return XedEncodeInstructions(InstList, 3, OutSize);
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}
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PUCHAR VmHandlerEncode2(XED_ICLASS_ENUM IClass, VM_OPERAND_SIZE_ENUM OperandSize1, VM_OPERAND_SIZE_ENUM OperandSize2, PUINT OutSize)
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{
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XED_ENCODER_INSTRUCTION InstList[3];
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XedInst0(&InstList[0], XedGlobalMachineState, XED_ICLASS_POPFQ, 64);
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XedInst2(&InstList[1], XedGlobalMachineState, IClass, VmOpSizeToBits(OperandSize1), XedReg(VmIRegToXReg(VM_IREG_1, OperandSize1)), XedReg(VmIRegToXReg(VM_IREG_2, OperandSize2)));
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XedInst0(&InstList[2], XedGlobalMachineState, XED_ICLASS_PUSHFQ, 64);
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return XedEncodeInstructions(InstList, 3, OutSize);
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}
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PUCHAR VmHandlerEncode3(XED_ICLASS_ENUM IClass, VM_OPERAND_SIZE_ENUM OperandSize1, VM_OPERAND_SIZE_ENUM OperandSize2, VM_OPERAND_SIZE_ENUM OperandSize3, PUINT OutSize)
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{
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XED_ENCODER_INSTRUCTION InstList[3];
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XedInst0(&InstList[0], XedGlobalMachineState, XED_ICLASS_POPFQ, 64);
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XedInst3(&InstList[1], XedGlobalMachineState, IClass, VmOpSizeToBits(OperandSize1), XedReg(VmIRegToXReg(VM_IREG_1, OperandSize1)), XedReg(VmIRegToXReg(VM_IREG_2, OperandSize2)), XedReg(VmIRegToXReg(VM_IREG_3, OperandSize3)));
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XedInst0(&InstList[2], XedGlobalMachineState, XED_ICLASS_PUSHFQ, 64);
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return XedEncodeInstructions(InstList, 3, OutSize);
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} |