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145 lines
4.5 KiB
145 lines
4.5 KiB
/// @file xed-classifiers.c
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// This file was automatically generated.
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// Do not edit this file.
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/*BEGIN_LEGAL
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Copyright (c) 2021 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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END_LEGAL */
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#include "xed-internal-header.h"
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xed_bool_t xed_classify_avx512(const xed_decoded_inst_t* d)
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{
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const xed_isa_set_enum_t isa_set = xed_decoded_inst_get_isa_set(d);
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switch(isa_set) {
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case XED_ISA_SET_AVX512BW_128:
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case XED_ISA_SET_AVX512BW_128N:
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case XED_ISA_SET_AVX512BW_256:
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case XED_ISA_SET_AVX512BW_512:
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case XED_ISA_SET_AVX512BW_KOP:
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case XED_ISA_SET_AVX512CD_128:
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case XED_ISA_SET_AVX512CD_256:
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case XED_ISA_SET_AVX512CD_512:
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case XED_ISA_SET_AVX512DQ_128:
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case XED_ISA_SET_AVX512DQ_128N:
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case XED_ISA_SET_AVX512DQ_256:
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case XED_ISA_SET_AVX512DQ_512:
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case XED_ISA_SET_AVX512DQ_KOP:
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case XED_ISA_SET_AVX512DQ_SCALAR:
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case XED_ISA_SET_AVX512ER_512:
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case XED_ISA_SET_AVX512ER_SCALAR:
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case XED_ISA_SET_AVX512F_128:
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case XED_ISA_SET_AVX512F_128N:
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case XED_ISA_SET_AVX512F_256:
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case XED_ISA_SET_AVX512F_512:
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case XED_ISA_SET_AVX512F_KOP:
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case XED_ISA_SET_AVX512F_SCALAR:
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case XED_ISA_SET_AVX512PF_512:
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case XED_ISA_SET_AVX512_4FMAPS_512:
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case XED_ISA_SET_AVX512_4FMAPS_SCALAR:
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case XED_ISA_SET_AVX512_4VNNIW_512:
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case XED_ISA_SET_AVX512_BF16_128:
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case XED_ISA_SET_AVX512_BF16_256:
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case XED_ISA_SET_AVX512_BF16_512:
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case XED_ISA_SET_AVX512_BITALG_128:
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case XED_ISA_SET_AVX512_BITALG_256:
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case XED_ISA_SET_AVX512_BITALG_512:
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case XED_ISA_SET_AVX512_FP16_128:
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case XED_ISA_SET_AVX512_FP16_128N:
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case XED_ISA_SET_AVX512_FP16_256:
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case XED_ISA_SET_AVX512_FP16_512:
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case XED_ISA_SET_AVX512_FP16_SCALAR:
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case XED_ISA_SET_AVX512_GFNI_128:
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case XED_ISA_SET_AVX512_GFNI_256:
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case XED_ISA_SET_AVX512_GFNI_512:
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case XED_ISA_SET_AVX512_IFMA_128:
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case XED_ISA_SET_AVX512_IFMA_256:
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case XED_ISA_SET_AVX512_IFMA_512:
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case XED_ISA_SET_AVX512_VAES_128:
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case XED_ISA_SET_AVX512_VAES_256:
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case XED_ISA_SET_AVX512_VAES_512:
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case XED_ISA_SET_AVX512_VBMI2_128:
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case XED_ISA_SET_AVX512_VBMI2_256:
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case XED_ISA_SET_AVX512_VBMI2_512:
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case XED_ISA_SET_AVX512_VBMI_128:
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case XED_ISA_SET_AVX512_VBMI_256:
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case XED_ISA_SET_AVX512_VBMI_512:
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case XED_ISA_SET_AVX512_VNNI_128:
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case XED_ISA_SET_AVX512_VNNI_256:
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case XED_ISA_SET_AVX512_VNNI_512:
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case XED_ISA_SET_AVX512_VP2INTERSECT_128:
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case XED_ISA_SET_AVX512_VP2INTERSECT_256:
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case XED_ISA_SET_AVX512_VP2INTERSECT_512:
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case XED_ISA_SET_AVX512_VPCLMULQDQ_128:
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case XED_ISA_SET_AVX512_VPCLMULQDQ_256:
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case XED_ISA_SET_AVX512_VPCLMULQDQ_512:
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case XED_ISA_SET_AVX512_VPOPCNTDQ_128:
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case XED_ISA_SET_AVX512_VPOPCNTDQ_256:
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case XED_ISA_SET_AVX512_VPOPCNTDQ_512:
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return 1;
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default:
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return 0;
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}
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}
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xed_bool_t xed_classify_avx512_maskop(const xed_decoded_inst_t* d)
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{
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const xed_isa_set_enum_t isa_set = xed_decoded_inst_get_isa_set(d);
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switch(isa_set) {
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case XED_ISA_SET_AVX512BW_KOP:
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case XED_ISA_SET_AVX512DQ_KOP:
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case XED_ISA_SET_AVX512F_KOP:
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return 1;
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default:
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return 0;
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}
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}
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xed_bool_t xed_classify_avx(const xed_decoded_inst_t* d)
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{
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const xed_isa_set_enum_t isa_set = xed_decoded_inst_get_isa_set(d);
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switch(isa_set) {
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case XED_ISA_SET_AVX:
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case XED_ISA_SET_AVX2:
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case XED_ISA_SET_AVX2GATHER:
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case XED_ISA_SET_AVXAES:
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case XED_ISA_SET_AVX_GFNI:
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case XED_ISA_SET_AVX_VNNI:
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case XED_ISA_SET_F16C:
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case XED_ISA_SET_FMA:
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return 1;
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default:
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return 0;
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}
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}
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xed_bool_t xed_classify_sse(const xed_decoded_inst_t* d)
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{
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const xed_isa_set_enum_t isa_set = xed_decoded_inst_get_isa_set(d);
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switch(isa_set) {
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case XED_ISA_SET_AES:
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case XED_ISA_SET_PCLMULQDQ:
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case XED_ISA_SET_SSE:
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case XED_ISA_SET_SSE2:
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case XED_ISA_SET_SSE3:
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case XED_ISA_SET_SSE4:
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case XED_ISA_SET_SSE42:
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case XED_ISA_SET_SSE4A:
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case XED_ISA_SET_SSEMXCSR:
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case XED_ISA_SET_SSSE3:
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return 1;
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default:
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return 0;
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}
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}
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