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1515 lines
86 KiB
1515 lines
86 KiB
/// @file xed-init-reg-class.c
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// This file was automatically generated.
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// Do not edit this file.
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/*BEGIN_LEGAL
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Copyright (c) 2021 Intel Corporation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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END_LEGAL */
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#include "xed-internal-header.h"
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void xed_init_reg_mappings(void)
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{
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xed_reg_class_array[XED_REG_INVALID]= XED_REG_CLASS_INVALID;
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xed_reg_class_array[XED_REG_ERROR]= XED_REG_CLASS_INVALID;
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xed_reg_class_array[XED_REG_RAX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_EAX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_AX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_AH]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_AL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RCX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_ECX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_CX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_CH]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_CL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RDX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_EDX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_DX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_DH]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_DL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RBX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_EBX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_BX]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_BH]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_BL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RSP]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_ESP]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_SP]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_SPL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RBP]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_EBP]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_BP]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_BPL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RSI]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_ESI]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_SI]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_SIL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RDI]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_EDI]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_DI]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_DIL]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R8]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R8D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R8W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R8B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R9]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R9D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R9W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R9B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R10]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R10D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R10W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R10B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R11]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R11D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R11W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R11B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R12]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R12D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R12W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R12B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R13]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R13D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R13W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R13B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R14]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R14D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R14W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R14B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R15]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R15D]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R15W]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_R15B]= XED_REG_CLASS_GPR;
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xed_reg_class_array[XED_REG_RIP]= XED_REG_CLASS_IP;
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xed_reg_class_array[XED_REG_EIP]= XED_REG_CLASS_IP;
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xed_reg_class_array[XED_REG_IP]= XED_REG_CLASS_IP;
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xed_reg_class_array[XED_REG_FLAGS]= XED_REG_CLASS_FLAGS;
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xed_reg_class_array[XED_REG_EFLAGS]= XED_REG_CLASS_FLAGS;
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xed_reg_class_array[XED_REG_RFLAGS]= XED_REG_CLASS_FLAGS;
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xed_reg_class_array[XED_REG_ES]= XED_REG_CLASS_SR;
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xed_reg_class_array[XED_REG_CS]= XED_REG_CLASS_SR;
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xed_reg_class_array[XED_REG_SS]= XED_REG_CLASS_SR;
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xed_reg_class_array[XED_REG_DS]= XED_REG_CLASS_SR;
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xed_reg_class_array[XED_REG_FS]= XED_REG_CLASS_SR;
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xed_reg_class_array[XED_REG_GS]= XED_REG_CLASS_SR;
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xed_reg_class_array[XED_REG_MMX0]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_MMX1]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_MMX2]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_MMX3]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_MMX4]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_MMX5]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_MMX6]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_MMX7]= XED_REG_CLASS_MMX;
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xed_reg_class_array[XED_REG_ST0]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_ST1]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_ST2]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_ST3]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_ST4]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_ST5]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_ST6]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_ST7]= XED_REG_CLASS_X87;
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xed_reg_class_array[XED_REG_CR0]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR1]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR2]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR3]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR4]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR5]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR6]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR7]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR8]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR9]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR10]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR11]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR12]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR13]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR14]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_CR15]= XED_REG_CLASS_CR;
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xed_reg_class_array[XED_REG_DR0]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_DR1]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_DR2]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_DR3]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_DR4]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_DR5]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_DR6]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_DR7]= XED_REG_CLASS_DR;
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xed_reg_class_array[XED_REG_STACKPUSH]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_STACKPOP]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_GDTR]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_LDTR]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_IDTR]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_TR]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_TSC]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_TSCAUX]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_MSRS]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_X87CONTROL]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87STATUS]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87TAG]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87PUSH]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87POP]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87POP2]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87OPCODE]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87LASTCS]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87LASTIP]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87LASTDS]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_X87LASTDP]= XED_REG_CLASS_PSEUDOX87;
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xed_reg_class_array[XED_REG_XCR0]= XED_REG_CLASS_XCR;
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xed_reg_class_array[XED_REG_MXCSR]= XED_REG_CLASS_MXCSR;
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xed_reg_class_array[XED_REG_TMP0]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP1]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP2]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP3]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP4]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP5]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP6]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP7]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP8]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP9]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP10]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP11]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP12]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP13]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP14]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_TMP15]= XED_REG_CLASS_TMP;
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xed_reg_class_array[XED_REG_K0]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_K1]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_K2]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_K3]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_K4]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_K5]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_K6]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_K7]= XED_REG_CLASS_MASK;
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xed_reg_class_array[XED_REG_BND0]= XED_REG_CLASS_BOUND;
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xed_reg_class_array[XED_REG_BND1]= XED_REG_CLASS_BOUND;
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xed_reg_class_array[XED_REG_BND2]= XED_REG_CLASS_BOUND;
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xed_reg_class_array[XED_REG_BND3]= XED_REG_CLASS_BOUND;
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xed_reg_class_array[XED_REG_BNDCFGU]= XED_REG_CLASS_BNDCFG;
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xed_reg_class_array[XED_REG_BNDSTATUS]= XED_REG_CLASS_BNDSTAT;
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xed_reg_class_array[XED_REG_SSP]= XED_REG_CLASS_MSR;
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xed_reg_class_array[XED_REG_IA32_U_CET]= XED_REG_CLASS_MSR;
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xed_reg_class_array[XED_REG_FSBASE]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_GSBASE]= XED_REG_CLASS_PSEUDO;
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xed_reg_class_array[XED_REG_XMM0]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM1]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM2]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM3]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM4]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM5]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM6]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM7]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM8]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM9]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM10]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM11]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM12]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM13]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM14]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_XMM15]= XED_REG_CLASS_XMM;
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xed_reg_class_array[XED_REG_YMM0]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM1]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM2]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM3]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM4]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM5]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM6]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM7]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM8]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM9]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM10]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM11]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM12]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM13]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM14]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_YMM15]= XED_REG_CLASS_YMM;
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xed_reg_class_array[XED_REG_ZMM0]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM1]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM2]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM3]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM4]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM5]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM6]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM7]= XED_REG_CLASS_ZMM;
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xed_reg_class_array[XED_REG_ZMM8]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM9]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM10]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM11]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM12]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM13]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM14]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM15]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM16]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM17]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM18]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM19]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM20]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM21]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM22]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM23]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM24]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM25]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM26]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM27]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM28]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM29]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM30]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_ZMM31]= XED_REG_CLASS_ZMM;
|
|
xed_reg_class_array[XED_REG_XMM16]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM17]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM18]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM19]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM20]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM21]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM22]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM23]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM24]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM25]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM26]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM27]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM28]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM29]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM30]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_XMM31]= XED_REG_CLASS_XMM;
|
|
xed_reg_class_array[XED_REG_YMM16]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM17]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM18]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM19]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM20]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM21]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM22]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM23]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM24]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM25]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM26]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM27]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM28]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM29]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM30]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_YMM31]= XED_REG_CLASS_YMM;
|
|
xed_reg_class_array[XED_REG_UIF]= XED_REG_CLASS_UIF;
|
|
xed_reg_class_array[XED_REG_TMM0]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TMM1]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TMM2]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TMM3]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TMM4]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TMM5]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TMM6]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TMM7]= XED_REG_CLASS_TREG;
|
|
xed_reg_class_array[XED_REG_TILECONFIG]= XED_REG_CLASS_PSEUDO;
|
|
xed_largest_enclosing_register_array[XED_REG_INVALID]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array_32[XED_REG_INVALID]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ERROR]= XED_REG_ERROR;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ERROR]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_RAX]= XED_REG_RAX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RAX]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_EAX]= XED_REG_RAX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_EAX]= XED_REG_EAX;
|
|
xed_largest_enclosing_register_array[XED_REG_AX]= XED_REG_RAX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_AX]= XED_REG_EAX;
|
|
xed_largest_enclosing_register_array[XED_REG_AH]= XED_REG_RAX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_AH]= XED_REG_EAX;
|
|
xed_largest_enclosing_register_array[XED_REG_AL]= XED_REG_RAX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_AL]= XED_REG_EAX;
|
|
xed_largest_enclosing_register_array[XED_REG_RCX]= XED_REG_RCX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RCX]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ECX]= XED_REG_RCX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ECX]= XED_REG_ECX;
|
|
xed_largest_enclosing_register_array[XED_REG_CX]= XED_REG_RCX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CX]= XED_REG_ECX;
|
|
xed_largest_enclosing_register_array[XED_REG_CH]= XED_REG_RCX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CH]= XED_REG_ECX;
|
|
xed_largest_enclosing_register_array[XED_REG_CL]= XED_REG_RCX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CL]= XED_REG_ECX;
|
|
xed_largest_enclosing_register_array[XED_REG_RDX]= XED_REG_RDX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RDX]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_EDX]= XED_REG_RDX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_EDX]= XED_REG_EDX;
|
|
xed_largest_enclosing_register_array[XED_REG_DX]= XED_REG_RDX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DX]= XED_REG_EDX;
|
|
xed_largest_enclosing_register_array[XED_REG_DH]= XED_REG_RDX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DH]= XED_REG_EDX;
|
|
xed_largest_enclosing_register_array[XED_REG_DL]= XED_REG_RDX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DL]= XED_REG_EDX;
|
|
xed_largest_enclosing_register_array[XED_REG_RBX]= XED_REG_RBX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RBX]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_EBX]= XED_REG_RBX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_EBX]= XED_REG_EBX;
|
|
xed_largest_enclosing_register_array[XED_REG_BX]= XED_REG_RBX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BX]= XED_REG_EBX;
|
|
xed_largest_enclosing_register_array[XED_REG_BH]= XED_REG_RBX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BH]= XED_REG_EBX;
|
|
xed_largest_enclosing_register_array[XED_REG_BL]= XED_REG_RBX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BL]= XED_REG_EBX;
|
|
xed_largest_enclosing_register_array[XED_REG_RSP]= XED_REG_RSP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RSP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ESP]= XED_REG_RSP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ESP]= XED_REG_ESP;
|
|
xed_largest_enclosing_register_array[XED_REG_SP]= XED_REG_RSP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_SP]= XED_REG_ESP;
|
|
xed_largest_enclosing_register_array[XED_REG_SPL]= XED_REG_RSP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_SPL]= XED_REG_ESP;
|
|
xed_largest_enclosing_register_array[XED_REG_RBP]= XED_REG_RBP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RBP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_EBP]= XED_REG_RBP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_EBP]= XED_REG_EBP;
|
|
xed_largest_enclosing_register_array[XED_REG_BP]= XED_REG_RBP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BP]= XED_REG_EBP;
|
|
xed_largest_enclosing_register_array[XED_REG_BPL]= XED_REG_RBP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BPL]= XED_REG_EBP;
|
|
xed_largest_enclosing_register_array[XED_REG_RSI]= XED_REG_RSI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RSI]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ESI]= XED_REG_RSI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ESI]= XED_REG_ESI;
|
|
xed_largest_enclosing_register_array[XED_REG_SI]= XED_REG_RSI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_SI]= XED_REG_ESI;
|
|
xed_largest_enclosing_register_array[XED_REG_SIL]= XED_REG_RSI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_SIL]= XED_REG_ESI;
|
|
xed_largest_enclosing_register_array[XED_REG_RDI]= XED_REG_RDI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RDI]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_EDI]= XED_REG_RDI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_EDI]= XED_REG_EDI;
|
|
xed_largest_enclosing_register_array[XED_REG_DI]= XED_REG_RDI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DI]= XED_REG_EDI;
|
|
xed_largest_enclosing_register_array[XED_REG_DIL]= XED_REG_RDI;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DIL]= XED_REG_EDI;
|
|
xed_largest_enclosing_register_array[XED_REG_R8]= XED_REG_R8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R8]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R8D]= XED_REG_R8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R8D]= XED_REG_R8D;
|
|
xed_largest_enclosing_register_array[XED_REG_R8W]= XED_REG_R8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R8W]= XED_REG_R8D;
|
|
xed_largest_enclosing_register_array[XED_REG_R8B]= XED_REG_R8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R8B]= XED_REG_R8D;
|
|
xed_largest_enclosing_register_array[XED_REG_R9]= XED_REG_R9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R9]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R9D]= XED_REG_R9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R9D]= XED_REG_R9D;
|
|
xed_largest_enclosing_register_array[XED_REG_R9W]= XED_REG_R9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R9W]= XED_REG_R9D;
|
|
xed_largest_enclosing_register_array[XED_REG_R9B]= XED_REG_R9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R9B]= XED_REG_R9D;
|
|
xed_largest_enclosing_register_array[XED_REG_R10]= XED_REG_R10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R10]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R10D]= XED_REG_R10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R10D]= XED_REG_R10D;
|
|
xed_largest_enclosing_register_array[XED_REG_R10W]= XED_REG_R10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R10W]= XED_REG_R10D;
|
|
xed_largest_enclosing_register_array[XED_REG_R10B]= XED_REG_R10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R10B]= XED_REG_R10D;
|
|
xed_largest_enclosing_register_array[XED_REG_R11]= XED_REG_R11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R11]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R11D]= XED_REG_R11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R11D]= XED_REG_R11D;
|
|
xed_largest_enclosing_register_array[XED_REG_R11W]= XED_REG_R11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R11W]= XED_REG_R11D;
|
|
xed_largest_enclosing_register_array[XED_REG_R11B]= XED_REG_R11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R11B]= XED_REG_R11D;
|
|
xed_largest_enclosing_register_array[XED_REG_R12]= XED_REG_R12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R12]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R12D]= XED_REG_R12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R12D]= XED_REG_R12D;
|
|
xed_largest_enclosing_register_array[XED_REG_R12W]= XED_REG_R12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R12W]= XED_REG_R12D;
|
|
xed_largest_enclosing_register_array[XED_REG_R12B]= XED_REG_R12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R12B]= XED_REG_R12D;
|
|
xed_largest_enclosing_register_array[XED_REG_R13]= XED_REG_R13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R13]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R13D]= XED_REG_R13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R13D]= XED_REG_R13D;
|
|
xed_largest_enclosing_register_array[XED_REG_R13W]= XED_REG_R13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R13W]= XED_REG_R13D;
|
|
xed_largest_enclosing_register_array[XED_REG_R13B]= XED_REG_R13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R13B]= XED_REG_R13D;
|
|
xed_largest_enclosing_register_array[XED_REG_R14]= XED_REG_R14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R14]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R14D]= XED_REG_R14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R14D]= XED_REG_R14D;
|
|
xed_largest_enclosing_register_array[XED_REG_R14W]= XED_REG_R14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R14W]= XED_REG_R14D;
|
|
xed_largest_enclosing_register_array[XED_REG_R14B]= XED_REG_R14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R14B]= XED_REG_R14D;
|
|
xed_largest_enclosing_register_array[XED_REG_R15]= XED_REG_R15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R15]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_R15D]= XED_REG_R15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R15D]= XED_REG_R15D;
|
|
xed_largest_enclosing_register_array[XED_REG_R15W]= XED_REG_R15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R15W]= XED_REG_R15D;
|
|
xed_largest_enclosing_register_array[XED_REG_R15B]= XED_REG_R15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_R15B]= XED_REG_R15D;
|
|
xed_largest_enclosing_register_array[XED_REG_RIP]= XED_REG_RIP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RIP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_EIP]= XED_REG_RIP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_EIP]= XED_REG_EIP;
|
|
xed_largest_enclosing_register_array[XED_REG_IP]= XED_REG_RIP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_IP]= XED_REG_EIP;
|
|
xed_largest_enclosing_register_array[XED_REG_FLAGS]= XED_REG_RFLAGS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_FLAGS]= XED_REG_EFLAGS;
|
|
xed_largest_enclosing_register_array[XED_REG_EFLAGS]= XED_REG_RFLAGS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_EFLAGS]= XED_REG_EFLAGS;
|
|
xed_largest_enclosing_register_array[XED_REG_RFLAGS]= XED_REG_RFLAGS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_RFLAGS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ES]= XED_REG_ES;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ES]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CS]= XED_REG_CS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_SS]= XED_REG_SS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_SS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DS]= XED_REG_DS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_FS]= XED_REG_FS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_FS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_GS]= XED_REG_GS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_GS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX0]= XED_REG_MMX0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX1]= XED_REG_MMX1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX2]= XED_REG_MMX2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX3]= XED_REG_MMX3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX4]= XED_REG_MMX4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX5]= XED_REG_MMX5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX6]= XED_REG_MMX6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MMX7]= XED_REG_MMX7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MMX7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST0]= XED_REG_ST0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST1]= XED_REG_ST1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST2]= XED_REG_ST2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST3]= XED_REG_ST3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST4]= XED_REG_ST4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST5]= XED_REG_ST5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST6]= XED_REG_ST6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ST7]= XED_REG_ST7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ST7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR0]= XED_REG_CR0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR1]= XED_REG_CR1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR2]= XED_REG_CR2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR3]= XED_REG_CR3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR4]= XED_REG_CR4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR5]= XED_REG_CR5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR6]= XED_REG_CR6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR7]= XED_REG_CR7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR8]= XED_REG_CR8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR8]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR9]= XED_REG_CR9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR9]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR10]= XED_REG_CR10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR10]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR11]= XED_REG_CR11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR11]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR12]= XED_REG_CR12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR12]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR13]= XED_REG_CR13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR13]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR14]= XED_REG_CR14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR14]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_CR15]= XED_REG_CR15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_CR15]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR0]= XED_REG_DR0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR1]= XED_REG_DR1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR2]= XED_REG_DR2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR3]= XED_REG_DR3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR4]= XED_REG_DR4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR5]= XED_REG_DR5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR6]= XED_REG_DR6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_DR7]= XED_REG_DR7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_DR7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_STACKPUSH]= XED_REG_STACKPUSH;
|
|
xed_largest_enclosing_register_array_32[XED_REG_STACKPUSH]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_STACKPOP]= XED_REG_STACKPOP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_STACKPOP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_GDTR]= XED_REG_GDTR;
|
|
xed_largest_enclosing_register_array_32[XED_REG_GDTR]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_LDTR]= XED_REG_LDTR;
|
|
xed_largest_enclosing_register_array_32[XED_REG_LDTR]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_IDTR]= XED_REG_IDTR;
|
|
xed_largest_enclosing_register_array_32[XED_REG_IDTR]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TR]= XED_REG_TR;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TR]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TSC]= XED_REG_TSC;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TSC]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TSCAUX]= XED_REG_TSCAUX;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TSCAUX]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MSRS]= XED_REG_MSRS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MSRS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87CONTROL]= XED_REG_X87CONTROL;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87CONTROL]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87STATUS]= XED_REG_X87STATUS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87STATUS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87TAG]= XED_REG_X87TAG;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87TAG]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87PUSH]= XED_REG_X87PUSH;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87PUSH]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87POP]= XED_REG_X87POP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87POP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87POP2]= XED_REG_X87POP2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87POP2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87OPCODE]= XED_REG_X87OPCODE;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87OPCODE]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87LASTCS]= XED_REG_X87LASTCS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87LASTCS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87LASTIP]= XED_REG_X87LASTIP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87LASTIP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87LASTDS]= XED_REG_X87LASTDS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87LASTDS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_X87LASTDP]= XED_REG_X87LASTDP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_X87LASTDP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XCR0]= XED_REG_XCR0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XCR0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_MXCSR]= XED_REG_MXCSR;
|
|
xed_largest_enclosing_register_array_32[XED_REG_MXCSR]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP0]= XED_REG_TMP0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP1]= XED_REG_TMP1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP2]= XED_REG_TMP2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP3]= XED_REG_TMP3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP4]= XED_REG_TMP4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP5]= XED_REG_TMP5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP6]= XED_REG_TMP6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP7]= XED_REG_TMP7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP8]= XED_REG_TMP8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP8]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP9]= XED_REG_TMP9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP9]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP10]= XED_REG_TMP10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP10]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP11]= XED_REG_TMP11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP11]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP12]= XED_REG_TMP12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP12]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP13]= XED_REG_TMP13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP13]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP14]= XED_REG_TMP14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP14]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMP15]= XED_REG_TMP15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMP15]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K0]= XED_REG_K0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K1]= XED_REG_K1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K2]= XED_REG_K2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K3]= XED_REG_K3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K4]= XED_REG_K4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K5]= XED_REG_K5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K6]= XED_REG_K6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_K7]= XED_REG_K7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_K7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_BND0]= XED_REG_BND0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BND0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_BND1]= XED_REG_BND1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BND1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_BND2]= XED_REG_BND2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BND2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_BND3]= XED_REG_BND3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BND3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_BNDCFGU]= XED_REG_BNDCFGU;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BNDCFGU]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_BNDSTATUS]= XED_REG_BNDSTATUS;
|
|
xed_largest_enclosing_register_array_32[XED_REG_BNDSTATUS]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_SSP]= XED_REG_SSP;
|
|
xed_largest_enclosing_register_array_32[XED_REG_SSP]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_IA32_U_CET]= XED_REG_IA32_U_CET;
|
|
xed_largest_enclosing_register_array_32[XED_REG_IA32_U_CET]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_FSBASE]= XED_REG_FSBASE;
|
|
xed_largest_enclosing_register_array_32[XED_REG_FSBASE]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_GSBASE]= XED_REG_GSBASE;
|
|
xed_largest_enclosing_register_array_32[XED_REG_GSBASE]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM0]= XED_REG_ZMM0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM1]= XED_REG_ZMM1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM2]= XED_REG_ZMM2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM3]= XED_REG_ZMM3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM4]= XED_REG_ZMM4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM5]= XED_REG_ZMM5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM6]= XED_REG_ZMM6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM7]= XED_REG_ZMM7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM8]= XED_REG_ZMM8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM8]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM9]= XED_REG_ZMM9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM9]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM10]= XED_REG_ZMM10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM10]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM11]= XED_REG_ZMM11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM11]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM12]= XED_REG_ZMM12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM12]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM13]= XED_REG_ZMM13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM13]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM14]= XED_REG_ZMM14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM14]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM15]= XED_REG_ZMM15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM15]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM0]= XED_REG_ZMM0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM1]= XED_REG_ZMM1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM2]= XED_REG_ZMM2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM3]= XED_REG_ZMM3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM4]= XED_REG_ZMM4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM5]= XED_REG_ZMM5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM6]= XED_REG_ZMM6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM7]= XED_REG_ZMM7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM8]= XED_REG_ZMM8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM8]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM9]= XED_REG_ZMM9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM9]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM10]= XED_REG_ZMM10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM10]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM11]= XED_REG_ZMM11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM11]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM12]= XED_REG_ZMM12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM12]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM13]= XED_REG_ZMM13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM13]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM14]= XED_REG_ZMM14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM14]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM15]= XED_REG_ZMM15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM15]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM0]= XED_REG_ZMM0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM1]= XED_REG_ZMM1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM2]= XED_REG_ZMM2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM3]= XED_REG_ZMM3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM4]= XED_REG_ZMM4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM5]= XED_REG_ZMM5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM6]= XED_REG_ZMM6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM7]= XED_REG_ZMM7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM8]= XED_REG_ZMM8;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM8]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM9]= XED_REG_ZMM9;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM9]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM10]= XED_REG_ZMM10;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM10]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM11]= XED_REG_ZMM11;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM11]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM12]= XED_REG_ZMM12;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM12]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM13]= XED_REG_ZMM13;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM13]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM14]= XED_REG_ZMM14;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM14]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM15]= XED_REG_ZMM15;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM15]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM16]= XED_REG_ZMM16;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM16]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM17]= XED_REG_ZMM17;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM17]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM18]= XED_REG_ZMM18;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM18]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM19]= XED_REG_ZMM19;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM19]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM20]= XED_REG_ZMM20;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM20]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM21]= XED_REG_ZMM21;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM21]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM22]= XED_REG_ZMM22;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM22]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM23]= XED_REG_ZMM23;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM23]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM24]= XED_REG_ZMM24;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM24]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM25]= XED_REG_ZMM25;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM25]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM26]= XED_REG_ZMM26;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM26]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM27]= XED_REG_ZMM27;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM27]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM28]= XED_REG_ZMM28;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM28]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM29]= XED_REG_ZMM29;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM29]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM30]= XED_REG_ZMM30;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM30]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_ZMM31]= XED_REG_ZMM31;
|
|
xed_largest_enclosing_register_array_32[XED_REG_ZMM31]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM16]= XED_REG_ZMM16;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM16]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM17]= XED_REG_ZMM17;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM17]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM18]= XED_REG_ZMM18;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM18]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM19]= XED_REG_ZMM19;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM19]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM20]= XED_REG_ZMM20;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM20]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM21]= XED_REG_ZMM21;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM21]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM22]= XED_REG_ZMM22;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM22]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM23]= XED_REG_ZMM23;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM23]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM24]= XED_REG_ZMM24;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM24]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM25]= XED_REG_ZMM25;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM25]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM26]= XED_REG_ZMM26;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM26]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM27]= XED_REG_ZMM27;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM27]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM28]= XED_REG_ZMM28;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM28]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM29]= XED_REG_ZMM29;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM29]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM30]= XED_REG_ZMM30;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM30]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_XMM31]= XED_REG_ZMM31;
|
|
xed_largest_enclosing_register_array_32[XED_REG_XMM31]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM16]= XED_REG_ZMM16;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM16]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM17]= XED_REG_ZMM17;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM17]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM18]= XED_REG_ZMM18;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM18]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM19]= XED_REG_ZMM19;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM19]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM20]= XED_REG_ZMM20;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM20]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM21]= XED_REG_ZMM21;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM21]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM22]= XED_REG_ZMM22;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM22]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM23]= XED_REG_ZMM23;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM23]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM24]= XED_REG_ZMM24;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM24]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM25]= XED_REG_ZMM25;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM25]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM26]= XED_REG_ZMM26;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM26]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM27]= XED_REG_ZMM27;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM27]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM28]= XED_REG_ZMM28;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM28]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM29]= XED_REG_ZMM29;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM29]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM30]= XED_REG_ZMM30;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM30]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_YMM31]= XED_REG_ZMM31;
|
|
xed_largest_enclosing_register_array_32[XED_REG_YMM31]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_UIF]= XED_REG_UIF;
|
|
xed_largest_enclosing_register_array_32[XED_REG_UIF]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM0]= XED_REG_TMM0;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM0]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM1]= XED_REG_TMM1;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM1]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM2]= XED_REG_TMM2;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM2]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM3]= XED_REG_TMM3;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM3]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM4]= XED_REG_TMM4;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM4]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM5]= XED_REG_TMM5;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM5]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM6]= XED_REG_TMM6;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM6]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TMM7]= XED_REG_TMM7;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TMM7]= XED_REG_INVALID;
|
|
xed_largest_enclosing_register_array[XED_REG_TILECONFIG]= XED_REG_TILECONFIG;
|
|
xed_largest_enclosing_register_array_32[XED_REG_TILECONFIG]= XED_REG_INVALID;
|
|
xed_gpr_reg_class_array[XED_REG_RAX]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_EAX]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_AX]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_AH]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_AL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_RCX]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_ECX]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_CX]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_CH]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_CL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_RDX]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_EDX]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_DX]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_DH]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_DL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_RBX]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_EBX]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_BX]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_BH]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_BL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_RSP]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_ESP]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_SP]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_SPL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_RBP]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_EBP]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_BP]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_BPL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_RSI]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_ESI]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_SI]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_SIL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_RDI]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_EDI]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_DI]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_DIL]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R8]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R8D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R8W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R8B]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R9]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R9D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R9W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R9B]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R10]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R10D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R10W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R10B]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R11]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R11D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R11W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R11B]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R12]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R12D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R12W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R12B]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R13]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R13D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R13W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R13B]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R14]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R14D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R14W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R14B]= XED_REG_CLASS_GPR8;
|
|
xed_gpr_reg_class_array[XED_REG_R15]= XED_REG_CLASS_GPR64;
|
|
xed_gpr_reg_class_array[XED_REG_R15D]= XED_REG_CLASS_GPR32;
|
|
xed_gpr_reg_class_array[XED_REG_R15W]= XED_REG_CLASS_GPR16;
|
|
xed_gpr_reg_class_array[XED_REG_R15B]= XED_REG_CLASS_GPR8;
|
|
xed_reg_width_bits[XED_REG_INVALID][0] = 0;
|
|
xed_reg_width_bits[XED_REG_INVALID][1] = 0;
|
|
xed_reg_width_bits[XED_REG_ERROR][0] = 0;
|
|
xed_reg_width_bits[XED_REG_ERROR][1] = 0;
|
|
xed_reg_width_bits[XED_REG_RAX][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RAX][1] = 64;
|
|
xed_reg_width_bits[XED_REG_EAX][0] = 32;
|
|
xed_reg_width_bits[XED_REG_EAX][1] = 32;
|
|
xed_reg_width_bits[XED_REG_AX][0] = 16;
|
|
xed_reg_width_bits[XED_REG_AX][1] = 16;
|
|
xed_reg_width_bits[XED_REG_AH][0] = 8;
|
|
xed_reg_width_bits[XED_REG_AH][1] = 8;
|
|
xed_reg_width_bits[XED_REG_AL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_AL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RCX][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RCX][1] = 64;
|
|
xed_reg_width_bits[XED_REG_ECX][0] = 32;
|
|
xed_reg_width_bits[XED_REG_ECX][1] = 32;
|
|
xed_reg_width_bits[XED_REG_CX][0] = 16;
|
|
xed_reg_width_bits[XED_REG_CX][1] = 16;
|
|
xed_reg_width_bits[XED_REG_CH][0] = 8;
|
|
xed_reg_width_bits[XED_REG_CH][1] = 8;
|
|
xed_reg_width_bits[XED_REG_CL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_CL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RDX][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RDX][1] = 64;
|
|
xed_reg_width_bits[XED_REG_EDX][0] = 32;
|
|
xed_reg_width_bits[XED_REG_EDX][1] = 32;
|
|
xed_reg_width_bits[XED_REG_DX][0] = 16;
|
|
xed_reg_width_bits[XED_REG_DX][1] = 16;
|
|
xed_reg_width_bits[XED_REG_DH][0] = 8;
|
|
xed_reg_width_bits[XED_REG_DH][1] = 8;
|
|
xed_reg_width_bits[XED_REG_DL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_DL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RBX][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RBX][1] = 64;
|
|
xed_reg_width_bits[XED_REG_EBX][0] = 32;
|
|
xed_reg_width_bits[XED_REG_EBX][1] = 32;
|
|
xed_reg_width_bits[XED_REG_BX][0] = 16;
|
|
xed_reg_width_bits[XED_REG_BX][1] = 16;
|
|
xed_reg_width_bits[XED_REG_BH][0] = 8;
|
|
xed_reg_width_bits[XED_REG_BH][1] = 8;
|
|
xed_reg_width_bits[XED_REG_BL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_BL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RSP][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RSP][1] = 64;
|
|
xed_reg_width_bits[XED_REG_ESP][0] = 32;
|
|
xed_reg_width_bits[XED_REG_ESP][1] = 32;
|
|
xed_reg_width_bits[XED_REG_SP][0] = 16;
|
|
xed_reg_width_bits[XED_REG_SP][1] = 16;
|
|
xed_reg_width_bits[XED_REG_SPL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_SPL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RBP][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RBP][1] = 64;
|
|
xed_reg_width_bits[XED_REG_EBP][0] = 32;
|
|
xed_reg_width_bits[XED_REG_EBP][1] = 32;
|
|
xed_reg_width_bits[XED_REG_BP][0] = 16;
|
|
xed_reg_width_bits[XED_REG_BP][1] = 16;
|
|
xed_reg_width_bits[XED_REG_BPL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_BPL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RSI][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RSI][1] = 64;
|
|
xed_reg_width_bits[XED_REG_ESI][0] = 32;
|
|
xed_reg_width_bits[XED_REG_ESI][1] = 32;
|
|
xed_reg_width_bits[XED_REG_SI][0] = 16;
|
|
xed_reg_width_bits[XED_REG_SI][1] = 16;
|
|
xed_reg_width_bits[XED_REG_SIL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_SIL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RDI][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RDI][1] = 64;
|
|
xed_reg_width_bits[XED_REG_EDI][0] = 32;
|
|
xed_reg_width_bits[XED_REG_EDI][1] = 32;
|
|
xed_reg_width_bits[XED_REG_DI][0] = 16;
|
|
xed_reg_width_bits[XED_REG_DI][1] = 16;
|
|
xed_reg_width_bits[XED_REG_DIL][0] = 8;
|
|
xed_reg_width_bits[XED_REG_DIL][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R8][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R8][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R8D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R8D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R8W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R8W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R8B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R8B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R9][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R9][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R9D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R9D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R9W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R9W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R9B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R9B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R10][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R10][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R10D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R10D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R10W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R10W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R10B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R10B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R11][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R11][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R11D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R11D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R11W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R11W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R11B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R11B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R12][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R12][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R12D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R12D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R12W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R12W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R12B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R12B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R13][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R13][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R13D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R13D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R13W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R13W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R13B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R13B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R14][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R14][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R14D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R14D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R14W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R14W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R14B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R14B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_R15][0] = 64;
|
|
xed_reg_width_bits[XED_REG_R15][1] = 64;
|
|
xed_reg_width_bits[XED_REG_R15D][0] = 32;
|
|
xed_reg_width_bits[XED_REG_R15D][1] = 32;
|
|
xed_reg_width_bits[XED_REG_R15W][0] = 16;
|
|
xed_reg_width_bits[XED_REG_R15W][1] = 16;
|
|
xed_reg_width_bits[XED_REG_R15B][0] = 8;
|
|
xed_reg_width_bits[XED_REG_R15B][1] = 8;
|
|
xed_reg_width_bits[XED_REG_RIP][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RIP][1] = 64;
|
|
xed_reg_width_bits[XED_REG_EIP][0] = 32;
|
|
xed_reg_width_bits[XED_REG_EIP][1] = 32;
|
|
xed_reg_width_bits[XED_REG_IP][0] = 16;
|
|
xed_reg_width_bits[XED_REG_IP][1] = 16;
|
|
xed_reg_width_bits[XED_REG_FLAGS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_FLAGS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_EFLAGS][0] = 32;
|
|
xed_reg_width_bits[XED_REG_EFLAGS][1] = 32;
|
|
xed_reg_width_bits[XED_REG_RFLAGS][0] = 64;
|
|
xed_reg_width_bits[XED_REG_RFLAGS][1] = 64;
|
|
xed_reg_width_bits[XED_REG_ES][0] = 16;
|
|
xed_reg_width_bits[XED_REG_ES][1] = 16;
|
|
xed_reg_width_bits[XED_REG_CS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_CS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_SS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_SS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_DS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_DS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_FS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_FS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_GS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_GS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_MMX0][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX0][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX1][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX1][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX2][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX2][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX3][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX3][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX4][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX4][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX5][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX5][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX6][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX6][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX7][0] = 64;
|
|
xed_reg_width_bits[XED_REG_MMX7][1] = 64;
|
|
xed_reg_width_bits[XED_REG_ST0][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST0][1] = 80;
|
|
xed_reg_width_bits[XED_REG_ST1][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST1][1] = 80;
|
|
xed_reg_width_bits[XED_REG_ST2][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST2][1] = 80;
|
|
xed_reg_width_bits[XED_REG_ST3][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST3][1] = 80;
|
|
xed_reg_width_bits[XED_REG_ST4][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST4][1] = 80;
|
|
xed_reg_width_bits[XED_REG_ST5][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST5][1] = 80;
|
|
xed_reg_width_bits[XED_REG_ST6][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST6][1] = 80;
|
|
xed_reg_width_bits[XED_REG_ST7][0] = 80;
|
|
xed_reg_width_bits[XED_REG_ST7][1] = 80;
|
|
xed_reg_width_bits[XED_REG_CR0][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR0][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR1][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR1][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR2][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR2][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR3][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR3][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR4][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR4][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR5][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR5][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR6][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR6][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR7][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR7][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR8][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR8][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR9][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR9][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR10][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR10][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR11][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR11][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR12][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR12][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR13][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR13][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR14][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR14][1] = 64;
|
|
xed_reg_width_bits[XED_REG_CR15][0] = 32;
|
|
xed_reg_width_bits[XED_REG_CR15][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR0][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR0][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR1][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR1][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR2][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR2][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR3][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR3][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR4][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR4][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR5][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR5][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR6][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR6][1] = 64;
|
|
xed_reg_width_bits[XED_REG_DR7][0] = 32;
|
|
xed_reg_width_bits[XED_REG_DR7][1] = 64;
|
|
xed_reg_width_bits[XED_REG_STACKPUSH][0] = 0;
|
|
xed_reg_width_bits[XED_REG_STACKPUSH][1] = 0;
|
|
xed_reg_width_bits[XED_REG_STACKPOP][0] = 0;
|
|
xed_reg_width_bits[XED_REG_STACKPOP][1] = 0;
|
|
xed_reg_width_bits[XED_REG_GDTR][0] = 80;
|
|
xed_reg_width_bits[XED_REG_GDTR][1] = 80;
|
|
xed_reg_width_bits[XED_REG_LDTR][0] = 80;
|
|
xed_reg_width_bits[XED_REG_LDTR][1] = 80;
|
|
xed_reg_width_bits[XED_REG_IDTR][0] = 80;
|
|
xed_reg_width_bits[XED_REG_IDTR][1] = 80;
|
|
xed_reg_width_bits[XED_REG_TR][0] = 80;
|
|
xed_reg_width_bits[XED_REG_TR][1] = 80;
|
|
xed_reg_width_bits[XED_REG_TSC][0] = 32;
|
|
xed_reg_width_bits[XED_REG_TSC][1] = 32;
|
|
xed_reg_width_bits[XED_REG_TSCAUX][0] = 32;
|
|
xed_reg_width_bits[XED_REG_TSCAUX][1] = 32;
|
|
xed_reg_width_bits[XED_REG_MSRS][0] = 0;
|
|
xed_reg_width_bits[XED_REG_MSRS][1] = 0;
|
|
xed_reg_width_bits[XED_REG_X87CONTROL][0] = 16;
|
|
xed_reg_width_bits[XED_REG_X87CONTROL][1] = 16;
|
|
xed_reg_width_bits[XED_REG_X87STATUS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_X87STATUS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_X87TAG][0] = 16;
|
|
xed_reg_width_bits[XED_REG_X87TAG][1] = 16;
|
|
xed_reg_width_bits[XED_REG_X87PUSH][0] = 0;
|
|
xed_reg_width_bits[XED_REG_X87PUSH][1] = 0;
|
|
xed_reg_width_bits[XED_REG_X87POP][0] = 0;
|
|
xed_reg_width_bits[XED_REG_X87POP][1] = 0;
|
|
xed_reg_width_bits[XED_REG_X87POP2][0] = 0;
|
|
xed_reg_width_bits[XED_REG_X87POP2][1] = 0;
|
|
xed_reg_width_bits[XED_REG_X87OPCODE][0] = 11;
|
|
xed_reg_width_bits[XED_REG_X87OPCODE][1] = 11;
|
|
xed_reg_width_bits[XED_REG_X87LASTCS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_X87LASTCS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_X87LASTIP][0] = 32;
|
|
xed_reg_width_bits[XED_REG_X87LASTIP][1] = 64;
|
|
xed_reg_width_bits[XED_REG_X87LASTDS][0] = 16;
|
|
xed_reg_width_bits[XED_REG_X87LASTDS][1] = 16;
|
|
xed_reg_width_bits[XED_REG_X87LASTDP][0] = 32;
|
|
xed_reg_width_bits[XED_REG_X87LASTDP][1] = 64;
|
|
xed_reg_width_bits[XED_REG_XCR0][0] = 64;
|
|
xed_reg_width_bits[XED_REG_XCR0][1] = 64;
|
|
xed_reg_width_bits[XED_REG_MXCSR][0] = 32;
|
|
xed_reg_width_bits[XED_REG_MXCSR][1] = 32;
|
|
xed_reg_width_bits[XED_REG_TMP0][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP0][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP1][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP1][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP2][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP2][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP3][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP3][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP4][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP4][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP5][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP5][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP6][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP6][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP7][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP7][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP8][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP8][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP9][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP9][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP10][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP10][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP11][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP11][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP12][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP12][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP13][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP13][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP14][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP14][1] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP15][0] = 0;
|
|
xed_reg_width_bits[XED_REG_TMP15][1] = 0;
|
|
xed_reg_width_bits[XED_REG_K0][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K0][1] = 64;
|
|
xed_reg_width_bits[XED_REG_K1][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K1][1] = 64;
|
|
xed_reg_width_bits[XED_REG_K2][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K2][1] = 64;
|
|
xed_reg_width_bits[XED_REG_K3][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K3][1] = 64;
|
|
xed_reg_width_bits[XED_REG_K4][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K4][1] = 64;
|
|
xed_reg_width_bits[XED_REG_K5][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K5][1] = 64;
|
|
xed_reg_width_bits[XED_REG_K6][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K6][1] = 64;
|
|
xed_reg_width_bits[XED_REG_K7][0] = 64;
|
|
xed_reg_width_bits[XED_REG_K7][1] = 64;
|
|
xed_reg_width_bits[XED_REG_BND0][0] = 128;
|
|
xed_reg_width_bits[XED_REG_BND0][1] = 128;
|
|
xed_reg_width_bits[XED_REG_BND1][0] = 128;
|
|
xed_reg_width_bits[XED_REG_BND1][1] = 128;
|
|
xed_reg_width_bits[XED_REG_BND2][0] = 128;
|
|
xed_reg_width_bits[XED_REG_BND2][1] = 128;
|
|
xed_reg_width_bits[XED_REG_BND3][0] = 128;
|
|
xed_reg_width_bits[XED_REG_BND3][1] = 128;
|
|
xed_reg_width_bits[XED_REG_BNDCFGU][0] = 64;
|
|
xed_reg_width_bits[XED_REG_BNDCFGU][1] = 64;
|
|
xed_reg_width_bits[XED_REG_BNDSTATUS][0] = 64;
|
|
xed_reg_width_bits[XED_REG_BNDSTATUS][1] = 64;
|
|
xed_reg_width_bits[XED_REG_SSP][0] = 32;
|
|
xed_reg_width_bits[XED_REG_SSP][1] = 64;
|
|
xed_reg_width_bits[XED_REG_IA32_U_CET][0] = 0;
|
|
xed_reg_width_bits[XED_REG_IA32_U_CET][1] = 0;
|
|
xed_reg_width_bits[XED_REG_FSBASE][0] = 0;
|
|
xed_reg_width_bits[XED_REG_FSBASE][1] = 0;
|
|
xed_reg_width_bits[XED_REG_GSBASE][0] = 0;
|
|
xed_reg_width_bits[XED_REG_GSBASE][1] = 0;
|
|
xed_reg_width_bits[XED_REG_XMM0][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM0][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM1][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM1][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM2][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM2][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM3][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM3][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM4][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM4][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM5][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM5][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM6][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM6][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM7][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM7][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM8][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM8][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM9][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM9][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM10][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM10][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM11][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM11][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM12][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM12][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM13][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM13][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM14][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM14][1] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM15][0] = 128;
|
|
xed_reg_width_bits[XED_REG_XMM15][1] = 128;
|
|
xed_reg_width_bits[XED_REG_YMM0][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM0][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM1][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM1][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM2][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM2][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM3][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM3][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM4][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM4][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM5][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM5][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM6][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM6][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM7][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM7][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM8][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM8][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM9][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM9][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM10][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM10][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM11][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM11][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM12][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM12][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM13][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM13][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM14][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM14][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM15][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM15][1] = 256;
|
|
xed_reg_width_bits[XED_REG_ZMM0][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM0][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM1][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM1][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM2][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM2][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM3][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM3][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM4][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM4][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM5][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM5][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM6][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM6][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM7][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM7][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM8][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM8][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM9][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM9][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM10][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM10][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM11][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM11][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM12][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM12][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM13][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM13][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM14][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM14][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM15][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM15][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM16][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM16][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM17][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM17][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM18][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM18][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM19][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM19][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM20][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM20][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM21][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM21][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM22][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM22][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM23][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM23][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM24][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM24][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM25][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM25][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM26][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM26][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM27][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM27][1] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM28][0] = 512;
|
|
xed_reg_width_bits[XED_REG_ZMM28][1] = 512;
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xed_reg_width_bits[XED_REG_ZMM29][0] = 512;
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xed_reg_width_bits[XED_REG_ZMM29][1] = 512;
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xed_reg_width_bits[XED_REG_ZMM30][0] = 512;
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xed_reg_width_bits[XED_REG_ZMM30][1] = 512;
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xed_reg_width_bits[XED_REG_ZMM31][0] = 512;
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xed_reg_width_bits[XED_REG_ZMM31][1] = 512;
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xed_reg_width_bits[XED_REG_XMM16][0] = 128;
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xed_reg_width_bits[XED_REG_XMM16][1] = 128;
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xed_reg_width_bits[XED_REG_XMM17][0] = 128;
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xed_reg_width_bits[XED_REG_XMM17][1] = 128;
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xed_reg_width_bits[XED_REG_XMM18][0] = 128;
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xed_reg_width_bits[XED_REG_XMM18][1] = 128;
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xed_reg_width_bits[XED_REG_XMM19][0] = 128;
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xed_reg_width_bits[XED_REG_XMM19][1] = 128;
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xed_reg_width_bits[XED_REG_XMM20][0] = 128;
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xed_reg_width_bits[XED_REG_XMM20][1] = 128;
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xed_reg_width_bits[XED_REG_XMM21][0] = 128;
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xed_reg_width_bits[XED_REG_XMM21][1] = 128;
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xed_reg_width_bits[XED_REG_XMM22][0] = 128;
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xed_reg_width_bits[XED_REG_XMM22][1] = 128;
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xed_reg_width_bits[XED_REG_XMM23][0] = 128;
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xed_reg_width_bits[XED_REG_XMM23][1] = 128;
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xed_reg_width_bits[XED_REG_XMM24][0] = 128;
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xed_reg_width_bits[XED_REG_XMM24][1] = 128;
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xed_reg_width_bits[XED_REG_XMM25][0] = 128;
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xed_reg_width_bits[XED_REG_XMM25][1] = 128;
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xed_reg_width_bits[XED_REG_XMM26][0] = 128;
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xed_reg_width_bits[XED_REG_XMM26][1] = 128;
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xed_reg_width_bits[XED_REG_XMM27][0] = 128;
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xed_reg_width_bits[XED_REG_XMM27][1] = 128;
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xed_reg_width_bits[XED_REG_XMM28][0] = 128;
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xed_reg_width_bits[XED_REG_XMM28][1] = 128;
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xed_reg_width_bits[XED_REG_XMM29][0] = 128;
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xed_reg_width_bits[XED_REG_XMM29][1] = 128;
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xed_reg_width_bits[XED_REG_XMM30][0] = 128;
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xed_reg_width_bits[XED_REG_XMM30][1] = 128;
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xed_reg_width_bits[XED_REG_XMM31][0] = 128;
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xed_reg_width_bits[XED_REG_XMM31][1] = 128;
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xed_reg_width_bits[XED_REG_YMM16][0] = 256;
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xed_reg_width_bits[XED_REG_YMM16][1] = 256;
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xed_reg_width_bits[XED_REG_YMM17][0] = 256;
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xed_reg_width_bits[XED_REG_YMM17][1] = 256;
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xed_reg_width_bits[XED_REG_YMM18][0] = 256;
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xed_reg_width_bits[XED_REG_YMM18][1] = 256;
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xed_reg_width_bits[XED_REG_YMM19][0] = 256;
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xed_reg_width_bits[XED_REG_YMM19][1] = 256;
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xed_reg_width_bits[XED_REG_YMM20][0] = 256;
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xed_reg_width_bits[XED_REG_YMM20][1] = 256;
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xed_reg_width_bits[XED_REG_YMM21][0] = 256;
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xed_reg_width_bits[XED_REG_YMM21][1] = 256;
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xed_reg_width_bits[XED_REG_YMM22][0] = 256;
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xed_reg_width_bits[XED_REG_YMM22][1] = 256;
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xed_reg_width_bits[XED_REG_YMM23][0] = 256;
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xed_reg_width_bits[XED_REG_YMM23][1] = 256;
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|
xed_reg_width_bits[XED_REG_YMM24][0] = 256;
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xed_reg_width_bits[XED_REG_YMM24][1] = 256;
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xed_reg_width_bits[XED_REG_YMM25][0] = 256;
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|
xed_reg_width_bits[XED_REG_YMM25][1] = 256;
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|
xed_reg_width_bits[XED_REG_YMM26][0] = 256;
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|
xed_reg_width_bits[XED_REG_YMM26][1] = 256;
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|
xed_reg_width_bits[XED_REG_YMM27][0] = 256;
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|
xed_reg_width_bits[XED_REG_YMM27][1] = 256;
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|
xed_reg_width_bits[XED_REG_YMM28][0] = 256;
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|
xed_reg_width_bits[XED_REG_YMM28][1] = 256;
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|
xed_reg_width_bits[XED_REG_YMM29][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM29][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM30][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM30][1] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM31][0] = 256;
|
|
xed_reg_width_bits[XED_REG_YMM31][1] = 256;
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|
xed_reg_width_bits[XED_REG_UIF][0] = 1;
|
|
xed_reg_width_bits[XED_REG_UIF][1] = 1;
|
|
xed_reg_width_bits[XED_REG_TMM0][0] = 8192;
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|
xed_reg_width_bits[XED_REG_TMM0][1] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM1][0] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM1][1] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM2][0] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM2][1] = 8192;
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|
xed_reg_width_bits[XED_REG_TMM3][0] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM3][1] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM4][0] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM4][1] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM5][0] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM5][1] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM6][0] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM6][1] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM7][0] = 8192;
|
|
xed_reg_width_bits[XED_REG_TMM7][1] = 8192;
|
|
xed_reg_width_bits[XED_REG_TILECONFIG][0] = 512;
|
|
xed_reg_width_bits[XED_REG_TILECONFIG][1] = 512;
|
|
}
|