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818 lines
25 KiB
818 lines
25 KiB
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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# This file is for defining sets of extensions implemented by various chips
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#
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# The first column is a chip name. It will become the source for the enum xed_chip_t XED_CHIP_*
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# The rest of the columns are ISA extensions that that CHIP implements
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# ALL_OF(x) is a macro that refers to the set defined previously for some chip x.
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# NOT(y) is a macro that removes a specific ISA extension (processed last)
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I86: I86 LAHF
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I86FP: I86 LAHF X87
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I186: ALL_OF(I86) I186
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# BOUND, ENTER, INS/INSB/INSW, LEAVE, OUTS/OUTSB/OUTSW, POPA, PUSHA
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I186FP: ALL_OF(I186) X87
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I286REAL: ALL_OF(I186) I286REAL X87
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I286: ALL_OF(I286REAL) I286PROTECTED
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# ARPL, CLTS, LAR, LGDT, LIDT, LLDT, LMSW,
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# LOADALL(undoc), LSL, LTR, SGDT, SIDT,SLDT, SMSW, STR,VERR,VERW
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I2186FP: ALL_OF(I286) X87
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# 386 did not add any instr to real mode
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I386REAL: ALL_OF(I286REAL)
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I386: ALL_OF(I386REAL) ALL_OF(I286) I386
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# BSF, BSR, BT, BTC, BTR,BTS, CDQ, CMPSD,CWDE, INSD, IRET*, JECXZ,
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# LFS, LGS,LSS, LOADALL(undoc), LODSD, LOOP, MOVSD
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# MOVSX, OUTSD, POPAD POPFD, PUSHAD PUSHD PUSHFD, SCASD
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# SETcc* SHLD, SHRD, STOSD
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I386FP: ALL_OF(I386) X87
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I486REAL: ALL_OF(I386REAL) I486REAL # BSWAP, CMPXCHG, CPUID, INVD, INVLPG, RSM,WBINVD,XADD
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I486: ALL_OF(I486REAL) ALL_OF(I386) I486 X87 # RSM
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PENTIUMREAL: ALL_OF(I486REAL) PENTIUMREAL # CMPXCHG8B, RDMSR, RDTSC, WRMSR
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PENTIUM: ALL_OF(PENTIUMREAL) ALL_OF(I486)
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# Quark is PENTIUM ISA, but not Pentium implementation.
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QUARK: ALL_OF(PENTIUM)
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PENTIUMMMXREAL: ALL_OF(PENTIUMREAL) RDPMC # P55C++ RDPMC
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PENTIUMMMX: ALL_OF(PENTIUMMMXREAL) ALL_OF(PENTIUM) PENTIUMMMX # P55C++
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ALLREAL: ALL_OF(PENTIUMMMXREAL)
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# P6, PentiumPro, PPRO:
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# The SSE_PREFETCH were on P6 as fat NOPs, but XED only recognizes them on >=PENTIUM3
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PENTIUMPRO: ALL_OF(PENTIUM) PPRO PPRO_UD0_SHORT CMOV FCMOV RDPMC FAT_NOP PREFETCH_NOP # NO MMX (Orig P6)
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# FCMOV*, CMOV*, RDPMC, SYSCALL, SYSENTER, SYSEXIT,SYSRET, UD2, F[U]COMI[P]
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# note conflict with PENTIUM2 addition of SYSENTER/SYSEXIT
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PENTIUM2: ALL_OF(PENTIUM) PENTIUMMMX PPRO CMOV FCMOV FAT_NOP RDPMC PREFETCH_NOP FXSAVE
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# FXSAVE/FXRSTOR, SYSENTER,SYSEXIT P6
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# we keep SSEMXCSR separate from SSE to accommodate chip-check for KNC
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# which only implements LDMXCSR/STMXCSR from SSE.
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# The SSE_PREFETCH came in as NOPs on P6/PPRO. innaccuracy...
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PENTIUM3: ALL_OF(PENTIUM2) SSE SSEMXCSR SSE_PREFETCH # SSE(incl. ldmxcsr/stmxcsr) (KNI)
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# SSE2MMX is a several purely mmx instructions that came with SSE2 (PADDQ, PSUBQ, PMULUDQ).
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# They are really part of SSE2.
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PENTIUM4: ALL_OF(PENTIUM3) NOT(PPRO_UD0_SHORT) PPRO_UD0_LONG SSE2 SSE2MMX CLFSH PAUSE
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# MONITOR is (MONITOR and MWAIT) instructions
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# SSE3X87 is two x87 instructions that came with SSE3.
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P4PRESCOTT: ALL_OF(PENTIUM4) SSE3 SSE3X87 MONITOR LONGMODE CMPXCHG16B FXSAVE64
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# Made a chip for the P4's that omit LAHF in 64b mode
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P4PRESCOTT_NOLAHF: ALL_OF(P4PRESCOTT) NOT(LAHF)
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P4PRESCOTT_VTX: ALL_OF(P4PRESCOTT) VTX
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# SSSE3MMX is a a bunch of purely mmx instructions that came with SSSE3.
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# They are really part of SSSE3. The 3DNOW_PREFETCH instr were nops.
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# previously listed as CORE2
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MEROM: ALL_OF(P4PRESCOTT) VTX SSSE3 SSSE3MMX SMX 3DNOW_PREFETCH
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PENRYN: ALL_OF(MEROM) SSE4
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PENRYN_E: ALL_OF(PENRYN) XSAVE
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NEHALEM: ALL_OF(PENRYN) SSE42 POPCNT RDTSCP
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WESTMERE: ALL_OF(NEHALEM) AES PCLMULQDQ
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# ATOM
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BONNELL: ALL_OF(MEROM) MOVBE NOT(SMX) NOT(PPRO_UD0_LONG) PPRO_UD0_SHORT
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SALTWELL: ALL_OF(BONNELL)
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# PREFETCHW semantics added to PREFETCHW opcode but not subject
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# to chip-check because of prior implementation as NOP.
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SILVERMONT: ALL_OF(WESTMERE) MOVBE RDRAND PREFETCHW VMFUNC NOT(PPRO_UD0_LONG) PPRO_UD0_SHORT
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/via/xed-via-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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# VIA CENTAUR CHIPS???
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#VIA: ALL_OF(P4PRESCOTT) VIA_PADLOCK_RNG VIA_PADLOCK_AES VIA_PADLOCK_SHA
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VIA: VIA_PADLOCK_RNG VIA_PADLOCK_AES VIA_PADLOCK_SHA VIA_PADLOCK_MONTMUL
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2020 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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# This is based mostly on my read of the wikpedia page:
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# https://en.wikipedia.org/wiki/Template:AMD_x86_CPU_features
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# FIXME: need a proper baseline for AMD_K10 as a starting point. I
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# used WESTMERE to avoid TSX/RTM.
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# FIXME: not sure when LZCNT entered the picture
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# FIXME: guessing about F16C and RDWRFSGS
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AMD_K10: ALL_OF(WESTMERE) PREFETCHW 3DNOW 3DNOW_PREFETCH SSE4A AMD SVM PREFETCH_NOP LZCNT
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AMD_BULLDOZER: ALL_OF(AMD_K10) \
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NOT(3DNOW) \
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FMA4 LWP XOP \
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AVX AVXAES XSAVE XSAVEOPT F16C RDWRFSGS
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AMD_PILEDRIVER: ALL_OF(AMD_BULLDOZER) TBM FMA
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AMD_ZEN: ALL_OF(AMD_PILEDRIVER) \
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NOT(FMA4) \
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NOT(LWP) \
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NOT(XOP) \
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AVX2 AVX2GATHER \
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BMI2 MOVBE ADOX_ADCX SHA \
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RDRAND RDSEED \
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SMAP XSAVEC XSAVES CLFLUSHOPT CLZERO
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AMD_ZENPLUS: ALL_OF(AMD_ZEN)
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# Guessing about MONITORX
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AMD_ZEN2: ALL_OF(AMD_ZENPLUS) \
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WBNOINVD CLWB RDPID RDPRU MCOMMIT \
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MONITORX
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# Guessing
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AMD_FUTURE: ALL_OF(AMD_ZEN2) \
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SNP \
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AMD_INVLPGB
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/glm/glm-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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GOLDMONT: ALL_OF(SILVERMONT) MPX SHA RDSEED RDWRFSGS \
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XSAVE XSAVEOPT XSAVEC XSAVES SMAP \
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CLFLUSHOPT
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GOLDMONT_PLUS: ALL_OF(GOLDMONT) PTWRITE RDPID SGX
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# and UMIP but not instr for that
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/tremont/tremont-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2020 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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TREMONT: ALL_OF(GOLDMONT_PLUS) CLWB GFNI NOT(SGX)
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SNOW_RIDGE: ALL_OF(TREMONT) WAITPKG MOVDIR CLDEMOTE NOT(SGX)
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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SANDYBRIDGE: ALL_OF(WESTMERE) AVX AVXAES XSAVE XSAVEOPT
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/ivbavx/ivb-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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IVYBRIDGE: ALL_OF(SANDYBRIDGE) RDRAND F16C RDWRFSGS
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/hsw-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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HASWELL: ALL_OF(IVYBRIDGE) FMA BMI1 BMI2 LZCNT AVX2 AVX2GATHER INVPCID MOVBE VMFUNC RTM
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/bdw/bdw-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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# PREFETCHW semantics added to PREFETCHW opcode but not subject
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# to chip-check because of prior implementation as NOP
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BROADWELL: ALL_OF(HASWELL) ADOX_ADCX RDSEED SMAP PREFETCHW
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/skl/skl-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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SKYLAKE: ALL_OF(BROADWELL) MPX XSAVEC XSAVES SGX CLFLUSHOPT
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COMET_LAKE: ALL_OF(SKYLAKE) PKU
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/skx/skx-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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SKYLAKE_SERVER: ALL_OF(SKYLAKE) PKU \
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CLWB \
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AVX512F_512 \
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AVX512F_128 \
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AVX512F_128N \
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AVX512F_256 \
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AVX512F_KOP \
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AVX512F_SCALAR \
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AVX512BW_128 \
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AVX512BW_128N \
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AVX512BW_256 \
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AVX512BW_512 \
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AVX512BW_KOP \
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AVX512CD_128 \
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AVX512CD_256 \
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AVX512CD_512 \
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AVX512DQ_128 \
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AVX512DQ_128N \
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AVX512DQ_256 \
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AVX512DQ_512 \
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AVX512DQ_KOP \
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AVX512DQ_SCALAR
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/clx/clx-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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# Cascade Lake (CLX) based on Coffee Lake CPU.
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# Coffee Lake has same ISA as SKX.
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CASCADE_LAKE: ALL_OF(SKYLAKE_SERVER) \
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AVX512_VNNI_128 \
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AVX512_VNNI_256 \
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AVX512_VNNI_512
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/cpx/cooper-lake-chips.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
|
|
COOPER_LAKE: ALL_OF(CASCADE_LAKE) \
|
|
AVX512_BF16_128 \
|
|
AVX512_BF16_256 \
|
|
AVX512_BF16_512
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
# No HSW INVPCID, RTM, VMFUNC
|
|
# No BDW SMAP
|
|
KNL: ALL_OF(IVYBRIDGE) \
|
|
AVX512F_SCALAR \
|
|
AVX512F_KOP \
|
|
AVX512F_512 \
|
|
AVX512F_128N \
|
|
AVX512CD_512 \
|
|
AVX512ER_512 \
|
|
AVX512ER_SCALAR \
|
|
AVX512PF_512 \
|
|
PREFETCHWT1 \
|
|
ADOX_ADCX RDSEED FMA BMI1 BMI2 LZCNT AVX2 AVX2GATHER MOVBE
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/knm/knm-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
# VMFUNC was partially implmented on KNL but VMX was disabled.
|
|
KNM: ALL_OF(KNL) VMFUNC \
|
|
AVX512_4VNNIW_512 \
|
|
AVX512_4FMAPS_512 \
|
|
AVX512_4FMAPS_SCALAR \
|
|
AVX512_VPOPCNTDQ_512
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/cnl/cnl-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
# CANNONLAKE does not have CLWB
|
|
CANNONLAKE: ALL_OF(SKYLAKE_SERVER) SHA \
|
|
NOT(CLWB) \
|
|
AVX512_IFMA_128 \
|
|
AVX512_IFMA_256 \
|
|
AVX512_IFMA_512 \
|
|
AVX512_VBMI_128 \
|
|
AVX512_VBMI_256 \
|
|
AVX512_VBMI_512
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/icl/icl-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
# NOT(HLE) but no HLE instr support.
|
|
ICE_LAKE: \
|
|
ALL_OF(SKYLAKE_SERVER) \
|
|
NOT(CLWB) \
|
|
NOT(MPX) \
|
|
RDPID \
|
|
SHA \
|
|
AVX512_IFMA_128 \
|
|
AVX512_IFMA_256 \
|
|
AVX512_IFMA_512 \
|
|
AVX512_VBMI_128 \
|
|
AVX512_VBMI_256 \
|
|
AVX512_VBMI_512 \
|
|
AVX512_VBMI2_128 \
|
|
AVX512_VBMI2_256 \
|
|
AVX512_VBMI2_512 \
|
|
AVX512_BITALG_512 \
|
|
AVX512_BITALG_256 \
|
|
AVX512_BITALG_128 \
|
|
AVX512_VPOPCNTDQ_128 \
|
|
AVX512_VPOPCNTDQ_256 \
|
|
AVX512_VPOPCNTDQ_512 \
|
|
AVX512_GFNI_128 \
|
|
AVX512_GFNI_256 \
|
|
AVX512_GFNI_512 \
|
|
AVX_GFNI \
|
|
GFNI \
|
|
AVX512_VAES_128 \
|
|
AVX512_VAES_256 \
|
|
AVX512_VAES_512 \
|
|
VAES \
|
|
AVX512_VPCLMULQDQ_128 \
|
|
AVX512_VPCLMULQDQ_256 \
|
|
AVX512_VPCLMULQDQ_512 \
|
|
VPCLMULQDQ \
|
|
AVX512_VNNI_128 \
|
|
AVX512_VNNI_256 \
|
|
AVX512_VNNI_512
|
|
|
|
|
|
ICE_LAKE_SERVER: \
|
|
ALL_OF(ICE_LAKE) \
|
|
CLWB \
|
|
SGX_ENCLV \
|
|
PCONFIG \
|
|
WBNOINVD
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/tgl/tgl-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
TIGER_LAKE: \
|
|
ALL_OF(ICE_LAKE_SERVER) \
|
|
KEYLOCKER \
|
|
KEYLOCKER_WIDE \
|
|
CET \
|
|
MOVDIR \
|
|
AVX512_VP2INTERSECT_128 \
|
|
AVX512_VP2INTERSECT_256 \
|
|
AVX512_VP2INTERSECT_512
|
|
|
|
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/adl/adl-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
# MKTME has no new instr
|
|
ALDER_LAKE: \
|
|
ALL_OF(SNOW_RIDGE) \
|
|
NOT(SGX_ENCLV) \
|
|
NOT(MPX) \
|
|
KEYLOCKER \
|
|
KEYLOCKER_WIDE \
|
|
CET \
|
|
PCONFIG \
|
|
INVPCID \
|
|
SERIALIZE \
|
|
AVX \
|
|
AVX_VNNI \
|
|
VPCLMULQDQ \
|
|
VAES \
|
|
F16C \
|
|
AVXAES \
|
|
PKU \
|
|
FMA \
|
|
BMI1 \
|
|
BMI2 \
|
|
AVX2 \
|
|
AVX_GFNI \
|
|
AVX2GATHER \
|
|
ADOX_ADCX \
|
|
LZCNT \
|
|
WBNOINVD \
|
|
HRESET
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/spr/spr-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
SAPPHIRE_RAPIDS: \
|
|
ALL_OF(TIGER_LAKE) \
|
|
NOT(KEYLOCKER) \
|
|
NOT(KEYLOCKER_WIDE) \
|
|
UINTR \
|
|
PTWRITE \
|
|
CLDEMOTE \
|
|
ENQCMD \
|
|
SERIALIZE \
|
|
TSX_LDTRK \
|
|
WAITPKG \
|
|
AVX512_BF16_128 \
|
|
AVX512_BF16_256 \
|
|
AVX512_BF16_512 \
|
|
AVX_VNNI \
|
|
AMX_TILE \
|
|
AMX_INT8 \
|
|
AMX_BF16 \
|
|
TDX \
|
|
AVX512_BF16_128 \
|
|
AVX512_BF16_256 \
|
|
AVX512_BF16_512 \
|
|
AVX512_FP16_128N \
|
|
AVX512_FP16_128 \
|
|
AVX512_FP16_256 \
|
|
AVX512_FP16_512 \
|
|
AVX512_FP16_SCALAR
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/future/future-chips.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
# This is intentionally *completely* inaccurate but Intel is not
|
|
# saying which chips will have these instructions publicly at this
|
|
# time and I had to put the new instructions on some chip so I made
|
|
# somethign up.
|
|
|
|
FUTURE: \
|
|
ALL_OF(SAPPHIRE_RAPIDS) \
|
|
TDX
|