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86771 lines
2.6 MiB
86771 lines
2.6 MiB
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###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-isa.txt
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#BEGIN_LEGAL
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#
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#Copyright (c) 2019 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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#END_LEGAL
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INSTRUCTIONS()::
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{
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ICLASS : FADD
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FMUL
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FCOMP
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FSUB
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FSUBR
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FDIV
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FDIVR
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FADD
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FMUL
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FCOM
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
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PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FCOM
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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COMMENT : UNDOC DC D0..D7 is an undocumented alaias (see sandpile.org)
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PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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IFORM : FCOM_ST0_X87_DCD0
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}
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{
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ICLASS : FCOMP
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FCOMP
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ATTRIBUTES: NOTSX
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COMMENT : UNDOC ALIASES
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
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PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
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IFORM : FCOMP_ST0_X87_DCD1
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PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
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IFORM : FCOMP_ST0_X87_DED0
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}
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{
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ICLASS : FSUB
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FSUBR
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FDIV
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FDIVR
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
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OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FLD
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
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OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FST
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
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OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FSTP
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
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OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
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PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
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OPERANDS : MEM0:w:mem80real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
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PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
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OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FSTP
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]
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OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
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COMMENT : UNDOC ALIASES
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PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]
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OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
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IFORM : FSTP_X87_ST0_DFD0
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PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]
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OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
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IFORM : FSTP_X87_ST0_DFD1
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}
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{
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ICLASS : FSTPNCE
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
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COMMENT : UNDOC ALIASES - empty top of stack behavior differs from FSTP.
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PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
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OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FLDENV
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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ATTRIBUTES : X87_CONTROL NOTSX
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FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
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# EOSZ=1
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()
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OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()
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OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()
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OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP
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# EOSZ!=1
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()
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OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP
|
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()
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OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FLDCW
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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ATTRIBUTES : X87_CONTROL NOTSX
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FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
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OPERANDS : MEM0:r:mem16 REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FNSTENV
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
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ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
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FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
|
# EOSZ=1
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()
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|
OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP
|
|
# EOSZ!=1
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP
|
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PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP
|
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}
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{
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|
ICLASS : FNSTCW
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
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EXTENSION : X87
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ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
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|
FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87CONTROL:r:SUPP REG1=XED_REG_X87STATUS:w:SUPP
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}
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{
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ICLASS : FLD
|
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ATTRIBUTES: NOTSX
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CPL : 3
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CATEGORY : X87_ALU
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EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87PUSH:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FXCH
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FXCH
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
COMMENT : UNDOC ALIAS
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
IFORM : FXCH_ST0_X87_DFC1
|
|
|
|
PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
IFORM : FXCH_ST0_X87_DDC1
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : FNOP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: NOP X87_CONTROL NOTSX
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : FCHS
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FABS
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FTST
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FXAM
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLD1
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]
|
|
OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLDL2T
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]
|
|
OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLDL2E
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]
|
|
OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLDPI
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]
|
|
OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLDLG2
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]
|
|
OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLDLN2
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]
|
|
OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLDZ
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]
|
|
OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : F2XM1
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FYL2X
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]
|
|
OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FPTAN
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FPATAN
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]
|
|
OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FXTRACT
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FPREM1
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FDECSTP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]
|
|
OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FINCSTP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]
|
|
OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FPREM
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FYL2XP1
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]
|
|
OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSQRT
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSINCOS
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FRNDINT
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSCALE
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSIN
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCOS
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ]
|
|
PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]
|
|
OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIADD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIMUL
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FICOM
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FICOMP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISUB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISUBR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIDIV
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIDIVR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVE
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVBE
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVU
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FUCOMPP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001]
|
|
OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:rw:SUPP REG3=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FILD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISTTP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : SSE3
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIST
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISTP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVNB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVNE
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVNBE
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCMOVNU
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FCMOV
|
|
EXTENSION : X87
|
|
ISA_SET : FCMOV
|
|
FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FNCLEX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010]
|
|
OPERANDS : REG0=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FNINIT
|
|
CPL : 3
|
|
ATTRIBUTES : x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011]
|
|
OPERANDS : REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSETPM287_NOP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: NOP NOTSX
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100]
|
|
OPERANDS :
|
|
COMMENT : UNDOC
|
|
}
|
|
{
|
|
ICLASS : FENI8087_NOP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: NOP NOTSX
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000]
|
|
OPERANDS :
|
|
COMMENT : UNDOC
|
|
}
|
|
{
|
|
ICLASS : FDISI8087_NOP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: NOP NOTSX
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001]
|
|
COMMENT : UNDOC
|
|
OPERANDS :
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : FUCOMI
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ISA_SET : PPRO
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCOMI
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ISA_SET : PPRO
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ]
|
|
PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FADD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FMUL
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCOMP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSUB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSUBR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FDIV
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FDIVR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FADD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FMUL
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSUBR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSUB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FDIVR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FDIV
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FLD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISTTP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : SSE3
|
|
ISA_SET : SSE3X87
|
|
ATTRIBUTES : NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FST
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FRSTOR
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES : x87_mmx_state_w X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
# EOSZ=1
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP
|
|
# EOSZ!=1
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()
|
|
OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FNSAVE
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES : x87_mmx_state_r x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem94 \
|
|
REG0=XED_REG_X87CONTROL:rw:SUPP \
|
|
REG1=XED_REG_X87TAG:rw:SUPP \
|
|
REG3=XED_REG_X87STATUS:rw:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem94 \
|
|
REG0=XED_REG_X87CONTROL:rw:SUPP \
|
|
REG1=XED_REG_X87TAG:rw:SUPP \
|
|
REG3=XED_REG_X87STATUS:rw:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem94 \
|
|
REG0=XED_REG_X87CONTROL:rw:SUPP \
|
|
REG1=XED_REG_X87TAG:rw:SUPP \
|
|
REG3=XED_REG_X87STATUS:rw:SUPP
|
|
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem108 \
|
|
REG0=XED_REG_X87CONTROL:rw:SUPP \
|
|
REG1=XED_REG_X87TAG:rw:SUPP \
|
|
REG3=XED_REG_X87STATUS:rw:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem108 \
|
|
REG0=XED_REG_X87CONTROL:rw:SUPP \
|
|
REG1=XED_REG_X87TAG:rw:SUPP \
|
|
REG3=XED_REG_X87STATUS:rw:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem108 \
|
|
REG0=XED_REG_X87CONTROL:rw:SUPP \
|
|
REG1=XED_REG_X87TAG:rw:SUPP \
|
|
REG3=XED_REG_X87STATUS:rw:SUPP
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()
|
|
OPERANDS : MEM0:w:mem108 \
|
|
REG0=XED_REG_X87CONTROL:rw:SUPP \
|
|
REG1=XED_REG_X87TAG:rw:SUPP \
|
|
REG3=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FNSTSW
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
|
PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FFREE
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
|
PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FST
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FUCOM
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FUCOMP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIADD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIMUL
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FICOM
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FICOMP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISUB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISUBR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIDIV
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIDIVR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FADDP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
COMMENT : 2011-02-10: the pop essentially occurs later. faddp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
|
|
}
|
|
{
|
|
ICLASS : FMULP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
COMMENT : 2011-02-10: the pop essentially occurs later. fmulp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
|
|
}
|
|
{
|
|
ICLASS : FCOMPP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ]
|
|
PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001]
|
|
OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FSUBRP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
COMMENT : 2011-02-10: the pop essentially occurs later. fsubrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
|
|
|
|
}
|
|
{
|
|
ICLASS : FSUBP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
COMMENT : 2011-02-10: the pop essentially occurs later. fsubp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
|
|
}
|
|
{
|
|
ICLASS : FDIVRP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
COMMENT : 2011-02-10: the pop essentially occurs later. fdivrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
|
|
|
|
}
|
|
{
|
|
ICLASS : FDIVP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
COMMENT : 2011-02-10: the pop essentially occurs later. fdivp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it.
|
|
}
|
|
{
|
|
ICLASS : FILD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISTTP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : SSE3
|
|
ISA_SET : SSE3X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FIST
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISTP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FBLD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80dec REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FILD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FBSTP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:mem80dec REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FISTP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FFREEP
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES: X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87POP:r:SUPP
|
|
COMMENT : UNDOC
|
|
}
|
|
{
|
|
ICLASS : FNSTSW
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX
|
|
FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ]
|
|
PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000]
|
|
OPERANDS : REG0=XED_REG_AX:w:IMPL REG1=XED_REG_X87STATUS:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : FUCOMIP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ISA_SET : PPRO
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ]
|
|
PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FCOMIP
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ISA_SET : PPRO
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ]
|
|
PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : ADD_LOCK
|
|
DISASM : add
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADD_LOCK_MEMb_IMMb_80r0
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADD_MEMb_IMMb_80r0
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
IFORM : ADD_GPR8_IMMb_80r0
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : OR_LOCK
|
|
DISASM : or
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : OR_LOCK_MEMb_IMMb_80r1
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : OR_MEMb_IMMb_80r1
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : OR_GPR8_IMMb_80r1
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADC_LOCK
|
|
DISASM : adc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADC_LOCK_MEMb_IMMb_80r2
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADC_MEMb_IMMb_80r2
|
|
}
|
|
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : ADC_GPR8_IMMb_80r2
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : SBB_LOCK
|
|
DISASM : sbb
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SBB_LOCK_MEMb_IMMb_80r3
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SBB_MEMb_IMMb_80r3
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : SBB_GPR8_IMMb_80r3
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : AND_LOCK
|
|
DISASM : and
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : AND_LOCK_MEMb_IMMb_80r4
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : AND_MEMb_IMMb_80r4
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
IFORM : AND_GPR8_IMMb_80r4
|
|
}
|
|
|
|
{
|
|
ICLASS : SUB_LOCK
|
|
DISASM : sub
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SUB_LOCK_MEMb_IMMb_80r5
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SUB_MEMb_IMMb_80r5
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : SUB_GPR8_IMMb_80r5
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : XOR_LOCK
|
|
DISASM : xor
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : XOR_LOCK_MEMb_IMMb_80r6
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : XOR_MEMb_IMMb_80r6
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
IFORM : XOR_GPR8_IMMb_80r6
|
|
}
|
|
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()
|
|
OPERANDS : MEM0:r:b IMM0:r:b:i8
|
|
IFORM : CMP_MEMb_IMMb_80r7
|
|
|
|
PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8
|
|
IFORM : CMP_GPR8_IMMb_80r7
|
|
}
|
|
{
|
|
ICLASS : ADD_LOCK
|
|
DISASM : add
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:z
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : OR_LOCK
|
|
DISASM : or
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:z
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADC_LOCK
|
|
DISASM : adc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:z
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : SBB_LOCK
|
|
DISASM : sbb
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:z
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : AND_LOCK
|
|
DISASM : and
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:z
|
|
}
|
|
|
|
{
|
|
ICLASS : SUB_LOCK
|
|
DISASM : sub
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:z
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : XOR_LOCK
|
|
DISASM : xor
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:z
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz()
|
|
OPERANDS : MEM0:r:v IMM0:r:z
|
|
PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():r IMM0:r:z
|
|
}
|
|
|
|
{
|
|
ICLASS : ADD_LOCK
|
|
DISASM : add
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADD_LOCK_MEMb_IMMb_82r0
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADD_MEMb_IMMb_82r0
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : ADD_GPR8_IMMb_82r0
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : OR_LOCK
|
|
DISASM : or
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : OR_LOCK_MEMb_IMMb_82r1
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : OR_MEMb_IMMb_82r1
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : OR_GPR8_IMMb_82r1
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADC_LOCK
|
|
DISASM : adc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADC_LOCK_MEMb_IMMb_82r2
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : ADC_MEMb_IMMb_82r2
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : ADC_GPR8_IMMb_82r2
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SBB_LOCK
|
|
DISASM : sbb
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SBB_LOCK_MEMb_IMMb_82r3
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SBB_MEMb_IMMb_82r3
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : SBB_GPR8_IMMb_82r3
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : AND_LOCK
|
|
DISASM : and
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : AND_LOCK_MEMb_IMMb_82r4
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : AND_MEMb_IMMb_82r4
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
IFORM : AND_GPR8_IMMb_82r4
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SUB_LOCK
|
|
DISASM : sub
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SUB_LOCK_MEMb_IMMb_82r5
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:i8
|
|
IFORM : SUB_MEMb_IMMb_82r5
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8
|
|
IFORM : SUB_GPR8_IMMb_82r5
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XOR_LOCK
|
|
DISASM : xor
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : XOR_LOCK_MEMb_IMMb_82r6
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : XOR_MEMb_IMMb_82r6
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
IFORM : XOR_GPR8_IMMb_82r6
|
|
}
|
|
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8()
|
|
OPERANDS : MEM0:r:b IMM0:r:b:i8
|
|
IFORM : CMP_MEMb_IMMb_82r7
|
|
|
|
PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8()
|
|
OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8
|
|
IFORM : CMP_GPR8_IMMb_82r7
|
|
}
|
|
|
|
{
|
|
ICLASS : ADD_LOCK
|
|
DISASM : add
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : OR_LOCK
|
|
DISASM : or
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : ADC_LOCK
|
|
DISASM : adc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SBB_LOCK
|
|
DISASM : sbb
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : AND_LOCK
|
|
DISASM : and
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SUB_LOCK
|
|
DISASM : sub
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : XOR_LOCK
|
|
DISASM : xor
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()
|
|
OPERANDS : MEM0:r:v IMM0:r:b:i8
|
|
|
|
PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_B():r IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : POP
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM()
|
|
OPERANDS : MEM0:w:v REG0=XED_REG_STACKPOP:r:spw:SUPP
|
|
|
|
PATTERN : 0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64()
|
|
OPERANDS : REG0=GPRv_B():w REG1=XED_REG_STACKPOP:r:spw:SUPP
|
|
IFORM : POP_GPRv_8F
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : ROL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : ROL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ]
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : ROR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : ROR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ]
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
# 2009-02-09: THIS WAS MISSING ENTIRELY UNTIL NOW
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : ROR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-mod ]
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : ROR_MEMb_ONE
|
|
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : ROR_GPR8_ONE
|
|
}
|
|
|
|
{
|
|
ICLASS : ROR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-mod ]
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : ROR_MEMv_ONE
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : ROR_GPRv_ONE
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : ROR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u cf-mod ]
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
|
|
{
|
|
ICLASS : ROR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ROL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-mod ]
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : ROL_MEMb_ONE
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : ROL_GPR8_ONE
|
|
}
|
|
|
|
{
|
|
ICLASS : ROL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-mod ]
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : ROL_MEMv_ONE
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : ROL_GPRv_ONE
|
|
}
|
|
{
|
|
ICLASS : ROL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u cf-mod ] # REMOVED cf-tst 2009-02-08
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : ROL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
|
|
#################
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : RCL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : RCR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : SHL_MEMb_IMMb_C0r4
|
|
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
IFORM : SHL_GPR8_IMMb_C0r4
|
|
}
|
|
{
|
|
ICLASS : SHR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
IFORM : SHL_MEMb_IMMb_C0r6
|
|
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
IFORM : SHL_GPR8_IMMb_C0r6
|
|
}
|
|
{
|
|
ICLASS : SAR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b
|
|
PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : RCL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : RCR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
IFORM : SHL_MEMv_IMMb_C1r4
|
|
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
IFORM : SHL_GPRv_IMMb_C1r4
|
|
}
|
|
{
|
|
ICLASS : SHR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
IFORM : SHL_MEMv_IMMb_C1r6
|
|
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
IFORM : SHL_GPRv_IMMb_C1r6
|
|
}
|
|
{
|
|
ICLASS : SAR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : RCL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-tst cf-mod ]
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : RCL_MEMb_ONE
|
|
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : RCL_GPR8_ONE
|
|
}
|
|
{
|
|
ICLASS : RCR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-tst cf-mod ]
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : RCR_MEMb_ONE
|
|
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : RCR_GPR8_ONE
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : SHL_MEMb_ONE_D0r4
|
|
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : SHL_GPR8_ONE_D0r4
|
|
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : SHL_MEMb_ONE_D0r6
|
|
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : SHL_GPR8_ONE_D0r6
|
|
}
|
|
{
|
|
ICLASS : SHR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : SHR_MEMb_ONE
|
|
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : SHR_GPR8_ONE
|
|
}
|
|
|
|
{
|
|
ICLASS : SAR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:b IMM0:r:b:IMPL
|
|
IFORM : SAR_MEMb_ONE
|
|
PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL
|
|
IFORM : SAR_GPR8_ONE
|
|
}
|
|
{
|
|
ICLASS : RCL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-tst cf-mod ]
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : RCL_MEMv_ONE
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : RCL_GPRv_ONE
|
|
}
|
|
{
|
|
ICLASS : RCR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod cf-tst cf-mod ]
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : RCR_MEMv_ONE
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : RCR_GPRv_ONE
|
|
}
|
|
|
|
{
|
|
ICLASS : SHR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : SHR_MEMv_ONE
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : SHR_GPRv_ONE
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : SHL_MEMv_ONE_D1r6
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : SHL_GPRv_ONE_D1r6
|
|
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : SHL_MEMv_ONE_D1r4
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : SHL_GPRv_ONE_D1r4
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : SAR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : IMPLICIT_ONE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE()
|
|
OPERANDS : MEM0:rw:v IMM0:r:b:IMPL
|
|
IFORM : SAR_MEMv_ONE
|
|
|
|
PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL
|
|
IFORM : SAR_GPRv_ONE
|
|
}
|
|
{
|
|
ICLASS : RCL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : RCR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_MEMb_CL_D2r4
|
|
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_GPR8_CL_D2r4
|
|
}
|
|
{
|
|
ICLASS : SHR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_MEMb_CL_D2r6
|
|
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_GPR8_CL_D2r6
|
|
}
|
|
{
|
|
ICLASS : SAR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL
|
|
PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
|
|
{
|
|
ICLASS : RCL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : RCL
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : RCR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : RCR
|
|
CPL : 3
|
|
CATEGORY : ROTATE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u cf-tst cf-mod ]
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_MEMv_CL_D3r4
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_GPRv_CL_D3r4
|
|
}
|
|
{
|
|
ICLASS : SHR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : SHR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_MEMv_CL_D3r6
|
|
}
|
|
{
|
|
ICLASS : SHL
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
IFORM : SHL_GPRv_CL_D3r6
|
|
}
|
|
{
|
|
ICLASS : SAR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : SAR
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8()
|
|
OPERANDS : MEM0:r:b IMM0:r:b:i8
|
|
IFORM : TEST_MEMb_IMMb_F6r0
|
|
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8()
|
|
OPERANDS : MEM0:r:b IMM0:r:b:i8
|
|
IFORM : TEST_MEMb_IMMb_F6r1
|
|
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8
|
|
IFORM : TEST_GPR8_IMMb_F6r0
|
|
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8
|
|
IFORM : TEST_GPR8_IMMb_F6r1
|
|
}
|
|
|
|
{
|
|
ICLASS : NOT_LOCK
|
|
DISASM : not
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : NOT
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : NOT
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw
|
|
}
|
|
{
|
|
ICLASS : NEG_LOCK
|
|
DISASM : neg
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : NEG
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : NEG
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw
|
|
}
|
|
{
|
|
ICLASS : MUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : IMUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP
|
|
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : DIV
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : IDIV
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
|
|
PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP
|
|
PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()
|
|
OPERANDS : MEM0:r:v IMM0:r:z
|
|
IFORM : TEST_MEMv_IMMz_F7r0
|
|
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz()
|
|
OPERANDS : MEM0:r:v IMM0:r:z
|
|
IFORM : TEST_MEMv_IMMz_F7r1
|
|
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():r IMM0:r:z
|
|
IFORM : TEST_GPRv_IMMz_F7r0
|
|
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():r IMM0:r:z
|
|
IFORM : TEST_GPRv_IMMz_F7r1
|
|
}
|
|
{
|
|
ICLASS : NOT_LOCK
|
|
DISASM : not
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : NOT
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : NOT
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw
|
|
}
|
|
{
|
|
ICLASS : NEG_LOCK
|
|
DISASM : neg
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : NEG
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : NEG
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw
|
|
}
|
|
{
|
|
ICLASS : MUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : MUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : IMUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP
|
|
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : DIV
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : IDIV
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ]
|
|
PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP
|
|
PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : INC_LOCK
|
|
DISASM : inc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : INC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : INC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw
|
|
}
|
|
{
|
|
ICLASS : DEC_LOCK
|
|
DISASM : dec
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : DEC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b
|
|
}
|
|
{
|
|
ICLASS : DEC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw
|
|
}
|
|
{
|
|
ICLASS : INC_LOCK
|
|
DISASM : inc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : INC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : INC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw
|
|
IFORM : INC_GPRv_FFr0
|
|
}
|
|
{
|
|
ICLASS : DEC_LOCK
|
|
DISASM : dec
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : DEC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v
|
|
}
|
|
{
|
|
ICLASS : DEC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw
|
|
IFORM : DEC_GPRv_FFr1
|
|
}
|
|
|
|
{
|
|
ICLASS : CALL_NEAR
|
|
DISASM_INTEL: call
|
|
DISASM_ATTSV: call
|
|
CPL : 3
|
|
CATEGORY : CALL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH
|
|
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK()
|
|
OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP
|
|
PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK()
|
|
OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CALL_NEAR
|
|
DISASM_INTEL: call
|
|
DISASM_ATTSV: call
|
|
CPL : 3
|
|
CATEGORY : CALL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0xE8 not64 BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_EIP:rw:SUPP
|
|
PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JMP
|
|
CPL : 3
|
|
CATEGORY : UNCOND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK()
|
|
OPERANDS : MEM0:r:v REG0=rIP():w:SUPP
|
|
PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK()
|
|
OPERANDS : REG0=GPRv_B():r REG1=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : JMP_FAR
|
|
DISASM_INTEL: jmp far
|
|
DISASM_ATTSV: ljmp
|
|
CPL : 3
|
|
ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH
|
|
CATEGORY : UNCOND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:p2 REG0=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM()
|
|
OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP
|
|
|
|
PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64()
|
|
OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
IFORM : PUSH_GPRv_FFr6
|
|
}
|
|
{
|
|
ICLASS : SLDT
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE NOTSX
|
|
PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:w REG0=XED_REG_LDTR:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():w REG1=XED_REG_LDTR:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : STR
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE NOTSX
|
|
PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:w REG0=XED_REG_TR:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():w REG1=XED_REG_TR:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : LLDT
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES : PROTECTED_MODE RING0 NOTSX
|
|
PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:w REG0=XED_REG_LDTR:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=GPR16_B():r REG1=XED_REG_LDTR:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : LTR
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES : PROTECTED_MODE RING0 NOTSX
|
|
PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:w REG0=XED_REG_TR:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=GPR16_B():r REG1=XED_REG_TR:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : VERR
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:w
|
|
COMMENT : reads a selector
|
|
}
|
|
{
|
|
ICLASS : VERR
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=GPR16_B():r
|
|
COMMENT : reads a selector
|
|
}
|
|
{
|
|
ICLASS : VERW
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:w
|
|
COMMENT : reads a selector
|
|
}
|
|
{
|
|
ICLASS : VERW
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=GPR16_B():r
|
|
COMMENT : reads a selector
|
|
}
|
|
{
|
|
ICLASS : LGDT
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : 66 is OSZ; F2/F3 ignored
|
|
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()
|
|
OPERANDS : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()
|
|
OPERANDS : MEM0:r:s REG0=XED_REG_GDTR:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : SMSW
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
COMMENT : 66 is OSZ; F2/F3 ignored
|
|
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:w REG0=XED_REG_CR0:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : SMSW
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
COMMENT : 66 is OSZ; F2/F3 ignored
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : LMSW
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
ATTRIBUTES: RING0 NOTSX
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:w REG0=XED_REG_CR0:w:SUPP
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=GPR16_B():r REG1=XED_REG_CR0:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : BT
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:r:v IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BT
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():r IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTS_LOCK
|
|
DISASM : bts
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTS
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTS
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTR_LOCK
|
|
DISASM : btr
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTR
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTR
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTC_LOCK
|
|
DISASM : btc
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTC
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix
|
|
OPERANDS : MEM0:rw:v IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BTC
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rw IMM0:r:b
|
|
}
|
|
|
|
# NOTE: VMXON and VMCLEAR almost conflict when there is a redundant 66
|
|
# on VMXON. It should be (and is) a VMXON. VMCLEAR is required to
|
|
# "not have" f2/f3; osz_refining_prefix handles this.
|
|
|
|
{
|
|
ICLASS : VMCLEAR
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: NOTSX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()
|
|
OPERANDS : MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : VMPTRLD
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: NOTSX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()
|
|
OPERANDS : MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : VMPTRST
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: NOTSX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()
|
|
OPERANDS : MEM0:w:q
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VMXON
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: PROTECTED_MODE NOTSX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()
|
|
OPERANDS : MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG8B_LOCK
|
|
DISASM : cmpxchg8b
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : PENTIUMREAL
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix
|
|
OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix
|
|
OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG8B
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : PENTIUMREAL
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG16B_LOCK
|
|
DISASM : cmpxchg16b
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : LONGMODE
|
|
ISA_SET : CMPXCHG16B
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT LOCKED
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix
|
|
OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG16B
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : LONGMODE
|
|
ISA_SET : CMPXCHG16B
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT LOCKABLE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
|
|
PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR8_B():w IMM0:r:b
|
|
IFORM : MOV_GPR8_IMMb_C6r0
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP HLE_REL_ABLE
|
|
PATTERN : 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:b IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_B():w IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : HLE_REL_ABLE
|
|
PATTERN : 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()
|
|
OPERANDS : MEM0:w:v IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : PSRLW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRAW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:i16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSLLW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRAW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:i16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSLLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRLD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRAD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:i32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSLLD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRLD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRAD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:i32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSLLD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRLQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSLLQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRLQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRLDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSLLQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSLLDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : FXSAVE
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
ISA_SET : FXSAVE
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : FXRSTOR
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
ISA_SET : FXSAVE
|
|
ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM()
|
|
OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : FXSAVE64
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
ISA_SET : FXSAVE64
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : FXRSTOR64
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
ISA_SET : FXSAVE64
|
|
ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM()
|
|
OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : LDMXCSR
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
ISA_SET : SSEMXCSR
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES : MXCSR
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()
|
|
OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : STMXCSR
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
ISA_SET : SSEMXCSR
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES : MXCSR_RD
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()
|
|
OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : PREFETCHNTA
|
|
CPL : 3
|
|
CATEGORY : PREFETCH
|
|
ATTRIBUTES: PREFETCH NONTEMPORAL
|
|
EXTENSION : SSE
|
|
ISA_SET : SSE_PREFETCH
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
{
|
|
ICLASS : PREFETCHT0
|
|
CPL : 3
|
|
CATEGORY : PREFETCH
|
|
ATTRIBUTES: PREFETCH
|
|
EXTENSION : SSE
|
|
ISA_SET : SSE_PREFETCH
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
{
|
|
ICLASS : PREFETCHT1
|
|
CPL : 3
|
|
CATEGORY : PREFETCH
|
|
ATTRIBUTES: PREFETCH
|
|
EXTENSION : SSE
|
|
ISA_SET : SSE_PREFETCH
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
{
|
|
ICLASS : PREFETCHT2
|
|
CPL : 3
|
|
CATEGORY : PREFETCH
|
|
ATTRIBUTES: PREFETCH
|
|
EXTENSION : SSE
|
|
ISA_SET : SSE_PREFETCH
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : NOP
|
|
CPL : 3
|
|
UNAME : NOP0F18
|
|
CATEGORY : WIDENOP
|
|
ATTRIBUTES: NOP
|
|
EXTENSION : BASE
|
|
ISA_SET : FAT_NOP
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r0
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r1
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r2
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r3
|
|
|
|
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v
|
|
IFORM : NOP_MEMv_0F18r4
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r4
|
|
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v
|
|
IFORM : NOP_MEMv_0F18r5
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r5
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r6
|
|
|
|
PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r
|
|
IFORM : NOP_GPRv_0F18r7
|
|
}
|
|
|
|
{
|
|
ICLASS : NOP
|
|
CPL : 3
|
|
UNAME : NOP0F18r6
|
|
CATEGORY : WIDENOP
|
|
ATTRIBUTES: NOP
|
|
EXTENSION : BASE
|
|
ISA_SET : FAT_NOP
|
|
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v
|
|
IFORM : NOP_MEMv_0F18r6
|
|
}
|
|
|
|
{
|
|
ICLASS : NOP
|
|
CPL : 3
|
|
UNAME : NOP0F18r7
|
|
CATEGORY : WIDENOP
|
|
ATTRIBUTES: NOP
|
|
EXTENSION : BASE
|
|
ISA_SET : FAT_NOP
|
|
|
|
PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v
|
|
IFORM : NOP_MEMv_0F18r7
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F19
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : FAT_NOP
|
|
PATTERN : 0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F19
|
|
|
|
PATTERN : 0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F19
|
|
}
|
|
{
|
|
ICLASS : NOP
|
|
CPL : 3
|
|
UNAME : NOP0F1A
|
|
CATEGORY : WIDENOP
|
|
ATTRIBUTES: NOP
|
|
EXTENSION : BASE
|
|
ISA_SET : FAT_NOP
|
|
PATTERN : 0x0F 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1A
|
|
|
|
PATTERN : 0x0F 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1A
|
|
}
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F1B
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : FAT_NOP
|
|
PATTERN : 0x0F 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1B
|
|
|
|
PATTERN : 0x0F 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1B
|
|
}
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F1C
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : FAT_NOP
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
|
|
PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1C
|
|
}
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F1D
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : FAT_NOP
|
|
PATTERN : 0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1D
|
|
|
|
PATTERN : 0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1D
|
|
}
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F1E
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : FAT_NOP
|
|
PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1E
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
}
|
|
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F1F
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : FAT_NOP
|
|
PATTERN : 0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1F
|
|
PATTERN : 0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1F
|
|
}
|
|
{
|
|
ICLASS : VMCALL
|
|
CPL : 3
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
|
|
FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : VMLAUNCH
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
|
|
FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : VMRESUME
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF.
|
|
FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : VMXOFF
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES: NOTSX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-mod pf-mod ]
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : SGDT
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()
|
|
OPERANDS : MEM0:w:s64 REG0=XED_REG_GDTR:r:SUPP
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()
|
|
OPERANDS : MEM0:w:s REG0=XED_REG_GDTR:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : LIDT
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
ATTRIBUTES: RING0 NOTSX
|
|
COMMENT : 66 is OSZ; F2/F3 ignored
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()
|
|
OPERANDS : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()
|
|
OPERANDS : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : MONITOR
|
|
CPL : 0
|
|
CATEGORY : MISC
|
|
EXTENSION : MONITOR
|
|
ISA_SET : MONITOR
|
|
ATTRIBUTES: RING0 NOTSX
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64
|
|
OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32
|
|
OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : MWAIT
|
|
CPL : 0
|
|
CATEGORY : MISC
|
|
EXTENSION : MONITOR
|
|
ISA_SET : MONITOR
|
|
ATTRIBUTES: RING0 NOTSX
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : SIDT
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : 66 is OSZ; F2/F3 ignored
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()
|
|
OPERANDS : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : SIDT
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
COMMENT : 66 is OSZ; F2/F3 ignored
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()
|
|
OPERANDS : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : INVLPG
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION BYTEOP RING0 NOTSX
|
|
PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SWAPGS
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES: RING0 NOTSX
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : RDTSCP
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : RDTSCP
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_TSC:r:SUPP REG4=XED_REG_TSCAUX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : SFENCE
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : SSE
|
|
ATTRIBUTES: IGNORES_OSFXSR
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : CLFLUSH
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : CLFSH
|
|
ISA_SET : CLFSH
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
{
|
|
ICLASS : LFENCE
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : SSE2
|
|
ISA_SET : SSE2
|
|
ATTRIBUTES: IGNORES_OSFXSR
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : MFENCE
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : SSE2
|
|
ISA_SET : SSE2
|
|
ATTRIBUTES: IGNORES_OSFXSR
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : MOVHLPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32
|
|
}
|
|
{
|
|
ICLASS : MOVLPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32
|
|
}
|
|
{
|
|
ICLASS : MOVLHPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32
|
|
}
|
|
{
|
|
ICLASS : MOVHPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32
|
|
}
|
|
{
|
|
ICLASS : ADD_LOCK
|
|
DISASM : add
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r
|
|
IFORM : ADD_GPR8_GPR8_00
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADD_LOCK
|
|
DISASM : add
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
IFORM : ADD_GPRv_GPRv_01
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():rw MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r
|
|
IFORM : ADD_GPR8_GPR8_02
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
IFORM : ADD_GPRv_GPRv_03
|
|
}
|
|
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x04 SIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : ADD
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x05 SIMMz()
|
|
OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x06 not64
|
|
OPERANDS : REG0=XED_REG_ES:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : POP
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x07 not64
|
|
OPERANDS : REG0=XED_REG_ES:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : OR_LOCK
|
|
DISASM : or
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r
|
|
IFORM : OR_GPR8_GPR8_08
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : OR_LOCK
|
|
DISASM : or
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
IFORM : OR_GPRv_GPRv_09
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():rw MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r
|
|
IFORM : OR_GPR8_GPR8_0A
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
IFORM : OR_GPRv_GPRv_0B
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x0C UIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : OR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x0D SIMMz()
|
|
OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x0E not64
|
|
OPERANDS : REG0=XED_REG_CS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : ADC_LOCK
|
|
DISASM : adc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r
|
|
IFORM : ADC_GPR8_GPR8_10
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADC_LOCK
|
|
DISASM : adc
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
IFORM : ADC_GPRv_GPRv_11
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():rw MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r
|
|
IFORM : ADC_GPR8_GPR8_12
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
IFORM : ADC_GPRv_GPRv_13
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x14 SIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : ADC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x15 SIMMz()
|
|
OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x16 not64
|
|
OPERANDS : REG0=XED_REG_SS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : POP
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x17 not64
|
|
COMMENT : Inhibits all interrupts until after next instr
|
|
OPERANDS : REG0=XED_REG_SS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : SBB_LOCK
|
|
DISASM : sbb
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r
|
|
IFORM : SBB_GPR8_GPR8_18
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SBB_LOCK
|
|
DISASM : sbb
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
|
|
PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
IFORM : SBB_GPRv_GPRv_19
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r
|
|
IFORM : SBB_GPR8_GPR8_1A
|
|
|
|
PATTERN : 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():rw MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
IFORM : SBB_GPRv_GPRv_1B
|
|
|
|
PATTERN : 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x1C SIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SBB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x1D SIMMz()
|
|
OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x1E not64
|
|
OPERANDS : REG0=XED_REG_DS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : POP
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x1F not64
|
|
OPERANDS : REG0=XED_REG_DS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : AND_LOCK
|
|
DISASM : and
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r
|
|
IFORM : AND_GPR8_GPR8_20
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : AND_LOCK
|
|
DISASM : and
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
IFORM : AND_GPRv_GPRv_21
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r
|
|
IFORM : AND_GPR8_GPR8_22
|
|
|
|
PATTERN : 0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():rw MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
IFORM : AND_GPRv_GPRv_23
|
|
|
|
PATTERN : 0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x24 SIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : AND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x25 SIMMz()
|
|
OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : DAA
|
|
CPL : 3
|
|
CATEGORY : DECIMAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x27 not64
|
|
OPERANDS : REG0=XED_REG_AL:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SUB_LOCK
|
|
DISASM : sub
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r
|
|
IFORM : SUB_GPR8_GPR8_28
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : SUB_LOCK
|
|
DISASM : sub
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
IFORM : SUB_GPRv_GPRv_29
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r
|
|
IFORM : SUB_GPR8_GPR8_2A
|
|
PATTERN : 0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():rw MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
IFORM : SUB_GPRv_GPRv_2B
|
|
|
|
PATTERN : 0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x2C SIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : SUB
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x2D SIMMz()
|
|
OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : DAS
|
|
CPL : 3
|
|
CATEGORY : DECIMAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ]
|
|
PATTERN : 0x2F not64
|
|
OPERANDS : REG0=XED_REG_AL:rw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : XOR_LOCK
|
|
DISASM : xor
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r
|
|
IFORM : XOR_GPR8_GPR8_30
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : XOR_LOCK
|
|
DISASM : xor
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
|
|
PATTERN : 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
IFORM : XOR_GPRv_GPRv_31
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r
|
|
IFORM : XOR_GPR8_GPR8_32
|
|
|
|
PATTERN : 0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():rw MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
IFORM : XOR_GPRv_GPRv_33
|
|
|
|
PATTERN : 0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x34 UIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : XOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x35 SIMMz()
|
|
OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : AAA
|
|
CPL : 3
|
|
CATEGORY : DECIMAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ]
|
|
PATTERN : 0x37 not64
|
|
OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:b REG0=GPR8_R():r
|
|
|
|
PATTERN : 0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r
|
|
IFORM : CMP_GPR8_GPR8_38
|
|
}
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
PATTERN : 0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : CMP_GPRv_GPRv_39
|
|
}
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():r MEM0:r:b
|
|
PATTERN : 0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():r REG1=GPR8_B():r
|
|
IFORM : CMP_GPR8_GPR8_3A
|
|
}
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():r MEM0:r:v
|
|
PATTERN : 0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():r REG1=GPRv_B():r
|
|
IFORM : CMP_GPRv_GPRv_3B
|
|
}
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x3C SIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : CMP
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x3D SIMMz()
|
|
OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : AAS
|
|
CPL : 3
|
|
CATEGORY : DECIMAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ]
|
|
PATTERN : 0x3F not64
|
|
OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : INC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0b0100_0 SRM[rrr] not64
|
|
OPERANDS : REG0=GPRv_SB():rw
|
|
IFORM : INC_GPRv_40
|
|
}
|
|
{
|
|
ICLASS : DEC
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0b0100_1 SRM[rrr] not64
|
|
OPERANDS : REG0=GPRv_SB():rw
|
|
IFORM : DEC_GPRv_48
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0b0101_0 SRM[rrr] DF64()
|
|
OPERANDS : REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
IFORM : PUSH_GPRv_50
|
|
}
|
|
{
|
|
ICLASS : POP
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0b0101_1 SRM[rrr] DF64()
|
|
OPERANDS : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP
|
|
IFORM : POP_GPRv_58
|
|
}
|
|
{
|
|
ICLASS : PUSHA
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
# EOSZ=1 not64
|
|
PATTERN : 0x60 mode16 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP
|
|
PATTERN : 0x60 mode32 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : PUSHAD
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
# EOSZ=2 not64
|
|
PATTERN : 0x60 mode16 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP
|
|
PATTERN : 0x60 mode32 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : POPA
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
# EOSZ=1 not64
|
|
PATTERN : 0x61 mode16 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP
|
|
PATTERN : 0x61 mode32 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP
|
|
|
|
COMMENT : eSP value on the stack is ignored! 2008-08-14
|
|
}
|
|
{
|
|
ICLASS : POPAD
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
# EOSZ=2 not64
|
|
PATTERN : 0x61 mode16 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP
|
|
PATTERN : 0x61 mode32 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP
|
|
|
|
COMMENT : eSP value on the stack is ignored! 2008-08-14
|
|
}
|
|
{
|
|
ICLASS : BOUND
|
|
CPL : 3
|
|
CATEGORY : INTERRUPT
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: EXCEPTION_BR
|
|
ISA_SET : I186
|
|
# EOSZ=1
|
|
PATTERN : 0x62 mode16 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():r MEM0:r:a16
|
|
PATTERN : 0x62 mode32 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():r MEM0:r:a16
|
|
# EOSZ=2
|
|
PATTERN : 0x62 mode16 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():r MEM0:r:a32
|
|
PATTERN : 0x62 mode32 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():r MEM0:r:a32
|
|
}
|
|
{
|
|
ICLASS : ARPL
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
|
|
OPERANDS : MEM0:rw:w REG0=GPR16_R():r
|
|
}
|
|
{
|
|
ICLASS : ARPL
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES: PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64
|
|
OPERANDS : REG0=GPR16_B():rw REG1=GPR16_R():r
|
|
}
|
|
{
|
|
ICLASS : MOVSXD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : LONGMODE
|
|
COMMENT : Prescott reads 32b for the 16b version. My testing indicates Merom, Nehalem and later reference 16b \
|
|
for the 16b version. I did not find an accessible Penryn. Oct 2017 (rev64) SDM documents modern behavior. \
|
|
2019 AMD docs say "mem32" and I am told AMD does reference 32b always.
|
|
PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:z
|
|
}
|
|
{
|
|
ICLASS : MOVSXD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : LONGMODE
|
|
PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPRz_B():r
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
PATTERN : 0x68 DF64() SIMMz()
|
|
OPERANDS : IMM0:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : IMUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:z
|
|
|
|
PATTERN : 0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz()
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:z
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
PATTERN : 0x6A DF64() SIMM8()
|
|
OPERANDS : IMM0:r:b:i8 REG0=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : IMUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:b:i8
|
|
|
|
PATTERN : 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8()
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:b:i8
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_INSB
|
|
DISASM : insb
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6C repe
|
|
OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6C repne
|
|
OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : INSB
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : fixed_base0 NOTSX BYTEOP
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6C norep
|
|
OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_INSW
|
|
DISASM : insw
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : REP fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6D mode16 no66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode32 66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode64 norexw_prefix 66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0x6D mode16 no66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode32 66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode64 norexw_prefix 66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : INSW
|
|
DISASM : insw
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6D mode16 no66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
PATTERN : 0x6D mode32 66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
PATTERN : 0x6D mode64 norexw_prefix 66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_INSD
|
|
DISASM : insd
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES :REP fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
|
|
PATTERN : 0x6D mode16 66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode32 no66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode64 norexw_prefix no66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0x6D mode64 rexw_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0x6D mode16 66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode32 no66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6D mode64 norexw_prefix no66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0x6D mode64 rexw_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : INSD
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6D mode16 66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
PATTERN : 0x6D mode32 no66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
PATTERN : 0x6D mode64 norexw_prefix no66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
|
|
PATTERN : 0x6D mode64 rexw_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_OUTSB
|
|
DISASM : outsb
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6E repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6E repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : OUTSB
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : fixed_base0 NOTSX BYTEOP
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
|
|
PATTERN : 0x6E norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_OUTSW
|
|
DISASM : outsw
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES :REP fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6F mode16 no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode32 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
|
|
PATTERN : 0x6F mode16 no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode32 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : OUTSW
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
PATTERN : 0x6F mode16 no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0x6F mode32 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0x6F mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_OUTSD
|
|
DISASM : outsd
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES :REP fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
|
|
PATTERN : 0x6F mode16 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode32 no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0x6F mode64 rexw_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0x6F mode16 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode32 no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0x6F mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0x6F mode64 rexw_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : OUTSD
|
|
CPL : 3
|
|
CATEGORY : IOSTRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : fixed_base0 NOTSX
|
|
FLAGS : READONLY [ iopl-tst df-tst ]
|
|
|
|
PATTERN : 0x6F mode16 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0x6F mode32 no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0x6F mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
|
|
PATTERN : 0x6F mode64 rexw_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JO
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x70 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNO
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x71 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JB
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x72 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNB
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x73 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JZ
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x74 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNZ
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x75 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JBE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x76 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNBE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x77 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JS
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x78 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNS
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x79 not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JP
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ pf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x7A not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNP
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ pf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x7B not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JL
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x7C not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNL
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x7D not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JLE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x7E not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNLE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
PATTERN : 0x7F not64 BRANCH_HINT() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : XCHG
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():rw
|
|
PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():rw
|
|
}
|
|
{
|
|
ICLASS : XCHG
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
ATTRIBUTES : BYTEOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XCHG
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():rw
|
|
PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():rw
|
|
}
|
|
{
|
|
ICLASS : XCHG
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
ATTRIBUTES : BYTEOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
|
|
PATTERN : 0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w REG1=GPR8_R():r
|
|
IFORM : MOV_GPR8_GPR8_88
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
ATTRIBUTES : BYTEOP HLE_REL_ABLE
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b REG0=GPR8_R():r
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : HLE_REL_ABLE
|
|
PATTERN : 0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():w REG1=GPRv_R():r
|
|
IFORM : MOV_GPRv_GPRv_89
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
ATTRIBUTES : BYTEOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR8_R():w MEM0:r:b
|
|
|
|
PATTERN : 0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_R():w REG1=GPR8_B():r
|
|
IFORM : MOV_GPR8_GPR8_8A
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r
|
|
IFORM : MOV_GPRv_GPRv_8B
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:w REG0=SEG():r
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():w REG1=SEG():r
|
|
}
|
|
{
|
|
ICLASS : LEA
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT()
|
|
OPERANDS : REG0=GPRv_R():w AGEN:r
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS
|
|
PATTERN : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=SEG_MOV():w MEM0:r:w
|
|
IFORM : MOV_SEG_MEMw
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS
|
|
PATTERN : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=SEG_MOV():w REG1=GPR16_B():r
|
|
IFORM : MOV_SEG_GPR16
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP90
|
|
CPL : 3
|
|
CATEGORY : NOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : I86
|
|
PATTERN : 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix
|
|
OPERANDS :
|
|
IFORM : NOP_90
|
|
}
|
|
{
|
|
ICLASS : PAUSE
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : PAUSE
|
|
ISA_SET : PAUSE
|
|
PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1
|
|
OPERANDS :
|
|
COMMENT : 2008-06-11 Ignores REX completely. Introduced on PENTIUM4
|
|
}
|
|
{
|
|
ICLASS : NOP
|
|
CPL : 3
|
|
CATEGORY : NOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : I86
|
|
PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0
|
|
OPERANDS :
|
|
IFORM : NOP_90
|
|
COMMENT : This is the encoding of PAUSE on pre-P4 systems
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : XCHG
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
|
|
PATTERN : 0b1001_0 SRM[rrr] SRM!=0
|
|
OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL
|
|
|
|
# This is strange. REG0 is r8w, r8d or r8 depending on the EOSZ. mode64
|
|
PATTERN : 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix
|
|
OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL
|
|
}
|
|
{
|
|
ICLASS : CBW
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x98 mode16 no66_prefix
|
|
OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP
|
|
PATTERN : 0x98 mode32 66_prefix
|
|
OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP
|
|
PATTERN : 0x98 mode64 norexw_prefix 66_prefix
|
|
OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CDQE
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : LONGMODE
|
|
PATTERN : 0x98 mode64 rexw_prefix
|
|
OPERANDS : REG0=XED_REG_RAX:w:SUPP REG1=XED_REG_EAX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CWDE
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0x98 mode16 66_prefix
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP
|
|
PATTERN : 0x98 mode32 no66_prefix
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP
|
|
PATTERN : 0x98 mode64 norexw_prefix no66_prefix
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CWD
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x99 mode16 no66_prefix
|
|
OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP
|
|
PATTERN : 0x99 mode32 66_prefix
|
|
OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP
|
|
PATTERN : 0x99 mode64 norexw_prefix 66_prefix
|
|
OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CQO
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : LONGMODE
|
|
PATTERN : 0x99 mode64 rexw_prefix
|
|
OPERANDS : REG0=XED_REG_RDX:w:SUPP REG1=XED_REG_RAX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : CDQ
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0x99 mode16 66_prefix
|
|
OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP
|
|
PATTERN : 0x99 mode32 no66_prefix
|
|
OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP
|
|
PATTERN : 0x99 mode64 norexw_prefix no66_prefix
|
|
OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : CALL_FAR
|
|
DISASM_INTEL : call far
|
|
DISASM_ATTSV : lcall
|
|
CPL : 3
|
|
CATEGORY : CALL
|
|
ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
|
|
COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented)
|
|
|
|
PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : CALL_FAR
|
|
DISASM_INTEL : call far
|
|
DISASM_ATTSV : lcall
|
|
CPL : 3
|
|
CATEGORY : CALL
|
|
ATTRIBUTES : FAR_XFER NOTSX
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
|
|
COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented)
|
|
|
|
PATTERN : 0x9A not64 BRDISPz() UIMM16()
|
|
OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=XED_REG_EIP:w:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : FWAIT
|
|
CPL : 3
|
|
CATEGORY : X87_ALU
|
|
EXTENSION : X87
|
|
ATTRIBUTES : X87_CONTROL NOTSX
|
|
PATTERN : 0x9B
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : PUSHF
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ]
|
|
# DF64() EOSZ=1
|
|
PATTERN : 0x9C mode16 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP
|
|
PATTERN : 0x9C mode32 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP
|
|
PATTERN : 0x9C mode64 norexw_prefix 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : PUSHFD
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ]
|
|
# DF64() EOSZ=2 not64
|
|
PATTERN : 0x9C mode32 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP
|
|
PATTERN : 0x9C mode16 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP
|
|
}
|
|
{
|
|
ICLASS : PUSHFQ
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : LONGMODE
|
|
FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ]
|
|
# DF64() EOSZ=3 mode64
|
|
PATTERN : 0x9C mode64 norexw_prefix no66_prefix DF64()
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP
|
|
PATTERN : 0x9C mode64 rexw_prefix DF64()
|
|
OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP
|
|
}
|
|
{
|
|
ICLASS : POPF
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
|
|
# DF64() EOSZ=1
|
|
PATTERN : 0x9D mode16 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP
|
|
PATTERN : 0x9D mode32 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP
|
|
PATTERN : 0x9D mode64 norexw_prefix 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : POPFD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
|
|
# DF64() EOSZ=2 not64
|
|
PATTERN : 0x9D mode16 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP
|
|
PATTERN : 0x9D mode32 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP
|
|
}
|
|
{
|
|
ICLASS : POPFQ
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : LONGMODE
|
|
FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
|
|
# DF64() EOSZ=3 mode64
|
|
PATTERN : 0x9D mode64 norexw_prefix no66_prefix DF64()
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP
|
|
PATTERN : 0x9D mode64 rexw_prefix DF64()
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP
|
|
}
|
|
{
|
|
ICLASS : SAHF
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : LAHF
|
|
FLAGS : MUST [ sf-ah zf-ah af-ah pf-ah cf-ah ]
|
|
PATTERN : 0x9E
|
|
OPERANDS : REG0=XED_REG_AH:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : LAHF
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : LAHF
|
|
FLAGS : MUST [ sf-tst zf-tst af-tst pf-tst cf-tst ]
|
|
PATTERN : 0x9F
|
|
OPERANDS : REG0=XED_REG_AH:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 BYTEOP
|
|
PATTERN : 0xA0 MEMDISPv() OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AL:w:IMPL MEM0:r:b SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0
|
|
PATTERN : 0xA1 MEMDISPv() OVERRIDE_SEG0()
|
|
OPERANDS : REG0=OrAX():w:IMPL MEM0:r:v SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 BYTEOP
|
|
PATTERN : 0xA2 MEMDISPv() OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:w:b REG0=XED_REG_AL:r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0
|
|
PATTERN : 0xA3 MEMDISPv() OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:w:v REG0=OrAX():r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_MOVSB
|
|
DISASM : movsb
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES :REP fixed_base0 fixed_base1 BYTEOP
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA4 repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xA4 repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : MOVSB
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA4 norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_MOVSW
|
|
DISASM : movsw
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES :REP fixed_base0 fixed_base1
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA5 mode16 no66_prefix repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode32 66_prefix repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xA5 mode16 no66_prefix repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode32 66_prefix repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : MOVSW
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 fixed_base1
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA5 mode16 no66_prefix norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
PATTERN : 0xA5 mode32 66_prefix norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
PATTERN : 0xA5 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_MOVSD
|
|
DISASM : movsd
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES :REP fixed_base0 fixed_base1
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA5 mode16 66_prefix repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode32 no66_prefix repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xA5 mode16 66_prefix repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode32 no66_prefix repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA5 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : MOVSD
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : fixed_base0 fixed_base1
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA5 mode16 66_prefix norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
PATTERN : 0xA5 mode32 no66_prefix norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
PATTERN : 0xA5 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_MOVSQ
|
|
DISASM : movsq
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES :REP fixed_base0 fixed_base1
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA5 mode64 rexw_prefix repe OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xA5 mode64 rexw_prefix repne OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : MOVSQ
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : fixed_base0 fixed_base1
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xA5 mode64 rexw_prefix norep OVERRIDE_SEG1()
|
|
OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:q BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REPE_CMPSB
|
|
DISASM : cmpsb
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA6 repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_CMPSB
|
|
DISASM : cmpsb
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA6 repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : CMPSB
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0xA6 norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REPE_CMPSW
|
|
DISASM : cmpsw
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA7 mode16 no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode32 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_CMPSW
|
|
DISASM : cmpsw
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA7 mode16 no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode32 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : CMPSW
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 fixed_base1
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0xA7 mode16 no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
PATTERN : 0xA7 mode32 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
PATTERN : 0xA7 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REPE_CMPSD
|
|
DISASM : cmpsd
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA7 mode16 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode32 no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_CMPSD
|
|
DISASM : cmpsd
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA7 mode16 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode32 no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
PATTERN : 0xA7 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : CMPSD
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : fixed_base0 fixed_base1
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0xA7 mode16 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
PATTERN : 0xA7 mode32 no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
PATTERN : 0xA7 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REPE_CMPSQ
|
|
DISASM : cmpsq
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA7 mode64 rexw_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_CMPSQ
|
|
DISASM : cmpsq
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : REP fixed_base0 fixed_base1
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xA7 mode64 rexw_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPSQ
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : fixed_base0 fixed_base1
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xA7 mode64 rexw_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:q BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0xA8 SIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8
|
|
}
|
|
{
|
|
ICLASS : TEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ]
|
|
PATTERN : 0xA9 SIMMz()
|
|
OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z
|
|
}
|
|
|
|
{
|
|
ICLASS : REP_STOSB
|
|
DISASM : stosb
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES :REP fixed_base0 BYTEOP
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAA repe
|
|
OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAA repne
|
|
OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : STOSB
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 BYTEOP
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAA norep
|
|
OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_STOSW
|
|
DISASM : stosw
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES :REP fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
|
|
PATTERN : 0xAB mode16 no66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode32 66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode64 norexw_prefix 66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xAB mode16 no66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode32 66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode64 norexw_prefix 66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : STOSW
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAB mode16 no66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP
|
|
PATTERN : 0xAB mode32 66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP
|
|
PATTERN : 0xAB mode64 norexw_prefix 66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_STOSD
|
|
DISASM : stosd
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES :REP fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAB mode16 66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode32 no66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode64 norexw_prefix no66_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xAB mode16 66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode32 no66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode64 norexw_prefix no66_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : STOSD
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAB mode16 66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP
|
|
PATTERN : 0xAB mode32 no66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP
|
|
PATTERN : 0xAB mode64 norexw_prefix no66_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_STOSQ
|
|
DISASM : stosq
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES :REP fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAB mode64 rexw_prefix repe
|
|
OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAB mode64 rexw_prefix repne
|
|
OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : STOSQ
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAB mode64 rexw_prefix norep
|
|
OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_LODSB
|
|
DISASM : lodsb
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES :REP fixed_base0 BYTEOP
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAC repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAC repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : LODSB
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 BYTEOP
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAC norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AL:w:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_LODSW
|
|
DISASM : lodsw
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES :REP fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAD mode16 no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode32 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xAD mode16 no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode32 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : LODSW
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAD mode16 no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0xAD mode32 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0xAD mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_LODSD
|
|
DISASM : lodsd
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES :REP fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAD mode16 66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode32 no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
|
|
PATTERN : 0xAD mode16 66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode32 no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : LODSD
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAD mode16 66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0xAD mode32 no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
PATTERN : 0xAD mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_LODSQ
|
|
DISASM : lodsq
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES :REP fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAD mode64 rexw_prefix repe OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAD mode64 rexw_prefix repne OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : LODSQ
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : READONLY [ df-tst ]
|
|
PATTERN : 0xAD mode64 rexw_prefix norep OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XED_REG_RAX:w:SUPP MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REPE_SCASB
|
|
DISASM : scasb
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0 BYTEOP
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
PATTERN : 0xAE repe
|
|
OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_SCASB
|
|
DISASM : scasb
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0 BYTEOP
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
PATTERN : 0xAE repne
|
|
OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : SCASB
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0 BYTEOP
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xAE norep
|
|
OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:r:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REPE_SCASW
|
|
DISASM : scasw
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xAF mode16 no66_prefix repe
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode32 66_prefix repe
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode64 norexw_prefix 66_prefix repe
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_SCASW
|
|
DISASM : scasw
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : REP fixed_base0
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
|
|
PATTERN : 0xAF mode16 no66_prefix repne
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode32 66_prefix repne
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode64 norexw_prefix 66_prefix repne
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : SCASW
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xAF mode16 no66_prefix norep
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
PATTERN : 0xAF mode32 66_prefix norep
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
PATTERN : 0xAF mode64 norexw_prefix 66_prefix norep
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REPE_SCASD
|
|
DISASM : scasd
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : REP fixed_base0
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
PATTERN : 0xAF mode16 66_prefix repe
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode32 no66_prefix repe
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode64 norexw_prefix no66_prefix repe
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_SCASD
|
|
DISASM : scasd
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : REP fixed_base0
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
PATTERN : 0xAF mode16 66_prefix repne
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode32 no66_prefix repne
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
PATTERN : 0xAF mode64 norexw_prefix no66_prefix repne
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : SCASD
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xAF mode16 66_prefix norep
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
PATTERN : 0xAF mode32 no66_prefix norep
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
PATTERN : 0xAF mode64 norexw_prefix no66_prefix norep
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REPE_SCASQ
|
|
DISASM : scasq
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : REP fixed_base0
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
PATTERN : 0xAF mode64 rexw_prefix repe
|
|
OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : REPNE_SCASQ
|
|
DISASM : scasq
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : REP fixed_base0
|
|
FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ]
|
|
PATTERN : 0xAF mode64 rexw_prefix repne
|
|
OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : SCASQ
|
|
CPL : 3
|
|
CATEGORY : STRINGOP
|
|
EXTENSION : LONGMODE
|
|
ATTRIBUTES : fixed_base0
|
|
FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0xAF mode64 rexw_prefix norep
|
|
OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:r:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
ATTRIBUTES : BYTEOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0b1011_0 SRM[rrr] UIMM8()
|
|
OPERANDS : REG0=GPR8_SB():w IMM0:r:b
|
|
# i had to come up with a partial nibble name
|
|
IFORM : MOV_GPR8_IMMb_B0
|
|
}
|
|
{
|
|
ICLASS : MOV
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0b1011_1 SRM[rrr] UIMMv()
|
|
OPERANDS : REG0=GPRv_SB():w IMM0:r:v
|
|
}
|
|
{
|
|
ICLASS : RET_NEAR
|
|
DISASM : ret
|
|
CPL : 3
|
|
CATEGORY : RET
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0xC2 DF64() UIMM16() IMMUNE66_LOOP64()
|
|
OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : RET_NEAR
|
|
DISASM : ret
|
|
CPL : 3
|
|
CATEGORY : RET
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0xC3 DF64() IMMUNE66_LOOP64()
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : LES
|
|
CPL : 3
|
|
CATEGORY : SEGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
|
|
OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_ES:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : LDS
|
|
CPL : 3
|
|
CATEGORY : SEGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
|
|
OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_DS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : ENTER
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION
|
|
PATTERN : 0xC8 DF64() UIMM16() UIMM8_1()
|
|
OPERANDS : IMM0:r:w IMM1:r:b REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=OrBP():rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : LEAVE
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : I186
|
|
ATTRIBUTES : fixed_base0
|
|
PATTERN : 0xC9 DF64()
|
|
# Ignoring STACKPOP semantics for LEAVE because it accesses memory at rBP because of
|
|
# the initial copy of rBP to rSP as part of the LEAVE's execution.
|
|
OPERANDS : MEM0:r:SUPP:v BASE0=ArBP():r:SUPP SEG0=FINAL_SSEG0():r:SUPP REG0=OrBP():rw:SUPP REG1=OrSP():rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : RET_FAR
|
|
DISASM_INTEL: ret far
|
|
DISASM_ATTSV: lcall
|
|
CPL : 3
|
|
CATEGORY : RET
|
|
ATTRIBUTES : FAR_XFER NOTSX
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
COMMENT : same privilege level does 2 pops (spw2). inter-privilege level does 4 (not represented)
|
|
PATTERN : 0xCA UIMM16()
|
|
OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : RET_FAR
|
|
DISASM_INTEL: ret far
|
|
DISASM_ATTSV: lcall
|
|
CPL : 3
|
|
CATEGORY : RET
|
|
ATTRIBUTES : FAR_XFER NOTSX
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xCB
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : INT3
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : INTERRUPT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ]
|
|
PATTERN : 0xCC
|
|
OPERANDS : REG0=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : INT
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : INTERRUPT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ]
|
|
PATTERN : 0xCD UIMM8()
|
|
OPERANDS : IMM0:r:b REG0=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : INTO
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : INTERRUPT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ]
|
|
PATTERN : 0xCE not64
|
|
OPERANDS : REG0=XED_REG_EIP:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : IRET
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : RET
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
|
|
PATTERN : 0xCF mode16 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
|
|
PATTERN : 0xCF mode32 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
|
|
PATTERN : 0xCF mode64 norexw_prefix 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : IRETD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : RET
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
|
|
PATTERN : 0xCF mode16 66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
|
|
PATTERN : 0xCF mode32 no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
|
|
PATTERN : 0xCF mode64 norexw_prefix no66_prefix
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : IRETQ
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : RET
|
|
EXTENSION : LONGMODE
|
|
FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ]
|
|
PATTERN : 0xCF mode64 rexw_prefix
|
|
# FIXME: This is only an approximate width for the stack pops
|
|
OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=XED_REG_RIP:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : AAM
|
|
CPL : 3
|
|
CATEGORY : DECIMAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ]
|
|
PATTERN : 0xD4 not64 UIMM8()
|
|
OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : AAD
|
|
CPL : 3
|
|
CATEGORY : DECIMAL
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ]
|
|
PATTERN : 0xD5 not64 UIMM8()
|
|
OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : SALC
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ cf-tst ]
|
|
PATTERN : 0xD6 not64
|
|
OPERANDS : REG0=XED_REG_AL:w:SUPP
|
|
COMMENT : was undocumented, but added to SDM v3 under "undefined opcodes" in 2017
|
|
}
|
|
{
|
|
ICLASS : XLAT
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : fixed_base0
|
|
PATTERN : 0xD7 OVERRIDE_SEG0()
|
|
OPERANDS : MEM0:r:SUPP:b BASE0=ArBX():r:SUPP INDEX=XED_REG_AL:r:SUPP REG0=XED_REG_AL:w:SUPP SEG0=FINAL_DSEG():r:SUPP SCALE=1:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : LOOPNE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
PATTERN : 0xE0 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
PATTERN : 0xE0 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
PATTERN : 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
|
|
COMMENT : REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC
|
|
PATTERN : 0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : LOOPE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
PATTERN : 0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
PATTERN : 0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
PATTERN : 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
|
|
COMMENT : REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC
|
|
PATTERN : 0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : LOOP
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xE2 DF64() BRDISP8() IMMUNE66_LOOP64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : JCXZ
|
|
COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0xE3 eamode16 BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=XED_REG_IP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JECXZ
|
|
COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0xE3 eamode32 not64 BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EIP:rw:SUPP
|
|
PATTERN : 0xE3 eamode32 mode64 BRDISP8() FORCE64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_RIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JRCXZ
|
|
COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : LONGMODE
|
|
PATTERN : 0xE3 eamode64 BRDISP8() FORCE64()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : IN
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP NOTSX
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xE4 UIMM8()
|
|
OPERANDS : REG0=XED_REG_AL:w:IMPL IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : IN
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xE5 UIMM8() IMMUNE_REXW()
|
|
OPERANDS : REG0=OeAX():w:IMPL IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : OUT
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX BYTEOP
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xE6 UIMM8()
|
|
OPERANDS : IMM0:r:b REG0=XED_REG_AL:r:IMPL
|
|
}
|
|
|
|
{
|
|
ICLASS : OUT
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xE7 UIMM8() IMMUNE_REXW()
|
|
OPERANDS : IMM0:r:b REG0=OeAX():r:IMPL
|
|
}
|
|
|
|
{
|
|
ICLASS : JMP
|
|
CPL : 3
|
|
CATEGORY : UNCOND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
PATTERN : 0xE9 not64 BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
PATTERN : 0xE9 mode64 FORCE64() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JMP_FAR
|
|
DISASM_INTEL: jmp far
|
|
DISASM_ATTSV: ljmp
|
|
CPL : 3
|
|
CATEGORY : UNCOND_BR
|
|
ATTRIBUTES : FAR_XFER NOTSX
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xEA not64 BRDISPz() UIMM16()
|
|
OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_EIP:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : JMP
|
|
CPL : 3
|
|
CATEGORY : UNCOND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xEB not64 BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
|
|
PATTERN : 0xEB mode64 FORCE64() BRDISP8()
|
|
OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : IN
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xEC
|
|
OPERANDS : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : IN
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xED IMMUNE_REXW()
|
|
OPERANDS : REG0=OeAX():w:IMPL REG1=XED_REG_DX:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : OUT
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xEE
|
|
OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : OUT
|
|
CPL : 3
|
|
CATEGORY : IO
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ iopl-tst ]
|
|
PATTERN : 0xEF IMMUNE_REXW()
|
|
OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=OeAX():r:IMPL
|
|
}
|
|
{
|
|
ICLASS : INT1
|
|
CPL : 3
|
|
CATEGORY : INTERRUPT
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0xF1
|
|
OPERANDS : REG0=rIP():w:SUPP
|
|
}
|
|
{
|
|
ICLASS : HLT
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ATTRIBUTES : RING0 NOTSX
|
|
ISA_SET : I86
|
|
PATTERN : 0xF4
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : CMC
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ cf-tst cf-mod ]
|
|
PATTERN : 0xF5
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : CLC
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ cf-0 ]
|
|
PATTERN : 0xF8
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : STC
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ cf-1 ]
|
|
PATTERN : 0xF9
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : CLI
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ vif-mod iopl-tst if-mod ]
|
|
PATTERN : 0xFA
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : STI
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
COMMENT : Inhibits all interrupts until after next instr
|
|
FLAGS : MUST [ vif-mod iopl-tst if-mod ]
|
|
PATTERN : 0xFB
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : CLD
|
|
ATTRIBUTES: NOTSX_COND
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ df-0 ]
|
|
PATTERN : 0xFC
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : STD
|
|
ATTRIBUTES: NOTSX_COND
|
|
CPL : 3
|
|
CATEGORY : FLAGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ df-1 ]
|
|
PATTERN : 0xFD
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : LAR
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES : PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
COMMENT : LAR only sometimes writes its destination register.
|
|
PATTERN : 0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:w
|
|
PATTERN : 0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : LSL
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286PROTECTED
|
|
ATTRIBUTES : PROTECTED_MODE
|
|
FLAGS : MUST [ zf-mod ]
|
|
PATTERN : 0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:w
|
|
|
|
PATTERN : 0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRz_B():r
|
|
}
|
|
{
|
|
ICLASS : SYSCALL
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : SYSCALL
|
|
EXTENSION : LONGMODE
|
|
ISA_SET : LONGMODE
|
|
FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x05 mode64 FORCE64()
|
|
OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:w:SUPP REG2=XED_REG_R11:w:SUPP
|
|
COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD
|
|
}
|
|
{
|
|
ICLASS : CLTS
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I286REAL
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x06
|
|
OPERANDS :
|
|
}
|
|
|
|
{
|
|
ICLASS : SYSRET
|
|
CPL : 0
|
|
CATEGORY : SYSRET
|
|
ATTRIBUTES: PROTECTED_MODE RING0 NOTSX
|
|
EXTENSION : LONGMODE
|
|
ISA_SET : LONGMODE
|
|
FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x0F 0x07 mode64 norexw_prefix
|
|
OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ECX:r:SUPP
|
|
COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD
|
|
}
|
|
{
|
|
ICLASS : SYSRET64
|
|
DISASM : sysret
|
|
CPL : 0
|
|
CATEGORY : SYSRET
|
|
ATTRIBUTES: PROTECTED_MODE RING0 NOTSX
|
|
EXTENSION : LONGMODE
|
|
ISA_SET : LONGMODE
|
|
FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x07 mode64 rexw_prefix
|
|
OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:r:SUPP REG2=XED_REG_R11:r:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : MOVUPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4M
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps
|
|
|
|
PATTERN : 0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
|
|
IFORM : MOVUPS_XMMps_XMMps_0F10
|
|
|
|
PATTERN : 0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps
|
|
|
|
PATTERN : 0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps
|
|
IFORM : MOVUPS_XMMps_XMMps_0F11
|
|
}
|
|
{
|
|
ICLASS : MOVLPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32
|
|
}
|
|
{
|
|
ICLASS : UNPCKLPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
COMMENT : mem form only uses q portion of the dq load. See SDM.
|
|
PATTERN : 0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq
|
|
PATTERN : 0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : UNPCKHPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq
|
|
PATTERN : 0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : MOVHPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32
|
|
}
|
|
{
|
|
ICLASS : MOVSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
PATTERN : 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:ss
|
|
|
|
PATTERN : 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
|
|
IFORM : MOVSS_XMMss_XMMss_0F10
|
|
|
|
PATTERN : 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : MEM0:w:ss REG0=XMM_R():r:ss
|
|
|
|
PATTERN : 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_B():w:ss REG1=XMM_R():r:ss
|
|
IFORM : MOVSS_XMMss_XMMss_0F11
|
|
}
|
|
{
|
|
ICLASS : MOVSLDUP
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : MOVSHDUP
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : MOVUPD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4M
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd
|
|
|
|
PATTERN : 0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd
|
|
IFORM : MOVUPD_XMMpd_XMMpd_0F10
|
|
|
|
PATTERN : 0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd
|
|
|
|
PATTERN : 0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd
|
|
IFORM : MOVUPD_XMMpd_XMMpd_0F11
|
|
}
|
|
{
|
|
ICLASS : MOVLPD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:sd MEM0:r:q
|
|
PATTERN : 0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:sd
|
|
}
|
|
{
|
|
ICLASS : UNPCKLPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
COMMENT : mem form only uses q portion of the dq load. See SDM.
|
|
PATTERN : 0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq
|
|
PATTERN : 0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : UNPCKHPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq
|
|
PATTERN : 0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : MOVHPD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:sd MEM0:r:q
|
|
PATTERN : 0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:sd
|
|
}
|
|
{
|
|
ICLASS : MOVSD_XMM
|
|
DISASM : movsd
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
PATTERN : 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:sd
|
|
|
|
PATTERN : 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd
|
|
IFORM : MOVSD_XMM_XMMsd_XMMsd_0F10
|
|
|
|
PATTERN : 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : MEM0:w:sd REG0=XMM_R():r:sd
|
|
|
|
PATTERN : 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_B():w:sd REG1=XMM_R():r:sd
|
|
IFORM : MOVSD_XMM_XMMsd_XMMsd_0F11
|
|
}
|
|
{
|
|
ICLASS : MOVDDUP
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:q
|
|
PATTERN : 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q
|
|
}
|
|
|
|
{
|
|
ICLASS : MOV_CR
|
|
DISASM : mov
|
|
CPL : 0
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : RING0 NOTSX
|
|
COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
|
|
PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
|
|
OPERANDS : REG0=CR_R():w REG1=GPR32_B():r
|
|
|
|
PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
|
|
OPERANDS : REG0=CR_R():w REG1=GPR64_B():r
|
|
}
|
|
|
|
{
|
|
ICLASS : MOV_CR
|
|
DISASM : mov
|
|
CPL : 0
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : RING0
|
|
COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
|
|
PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
|
|
OPERANDS : REG0=GPR32_B():w REG1=CR_R():r
|
|
|
|
PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
|
|
OPERANDS : REG0=GPR64_B():w REG1=CR_R():r
|
|
}
|
|
|
|
{
|
|
ICLASS : MOV_DR
|
|
DISASM : mov
|
|
CPL : 0
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : RING0 NOTSX
|
|
COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
|
|
PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
|
|
OPERANDS : REG0=DR_R():w REG1=GPR32_B():r
|
|
|
|
PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
|
|
OPERANDS : REG0=DR_R():w REG1=GPR64_B():r
|
|
}
|
|
|
|
{
|
|
ICLASS : MOV_DR
|
|
DISASM : mov
|
|
CPL : 0
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES : RING0
|
|
COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11
|
|
PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64
|
|
OPERANDS : REG0=GPR32_B():w REG1=DR_R():r
|
|
|
|
PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64
|
|
OPERANDS : REG0=GPR64_B():w REG1=DR_R():r
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : WRMSR
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : PENTIUMREAL
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x30
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : RDTSC
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : PENTIUMREAL
|
|
PATTERN : 0x0F 0x31
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_TSC:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : RDMSR
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : PENTIUMREAL
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x32
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : RDPMC
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : RDPMC
|
|
PATTERN : 0x0F 0x33
|
|
OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : SYSENTER
|
|
CPL : 3
|
|
CATEGORY : SYSCALL
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO
|
|
ATTRIBUTES: PROTECTED_MODE NOTSX
|
|
FLAGS : MUST [ vm-0 rf-0 if-0 ]
|
|
PATTERN : 0x0F 0x34 not64
|
|
OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP
|
|
PATTERN : 0x0F 0x34 mode64
|
|
OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP
|
|
COMMENT : AMD does not document support for this in 64b mode
|
|
}
|
|
{
|
|
ICLASS : SYSEXIT
|
|
CPL : 0
|
|
CATEGORY : SYSRET
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO
|
|
ATTRIBUTES: PROTECTED_MODE RING0 NOTSX
|
|
PATTERN : 0x0F 0x35 not64
|
|
OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP
|
|
PATTERN : 0x0F 0x35 mode64
|
|
OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RDX:r:SUPP
|
|
COMMENT : AMD does not document support for this in 64b mode
|
|
}
|
|
{
|
|
ICLASS : CMOVO
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ of-tst ]
|
|
PATTERN : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNO
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ of-tst ]
|
|
PATTERN : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVB
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ cf-tst ]
|
|
PATTERN : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNB
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ cf-tst ]
|
|
PATTERN : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVZ
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ zf-tst ]
|
|
PATTERN : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNZ
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ zf-tst ]
|
|
PATTERN : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVBE
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
PATTERN : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNBE
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
PATTERN : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
PATTERN : 0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : MOVMSKPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : SQRTPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : RSQRTPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : RCPPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : ANDPS
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud
|
|
PATTERN : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
|
|
}
|
|
{
|
|
ICLASS : ANDNPS
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud
|
|
PATTERN : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
|
|
}
|
|
{
|
|
ICLASS : ORPS
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud
|
|
PATTERN : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
|
|
}
|
|
{
|
|
ICLASS : XORPS
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud
|
|
PATTERN : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud
|
|
}
|
|
{
|
|
ICLASS : SQRTSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : RSQRTSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
PATTERN : 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : RCPSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
PATTERN : 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : MOVMSKPD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : SQRTPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : ANDPD
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq
|
|
PATTERN : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
|
|
}
|
|
{
|
|
ICLASS : ANDNPD
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq
|
|
PATTERN : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
|
|
}
|
|
{
|
|
ICLASS : ORPD
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq
|
|
PATTERN : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
|
|
}
|
|
{
|
|
ICLASS : XORPD
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq
|
|
PATTERN : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq
|
|
}
|
|
{
|
|
ICLASS : SQRTSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : PUNPCKLBW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u8 MEM0:r:d:u8
|
|
|
|
PATTERN : 0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u8 REG1=MMX_B():r:d:u8
|
|
}
|
|
{
|
|
ICLASS : PUNPCKLWD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:d:u16
|
|
PATTERN : 0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:d:u16
|
|
}
|
|
{
|
|
ICLASS : PUNPCKLDQ
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:d:u32
|
|
PATTERN : 0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:d:u32
|
|
}
|
|
{
|
|
ICLASS : PACKSSWB
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PACKSSWB
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PCMPGTB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8
|
|
}
|
|
{
|
|
ICLASS : PCMPGTB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
|
|
}
|
|
{
|
|
ICLASS : PCMPGTW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PCMPGTW
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PCMPGTD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32
|
|
}
|
|
{
|
|
ICLASS : PCMPGTD
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32
|
|
}
|
|
{
|
|
ICLASS : PACKUSWB
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PACKUSWB
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PUNPCKLBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
COMMENT : mem form only uses q portion of the dq load. See SDM.
|
|
PATTERN : 0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PUNPCKLWD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
COMMENT : mem form only uses q portion of the dq load. See SDM.
|
|
PATTERN : 0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PUNPCKLDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
COMMENT : mem form only uses q portion of the dq load. See SDM.
|
|
PATTERN : 0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PACKSSWB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT
|
|
PATTERN : 0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
|
|
PATTERN : 0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : PCMPGTB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8
|
|
PATTERN : 0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : PCMPGTW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
|
|
PATTERN : 0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : PCMPGTD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
PATTERN : 0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : PACKUSWB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT
|
|
PATTERN : 0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
|
|
PATTERN : 0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : PSHUFW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=MMX_R():w:q:u16 MEM0:r:q:u16 IMM0:r:b
|
|
PATTERN : 0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_R():w:q:u16 REG1=MMX_B():r:q:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PCMPEQB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8
|
|
PATTERN : 0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
|
|
}
|
|
{
|
|
ICLASS : PCMPEQW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
PATTERN : 0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PCMPEQD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32
|
|
PATTERN : 0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32
|
|
}
|
|
{
|
|
ICLASS : EMMS
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : x87_mmx_state_w NOTSX
|
|
PATTERN : 0x0F 0x77 no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : PSHUFD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b
|
|
PATTERN : 0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PCMPEQB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8
|
|
PATTERN : 0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : PCMPEQW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
|
|
PATTERN : 0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : PCMPEQD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
PATTERN : 0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : PSHUFLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b
|
|
PATTERN : 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSHUFHW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b
|
|
PATTERN : 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : JO
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JO
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ of-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JNO
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ of-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNO
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JB
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JB
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JNB
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
|
|
}
|
|
{
|
|
ICLASS : JNB
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JZ
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JZ
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JNZ
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
|
|
}
|
|
{
|
|
ICLASS : JNZ
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JBE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JBE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JNBE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNBE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SETO
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ of-tst ]
|
|
PATTERN : 0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNO
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ of-tst ]
|
|
PATTERN : 0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETB
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ cf-tst ]
|
|
PATTERN : 0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNB
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ cf-tst ]
|
|
PATTERN : 0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETZ
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ zf-tst ]
|
|
PATTERN : 0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNZ
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ zf-tst ]
|
|
PATTERN : 0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETBE
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
PATTERN : 0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNBE
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ cf-tst zf-tst ]
|
|
PATTERN : 0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x0F 0xA0 DF64()
|
|
OPERANDS : REG0=XED_REG_FS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : POP
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0xA1 DF64()
|
|
OPERANDS : REG0=XED_REG_FS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CPUID
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
PATTERN : 0x0F 0xA2
|
|
OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_EBX:w:SUPP REG2=XED_REG_ECX:crw:SUPP REG3=XED_REG_EDX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : BT
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
PATTERN : 0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
}
|
|
|
|
{
|
|
ICLASS : CMPXCHG_LOCK
|
|
DISASM : cmpxchg
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
ATTRIBUTES : BYTEOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rcw REG1=GPR8_R():r REG2=XED_REG_AL:rcw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : CMPXCHG_LOCK
|
|
DISASM : cmpxchg
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP
|
|
}
|
|
{
|
|
ICLASS : CMPXCHG
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=OrAX():rcw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : LSS
|
|
CPL : 3
|
|
CATEGORY : SEGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_SS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : BTR_LOCK
|
|
DISASM : btr
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : BTR
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : BTR
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
}
|
|
|
|
{
|
|
ICLASS : LFS
|
|
CPL : 3
|
|
CATEGORY : SEGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_FS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : LGS
|
|
CPL : 3
|
|
CATEGORY : SEGOP
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_GS:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : MOVZX
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:b
|
|
PATTERN : 0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r
|
|
PATTERN : 0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:w
|
|
PATTERN : 0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r
|
|
}
|
|
{
|
|
ICLASS : XADD_LOCK
|
|
DISASM : xadd
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():rw
|
|
}
|
|
{
|
|
ICLASS : XADD
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : BYTEOP LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:b REG0=GPR8_R():rw
|
|
}
|
|
{
|
|
ICLASS : XADD
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : XADD_LOCK
|
|
DISASM : xadd
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():rw
|
|
}
|
|
{
|
|
ICLASS : XADD
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():rw
|
|
}
|
|
{
|
|
ICLASS : XADD
|
|
CPL : 3
|
|
CATEGORY : SEMAPHORE
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
|
|
PATTERN : 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : CMPPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b
|
|
PATTERN : 0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : MOVNTI
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
ATTRIBUTES : IGNORES_OSFXSR NOTSX NONTEMPORAL
|
|
PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
|
|
OPERANDS : MEM0:w:d REG0=GPR32_R():r
|
|
PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:d REG0=GPR32_R():r
|
|
PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:q REG0=GPR64_R():r
|
|
}
|
|
{
|
|
ICLASS : PINSRW
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : NOTSX
|
|
PATTERN : 0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:w:u16 IMM0:r:b
|
|
PATTERN : 0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 REG1=GPR32_B():r IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PEXTRW
|
|
EXCEPTIONS: mmx-nomem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SHUFPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b
|
|
PATTERN : 0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : CMPSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss IMM0:r:b
|
|
PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : CMPPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b
|
|
PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PINSRW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:w IMM0:r:b
|
|
PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PEXTRW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
PATTERN : 0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SHUFPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b
|
|
PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : CMPSD_XMM
|
|
DISASM : cmpsd
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd IMM0:r:b
|
|
PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PSRLW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSRLW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSRLD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSRLD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSRLQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSRLQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSE2
|
|
ISA_SET : SSE2MMX
|
|
PATTERN : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64
|
|
PATTERN : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : PMULLW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
PATTERN : 0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PMOVMSKB
|
|
EXCEPTIONS: mmx-nomem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : SSE
|
|
COMMENT : KNI on PentiumIII. MMX instructions intro'd w/SSE
|
|
PATTERN : 0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:i8
|
|
}
|
|
{
|
|
ICLASS : ADDSUBPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : PSRLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : PSRLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PSRLD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : PSRLD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PSRLQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : PSRLQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PADDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMULLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMOVMSKB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
PATTERN : 0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : MOVQ2DQ
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
ATTRIBUTES : MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=MMX_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : ADDSUBPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : MOVDQ2Q
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
ATTRIBUTES : MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=MMX_R():w:q:u64 REG1=XMM_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : PAVGB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PAVGB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
|
|
}
|
|
{
|
|
ICLASS : PSRAW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSRAW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSRAD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSRAD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PAVGW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PAVGW
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PMULHUW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q:u16
|
|
}
|
|
{
|
|
ICLASS : PMULHUW
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q:u16
|
|
}
|
|
{
|
|
ICLASS : PMULHW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PMULHW
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : MOVNTQ
|
|
EXCEPTIONS: mmx-nofp2
|
|
ATTRIBUTES: NOTSX NONTEMPORAL
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q REG0=MMX_R():r:q
|
|
}
|
|
{
|
|
ICLASS : PAVGB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8
|
|
PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : PSRAW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : PSRAW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:u64
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PSRAD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : PSRAD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:u64
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PAVGW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16
|
|
PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : PMULHUW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16
|
|
PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : PMULHW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
|
|
PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : CVTTPD2DQ
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64
|
|
PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64
|
|
}
|
|
{
|
|
ICLASS : MOVNTDQ
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_1
|
|
PATTERN : 0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq
|
|
}
|
|
{
|
|
ICLASS : CVTDQ2PD
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
COMMENT : ignores MXCSR. 32b int fits in f64
|
|
|
|
PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32
|
|
PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:i32
|
|
}
|
|
{
|
|
ICLASS : CVTPD2DQ
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64
|
|
PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64
|
|
}
|
|
{
|
|
ICLASS : PSLLW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q
|
|
PATTERN : 0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSLLD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q
|
|
PATTERN : 0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSLLQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q
|
|
PATTERN : 0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PMULUDQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSE2
|
|
ISA_SET : SSE2MMX
|
|
PATTERN : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32
|
|
PATTERN : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q:u32
|
|
}
|
|
{
|
|
ICLASS : PMADDWD
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16
|
|
PATTERN : 0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PSADBW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : MASKMOVQ
|
|
EXCEPTIONS: mmx-nofp2
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL
|
|
PATTERN : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0()
|
|
OPERANDS : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : PSLLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : PSLLW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PSLLD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : PSLLD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PSLLQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u64 MEM0:r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : PSLLQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_7
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u64 REG1=XMM_B():r:dq:u64
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PMULUDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMADDWD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
|
|
PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : PSADBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : MASKMOVDQU
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL
|
|
PATTERN : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
{
|
|
ICLASS : LDDQU
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0xF0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix
|
|
OPERANDS : REG0=XMM_R():w:pd MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : INVD
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x08
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : WBINVD
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x09
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : UD0
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO_UD0_SHORT
|
|
ATTRIBUTES: NOTSX
|
|
COMMENT : Older processors (before NHM) did not take a MODRM byte sequence. Atom too.
|
|
PATTERN : 0x0F 0xFF MODE_SHORT_UD0=1
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : UD0
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO_UD0_LONG
|
|
ATTRIBUTES: NOTSX
|
|
|
|
PATTERN : 0x0F 0xFF MODE_SHORT_UD0=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():r MEM0:r:d
|
|
PATTERN : 0x0F 0xFF MODE_SHORT_UD0=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r
|
|
}
|
|
{
|
|
ICLASS : UD1
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():r MEM0:r:d
|
|
PATTERN : 0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r
|
|
}
|
|
{
|
|
ICLASS : UD2
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0x0B
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : MOVAPS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_1
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps
|
|
|
|
PATTERN : 0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps
|
|
IFORM : MOVAPS_XMMps_XMMps_0F28
|
|
|
|
PATTERN : 0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps
|
|
|
|
PATTERN : 0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps
|
|
IFORM : MOVAPS_XMMps_XMMps_0F29
|
|
}
|
|
|
|
{
|
|
ICLASS : CVTPI2PS
|
|
EXCEPTIONS: mmx-fp
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE
|
|
ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:q:f32 MEM0:r:q:i32
|
|
PATTERN : 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:q:f32 REG1=MMX_B():r:q:i32
|
|
}
|
|
{
|
|
ICLASS : MOVNTPS
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_1
|
|
PATTERN : 0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq REG0=XMM_R():r:ps
|
|
}
|
|
{
|
|
ICLASS : CVTTPS2PI
|
|
EXCEPTIONS: mmx-fp
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE
|
|
ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32
|
|
PATTERN : 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32
|
|
}
|
|
{
|
|
ICLASS : CVTPS2PI
|
|
EXCEPTIONS: mmx-fp
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE
|
|
ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32
|
|
PATTERN : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32
|
|
}
|
|
{
|
|
ICLASS : UCOMISS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : COMISS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : CVTSI2SS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:d:i32
|
|
PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix
|
|
OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=GPR32_B():r:d:i32
|
|
PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:q:i32
|
|
PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix
|
|
OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=GPR64_B():r:q:i32
|
|
}
|
|
{
|
|
ICLASS : CVTTSS2SI
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32
|
|
PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32
|
|
PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32
|
|
PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32
|
|
}
|
|
{
|
|
ICLASS : CVTSS2SI
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32
|
|
PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32
|
|
PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32
|
|
PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32
|
|
}
|
|
{
|
|
ICLASS : MOVAPD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_1
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd
|
|
|
|
PATTERN : 0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd
|
|
IFORM : MOVAPD_XMMpd_XMMpd_0F28
|
|
|
|
PATTERN : 0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd
|
|
|
|
PATTERN : 0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd
|
|
IFORM : MOVAPD_XMMpd_XMMpd_0F29
|
|
}
|
|
{
|
|
ICLASS : CVTPI2PD
|
|
EXCEPTIONS: mmx-nofp
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
ATTRIBUTES: MXCSR MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32
|
|
PATTERN : 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32
|
|
}
|
|
{
|
|
ICLASS : MOVNTPD
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_1
|
|
PATTERN : 0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq REG0=XMM_R():r:pd
|
|
}
|
|
{
|
|
ICLASS : CVTTPD2PI
|
|
EXCEPTIONS: mmx-fp-16align
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64
|
|
PATTERN : 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64
|
|
}
|
|
{
|
|
ICLASS : CVTPD2PI
|
|
EXCEPTIONS: mmx-fp-16align
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX
|
|
PATTERN : 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64
|
|
PATTERN : 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64
|
|
}
|
|
{
|
|
ICLASS : UCOMISD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : COMISD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : CVTSI2SD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:d:i32
|
|
PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix
|
|
OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=GPR32_B():r:d:i32
|
|
PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:q:i64
|
|
PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix
|
|
OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=GPR64_B():r:q:i64
|
|
}
|
|
{
|
|
ICLASS : CVTTSD2SI
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64
|
|
PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64
|
|
PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64
|
|
PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64
|
|
}
|
|
{
|
|
ICLASS : CVTSD2SI
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64
|
|
PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64
|
|
PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64
|
|
PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64
|
|
}
|
|
{
|
|
ICLASS : CMOVS
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst ]
|
|
PATTERN : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVS
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst ]
|
|
PATTERN : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNS
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst ]
|
|
PATTERN : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVNS
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst ]
|
|
PATTERN : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVP
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ pf-tst ]
|
|
PATTERN : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVP
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ pf-tst ]
|
|
PATTERN : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNP
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ pf-tst ]
|
|
PATTERN : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVNP
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ pf-tst ]
|
|
PATTERN : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVL
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
PATTERN : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVL
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
PATTERN : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNL
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
PATTERN : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVNL
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
PATTERN : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVLE
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
PATTERN : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVLE
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
PATTERN : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : CMOVNLE
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
PATTERN : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
}
|
|
{
|
|
ICLASS : CMOVNLE
|
|
CPL : 3
|
|
CATEGORY : CMOV
|
|
EXTENSION : BASE
|
|
ISA_SET : CMOV
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
PATTERN : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : ADDPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : MULPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : CVTPS2PD
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : 0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:f32
|
|
PATTERN : 0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:f32
|
|
}
|
|
{
|
|
ICLASS : CVTDQ2PS
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:dq:i32
|
|
PATTERN : 0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : SUBPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : MINPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : DIVPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : MAXPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : ADDSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : MULSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : CVTSS2SD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:ss:f32
|
|
PATTERN : 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=XMM_B():r:ss:f32
|
|
}
|
|
{
|
|
ICLASS : CVTTPS2DQ
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32
|
|
PATTERN : 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32
|
|
}
|
|
{
|
|
ICLASS : SUBSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : MINSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : DIVSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : MAXSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss
|
|
PATTERN : 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss
|
|
}
|
|
{
|
|
ICLASS : ADDPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : MULPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : CVTPD2PS
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:pd:f64
|
|
PATTERN : 0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:pd:f64
|
|
}
|
|
{
|
|
ICLASS : CVTPS2DQ
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32
|
|
PATTERN : 0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32
|
|
}
|
|
{
|
|
ICLASS : SUBPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : MINPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : DIVPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : MAXPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MXCSR
|
|
PATTERN : 0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : ADDSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : MULSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : CVTSD2SS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : CONVERT
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:sd:f64
|
|
PATTERN : 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=XMM_B():r:sd:f64
|
|
}
|
|
{
|
|
ICLASS : SUBSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : MINSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : DIVSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : MAXSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd
|
|
PATTERN : 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
|
|
}
|
|
{
|
|
ICLASS : PUNPCKHBW
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : SKIPLOW32 NOTSX
|
|
PATTERN : 0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d
|
|
}
|
|
{
|
|
ICLASS : PUNPCKHWD
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : SKIPLOW32 NOTSX
|
|
PATTERN : 0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d
|
|
}
|
|
{
|
|
ICLASS : PUNPCKHDQ
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : SKIPLOW32 NOTSX
|
|
PATTERN : 0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d
|
|
}
|
|
{
|
|
ICLASS : PACKSSDW
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32
|
|
}
|
|
{
|
|
ICLASS : PACKSSDW
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32
|
|
}
|
|
{
|
|
ICLASS : MOVD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:d
|
|
PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r
|
|
PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:d
|
|
PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r
|
|
|
|
|
|
PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:d
|
|
PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix
|
|
OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d
|
|
PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:d
|
|
PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64
|
|
OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d
|
|
}
|
|
{
|
|
ICLASS : MOVD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
ATTRIBUTES : NOTSX
|
|
PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q MEM0:r:d
|
|
|
|
PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix
|
|
OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r
|
|
|
|
PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q MEM0:r:d
|
|
|
|
PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64
|
|
OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r
|
|
|
|
|
|
PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:d REG0=MMX_R():r:d
|
|
|
|
PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix
|
|
OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d
|
|
|
|
PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()
|
|
OPERANDS : MEM0:w:d REG0=MMX_R():r:d
|
|
|
|
PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64
|
|
OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : MOVQ
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:q
|
|
IFORM : MOVQ_XMMdq_MEMq_0F6E
|
|
|
|
PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r
|
|
|
|
PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:q
|
|
IFORM : MOVQ_MEMq_XMMq_0F7E
|
|
|
|
PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix
|
|
OPERANDS : REG0=GPR64_B():w REG1=XMM_R():r:q
|
|
|
|
PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:q
|
|
IFORM : MOVQ_MEMq_XMMq_0FD6
|
|
|
|
PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q
|
|
IFORM : MOVQ_XMMdq_XMMq_0FD6
|
|
|
|
PATTERN : 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:q
|
|
IFORM : MOVQ_XMMdq_MEMq_0F7E
|
|
|
|
PATTERN : 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q
|
|
IFORM : MOVQ_XMMdq_XMMq_0F7E
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : MOVQ
|
|
EXCEPTIONS: mmx-nofp2 # FIXME guessing here...
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
|
|
PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q MEM0:r:q
|
|
IFORM : MOVQ_MMXq_MEMq_0F6E
|
|
|
|
PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix
|
|
OPERANDS : REG0=MMX_R():w:q REG1=GPR64_B():r
|
|
|
|
PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM()
|
|
OPERANDS : MEM0:w:q REG0=MMX_R():r:q
|
|
IFORM : MOVQ_MEMq_MMXq_0F7E
|
|
|
|
PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix
|
|
OPERANDS : REG0=GPR64_B():w REG1=MMX_R():r:q
|
|
|
|
PATTERN : 0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q MEM0:r:q
|
|
IFORM : MOVQ_MMXq_MEMq_0F6F
|
|
|
|
PATTERN : 0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q
|
|
IFORM : MOVQ_MMXq_MMXq_0F6F
|
|
|
|
PATTERN : 0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q REG0=MMX_R():r:q
|
|
IFORM : MOVQ_MEMq_MMXq_0F7F
|
|
|
|
PATTERN : 0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_B():w:q REG1=MMX_R():r:q
|
|
IFORM : MOVQ_MMXq_MMXq_0F7F
|
|
}
|
|
|
|
{
|
|
ICLASS : PUNPCKHBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PUNPCKHWD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PUNPCKHDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PACKSSDW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT
|
|
PATTERN : 0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
PATTERN : 0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : PUNPCKLQDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
COMMENT : mem form only uses q portion of the dq load. See SDM.
|
|
PATTERN : 0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PUNPCKHQDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q
|
|
}
|
|
{
|
|
ICLASS : MOVDQU
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4M
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
|
|
PATTERN : 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
IFORM : MOVDQU_XMMdq_XMMdq_0F6F
|
|
|
|
PATTERN : 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq
|
|
|
|
PATTERN : 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq
|
|
IFORM : MOVDQU_XMMdq_XMMdq_0F7F
|
|
}
|
|
{
|
|
ICLASS : VMREAD
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()
|
|
OPERANDS : MEM0:w:q REG0=GPR64_R():r
|
|
|
|
PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()
|
|
OPERANDS : REG0=GPR64_B():w REG1=GPR64_R():r
|
|
|
|
PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()
|
|
OPERANDS : MEM0:w:d REG0=GPR32_R():r
|
|
|
|
PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()
|
|
OPERANDS : REG0=GPR32_B():w REG1=GPR32_R():r
|
|
}
|
|
{
|
|
ICLASS : VMWRITE
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR64_R():r MEM0:r:q
|
|
|
|
PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()
|
|
OPERANDS : REG0=GPR64_R():r REG1=GPR64_B():r
|
|
|
|
PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR32_R():r MEM0:r:d
|
|
|
|
PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()
|
|
OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r
|
|
}
|
|
{
|
|
ICLASS : HADDPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : HSUBPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd
|
|
PATTERN : 0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd
|
|
}
|
|
{
|
|
ICLASS : MOVDQA
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_1
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq
|
|
|
|
PATTERN : 0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq
|
|
IFORM : MOVDQA_XMMdq_XMMdq_0F7F
|
|
|
|
PATTERN : 0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
|
|
PATTERN : 0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
IFORM : MOVDQA_XMMdq_XMMdq_0F6F
|
|
}
|
|
{
|
|
ICLASS : HADDPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : HSUBPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE3
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps
|
|
PATTERN : 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps
|
|
}
|
|
{
|
|
ICLASS : JS
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JS
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JNS
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNS
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JP
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ pf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JP
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ pf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JNP
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ pf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNP
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ pf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : JL
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JL
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JNL
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNL
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JLE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JLE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : JNLE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE
|
|
PATTERN : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
|
|
}
|
|
{
|
|
ICLASS : JNLE
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
ATTRIBUTES: MPX_PREFIX_ABLE
|
|
|
|
PATTERN : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32()
|
|
OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : SETS
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ sf-tst ]
|
|
PATTERN : 0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNS
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ sf-tst ]
|
|
PATTERN : 0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETP
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ pf-tst ]
|
|
PATTERN : 0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNP
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ pf-tst ]
|
|
PATTERN : 0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETL
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
PATTERN : 0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNL
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ sf-tst of-tst ]
|
|
PATTERN : 0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETLE
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
PATTERN : 0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : SETNLE
|
|
CPL : 3
|
|
CATEGORY : SETCC
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : BYTEOP
|
|
FLAGS : READONLY [ sf-tst of-tst zf-tst ]
|
|
PATTERN : 0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:b
|
|
PATTERN : 0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR8_B():w
|
|
}
|
|
{
|
|
ICLASS : PUSH
|
|
CPL : 3
|
|
CATEGORY : PUSH
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
PATTERN : 0x0F 0xA8 DF64()
|
|
OPERANDS : REG0=XED_REG_GS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : POP
|
|
CPL : 3
|
|
CATEGORY : POP
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN : 0x0F 0xA9 DF64()
|
|
OPERANDS : REG0=XED_REG_GS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP
|
|
}
|
|
{
|
|
ICLASS : RSM
|
|
CPL : 3
|
|
CATEGORY : SYSRET
|
|
EXTENSION : BASE
|
|
ISA_SET : I486
|
|
ATTRIBUTES: NOTSX
|
|
FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-mod rf-mod nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xAA
|
|
OPERANDS : REG0=rIP():w:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : BTS_LOCK
|
|
DISASM : bts
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : BTS
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : BTS
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SHRD
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : SHRD
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL
|
|
|
|
PATTERN : 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL
|
|
}
|
|
|
|
{
|
|
ICLASS : SHLD
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : SHLD
|
|
CPL : 3
|
|
CATEGORY : SHIFT
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL
|
|
|
|
PATTERN : 0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL
|
|
}
|
|
|
|
{
|
|
ICLASS : IMUL
|
|
CPL : 3
|
|
CATEGORY : BINARY
|
|
EXTENSION : BASE
|
|
ISA_SET : I86
|
|
FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():rw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r
|
|
}
|
|
|
|
{
|
|
ICLASS : BTC_LOCK
|
|
DISASM : btc
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
|
|
PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : BTC
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
ATTRIBUTES : LOCKABLE
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
|
|
PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix
|
|
OPERANDS : MEM0:rw:v REG0=GPRv_R():r
|
|
}
|
|
{
|
|
ICLASS : BTC
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ]
|
|
|
|
PATTERN : 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : BSF
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
|
|
COMMENT : replaced in the HSW builds
|
|
PATTERN : 0x0F 0xBC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBC MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : BSR
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
|
|
COMMENT : replaced in the HSW builds
|
|
PATTERN : 0x0F 0xBD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBD MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
{
|
|
ICLASS : MOVSX
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:b
|
|
}
|
|
{
|
|
ICLASS : MOVSX
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r
|
|
}
|
|
{
|
|
ICLASS : MOVSX
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:w
|
|
}
|
|
{
|
|
ICLASS : MOVSX
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
PATTERN : 0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r
|
|
}
|
|
{
|
|
ICLASS : BSWAP
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
PATTERN : 0x0F 0b1100_1 SRM[rrr]
|
|
OPERANDS : REG0=GPRv_SB():rw
|
|
}
|
|
{
|
|
ICLASS : PSUBUSB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBUSB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBUSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBUSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PMINUB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PMINUB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PAND
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PAND
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDUSB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PADDUSB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDUSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PADDUSW
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PMAXUB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PMAXUB
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PANDN
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PANDN
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBUSB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS : SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSUBUSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS : SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMINUB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PAND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PADDUSB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PADDUSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMAXUB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PANDN
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSUBSB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PMINSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : POR
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDSB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PMAXSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PXOR
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBSB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSUBSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMINSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : POR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PADDSB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PADDSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMAXSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PXOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSUBB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBQ
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSE2
|
|
ISA_SET : SSE2MMX
|
|
PATTERN : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PADDD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : MMX
|
|
ISA_SET : PENTIUMMMX
|
|
PATTERN : 0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSUBB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSUBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSUBD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSUBQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PADDB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PADDW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16
|
|
PATTERN : 0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : PADDD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE2
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PHADDW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PHADDW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PHADDD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PHADDD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PHADDSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PHADDSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PHSUBW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PHSUBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PHSUBD
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PHSUBD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PHSUBSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PHSUBSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMADDUBSW
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX
|
|
PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8
|
|
PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8
|
|
}
|
|
{
|
|
ICLASS : PMADDUBSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT
|
|
PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8
|
|
PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : PMULHRSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PMULHRSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSHUFB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSHUFB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSIGNB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSIGNB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSIGNW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSIGNW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PSIGND
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
EXCEPTIONS: mmx-mem
|
|
PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSIGND
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PALIGNR
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PALIGNR
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : PABSB
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PABSB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PABSW
|
|
EXCEPTIONS: mmx-mem
|
|
ATTRIBUTES: NOTSX
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q MEM0:r:q
|
|
PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PABSW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PABSD
|
|
EXCEPTIONS: mmx-mem
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar NOTSX
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=MMX_R():w:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PABSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar NOTSX
|
|
CATEGORY : MMX
|
|
EXTENSION : SSSE3
|
|
ISA_SET : SSSE3MMX
|
|
PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PABSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar REQUIRES_ALIGNMENT
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : PABSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar
|
|
CATEGORY : SSE
|
|
EXTENSION : SSSE3
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
####################################################################################
|
|
{
|
|
ICLASS : POPCNT
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : POPCNT
|
|
ATTRIBUTES: IGNORES_OSFXSR
|
|
# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix
|
|
# to get to the 16b form 32b and 64b modes.
|
|
FLAGS : MUST [ cf-0 zf-mod of-0 af-0 pf-0 sf-0 ]
|
|
PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w:v MEM0:r:v
|
|
PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : PCMPGTQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : CRC32
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
ATTRIBUTES : IGNORES_OSFXSR
|
|
# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix
|
|
# to get to the 16b form 32b and 64b modes.
|
|
|
|
COMMENT: The dest min size is 32b, even for EOSZ 16b.
|
|
|
|
# The byte-readers
|
|
|
|
PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRy_R():rw:y MEM0:r:b
|
|
PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRy_R():rw:y REG1=GPR8_B():r:b
|
|
|
|
|
|
# The scalable readers
|
|
|
|
PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRy_R():rw:y MEM0:r:v
|
|
PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRy_R():rw:y REG1=GPRv_B():r:v
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : BLENDPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : BLENDPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b
|
|
}
|
|
#######################################################################33
|
|
{
|
|
ICLASS : BLENDVPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 REG1=XED_REG_XMM0:r:SUPP:dq:u64
|
|
|
|
PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 REG2=XED_REG_XMM0:r:SUPP:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : BLENDVPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 REG1=XED_REG_XMM0:r:SUPP:dq:u32
|
|
|
|
PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 REG2=XED_REG_XMM0:r:SUPP:dq:u32
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : PCMPEQQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
|
|
PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : DPPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_2D
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : DPPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_2D
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : MOVNTDQA
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_1
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
PATTERN : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : EXTRACTPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:ps IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : INSERTPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ps MEM0:r:d IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : MPSADBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT
|
|
PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PACKUSDW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT
|
|
PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PBLENDW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PBLENDVB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq REG1=XED_REG_XMM0:r:dq:SUPP
|
|
|
|
PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq REG2=XED_REG_XMM0:r:dq:SUPP
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PEXTRB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:b REG0=XMM_R():r:dq IMM0:r:b
|
|
# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b???
|
|
PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PEXTRW_SSE4
|
|
DISASM_INTEL: pextrw
|
|
DISASM_ATTSV: pextrw
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
# this one aliases with the SSE2 version so we made a new name
|
|
|
|
PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:w REG0=XMM_R():r:dq IMM0:r:b
|
|
IFORM : PEXTRW_SSE4_MEMw_XMMdq_IMMb
|
|
|
|
# this one aliases with the SSE2 version so we made a new name
|
|
PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq IMM0:r:b
|
|
IFORM : PEXTRW_SSE4_GPR32_XMMdq_IMMb
|
|
}
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : PEXTRQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:dq IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PEXTRD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:dq IMM0:r:b
|
|
# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b???
|
|
PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PINSRB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:b IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PINSRD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:d IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PINSRQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:q IMM0:r:b
|
|
|
|
PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=GPR64_B():r:q IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : ROUNDPD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : ROUNDPS
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_2
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR
|
|
PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : ROUNDSD
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:q MEM0:r:q IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : ROUNDSS
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_3
|
|
PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:d MEM0:r:d IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:d REG1=XMM_B():r:d IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PTEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
FLAGS : MUST [ cf-mod zf-mod of-0 af-0 pf-0 sf-0 ]
|
|
PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : PHMINPOSUW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : PMAXSB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMAXSD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMAXUD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMAXUW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
{
|
|
ICLASS : PMINSB
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMINSD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMINUD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMINUW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
{
|
|
ICLASS : PMULLD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
{
|
|
ICLASS : PMULDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PMOVSXBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8
|
|
PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8
|
|
}
|
|
{
|
|
ICLASS : PMOVSXBD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8
|
|
PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8
|
|
}
|
|
{
|
|
ICLASS : PMOVSXBQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8
|
|
PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8
|
|
}
|
|
|
|
{
|
|
ICLASS : PMOVSXWD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16
|
|
PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16
|
|
}
|
|
{
|
|
ICLASS : PMOVSXWQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16
|
|
PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16
|
|
}
|
|
{
|
|
ICLASS : PMOVSXDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32
|
|
PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : PMOVZXBW
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8
|
|
PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8
|
|
}
|
|
{
|
|
ICLASS : PMOVZXBD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8
|
|
PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8
|
|
}
|
|
{
|
|
ICLASS : PMOVZXBQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8
|
|
PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8
|
|
}
|
|
|
|
{
|
|
ICLASS : PMOVZXWD
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16
|
|
PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16
|
|
}
|
|
{
|
|
ICLASS : PMOVZXWQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16
|
|
PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16
|
|
}
|
|
{
|
|
ICLASS : PMOVZXDQ
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
EXCEPTIONS: SSE_TYPE_5
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32
|
|
PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : PCMPESTRI
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES:
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP
|
|
|
|
# 64b eosz=2
|
|
PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : PCMPESTRI64
|
|
DISASM : pcmpestri
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES:
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
# EOSZ=3
|
|
PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : PCMPISTRI
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES:
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP
|
|
|
|
|
|
PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : PCMPISTRI64
|
|
DISASM : pcmpistri
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES:
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : PCMPESTRM
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES:
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
|
|
|
|
|
|
PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
|
|
}
|
|
{
|
|
ICLASS : PCMPESTRM64
|
|
DISASM : pcmpestrm
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES:
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : PCMPISTRM
|
|
CPL : 3
|
|
CATEGORY : SSE
|
|
EXTENSION : SSE4
|
|
ISA_SET : SSE42
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES:
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP
|
|
|
|
PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : XGETBV
|
|
CPL : 3
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVE
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix
|
|
OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_EAX:w:SUPP REG3=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : XSETBV
|
|
CPL : 0
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVE
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix
|
|
OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_XCR0:w:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XSAVE
|
|
CPL : 3
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVE
|
|
COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header.
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM()
|
|
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
|
|
OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : XRSTOR
|
|
CPL : 3
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVE
|
|
COMMENT : variable length load and conditional reg write
|
|
ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM()
|
|
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
|
|
OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XSAVE64
|
|
CPL : 3
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVE
|
|
COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header.
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM()
|
|
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
|
|
OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : XRSTOR64
|
|
CPL : 3
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVE
|
|
COMMENT : variable length load and conditional reg write
|
|
ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM()
|
|
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR
|
|
OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
####################################################################################
|
|
|
|
{
|
|
ICLASS : MOVBE
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : MOVBE
|
|
COMMENT : Intro on Atom Silverthorne. Intercepted by Haswell.
|
|
#
|
|
# must allow 66 prefix. So "not_refning" gives us REFINING=0 which suffices to exclude F2/F3 prefixes.
|
|
#
|
|
PATTERN : 0x0F 0x38 0xF0 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:v
|
|
PATTERN : 0x0F 0x38 0xF1 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:v REG0=GPRv_R():r
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : GETSEC
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
ATTRIBUTES: PROTECTED_MODE NOTSX
|
|
EXTENSION : SMX
|
|
PATTERN : 0x0F 0x37 no_refining_prefix
|
|
OPERANDS : REG0=XED_REG_EAX:rcw:SUPP REG1=XED_REG_EBX:r:SUPP
|
|
}
|
|
|
|
|
|
####################################################################################
|
|
{
|
|
ICLASS : AESKEYGENASSIST
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AES
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : AESENC
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AES
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : AESENCLAST
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AES
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : AESDEC
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AES
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : AESDECLAST
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AES
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
|
|
PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : AESIMC
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AES
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
}
|
|
####################################################################################
|
|
{
|
|
ICLASS : PCLMULQDQ
|
|
CPL : 3
|
|
CATEGORY : PCLMULQDQ
|
|
EXTENSION : PCLMULQDQ
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b
|
|
}
|
|
|
|
|
|
#######################################################################
|
|
{
|
|
ICLASS : INVEPT
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES : RING0 NOTSX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR64_R():r MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR32_R():r MEM0:r:dq
|
|
COMMENT : SDM rev 27
|
|
}
|
|
{
|
|
ICLASS : INVVPID
|
|
CPL : 0
|
|
CATEGORY : VTX
|
|
EXTENSION : VTX
|
|
ATTRIBUTES : RING0 NOTSX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ]
|
|
PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR64_R():r MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR32_R():r MEM0:r:dq
|
|
COMMENT : SDM rev 27
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-amd-prefetch.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F0D_reg
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ISA_SET : PREFETCH_NOP
|
|
COMMENT : AMD 3DNOW prefetches that do not touch memory. This is the reg/reg form.
|
|
|
|
PATTERN : 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F0D
|
|
}
|
|
|
|
# The rest are all mem forms (MODRM.MOD!=3)
|
|
|
|
{
|
|
ICLASS : PREFETCH_EXCLUSIVE
|
|
CPL : 3
|
|
ATTRIBUTES: PREFETCH
|
|
CATEGORY : PREFETCH
|
|
EXTENSION : 3DNOW_PREFETCH
|
|
ISA_SET : PREFETCH_NOP
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
{
|
|
ICLASS : PREFETCHW
|
|
CPL : 3
|
|
ATTRIBUTES: PREFETCH
|
|
CATEGORY : PREFETCH
|
|
EXTENSION : 3DNOW_PREFETCH
|
|
COMMENT : was PREFETCH_MODIFIED, prefetch on >=broadwell and >=silvermont
|
|
ISA_SET : PREFETCH_NOP
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
IFORM : PREFETCHW_0F0Dr1
|
|
}
|
|
{
|
|
ICLASS : PREFETCH_RESERVED
|
|
CPL : 3
|
|
ATTRIBUTES: PREFETCH
|
|
CATEGORY : PREFETCH
|
|
EXTENSION : 3DNOW_PREFETCH
|
|
ISA_SET : PREFETCH_NOP
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
IFORM : PREFETCH_RESERVED_0F0Dr2
|
|
UNAME : PREFETCH_RESERVED_0F0Dr2
|
|
}
|
|
{
|
|
ICLASS : PREFETCHW
|
|
CPL : 3
|
|
ATTRIBUTES: PREFETCH
|
|
CATEGORY : PREFETCH
|
|
EXTENSION : 3DNOW_PREFETCH
|
|
COMMENT : was PREFETCH_MODIFIED
|
|
ISA_SET : PREFETCH_NOP
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
IFORM : PREFETCHW_0F0Dr3
|
|
}
|
|
{
|
|
ICLASS : PREFETCH_RESERVED
|
|
CPL : 3
|
|
ATTRIBUTES: PREFETCH
|
|
CATEGORY : PREFETCH
|
|
EXTENSION : 3DNOW_PREFETCH
|
|
ISA_SET : PREFETCH_NOP
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
IFORM : PREFETCH_RESERVED_0F0Dr4
|
|
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
IFORM : PREFETCH_RESERVED_0F0Dr5
|
|
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
IFORM : PREFETCH_RESERVED_0F0Dr6
|
|
|
|
PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
IFORM : PREFETCH_RESERVED_0F0Dr7
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/via/via-padlock-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
{
|
|
ICLASS : XSTORE
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_RNG
|
|
ISA_SET : VIA_PADLOCK_RNG
|
|
PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] not_refining
|
|
OPERANDS : MEM0:w:SUPP:b REG0=OrCX():r:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_XSTORE
|
|
DISASM : xstore
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_RNG
|
|
ISA_SET : VIA_PADLOCK_RNG
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix
|
|
OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_XCRYPTECB
|
|
DISASM : xcryptecb
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_AES
|
|
ISA_SET : VIA_PADLOCK_AES
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix
|
|
OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : REP_XCRYPTCBC
|
|
DISASM : xcryptcbc
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_AES
|
|
ISA_SET : VIA_PADLOCK_AES
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix
|
|
COMMENT : rAX contains a pointer to memory using ES segment.
|
|
OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : REP_XCRYPTCTR
|
|
DISASM : xcryptctr
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_AES
|
|
ISA_SET : VIA_PADLOCK_AES
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b011] RM[0b000] f3_refining_prefix
|
|
COMMENT : rAX contains a pointer to memory using ES segment.
|
|
OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
{
|
|
ICLASS : REP_XCRYPTCFB
|
|
DISASM : xcryptcfb
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_AES
|
|
ISA_SET : VIA_PADLOCK_AES
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b100] RM[0b000] f3_refining_prefix
|
|
COMMENT : rAX contains a pointer to memory using ES segment.
|
|
OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
{
|
|
ICLASS : REP_XCRYPTOFB
|
|
DISASM : xcryptofb
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_AES
|
|
ISA_SET : VIA_PADLOCK_AES
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b101] RM[0b000] f3_refining_prefix
|
|
COMMENT : rAX contains a pointer to memory using ES segment.
|
|
OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_XSHA1
|
|
DISASM : xsha1
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_SHA
|
|
ISA_SET : VIA_PADLOCK_SHA
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix
|
|
OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_XSHA256
|
|
DISASM : xsha256
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_SHA
|
|
ISA_SET : VIA_PADLOCK_SHA
|
|
ATTRIBUTES : REP FIXED_BASE0 BYTEOP
|
|
PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix
|
|
OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : REP_MONTMUL
|
|
DISASM : montmul
|
|
CPL : 3
|
|
CATEGORY : VIA_PADLOCK
|
|
EXTENSION : VIA_PADLOCK_MONTMUL
|
|
ISA_SET : VIA_PADLOCK_MONTMUL
|
|
ATTRIBUTES : REP FIXED_BASE0
|
|
COMMENT : EAX output value undefined, so list as write.
|
|
|
|
PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode16
|
|
OPERANDS : REG0=XED_REG_EAX:rw:SUPP \
|
|
REG1=XED_REG_ECX:rw:SUPP \
|
|
REG2=XED_REG_EDX:w:SUPP \
|
|
MEM0:rw:SUPP:pmmsz16 \
|
|
BASE0=ArSI():r:SUPP \
|
|
SEG0=FINAL_ESEG():r:SUPP
|
|
|
|
PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode32
|
|
OPERANDS : REG0=XED_REG_EAX:rw:SUPP \
|
|
REG1=XED_REG_ECX:rw:SUPP \
|
|
REG2=XED_REG_EDX:w:SUPP \
|
|
MEM0:rw:SUPP:pmmsz32 \
|
|
BASE0=ArSI():r:SUPP \
|
|
SEG0=FINAL_ESEG():r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-3dnow.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
{
|
|
ICLASS : FEMMS
|
|
CPL : 3
|
|
CATEGORY : MMX
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : x87_mmx_state_w AMDONLY
|
|
PATTERN : 0x0F 0x0E
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : PI2FW
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PI2FW
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PI2FD
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PI2FD
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PF2IW
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PF2IW
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PF2ID
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PF2ID
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFNACC
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFNACC
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFPNACC
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFPNACC
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFCMPGE
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFCMPGE
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFMIN
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFMIN
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFRCP
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFRCP
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFRSQRT
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFRSQRT
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFSUB
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFSUB
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFADD
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFADD
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFCMPGT
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFCMPGT
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFMAX
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFMAX
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFRCPIT1
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFRCPIT1
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFRSQIT1
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFRSQIT1
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFSUBR
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFSUBR
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFACC
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFACC
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFCMPEQ
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFCMPEQ
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFMUL
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFMUL
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PFRCPIT2
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PFRCPIT2
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PMULHRW
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PMULHRW
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PSWAPD
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PSWAPD
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
{
|
|
ICLASS : PAVGUSB
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF
|
|
OPERANDS : REG0=MMX_R():rw:q MEM0:r:q
|
|
}
|
|
{
|
|
ICLASS : PAVGUSB
|
|
CPL : 3
|
|
CATEGORY : 3DNOW
|
|
EXTENSION : 3DNOW
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF
|
|
OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-base.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
# file: xed-amd-base.txt
|
|
|
|
INSTRUCTIONS()::
|
|
# SYSCALL and SYSRET are supported in 32b mode only on AMD chips
|
|
|
|
{
|
|
ICLASS : SYSCALL_AMD
|
|
DISASM : syscall
|
|
CPL : 3
|
|
CATEGORY : SYSCALL
|
|
EXTENSION : BASE
|
|
ISA_SET : AMD
|
|
ATTRIBUTES : AMDONLY
|
|
FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x05 not64 IGNORE66()
|
|
OPERANDS : REG0=rIP():w:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : SYSRET_AMD
|
|
DISASM : sysret
|
|
CPL : 0
|
|
CATEGORY : SYSRET
|
|
ATTRIBUTES: PROTECTED_MODE RING0 AMDONLY
|
|
EXTENSION : BASE
|
|
ISA_SET : AMD
|
|
|
|
FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x07 not64
|
|
OPERANDS : REG0=XED_REG_EIP:w:SUPP
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-svm.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
{
|
|
ICLASS : VMRUN
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES: PROTECTED_MODE AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]
|
|
OPERANDS : REG0=ArAX():r:IMPL
|
|
}
|
|
{
|
|
ICLASS : VMMCALL
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES : AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : VMLOAD
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES: PROTECTED_MODE AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]
|
|
OPERANDS : REG0=ArAX():r:IMPL
|
|
}
|
|
{
|
|
ICLASS : VMSAVE
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES: PROTECTED_MODE AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : STGI
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES: PROTECTED_MODE AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : CLGI
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES: PROTECTED_MODE AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]
|
|
OPERANDS :
|
|
}
|
|
{
|
|
ICLASS : SKINIT
|
|
CPL : 3
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES: PROTECTED_MODE AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]
|
|
OPERANDS : REG0=XED_REG_EAX:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : INVLPGA
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SVM
|
|
ATTRIBUTES: PROTECTED_MODE AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]
|
|
OPERANDS : REG0=ArAX():r:IMPL REG1=XED_REG_ECX:r:IMPL
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-sse4a.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
# EXTRQ xmm:w:q, imm8, imm8 66 0F 78 /0 ib ib
|
|
# EXTRQ xmm:w:q, xmm:r:w 66 0F 79 /r
|
|
|
|
{
|
|
ICLASS : EXTRQ
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : SSE4a
|
|
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY
|
|
PATTERN : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1()
|
|
OPERANDS : REG0=XMM_B():w:q IMM0:r:b IMM1:r:b
|
|
PATTERN : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq
|
|
}
|
|
|
|
# INSERTQ xmm:w:q xmm:r:q, imm8, imm8 f2 0f 78 /r ib ib
|
|
# INSERTQ xmm:w:q xmm:r:dq, f2 0f 79 /r
|
|
|
|
{
|
|
ICLASS : INSERTQ
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : SSE4a
|
|
ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY
|
|
PATTERN : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()
|
|
OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b IMM1:r:b
|
|
PATTERN : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq
|
|
}
|
|
|
|
|
|
# MOVNTSD mem64:w:q, xmm:r:q f2 0f 2b /r
|
|
# MOVNTSS mem32:w:d, xmm:r:d f3 0f 2b /r
|
|
|
|
{
|
|
ICLASS : MOVNTSD
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE4a
|
|
ATTRIBUTES: NONTEMPORAL AMDONLY
|
|
PATTERN : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:q
|
|
}
|
|
{
|
|
ICLASS : MOVNTSS
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : SSE4a
|
|
ATTRIBUTES: NONTEMPORAL AMDONLY
|
|
PATTERN : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:d
|
|
}
|
|
|
|
#########################################################################################################
|
|
# These next one is not part of SSE4a or SSE5.
|
|
|
|
# LZCNT reg16, reg/mem16 F30FBD /r
|
|
# LZCNT reg32, reg/mem32 F30FBD /r
|
|
# LZCNT reg64, reg/mem64 F30FBD /r
|
|
|
|
{
|
|
ICLASS : LZCNT
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : AMD
|
|
FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ]
|
|
PATTERN : 0x0F 0xBD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w:v MEM0:r:v
|
|
PATTERN : 0x0F 0xBD f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : BSR
|
|
VERSION : 1
|
|
COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
|
|
PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-clzero.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
{
|
|
ICLASS : CLZERO
|
|
CPL : 3
|
|
CATEGORY : CLZERO
|
|
EXTENSION : CLZERO
|
|
ATTRIBUTES : AMDONLY
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]
|
|
OPERANDS : REG0=ArAX():r:SUPP
|
|
COMMENT : AMD "Zen" ~2016 (expected) CPU
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-monitorx.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
{
|
|
ICLASS : MONITORX
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : MONITORX
|
|
ISA_SET : MONITORX
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16
|
|
OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode64
|
|
OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode32
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP
|
|
}
|
|
{
|
|
ICLASS : MWAITX
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : MONITORX
|
|
ISA_SET : MONITORX
|
|
ATTRIBUTES: AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix
|
|
OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-mcommit.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
{
|
|
ICLASS : MCOMMIT
|
|
CPL : 3
|
|
CATEGORY : MISC
|
|
EXTENSION : MCOMMIT
|
|
ISA_SET : MCOMMIT
|
|
ATTRIBUTES: AMDONLY
|
|
FLAGS : MUST [ cf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix
|
|
OPERANDS :
|
|
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-rdpru.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
{
|
|
ICLASS: RDPRU
|
|
CPL: 3
|
|
CATEGORY: RDPRU
|
|
EXTENSION: RDPRU
|
|
ISA_SET: RDPRU
|
|
ATTRIBUTES: AMDONLY
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]
|
|
OPERANDS: REG0=XED_REG_EDX:w:SUPP:d REG1=XED_REG_EAX:w:SUPP:d REG2=XED_REG_ECX:r:SUPP:d
|
|
IFORM: RDPRU
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-snp.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : PSMASH
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SNP
|
|
ATTRIBUTES: AMDONLY
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64
|
|
OPERANDS : REG0=XED_REG_RAX:rw:IMPL
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : PVALIDATE
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SNP
|
|
ATTRIBUTES: AMDONLY
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix
|
|
OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_ECX:r:IMPL REG2=XED_REG_EDX:r:IMPL
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : RMPADJUST
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SNP
|
|
ATTRIBUTES: AMDONLY
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64
|
|
OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL REG2=XED_REG_RDX:r:IMPL
|
|
}
|
|
|
|
{
|
|
ICLASS : RMPUPDATE
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : SNP
|
|
ATTRIBUTES: AMDONLY
|
|
FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64
|
|
OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-invlpgb.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : INVLPGB
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : AMD_INVLPGB
|
|
ATTRIBUTES: AMDONLY
|
|
COMMENT : Is this 64b mode only?
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32
|
|
OPERANDS : REG0=XED_REG_EAX:r:IMPL \
|
|
REG1=XED_REG_EDX:r:IMPL \
|
|
REG2=XED_REG_ECX:r:IMPL
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64
|
|
OPERANDS : REG0=XED_REG_RAX:r:IMPL \
|
|
REG1=XED_REG_EDX:r:IMPL \
|
|
REG2=XED_REG_ECX:r:IMPL
|
|
}
|
|
{
|
|
ICLASS : TLBSYNC
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : AMD_INVLPGB
|
|
ATTRIBUTES: AMDONLY
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
XOP_INSTRUCTIONS()::
|
|
{
|
|
ICLASS: VPMACSSWW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16
|
|
|
|
PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSSWD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
|
|
|
|
PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSSDQL
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
|
|
|
|
PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSWW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16
|
|
|
|
PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSWD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
|
|
|
|
PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSDQL
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
|
|
|
|
PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMOV
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1
|
|
|
|
PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1
|
|
|
|
PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1
|
|
|
|
PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1
|
|
|
|
PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1
|
|
|
|
PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1
|
|
|
|
PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1
|
|
|
|
PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1
|
|
}
|
|
|
|
{
|
|
ICLASS: VPPERM
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16
|
|
|
|
PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16
|
|
|
|
PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 REG3=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADCSSWD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
|
|
|
|
PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADCSWD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32
|
|
|
|
PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSSDD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32
|
|
|
|
PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSSDQH
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
|
|
|
|
PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSDD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32
|
|
|
|
PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMACSDQH
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64
|
|
|
|
PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMUB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMUW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMUD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCOMUQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8
|
|
|
|
PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VFRCZPS
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFRCZPD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64
|
|
|
|
PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFRCZSS
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFRCZSD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8
|
|
|
|
PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8
|
|
|
|
PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16
|
|
|
|
PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16
|
|
|
|
PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32
|
|
|
|
PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32
|
|
|
|
PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROTQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64
|
|
|
|
PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64
|
|
|
|
PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8
|
|
|
|
PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8
|
|
|
|
PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16
|
|
|
|
PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16
|
|
|
|
PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32
|
|
|
|
PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32
|
|
|
|
PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64
|
|
|
|
PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64
|
|
|
|
PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDBW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDBD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8
|
|
|
|
PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDBQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8
|
|
|
|
PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDWD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16
|
|
|
|
PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDWQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16
|
|
|
|
PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDUBW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8
|
|
|
|
PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDUBD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8
|
|
|
|
PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDUBQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8
|
|
|
|
PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDUWD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16
|
|
|
|
PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDUWQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16
|
|
|
|
PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHSUBBW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8
|
|
|
|
PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHSUBWD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16
|
|
|
|
PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHSUBDQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32
|
|
|
|
PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHAB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8
|
|
|
|
PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 REG2=XMM_N():r:dq:i8
|
|
|
|
PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHAW
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16
|
|
|
|
PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i16 REG2=XMM_N():r:dq:i16
|
|
|
|
PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHAD
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32
|
|
|
|
PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XMM_N():r:dq:i32
|
|
|
|
PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHAQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64
|
|
|
|
PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i64 REG2=XMM_N():r:dq:i64
|
|
|
|
PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64
|
|
|
|
PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDDQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32
|
|
|
|
PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPHADDUDQ
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: XOP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32
|
|
|
|
PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32
|
|
}
|
|
|
|
{
|
|
ICLASS: BEXTR_XOP
|
|
DISASM: bextr
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ]
|
|
|
|
PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
|
|
OPERANDS: REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:d
|
|
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
|
|
OPERANDS: REG0=VGPRy_R():w:y MEM0:r:y IMM0:r:d
|
|
|
|
PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
|
|
OPERANDS: REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:d
|
|
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
|
|
OPERANDS: REG0=VGPRy_R():w:y REG1=VGPRy_B():r:y IMM0:r:d
|
|
}
|
|
|
|
{
|
|
ICLASS: BLCFILL
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: BLSFILL
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: BLCS
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: TZMSK
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: BLCIC
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: BLSIC
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: T1MSKC
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: BLCMSK
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: BLCI
|
|
CPL: 3
|
|
CATEGORY: TBM
|
|
ISA_SET: TBM
|
|
EXTENSION: TBM
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ]
|
|
|
|
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d
|
|
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
|
|
|
|
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
|
|
}
|
|
|
|
{
|
|
ICLASS: LLWPCB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: LWP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_B():w:y
|
|
}
|
|
|
|
{
|
|
ICLASS: SLWPCB
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: LWP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS: REG0=VGPRy_B():w:y
|
|
}
|
|
|
|
{
|
|
ICLASS: LWPINS
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: LWP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
FLAGS: MUST [ cf-mod ]
|
|
|
|
PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d
|
|
|
|
PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32()
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d
|
|
}
|
|
|
|
{
|
|
ICLASS: LWPVAL
|
|
CPL: 3
|
|
CATEGORY: XOP
|
|
ISA_SET: LWP
|
|
EXTENSION: XOP
|
|
ATTRIBUTES: AMDONLY
|
|
|
|
PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32()
|
|
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d
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|
|
|
PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32()
|
|
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-fma4-isa.txt
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|
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#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
AVX_INSTRUCTIONS()::
|
|
{
|
|
ICLASS: VFMADDSUBPS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32
|
|
|
|
PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUBPD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64
|
|
|
|
PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADDPS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32
|
|
|
|
PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADDPD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64
|
|
|
|
PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDPS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32
|
|
|
|
PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDPD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64
|
|
|
|
PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
|
|
|
|
PATTERN: VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
|
|
|
|
PATTERN: VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBPS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32
|
|
|
|
PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBPD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64
|
|
|
|
PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBSS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
|
|
|
|
PATTERN: VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBSD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
|
|
|
|
PATTERN: VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADDPS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32
|
|
|
|
PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADDPD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64
|
|
|
|
PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADDSS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
|
|
|
|
PATTERN: VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADDSD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
|
|
|
|
PATTERN: VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUBPS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32
|
|
|
|
PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32
|
|
|
|
PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32
|
|
|
|
PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUBPD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64
|
|
|
|
PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64
|
|
|
|
PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64
|
|
|
|
PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUBSS
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32
|
|
|
|
PATTERN: VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32
|
|
|
|
PATTERN: VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUBSD
|
|
CPL: 3
|
|
CATEGORY: FMA4
|
|
ISA_SET: FMA4
|
|
EXTENSION: FMA4
|
|
ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY
|
|
|
|
PATTERN: VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64
|
|
|
|
PATTERN: VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64
|
|
|
|
PATTERN: VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-vpermil2-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
|
|
{
|
|
ICLASS : VPERMIL2PS
|
|
CPL : 3
|
|
CATEGORY : XOP
|
|
EXTENSION : XOP
|
|
ISA_SET : XOP
|
|
ATTRIBUTES : AMDONLY
|
|
|
|
# 128b W0
|
|
PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 IMM0:r:b
|
|
|
|
# 256b W0
|
|
PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 IMM0:r:b
|
|
|
|
# 128b W1
|
|
PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 IMM0:r:b
|
|
|
|
# 256b W1
|
|
PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 IMM0:r:b
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPERMIL2PD
|
|
CPL : 3
|
|
CATEGORY : XOP
|
|
EXTENSION : XOP
|
|
ISA_SET : XOP
|
|
ATTRIBUTES : AMDONLY
|
|
|
|
# 128b W0
|
|
PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 IMM0:r:b
|
|
|
|
# 256b W0
|
|
PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 IMM0:r:b
|
|
|
|
# 128b W1
|
|
PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 IMM0:r:b
|
|
|
|
# 256b W1
|
|
PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 IMM0:r:b
|
|
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
|
|
UDELETE: NOP0F1A
|
|
UDELETE: NOP0F1B
|
|
|
|
|
|
|
|
{
|
|
ICLASS: BNDMK
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES: NO_RIP_REL
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: REG0=BND_R():w AGEN:r
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS: BNDCL
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES: EXCEPTION_BR
|
|
COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them.
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: REG0=BND_R():r AGEN:r
|
|
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64
|
|
OPERANDS: REG0=BND_R():r REG1=GPR64_B():r
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64
|
|
OPERANDS: REG0=BND_R():r REG1=GPR32_B():r
|
|
}
|
|
|
|
{
|
|
ICLASS: BNDCU
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES: EXCEPTION_BR
|
|
COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them.
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix
|
|
OPERANDS: REG0=BND_R():r AGEN:r
|
|
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64
|
|
OPERANDS: REG0=BND_R():r REG1=GPR64_B():r
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64
|
|
OPERANDS: REG0=BND_R():r REG1=GPR32_B():r
|
|
}
|
|
|
|
{
|
|
ICLASS: BNDCN
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES: EXCEPTION_BR
|
|
COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them.
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix
|
|
OPERANDS: REG0=BND_R():r AGEN:r
|
|
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64
|
|
OPERANDS: REG0=BND_R():r REG1=GPR64_B():r
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64
|
|
OPERANDS: REG0=BND_R():r REG1=GPR32_B():r
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS: BNDMOV
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES:
|
|
COMMENT: load form
|
|
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()
|
|
OPERANDS: REG0=BND_R():w REG1=BND_B():r
|
|
|
|
# 16b refs 64b memop (2x32b) but only if EASZ=32b!
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32
|
|
OPERANDS: REG0=BND_R():w MEM0:r:q:u32
|
|
|
|
# 32b refs 64b memop (2x32b)
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32
|
|
OPERANDS: REG0=BND_R():w MEM0:r:q:u32
|
|
|
|
# 64b refs 128b memop (2x64b)
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64
|
|
OPERANDS: REG0=BND_R():w MEM0:r:dq:u64
|
|
|
|
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS: BNDMOV
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES:
|
|
COMMENT: store form
|
|
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()
|
|
OPERANDS: REG0=BND_B():w REG1=BND_R():r
|
|
|
|
# 16b refs 64b memop (2x32b) but only if EASZ=32b!
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32
|
|
OPERANDS: MEM0:w:q:u32 REG0=BND_R():r
|
|
|
|
# 32b refs 64b memop (2x32b)
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32
|
|
OPERANDS: MEM0:w:q:u32 REG0=BND_R():r
|
|
|
|
# 64b refs 128b memop (2x64b)
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64
|
|
OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS: BNDLDX
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL
|
|
COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32
|
|
OPERANDS: REG0=BND_R():w MEM0:r:bnd32
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5
|
|
OPERANDS: REG0=BND_R():w MEM0:r:bnd64
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64
|
|
OPERANDS: REG0=BND_R():w MEM0:r:bnd64
|
|
PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64
|
|
OPERANDS: REG0=BND_R():w MEM0:r:bnd64
|
|
}
|
|
|
|
{
|
|
ICLASS: BNDSTX
|
|
CPL: 3
|
|
EXTENSION: MPX
|
|
CATEGORY: MPX
|
|
ISA_SET: MPX
|
|
ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL
|
|
COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32
|
|
OPERANDS: MEM0:w:bnd32 REG0=BND_R():r
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5
|
|
OPERANDS: MEM0:w:bnd64 REG0=BND_R():r
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64
|
|
OPERANDS: MEM0:w:bnd64 REG0=BND_R():r
|
|
PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64
|
|
OPERANDS: MEM0:w:bnd64 REG0=BND_R():r
|
|
}
|
|
|
|
{
|
|
ICLASS : NOP
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
ATTRIBUTES: NOP
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO
|
|
COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs.
|
|
|
|
PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1A
|
|
|
|
PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1B
|
|
|
|
PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1B
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : NOP
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
ATTRIBUTES: NOP
|
|
EXTENSION : BASE
|
|
ISA_SET : PPRO
|
|
COMMENT : For MPXMODE=0 operation
|
|
|
|
PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1A
|
|
|
|
PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1B
|
|
|
|
PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_B():r MEM0:r:v
|
|
IFORM : NOP_GPRv_MEMv_0F1A
|
|
|
|
PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_B():r MEM0:r:v
|
|
IFORM : NOP_GPRv_MEM_0F1B
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-nop-remove.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
UDELETE: NOP0F1E
|
|
|
|
{
|
|
ICLASS : NOP
|
|
#UNAME : NOP0F1E
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : PPRO
|
|
COMMENT : reg form MODRM.MOD=3 & MODRM.REG=0b001 f3 prefix is RDSSP{D,Q}
|
|
|
|
# mem forms
|
|
|
|
PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1E
|
|
|
|
|
|
# reg forms
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
# ...
|
|
# F3 with MODRM.REG=0b001 is for CET for all values of RM.
|
|
# ...
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
# ...
|
|
# F3 with MODRM.REG=0b111 with RM=2 or RM=3 is for CET
|
|
# ...
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
|
|
}
|
|
|
|
|
|
# REPLACE CERTAIN NOPS WITH MODAL OPTIONS basd on CET=0/1
|
|
{
|
|
ICLASS : NOP
|
|
#UNAME : NOP0F1E
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : PPRO
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : NOP
|
|
#UNAME : NOP0F1E
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : PPRO
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
|
|
PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1E
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING CLRSSBSY (CLRSSBSY-N/A-1)
|
|
{
|
|
ICLASS: CLRSSBSY
|
|
CPL: 0
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()
|
|
OPERANDS: MEM0:rw:q:u64
|
|
IFORM: CLRSSBSY_MEMu64
|
|
}
|
|
|
|
|
|
# EMITTING ENDBR32 (ENDBR32-N/A-1)
|
|
{
|
|
ICLASS: ENDBR32
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1
|
|
OPERANDS:
|
|
IFORM: ENDBR32
|
|
}
|
|
|
|
|
|
# EMITTING ENDBR64 (ENDBR64-N/A-1)
|
|
{
|
|
ICLASS: ENDBR64
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1
|
|
OPERANDS:
|
|
IFORM: ENDBR64
|
|
}
|
|
|
|
|
|
# EMITTING INCSSPD (INCSSPD-N/A-1)
|
|
{
|
|
ICLASS: INCSSPD
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0
|
|
OPERANDS: REG0=GPR32_B():r:d:u8 REG1=XED_REG_SSP:rw:SUPP:u64
|
|
IFORM: INCSSPD_GPR32u8
|
|
}
|
|
|
|
|
|
# EMITTING INCSSPQ (INCSSPQ-N/A-1)
|
|
{
|
|
ICLASS: INCSSPQ
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64
|
|
OPERANDS: REG0=GPR64_B():r:q:u8 REG1=XED_REG_SSP:rw:SUPP:u64
|
|
IFORM: INCSSPQ_GPR64u8
|
|
}
|
|
|
|
|
|
# EMITTING RDSSPD (RDSSPD-N/A-1)
|
|
{
|
|
ICLASS: RDSSPD
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1
|
|
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_SSP:r:SUPP:u64
|
|
IFORM: RDSSPD_GPR32u32
|
|
}
|
|
|
|
|
|
# EMITTING RDSSPQ (RDSSPQ-N/A-1)
|
|
{
|
|
ICLASS: RDSSPQ
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1
|
|
OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_SSP:r:SUPP:u64
|
|
IFORM: RDSSPQ_GPR64u64
|
|
}
|
|
|
|
|
|
# EMITTING RSTORSSP (RSTORSSP-N/A-1)
|
|
{
|
|
ICLASS: RSTORSSP
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: MEM0:rw:q:u64 REG0=XED_REG_SSP:w:SUPP:u64
|
|
IFORM: RSTORSSP_MEMu64
|
|
}
|
|
|
|
|
|
# EMITTING SAVEPREVSSP (SAVEPREVSSP-N/A-1)
|
|
{
|
|
ICLASS: SAVEPREVSSP
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix
|
|
OPERANDS: REG0=XED_REG_SSP:r:SUPP:u64
|
|
IFORM: SAVEPREVSSP
|
|
}
|
|
|
|
|
|
# EMITTING SETSSBSY (SETSSBSY-N/A-1)
|
|
{
|
|
ICLASS: SETSSBSY
|
|
CPL: 0
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix
|
|
OPERANDS:
|
|
IFORM: SETSSBSY
|
|
}
|
|
|
|
|
|
# EMITTING WRSSD (WRSSD-N/A-1)
|
|
{
|
|
ICLASS: WRSSD
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0
|
|
OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
|
|
IFORM: WRSSD_MEMu32_GPR32u32
|
|
}
|
|
|
|
|
|
# EMITTING WRSSQ (WRSSQ-N/A-1)
|
|
{
|
|
ICLASS: WRSSQ
|
|
CPL: 3
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64
|
|
OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
|
|
IFORM: WRSSQ_MEMu64_GPR64u64
|
|
}
|
|
|
|
|
|
# EMITTING WRUSSD (WRUSSD-N/A-1)
|
|
{
|
|
ICLASS: WRUSSD
|
|
CPL: 0
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0
|
|
OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
|
|
IFORM: WRUSSD_MEMu32_GPR32u32
|
|
}
|
|
|
|
|
|
# EMITTING WRUSSQ (WRUSSQ-N/A-1)
|
|
{
|
|
ICLASS: WRUSSQ
|
|
CPL: 0
|
|
CATEGORY: CET
|
|
EXTENSION: CET
|
|
ISA_SET: CET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64
|
|
OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
|
|
IFORM: WRUSSQ_MEMu64_GPR64u64
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdrand/rdrand-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : RDRAND
|
|
CPL : 3
|
|
CATEGORY : RDRAND
|
|
EXTENSION : RDRAND
|
|
ISA_SET : RDRAND
|
|
FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ]
|
|
PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining
|
|
OPERANDS : REG0=GPRv_B():w
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/sha/sha-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING SHA1MSG1 (SHA1MSG1-N/A-1)
|
|
{
|
|
ICLASS: SHA1MSG1
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
IFORM: SHA1MSG1_XMMi32_XMMi32_SHA
|
|
}
|
|
|
|
{
|
|
ICLASS: SHA1MSG1
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
IFORM: SHA1MSG1_XMMi32_MEMi32_SHA
|
|
}
|
|
|
|
|
|
# EMITTING SHA1MSG2 (SHA1MSG2-N/A-1)
|
|
{
|
|
ICLASS: SHA1MSG2
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
IFORM: SHA1MSG2_XMMi32_XMMi32_SHA
|
|
}
|
|
|
|
{
|
|
ICLASS: SHA1MSG2
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
IFORM: SHA1MSG2_XMMi32_MEMi32_SHA
|
|
}
|
|
|
|
|
|
# EMITTING SHA1NEXTE (SHA1NEXTE-N/A-1)
|
|
{
|
|
ICLASS: SHA1NEXTE
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
IFORM: SHA1NEXTE_XMMi32_XMMi32_SHA
|
|
}
|
|
|
|
{
|
|
ICLASS: SHA1NEXTE
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
IFORM: SHA1NEXTE_XMMi32_MEMi32_SHA
|
|
}
|
|
|
|
|
|
# EMITTING SHA1RNDS4 (SHA1RNDS4-N/A-1)
|
|
{
|
|
ICLASS: SHA1RNDS4
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8()
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b
|
|
IFORM: SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA
|
|
}
|
|
|
|
{
|
|
ICLASS: SHA1RNDS4
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8()
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 IMM0:r:b
|
|
IFORM: SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA
|
|
}
|
|
|
|
|
|
# EMITTING SHA256MSG1 (SHA256MSG1-N/A-1)
|
|
{
|
|
ICLASS: SHA256MSG1
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
IFORM: SHA256MSG1_XMMi32_XMMi32_SHA
|
|
}
|
|
|
|
{
|
|
ICLASS: SHA256MSG1
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
IFORM: SHA256MSG1_XMMi32_MEMi32_SHA
|
|
}
|
|
|
|
|
|
# EMITTING SHA256MSG2 (SHA256MSG2-N/A-1)
|
|
{
|
|
ICLASS: SHA256MSG2
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32
|
|
IFORM: SHA256MSG2_XMMi32_XMMi32_SHA
|
|
}
|
|
|
|
{
|
|
ICLASS: SHA256MSG2
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32
|
|
IFORM: SHA256MSG2_XMMi32_MEMi32_SHA
|
|
}
|
|
|
|
|
|
# EMITTING SHA256RNDS2 (SHA256RNDS2-N/A-1)
|
|
{
|
|
ICLASS: SHA256RNDS2
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XED_REG_XMM0:r:SUPP:dq:u8
|
|
IFORM: SHA256RNDS2_XMMi32_XMMi32_SHA
|
|
}
|
|
|
|
{
|
|
ICLASS: SHA256RNDS2
|
|
CPL: 3
|
|
CATEGORY: SHA
|
|
EXTENSION: SHA
|
|
ISA_SET: SHA
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 REG1=XED_REG_XMM0:r:SUPP:dq:u8
|
|
IFORM: SHA256RNDS2_XMMi32_MEMi32_SHA
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaveopt/xsaveopt-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : XSAVEOPT
|
|
CPL : 3
|
|
CATEGORY : XSAVEOPT
|
|
EXTENSION : XSAVEOPT
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX
|
|
COMMENT : Variable length Store and conditional reg read. reads/modifies header.
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM()
|
|
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR
|
|
OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XSAVEOPT64
|
|
CPL : 3
|
|
CATEGORY : XSAVEOPT
|
|
EXTENSION : XSAVEOPT
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX
|
|
COMMENT : Variable length Store and conditional reg read. reads/modifies header.
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM()
|
|
#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR
|
|
OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaves/xsaves-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : XSAVES
|
|
CPL : 0
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVES
|
|
COMMENT : variable length store and conditional reg read. does not read header
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix
|
|
OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XSAVES64
|
|
CPL : 0
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVES
|
|
COMMENT : variable length store and conditional reg read. does not read header
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix
|
|
OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : XRSTORS
|
|
CPL : 0
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVES
|
|
COMMENT : variable length load and conditional reg write.
|
|
ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix
|
|
OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XRSTORS64
|
|
CPL : 0
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVES
|
|
COMMENT : variable length load and conditional reg write
|
|
ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix
|
|
OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsavec/xsavec-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : XSAVEC
|
|
CPL : 3
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVEC
|
|
COMMENT : Variable length store and conditional reg read. does not read header
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix
|
|
OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : XSAVEC64
|
|
CPL : 3
|
|
CATEGORY : XSAVE
|
|
EXTENSION : XSAVEC
|
|
COMMENT : Variable length store and conditional reg read. does not read header
|
|
ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix
|
|
OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/clflushopt/clflushopt.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS: CLFLUSHOPT
|
|
CPL: 3
|
|
CATEGORY: CLFLUSHOPT
|
|
EXTENSION: CLFLUSHOPT
|
|
ISA_SET: CLFLUSHOPT
|
|
ATTRIBUTES: PREFETCH # check TSX-friendlyness
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdseed/rdseed-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : RDSEED
|
|
CPL : 3
|
|
CATEGORY : RDSEED
|
|
EXTENSION : RDSEED
|
|
ISA_SET : RDSEED
|
|
FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ]
|
|
PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining
|
|
OPERANDS : REG0=GPRv_B():w
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/fsgsbase/fsgsbase-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
|
|
{
|
|
ICLASS : RDFSBASE
|
|
CPL : 3
|
|
CATEGORY : RDWRFSGS
|
|
EXTENSION : RDWRFSGS
|
|
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix
|
|
OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y
|
|
|
|
}
|
|
{
|
|
ICLASS : RDGSBASE
|
|
CPL : 3
|
|
CATEGORY : RDWRFSGS
|
|
EXTENSION : RDWRFSGS
|
|
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix
|
|
OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : WRFSBASE
|
|
CPL : 3
|
|
CATEGORY : RDWRFSGS
|
|
EXTENSION : RDWRFSGS
|
|
ATTRIBUTES: NOTSX
|
|
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix
|
|
OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y
|
|
|
|
}
|
|
{
|
|
ICLASS : WRGSBASE
|
|
CPL : 3
|
|
CATEGORY : RDWRFSGS
|
|
EXTENSION : RDWRFSGS
|
|
ATTRIBUTES: NOTSX
|
|
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix
|
|
OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y
|
|
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/smap/smap-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : CLAC
|
|
CPL : 0
|
|
CATEGORY : SMAP
|
|
EXTENSION : SMAP
|
|
FLAGS : MUST [ ac-0 ]
|
|
# 0F 01 CA = 1100_1010 = 11_001_010
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
|
|
{
|
|
ICLASS : STAC
|
|
CPL : 0
|
|
CATEGORY : SMAP
|
|
EXTENSION : SMAP
|
|
FLAGS : MUST [ ac-1 ]
|
|
# 0F 01 CB = 1100_1011 = 11_001_011
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/sgx/sgx-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
# Both read EAX
|
|
# Both may read or write or r/w RBX, RCX, RDX
|
|
# ENCLU 0f 01 D7
|
|
# D7 = 1101 0111
|
|
|
|
# ENCLS 0f 01 CF
|
|
# CF = 1100_1111
|
|
|
|
|
|
|
|
{
|
|
ICLASS: ENCLU
|
|
CPL: 3
|
|
CATEGORY: SGX
|
|
EXTENSION: SGX
|
|
ISA_SET: SGX
|
|
COMMENT: May set flags
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix
|
|
OPERANDS: REG0=XED_REG_EAX:r:SUPP \
|
|
REG1=XED_REG_RBX:crw:SUPP \
|
|
REG2=XED_REG_RCX:crw:SUPP \
|
|
REG3=XED_REG_RDX:crw:SUPP
|
|
}
|
|
|
|
{
|
|
|
|
ICLASS: ENCLS
|
|
CPL: 0
|
|
CATEGORY: SGX
|
|
EXTENSION: SGX
|
|
ISA_SET: SGX
|
|
COMMENT: May set flags
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix
|
|
OPERANDS: REG0=XED_REG_EAX:r:SUPP \
|
|
REG1=XED_REG_RBX:crw:SUPP \
|
|
REG2=XED_REG_RCX:crw:SUPP \
|
|
REG3=XED_REG_RDX:crw:SUPP
|
|
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdpid/rdpid-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING RDPID (RDPID-N/A-1-32)
|
|
{
|
|
ICLASS: RDPID
|
|
CPL: 3
|
|
CATEGORY: RDPID
|
|
EXTENSION: RDPID
|
|
ISA_SET: RDPID
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64
|
|
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_TSCAUX:r:SUPP:d:u32
|
|
IFORM: RDPID_GPR32u32
|
|
}
|
|
|
|
|
|
# EMITTING RDPID (RDPID-N/A-1-64)
|
|
{
|
|
ICLASS: RDPID
|
|
CPL: 3
|
|
CATEGORY: RDPID
|
|
EXTENSION: RDPID
|
|
ISA_SET: RDPID
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64
|
|
OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_TSCAUX:r:SUPP:d:u32
|
|
IFORM: RDPID_GPR64u64
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/pt/intelpt-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
INSTRUCTIONS()::
|
|
{
|
|
ICLASS : PTWRITE
|
|
CPL : 3
|
|
CATEGORY : PTWRITE
|
|
EXTENSION : PTWRITE
|
|
ISA_SET : PTWRITE
|
|
PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix
|
|
OPERANDS : REG0=GPRy_B():r
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()
|
|
OPERANDS : MEM0:r:y
|
|
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/movdir/movdir-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING MOVDIR64B (MOVDIR64B-N/A-1)
|
|
{
|
|
ICLASS: MOVDIR64B
|
|
CPL: 3
|
|
CATEGORY: MOVDIR
|
|
EXTENSION: MOVDIR
|
|
ISA_SET: MOVDIR
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix not64
|
|
OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP SEG1=XED_REG_ES:r:SUPP
|
|
IFORM: MOVDIR64B_GPRa_MEM
|
|
|
|
PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix mode64
|
|
OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP
|
|
IFORM: MOVDIR64B_GPRa_MEM
|
|
}
|
|
|
|
|
|
# EMITTING MOVDIRI (MOVDIRI-N/A-1-32)
|
|
{
|
|
ICLASS: MOVDIRI
|
|
CPL: 3
|
|
CATEGORY: MOVDIR
|
|
EXTENSION: MOVDIR
|
|
ISA_SET: MOVDIR
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix
|
|
OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32
|
|
IFORM: MOVDIRI_MEMu32_GPR32u32
|
|
}
|
|
|
|
|
|
# EMITTING MOVDIRI (MOVDIRI-N/A-1-64)
|
|
{
|
|
ICLASS: MOVDIRI
|
|
CPL: 3
|
|
CATEGORY: MOVDIR
|
|
EXTENSION: MOVDIR
|
|
ISA_SET: MOVDIR
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 rexw_prefix
|
|
OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64
|
|
IFORM: MOVDIRI_MEMu64_GPR64u64
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/waitpkg/waitpkg-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING TPAUSE (TPAUSE-N/A-1-32)
|
|
{
|
|
ICLASS: TPAUSE
|
|
CPL: 3
|
|
CATEGORY: WAITPKG
|
|
EXTENSION: WAITPKG
|
|
ISA_SET: WAITPKG
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ]
|
|
PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix
|
|
OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32
|
|
IFORM: TPAUSE_GPR32u32
|
|
}
|
|
|
|
|
|
|
|
# EMITTING UMONITOR (UMONITOR-N/A-1)
|
|
{
|
|
ICLASS: UMONITOR
|
|
CPL: 3
|
|
CATEGORY: WAITPKG
|
|
EXTENSION: WAITPKG
|
|
ISA_SET: WAITPKG
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix
|
|
OPERANDS: REG0=A_GPR_B():r
|
|
IFORM: UMONITOR_GPRa
|
|
}
|
|
|
|
|
|
# EMITTING UMWAIT (UMWAIT-N/A-1-32)
|
|
{
|
|
ICLASS: UMWAIT
|
|
CPL: 3
|
|
CATEGORY: WAITPKG
|
|
EXTENSION: WAITPKG
|
|
ISA_SET: WAITPKG
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ]
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix
|
|
OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32
|
|
IFORM: UMWAIT_GPR32
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cldemote-nop-mod.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
UDELETE: NOP0F1C
|
|
|
|
{
|
|
ICLASS : NOP
|
|
#UNAME : NOP0F1C
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : PPRO
|
|
COMMENT : memory form with MODRM.REG=0b000 and no refining prefix is CLDEMOTE
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
|
|
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
}
|
|
|
|
# re-defined by another contemporaneous ISA extension
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F1C_REG
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : PPRO
|
|
|
|
# reg form
|
|
PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r
|
|
IFORM : NOP_GPRv_GPRv_0F1C
|
|
}
|
|
|
|
{
|
|
ICLASS : NOP
|
|
UNAME : NOP0F1C_MEM
|
|
CPL : 3
|
|
CATEGORY : WIDENOP
|
|
EXTENSION : BASE
|
|
ATTRIBUTES: NOP
|
|
ISA_SET : PPRO
|
|
|
|
PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=0
|
|
OPERANDS : MEM0:r:v REG0=GPRv_R():r
|
|
IFORM : NOP_MEMv_GPRv_0F1C
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cldemote-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING CLDEMOTE (CLDEMOTE-N/A-1)
|
|
{
|
|
ICLASS: CLDEMOTE
|
|
CPL: 3
|
|
CATEGORY: CLDEMOTE
|
|
EXTENSION: CLDEMOTE
|
|
ISA_SET: CLDEMOTE
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=1
|
|
OPERANDS: MEM0:r:b:u8
|
|
IFORM: CLDEMOTE_MEMu8
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/sgx-enclv/sgx-enclv-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING ENCLV (ENCLV-N/A-1)
|
|
{
|
|
ICLASS: ENCLV
|
|
CPL: 3
|
|
CATEGORY: SGX
|
|
EXTENSION: SGX_ENCLV
|
|
ISA_SET: SGX_ENCLV
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix
|
|
OPERANDS: REG0=XED_REG_EAX:r:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64
|
|
IFORM: ENCLV
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
# The neat thing is we can just end a nonterminal by starting a new one.
|
|
|
|
AVX_INSTRUCTIONS()::
|
|
{
|
|
ICLASS : VADDPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VADDPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VADDSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VADDSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VADDSUBPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VADDSUBPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VANDPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
|
|
PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VANDPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VANDNPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
|
|
PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VANDNPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VBLENDPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VBLENDPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VCMPPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VCMPPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VCMPSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VCMPSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCOMISD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ]
|
|
PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VCOMISS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ]
|
|
PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCVTDQ2PD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
COMMENT : ignores MXCSR. 32b int fits in f64
|
|
PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32
|
|
|
|
PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32
|
|
|
|
PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VCVTDQ2PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32
|
|
|
|
PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VCVTPD2DQ
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCVTTPD2DQ
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCVTPD2PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VCVTPS2DQ
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VCVTTPS2DQ
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VCVTPS2PD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f32
|
|
|
|
PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f32
|
|
|
|
PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f32
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VCVTSD2SI
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
|
|
|
|
PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
|
|
|
|
|
|
PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VCVTTSD2SI
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
|
|
|
|
|
|
PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VCVTSS2SI
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
|
|
|
|
PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
|
|
|
|
|
|
PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VCVTTSS2SI
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG
|
|
|
|
PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32
|
|
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VCVTSD2SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCVTSI2SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32
|
|
|
|
PATTERN : VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32
|
|
|
|
PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:i64
|
|
|
|
PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR64_B():r:q:i64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCVTSI2SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32
|
|
|
|
PATTERN : VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32
|
|
|
|
PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32
|
|
|
|
|
|
|
|
PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64
|
|
|
|
PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR64_B():r:q:i64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCVTSS2SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VDIVPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VDIVPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VDIVSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VDIVSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VEXTRACTF128
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:dq:f64 REG0=YMM_R():r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_B():w:dq:f64 REG1=YMM_R():r:dq:f64 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VDPPD
|
|
EXCEPTIONS: avx-type-2D
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : VDPPS
|
|
EXCEPTIONS: avx-type-2D
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VEXTRACTPS
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq:f32 IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VZEROALL
|
|
EXCEPTIONS: avx-type-8
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : xmm_state_w
|
|
|
|
PATTERN : VV1 0x77 VNP V0F VL256 NOVSR
|
|
OPERANDS:
|
|
|
|
}
|
|
|
|
# FIXME: how to denote partial upper clobber!
|
|
{
|
|
ICLASS : VZEROUPPER
|
|
EXCEPTIONS: avx-type-8
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : xmm_state_w NOTSX # FIXME: should be ymm_state_w?
|
|
|
|
PATTERN : VV1 0x77 VNP V0F VL128 NOVSR
|
|
OPERANDS:
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VHADDPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VHADDPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VHSUBPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VHSUBPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPERMILPD
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
# 2008-02-01 moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPD
|
|
PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:u64
|
|
|
|
PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:u64
|
|
|
|
########################################
|
|
# IMMEDIATE FORM
|
|
########################################
|
|
|
|
# 2008-02-01 moved norexw_prefix to after V0F3A to avoid a graph build conflict with VPHSUBW
|
|
PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPERMILPS
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
# moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPS
|
|
PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:u32
|
|
|
|
PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:u32
|
|
|
|
########################################
|
|
# IMMEDIATE FORM
|
|
########################################
|
|
|
|
# 2008-02-01: moved norexw_prefix after V0F3A due to graph-build collision with VPMADDUBSW
|
|
PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPERM2F128
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
|
|
# 2008-02-01 moved norexw_prefix to after V0F3A to avoid conflict with VPHSUBD
|
|
PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VBROADCASTSS
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO4_32
|
|
|
|
PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO8_32
|
|
}
|
|
{
|
|
ICLASS : VBROADCASTSD
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:q:f64 EMX_BROADCAST_1TO4_64
|
|
}
|
|
|
|
{
|
|
ICLASS : VBROADCASTF128
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX
|
|
COMMENT : There is no F128 type. I just set these to f64 for lack of anything better.
|
|
PATTERN : VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VINSERTF128
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64
|
|
|
|
PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64
|
|
}
|
|
|
|
{
|
|
ICLASS : VINSERTPS
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VLDDQU
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMASKMOVPS
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : maskop NONTEMPORAL
|
|
# load forms
|
|
PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq MEM0:r:qq:f32
|
|
|
|
# store forms
|
|
PATTERN : VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f32 REG0=XMM_N():r:dq REG1=XMM_R():r:dq:f32
|
|
|
|
PATTERN : VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f32 REG0=YMM_N():r:qq REG1=YMM_R():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VMASKMOVPD
|
|
EXCEPTIONS: avx-type-6
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : maskop
|
|
# load forms
|
|
PATTERN : VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:f64
|
|
|
|
# store forms
|
|
PATTERN : VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:f64
|
|
|
|
PATTERN : VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPTEST
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ zf-mod cf-mod ]
|
|
PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():r:qq REG1=YMM_B():r:qq
|
|
}
|
|
|
|
{
|
|
ICLASS : VTESTPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ zf-mod cf-mod ]
|
|
PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():r:qq:f32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VTESTPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ zf-mod cf-mod ]
|
|
PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():r:qq:f64 REG1=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VMAXPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VMAXPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMAXSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VMAXSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VMINPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VMINPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMINSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VMINSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
PATTERN : VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VMOVAPD
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
|
|
# 128b load
|
|
|
|
PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64
|
|
IFORM : VMOVAPD_XMMdq_XMMdq_28
|
|
|
|
# 128b store
|
|
|
|
PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64
|
|
|
|
PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64
|
|
IFORM : VMOVAPD_XMMdq_XMMdq_29
|
|
|
|
# 256b load
|
|
|
|
PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64
|
|
IFORM : VMOVAPD_YMMqq_YMMqq_28
|
|
|
|
# 256b store
|
|
|
|
PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64
|
|
|
|
PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64
|
|
IFORM : VMOVAPD_YMMqq_YMMqq_29
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMOVAPS
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
|
|
# 128b load
|
|
|
|
PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
IFORM : VMOVAPS_XMMdq_XMMdq_28
|
|
# 128b store
|
|
|
|
PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32
|
|
|
|
PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32
|
|
IFORM : VMOVAPS_XMMdq_XMMdq_29
|
|
|
|
# 256b load
|
|
|
|
PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
IFORM : VMOVAPS_YMMqq_YMMqq_28
|
|
|
|
# 256b store
|
|
|
|
PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32
|
|
|
|
PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32
|
|
IFORM : VMOVAPS_YMMqq_YMMqq_29
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMOVD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
# 32b load
|
|
PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:d
|
|
|
|
PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d
|
|
|
|
# 32b store
|
|
PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:d
|
|
|
|
PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d
|
|
|
|
|
|
|
|
# 32b load
|
|
PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:d
|
|
|
|
PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d
|
|
|
|
# 32b store
|
|
PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:d
|
|
|
|
PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d
|
|
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VMOVQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
# 64b load
|
|
PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:q
|
|
IFORM : VMOVQ_XMMdq_MEMq_6E
|
|
|
|
PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r:q
|
|
|
|
# 64b store
|
|
PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:q
|
|
IFORM : VMOVQ_MEMq_XMMq_7E
|
|
|
|
PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:q
|
|
|
|
|
|
# 2nd page of MOVQ forms
|
|
PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:q
|
|
IFORM : VMOVQ_XMMdq_MEMq_7E
|
|
|
|
PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q
|
|
IFORM : VMOVQ_XMMdq_XMMq_7E
|
|
|
|
PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:q
|
|
IFORM : VMOVQ_MEMq_XMMq_D6
|
|
|
|
PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q
|
|
IFORM : VMOVQ_XMMdq_XMMq_D6
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMOVDDUP
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64
|
|
|
|
|
|
PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMOVDQA
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT
|
|
|
|
# LOAD XMM
|
|
|
|
PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
IFORM : VMOVDQA_XMMdq_XMMdq_6F
|
|
|
|
# STORE XMM
|
|
|
|
PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq
|
|
|
|
PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq
|
|
IFORM : VMOVDQA_XMMdq_XMMdq_7F
|
|
|
|
# LOAD YMM
|
|
|
|
PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq
|
|
IFORM : VMOVDQA_YMMqq_YMMqq_6F
|
|
|
|
|
|
# STORE YMM
|
|
|
|
PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq
|
|
|
|
PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq
|
|
IFORM : VMOVDQA_YMMqq_YMMqq_7F
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VMOVDQU
|
|
EXCEPTIONS: avx-type-4M
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
# LOAD XMM
|
|
|
|
PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
IFORM : VMOVDQU_XMMdq_XMMdq_6F
|
|
|
|
# LOAD YMM
|
|
|
|
PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq
|
|
IFORM : VMOVDQU_YMMqq_YMMqq_6F
|
|
|
|
# STORE XMM
|
|
|
|
PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq
|
|
|
|
PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq
|
|
IFORM : VMOVDQU_XMMdq_XMMdq_7F
|
|
|
|
# STORE YMM
|
|
|
|
PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq
|
|
|
|
PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq
|
|
IFORM : VMOVDQU_YMMqq_YMMqq_7F
|
|
}
|
|
|
|
#################################################
|
|
## skipping to the end
|
|
#################################################
|
|
|
|
#################################################
|
|
## MACROS
|
|
#################################################
|
|
{
|
|
ICLASS : VMOVSHDUP
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VMOVSLDUP
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPOR
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128
|
|
|
|
PATTERN : VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128
|
|
}
|
|
{
|
|
ICLASS : VPAND
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128
|
|
|
|
PATTERN : VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128
|
|
}
|
|
{
|
|
ICLASS : VPANDN
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128
|
|
|
|
PATTERN : VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128
|
|
}
|
|
{
|
|
ICLASS : VPXOR
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128
|
|
|
|
PATTERN : VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPABSB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPABSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPABSD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPHMINPOSUW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPSHUFD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b
|
|
|
|
PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VPSHUFHW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b
|
|
|
|
PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VPSHUFLW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b
|
|
|
|
PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPACKSSWB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPACKSSDW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : VPACKUSWB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPACKUSDW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSLLW
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : VPSLLD
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : VPSLLQ
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRLW
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : VPSRLD
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : VPSRLQ
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRAW
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:u64
|
|
}
|
|
{
|
|
ICLASS : VPSRAD
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPADDB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPADDW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPADDD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : VPADDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64
|
|
|
|
PATTERN : VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPADDSB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPADDSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPADDUSB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPADDUSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPAVGB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPAVGW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPCMPEQB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPCMPEQW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : VPCMPEQD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
{
|
|
ICLASS : VPCMPEQQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPCMPGTB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPCMPGTW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPCMPGTD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : VPCMPGTQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64
|
|
|
|
PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPHADDW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPHADDD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : VPHADDSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPHSUBW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPHSUBD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : VPHSUBSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMULHUW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : VPMULHRSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMULHW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMULLW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMULLD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMULUDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
{
|
|
ICLASS : VPMULDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSADBW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPSHUFB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSIGNB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPSIGNW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPSIGND
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSUBSB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPSUBSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSUBUSB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPSUBUSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSUBB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPSUBW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPSUBD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
{
|
|
ICLASS : VPSUBQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64
|
|
|
|
PATTERN : VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPUNPCKHBW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKHWD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKHDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKHQDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPUNPCKLBW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKLWD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKLDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKLQDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPSRLDQ
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSLLDQ
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMOVLHPS
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 REG2=XMM_B():r:q:f32
|
|
}
|
|
{
|
|
ICLASS : VMOVHLPS
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPALIGNR
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VPBLENDW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
############################################################
|
|
{
|
|
ICLASS : VROUNDPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VROUNDPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VROUNDSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
PATTERN : VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VROUNDSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
PATTERN : VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : VSHUFPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VSHUFPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : VRCPPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VRCPSS
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: simd_scalar
|
|
PATTERN : VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VRSQRTPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VRSQRTSS
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: simd_scalar
|
|
PATTERN : VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VSQRTPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VSQRTPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VSQRTSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : MXCSR simd_scalar
|
|
PATTERN : VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
{
|
|
ICLASS : VSQRTSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
PATTERN : VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VUNPCKHPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VUNPCKHPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VSUBPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VSUBPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VSUBSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : MXCSR SIMD_SCALAR
|
|
PATTERN : VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
{
|
|
ICLASS : VSUBSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
PATTERN : VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VMULPD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VMULPS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VMULSD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : MXCSR simd_scalar
|
|
PATTERN : VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
{
|
|
ICLASS : VMULSS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
PATTERN : VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VORPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
|
|
PATTERN : VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
|
|
}
|
|
{
|
|
ICLASS : VORPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
|
|
PATTERN : VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMAXSB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPMAXSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMAXSD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMAXUB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPMAXUW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : VPMAXUD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMINSB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
{
|
|
ICLASS : VPMINSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMINSD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32
|
|
|
|
PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMINUB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
|
|
PATTERN : VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
}
|
|
{
|
|
ICLASS : VPMINUW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16
|
|
|
|
PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16
|
|
}
|
|
{
|
|
ICLASS : VPMINUD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPMADDWD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16
|
|
|
|
PATTERN : VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMADDUBSW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:i8
|
|
|
|
PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:i8
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VMPSADBW
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b
|
|
}
|
|
|
|
|
|
############################################################
|
|
{
|
|
ICLASS : VPSLLW
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSLLD
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b #NDD
|
|
}
|
|
{
|
|
ICLASS : VPSLLQ
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRAW
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:i16 REG1=XMM_B():r:dq:i16 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRAD
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRLW
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRLD
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRLQ
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VUCOMISD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ]
|
|
|
|
PATTERN : VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VUCOMISS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar MXCSR
|
|
|
|
FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ]
|
|
|
|
PATTERN : VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:d:f32
|
|
}
|
|
|
|
###############################################
|
|
|
|
|
|
{
|
|
ICLASS : VUNPCKLPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
PATTERN : VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VUNPCKLPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
PATTERN : VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VXORPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
|
|
|
|
PATTERN : VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VXORPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : LOGICAL_FP
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
}
|
|
|
|
|
|
############################################################################
|
|
|
|
{
|
|
ICLASS : VMOVSS
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar
|
|
|
|
# NOTE: REG1 is ignored!!!
|
|
PATTERN : VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32
|
|
|
|
PATTERN : VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32
|
|
IFORM : VMOVSS_XMMdq_XMMdq_XMMd_10
|
|
|
|
PATTERN : VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:d:f32
|
|
|
|
PATTERN : VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_R():r:d:f32
|
|
IFORM : VMOVSS_XMMdq_XMMdq_XMMd_11
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VMOVSD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : simd_scalar
|
|
|
|
# NOTE: REG1 is ignored!!!
|
|
PATTERN : VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64
|
|
IFORM : VMOVSD_XMMdq_XMMdq_XMMq_10
|
|
|
|
PATTERN : VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64
|
|
|
|
PATTERN : VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_R():r:q:f64
|
|
IFORM : VMOVSD_XMMdq_XMMdq_XMMq_11
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VMOVUPD
|
|
EXCEPTIONS: avx-type-4M
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64
|
|
|
|
PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64
|
|
IFORM : VMOVUPD_XMMdq_XMMdq_10
|
|
|
|
PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64
|
|
|
|
PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64
|
|
IFORM : VMOVUPD_XMMdq_XMMdq_11
|
|
|
|
# 256b versions
|
|
|
|
PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64
|
|
|
|
PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64
|
|
IFORM : VMOVUPD_YMMqq_YMMqq_10
|
|
|
|
PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64
|
|
|
|
PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64
|
|
IFORM : VMOVUPD_YMMqq_YMMqq_11
|
|
}
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : VMOVUPS
|
|
EXCEPTIONS: avx-type-4M
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32
|
|
|
|
PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32
|
|
IFORM : VMOVUPS_XMMdq_XMMdq_10
|
|
|
|
PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32
|
|
|
|
PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32
|
|
IFORM : VMOVUPS_XMMdq_XMMdq_11
|
|
|
|
# 256b versions
|
|
|
|
PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32
|
|
IFORM : VMOVUPS_YMMqq_YMMqq_10
|
|
|
|
PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32
|
|
|
|
PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32
|
|
IFORM : VMOVUPS_YMMqq_YMMqq_11
|
|
}
|
|
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : VMOVLPD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
COMMENT: 3op version uses high part of XMM_N
|
|
PATTERN : VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VMOVLPS
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
COMMENT: 3op version uses high part of XMM_N
|
|
PATTERN : VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f32
|
|
|
|
PATTERN : VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VMOVHPD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0
|
|
PATTERN : VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
|
|
PATTERN : VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:dq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VMOVHPS
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
|
|
COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0
|
|
PATTERN : VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 MEM0:r:q:f32
|
|
|
|
PATTERN : VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:dq:f32
|
|
}
|
|
############################################################################
|
|
|
|
{
|
|
ICLASS : VMOVMSKPD
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f64
|
|
|
|
# 256b versions
|
|
|
|
PATTERN : VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f64
|
|
}
|
|
|
|
{
|
|
ICLASS : VMOVMSKPS
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f32
|
|
|
|
# 256b versions
|
|
|
|
PATTERN : VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f32
|
|
}
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVMSKB
|
|
EXCEPTIONS: avx-type-7
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:u32 REG1=XMM_B():r:dq:i8
|
|
}
|
|
|
|
############################################################################
|
|
|
|
############################################################################
|
|
# SX versions
|
|
############################################################################
|
|
|
|
{
|
|
ICLASS : VPMOVSXBW
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8
|
|
PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8
|
|
}
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXBD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8
|
|
PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXBQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8
|
|
PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXWD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16
|
|
PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXWQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16
|
|
PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXDQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32
|
|
PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
############################################################################
|
|
# ZX versions
|
|
############################################################################
|
|
|
|
{
|
|
ICLASS : VPMOVZXBW
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8
|
|
PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8
|
|
}
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXBD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8
|
|
PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXBQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8
|
|
PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXWD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16
|
|
PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXWQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16
|
|
PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXDQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32
|
|
PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32
|
|
}
|
|
|
|
|
|
|
|
############################################################################
|
|
############################################################################
|
|
{
|
|
ICLASS : VPEXTRB
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
COMMENT: WIG
|
|
PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:b REG0=XMM_R():r:dq:u8 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u8 IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPEXTRW
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
COMMENT: WIG
|
|
|
|
PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:w REG0=XMM_R():r:dq:u16 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u16 IMM0:r:b
|
|
IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_15
|
|
|
|
# special C5 reg-only versions from SSE2:
|
|
|
|
PATTERN : VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:u16 IMM0:r:b
|
|
IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_C5
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPEXTRQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:q REG0=XMM_R():r:dq:u64 IMM0:r:b
|
|
PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq:u64 IMM0:r:b
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPEXTRD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled.
|
|
|
|
# 64b mode
|
|
PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b
|
|
PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b
|
|
|
|
# not64b mode
|
|
PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b
|
|
PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b
|
|
|
|
}
|
|
############################################################################
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPINSRB
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
COMMENT: WIG
|
|
PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:b:u8 IMM0:r:b
|
|
PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : VPINSRW
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
COMMENT : WIG
|
|
PATTERN : VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:w:u16 IMM0:r:b
|
|
|
|
PATTERN : VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : VPINSRD
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled
|
|
# 64b mode
|
|
PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
|
|
PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
|
|
|
|
# 32b mode
|
|
PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
|
|
PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VPINSRQ
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:q:u64 IMM0:r:b
|
|
PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b
|
|
}
|
|
|
|
############################################################################
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPCMPESTRI
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : STTNI
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
# outside of 64b mode, vex.w is ignored for this instr
|
|
PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP
|
|
PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP
|
|
|
|
# in 64b mode, vex.w changes the behavior for GPRs
|
|
PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP
|
|
PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : VPCMPESTRI64
|
|
DISASM : vpcmpestri
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : STTNI
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP
|
|
PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : VPCMPISTRI
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : STTNI
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
# outside of 64b mode, vex.w is ignored for this instr
|
|
PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP
|
|
PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP
|
|
|
|
# in 64b mode, vex.w changes the behavior for GPRs
|
|
PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP
|
|
PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : VPCMPISTRI64
|
|
DISASM : vpcmpistri
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : STTNI
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP
|
|
PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : VPCMPESTRM
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : STTNI
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
# outside of 64b mode, vex.w is ignored for this instr
|
|
PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
|
|
PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
|
|
|
|
# in 64b mode, vex.w changes the behavior for GPRs
|
|
PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
|
|
PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : VPCMPESTRM64
|
|
DISASM : vpcmpestrm
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : STTNI
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
|
|
PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP
|
|
PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : VPCMPISTRM
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : STTNI
|
|
EXTENSION : AVX
|
|
FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ]
|
|
PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP
|
|
PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP
|
|
}
|
|
####################################################################################
|
|
|
|
|
|
|
|
####################################################################################
|
|
{
|
|
ICLASS : VMASKMOVDQU
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : maskop fixed_base0 NOTSX NONTEMPORAL
|
|
PATTERN : VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP
|
|
}
|
|
|
|
####################################################################################
|
|
{
|
|
ICLASS : VLDMXCSR
|
|
EXCEPTIONS: avx-type-5L
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR
|
|
PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP
|
|
}
|
|
{
|
|
ICLASS : VSTMXCSR
|
|
EXCEPTIONS: avx-type-5
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
ATTRIBUTES: MXCSR_RD
|
|
PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP
|
|
}
|
|
#######################################################################################
|
|
|
|
{
|
|
ICLASS : VPBLENDVB
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
|
|
# W0 (modrm.rm memory op 2nd to last)
|
|
PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 REG2=XMM_SE():r:dq:i8
|
|
|
|
PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 REG3=XMM_SE():r:dq:i8
|
|
}
|
|
|
|
{
|
|
ICLASS : VBLENDVPD
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
|
|
# W0 (modrm.rm memory op 2nd to last)
|
|
PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:u64
|
|
|
|
PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:u64
|
|
|
|
PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:u64
|
|
|
|
PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:u64
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VBLENDVPS
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
|
|
# W0 (modrm.rm memory op 2nd to last)
|
|
PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:u32
|
|
|
|
PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:u32
|
|
|
|
PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:u32
|
|
|
|
PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:u32
|
|
|
|
|
|
}
|
|
|
|
#######################################################################################
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMOVNTDQA
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
|
|
PATTERN : VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VMOVNTDQ
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
PATTERN : VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:i32 REG0=XMM_R():r:dq:i32
|
|
|
|
}
|
|
{
|
|
ICLASS : VMOVNTPD
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
PATTERN : VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VMOVNTPS
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
PATTERN : VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32
|
|
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-movnt-store.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
|
|
{
|
|
ICLASS : VMOVNTDQ
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
PATTERN : VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:i32 REG0=YMM_R():r:qq:i32
|
|
|
|
}
|
|
{
|
|
ICLASS : VMOVNTPD
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
PATTERN : VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VMOVNTPS
|
|
EXCEPTIONS: avx-type-1
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
PATTERN : VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32
|
|
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-aes-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : VAESKEYGENASSIST
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AVXAES
|
|
PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b
|
|
PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VAESENC
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AVXAES
|
|
PATTERN : VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
PATTERN : VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : VAESENCLAST
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AVXAES
|
|
PATTERN : VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
PATTERN : VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : VAESDEC
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AVXAES
|
|
PATTERN : VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
PATTERN : VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : VAESDECLAST
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AVXAES
|
|
PATTERN : VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
PATTERN : VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
}
|
|
{
|
|
ICLASS : VAESIMC
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AES
|
|
EXTENSION : AVXAES
|
|
PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq
|
|
PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-pclmul-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
{
|
|
ICLASS : VPCLMULQDQ
|
|
EXCEPTIONS: avx-type-4
|
|
CPL : 3
|
|
CATEGORY : AVX
|
|
EXTENSION : AVX
|
|
PATTERN : VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b
|
|
PATTERN : VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/ivbavx/fp16-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
{
|
|
ICLASS : VCVTPH2PS
|
|
COMMENT : UPCONVERT -- NO IMMEDIATE
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : F16C
|
|
ATTRIBUTES : MXCSR
|
|
EXCEPTIONS: avx-type-11
|
|
# 128b form
|
|
|
|
PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:q:f16
|
|
|
|
PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:q:f16
|
|
|
|
|
|
# 256b form
|
|
|
|
PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:dq:f16
|
|
|
|
PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f16
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VCVTPS2PH
|
|
COMMENT : DOWNCONVERT -- HAS IMMEDIATE
|
|
CPL : 3
|
|
CATEGORY : CONVERT
|
|
EXTENSION : F16C
|
|
ATTRIBUTES : MXCSR
|
|
EXCEPTIONS: avx-type-11
|
|
# 128b imm8 form
|
|
|
|
PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0
|
|
OPERANDS : MEM0:w:q:f16 REG0=XMM_R():r:dq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0
|
|
OPERANDS : REG0=XMM_B():w:q:f16 REG1=XMM_R():r:dq:f32 IMM0:r:b
|
|
|
|
# 256b imm8 form
|
|
|
|
PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0
|
|
OPERANDS : MEM0:w:dq:f16 REG0=YMM_R():r:qq:f32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0
|
|
OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b
|
|
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/avx-fma-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0.
|
|
# Encoder must enforce equality between two parameters. Never had to do this before.
|
|
# Extra check?
|
|
# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually)
|
|
#############################################################################################
|
|
# Operand orders:
|
|
# A = B * C + D
|
|
#Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132
|
|
#Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213
|
|
#Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231
|
|
|
|
# dst is in MODRM.REG
|
|
# regsrc is in VEX.vvvv
|
|
# memop is in MODRM.RM
|
|
############################################################################################
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
##########################################################
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
##################################################################
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
##################################################################
|
|
{
|
|
ICLASS : VFMADD132PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMADD132PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMADD132SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
{
|
|
ICLASS : VFMADD132SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VFMADD213PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMADD213PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMADD213SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMADD213SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VFMADD231PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMADD231PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMADD231SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMADD231SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
|
|
###################################################
|
|
{
|
|
ICLASS : VFMADDSUB132PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMADDSUB213PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMADDSUB231PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VFMADDSUB132PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMADDSUB213PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMADDSUB231PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
|
|
}
|
|
###################################################
|
|
|
|
{
|
|
ICLASS : VFMSUBADD132PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMSUBADD213PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMSUBADD231PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VFMSUBADD132PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMSUBADD213PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMSUBADD231PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
|
|
}
|
|
|
|
|
|
###################################################
|
|
|
|
{
|
|
ICLASS : VFMSUB132PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMSUB132PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMSUB132SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
{
|
|
ICLASS : VFMSUB132SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VFMSUB213PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFMSUB213PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFMSUB213SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMSUB213SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VFMSUB231PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMSUB231PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMSUB231SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFMSUB231SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
###################################################
|
|
|
|
|
|
{
|
|
ICLASS : VFNMADD132PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFNMADD132PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFNMADD132SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
{
|
|
ICLASS : VFNMADD132SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VFNMADD213PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFNMADD213PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFNMADD213SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMADD213SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VFNMADD231PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMADD231PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMADD231SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMADD231SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
###################################################
|
|
|
|
|
|
{
|
|
ICLASS : VFNMSUB132PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB132PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB132SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB132SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VFNMSUB213PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB213PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB213SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB213SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
}
|
|
|
|
{
|
|
ICLASS : VFNMSUB231PD
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64
|
|
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64
|
|
# R/R 256
|
|
PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB231PS
|
|
EXCEPTIONS: avx-type-2
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR
|
|
# R/M 128
|
|
PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32
|
|
|
|
# R/M 256
|
|
PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
# R/R 256
|
|
PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB231SD
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64
|
|
# R/R 128
|
|
PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64
|
|
|
|
}
|
|
{
|
|
ICLASS : VFNMSUB231SS
|
|
EXCEPTIONS: avx-type-3
|
|
CPL : 3
|
|
CATEGORY : VFMA
|
|
EXTENSION : FMA
|
|
ATTRIBUTES: MXCSR simd_scalar
|
|
# R/M 128
|
|
PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32
|
|
# R/R 128
|
|
PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32
|
|
|
|
}
|
|
|
|
###################################################
|
|
|
|
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/gather-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
|
|
# DEST in MODRM.REG
|
|
# BASE in SIB.base
|
|
# INDEX in SIB.index
|
|
# MASK in VEX.VVVV -- NOTE mask is a signed integer!!!
|
|
|
|
# VL = 128 VL = 256
|
|
# dest/mask index memsz dest/mask index memsz
|
|
# qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b
|
|
# dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b
|
|
# dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b
|
|
# qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VGATHERDPD
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64
|
|
IFORM: VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64
|
|
IFORM: VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
{
|
|
ICLASS : VGATHERDPS
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
|
|
OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:d:f32 REG1=YMM_N():rw:qq:i32
|
|
IFORM: VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32
|
|
IFORM: VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
{
|
|
ICLASS : VGATHERQPD
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
|
|
OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64
|
|
IFORM: VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64
|
|
IFORM: VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
{
|
|
ICLASS : VGATHERQPS
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32
|
|
IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:d:f32 REG1=XMM_N():rw:q:i32
|
|
IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
|
|
{
|
|
ICLASS : VPGATHERDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64
|
|
IFORM: VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64
|
|
IFORM: VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
{
|
|
ICLASS : VPGATHERDD
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
|
|
OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:d:u32 REG1=YMM_N():rw:qq:i32
|
|
IFORM: VPGATHERDD_YMMu32_MEMd_YMMi32_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32
|
|
IFORM: VPGATHERDD_XMMu32_MEMd_XMMi32_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
{
|
|
ICLASS : VPGATHERQQ
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
|
|
OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64
|
|
IFORM: VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64
|
|
IFORM: VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
{
|
|
ICLASS : VPGATHERQD
|
|
CPL : 3
|
|
CATEGORY : AVX2GATHER
|
|
EXTENSION : AVX2GATHER
|
|
ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED
|
|
EXCEPTIONS: avx-type-12
|
|
|
|
# VL = 256 - when data/mask differ from index size see asterisks in above chart.
|
|
PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32
|
|
IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL256
|
|
|
|
# VL = 128 - index, mask and dest are all XMMs
|
|
PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16
|
|
OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:d:u32 REG1=XMM_N():rw:q:i32
|
|
IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL128
|
|
|
|
COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/hsw-int256-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
|
|
{
|
|
ICLASS : VPABSB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPABSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPABSD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPACKSSWB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPACKSSDW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
{
|
|
ICLASS : VPACKUSWB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPACKUSDW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSLLW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : VPSLLD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : VPSLLQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRLW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : VPSRLD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : VPSRLQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRAW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64
|
|
}
|
|
{
|
|
ICLASS : VPSRAD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64
|
|
|
|
PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPADDB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPADDW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPADDD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
{
|
|
ICLASS : VPADDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64
|
|
|
|
PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPADDSB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPADDSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPADDUSB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPADDUSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPAVGB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPAVGW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPCMPEQB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPCMPEQW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
{
|
|
ICLASS : VPCMPEQD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
{
|
|
ICLASS : VPCMPEQQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPCMPGTB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPCMPGTW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPCMPGTD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
{
|
|
ICLASS : VPCMPGTQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64
|
|
|
|
PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPHADDW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPHADDD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
{
|
|
ICLASS : VPHADDSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPHSUBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPHSUBD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
{
|
|
ICLASS : VPHSUBSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMADDWD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMADDUBSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMAXSB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPMAXSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMAXSD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMAXUB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPMAXUW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
{
|
|
ICLASS : VPMAXUD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMINSB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPMINSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMINSD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMINUB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPMINUW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
{
|
|
ICLASS : VPMINUD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMULHUW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
{
|
|
ICLASS : VPMULHRSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMULHW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMULLW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPMULLD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMULUDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
{
|
|
ICLASS : VPMULDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSADBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPSHUFB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSIGNB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPSIGNW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPSIGND
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPSUBSB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPSUBSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSUBUSB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPSUBUSW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSUBB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8
|
|
|
|
PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8
|
|
}
|
|
{
|
|
ICLASS : VPSUBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16
|
|
|
|
PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16
|
|
}
|
|
{
|
|
ICLASS : VPSUBD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32
|
|
|
|
PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32
|
|
}
|
|
{
|
|
ICLASS : VPSUBQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64
|
|
|
|
PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPUNPCKHBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKHWD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKHDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKHQDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPUNPCKLBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
|
|
PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKLWD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16
|
|
|
|
PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKLDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
{
|
|
ICLASS : VPUNPCKLQDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
|
|
PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPALIGNR
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VPBLENDW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VMPSADBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256
|
|
|
|
PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256
|
|
}
|
|
{
|
|
ICLASS : VPAND
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256
|
|
|
|
PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256
|
|
}
|
|
{
|
|
ICLASS : VPANDN
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256
|
|
|
|
PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256
|
|
}
|
|
{
|
|
ICLASS : VPXOR
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256
|
|
|
|
PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPBLENDVB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8
|
|
|
|
PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPMOVMSKB
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPSHUFD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VPSHUFHW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b
|
|
}
|
|
{
|
|
ICLASS : VPSHUFLW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPSRLDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSLLDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD
|
|
}
|
|
|
|
##############################################
|
|
|
|
{
|
|
ICLASS : VPSLLW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSLLD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD
|
|
}
|
|
{
|
|
ICLASS : VPSLLQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRAW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRAD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRLW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRLD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
|
|
PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD
|
|
}
|
|
{
|
|
ICLASS : VPSRLQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-7
|
|
PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD
|
|
}
|
|
|
|
|
|
|
|
############################################################################
|
|
# SX versions
|
|
############################################################################
|
|
|
|
{
|
|
ICLASS : VPMOVSXBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8
|
|
PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8
|
|
}
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXBD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8
|
|
PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXBQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8
|
|
PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXWD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16
|
|
PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXWQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16
|
|
PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVSXDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32
|
|
PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
############################################################################
|
|
# ZX versions
|
|
############################################################################
|
|
|
|
{
|
|
ICLASS : VPMOVZXBW
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8
|
|
PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8
|
|
}
|
|
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXBD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8
|
|
PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXBQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8
|
|
PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXWD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16
|
|
PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXWQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16
|
|
PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16
|
|
}
|
|
############################################################################
|
|
{
|
|
ICLASS : VPMOVZXDQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-5
|
|
PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32
|
|
PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32
|
|
}
|
|
|
|
|
|
##################################
|
|
# newer stuff 2009-08-14
|
|
|
|
|
|
{
|
|
ICLASS : VINSERTI128
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VEXTRACTI128
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b
|
|
}
|
|
|
|
|
|
###########################################################################
|
|
|
|
### # VPMASKMOVD masked load and store
|
|
### # VPMASKMOVQ masked load and store
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPMASKMOVD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
ATTRIBUTES: maskop
|
|
EXCEPTIONS: avx-type-6
|
|
PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
|
|
|
|
PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
}
|
|
{
|
|
ICLASS : VPMASKMOVQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
ATTRIBUTES: maskop
|
|
EXCEPTIONS: avx-type-6
|
|
|
|
PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
|
|
|
|
|
|
PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
|
|
}
|
|
|
|
{
|
|
ICLASS : VPMASKMOVD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
ATTRIBUTES: maskop
|
|
EXCEPTIONS: avx-type-6
|
|
PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32
|
|
|
|
|
|
PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32
|
|
}
|
|
{
|
|
ICLASS : VPMASKMOVQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
ATTRIBUTES: maskop
|
|
EXCEPTIONS: avx-type-6
|
|
PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64
|
|
|
|
|
|
PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64
|
|
}
|
|
###########################################################################
|
|
|
|
|
|
### # VPERM2I128 256b only
|
|
|
|
{
|
|
ICLASS : VPERM2I128
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4...
|
|
|
|
PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VPERMQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
|
|
PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b
|
|
}
|
|
|
|
{
|
|
ICLASS : VPERMPD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
|
|
PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPERMD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
|
|
|
|
PATTERN : VV1 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
|
|
PATTERN : VV1 0x36 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
}
|
|
{
|
|
ICLASS : VPERMPS
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
|
|
PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32
|
|
|
|
PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32
|
|
}
|
|
|
|
|
|
###########################################################################
|
|
|
|
|
|
### # VPBLENDD imm 128/256
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPBLENDD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
|
|
PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b
|
|
|
|
|
|
PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b
|
|
|
|
PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b
|
|
}
|
|
|
|
|
|
|
|
###########################################################################
|
|
|
|
{
|
|
ICLASS : VPBROADCASTB
|
|
COMMENT : gpr 128/256
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
|
|
PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8
|
|
|
|
PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8
|
|
|
|
PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8
|
|
|
|
PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPBROADCASTW
|
|
COMMENT : gpr 128/256
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
|
|
PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16
|
|
|
|
PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16
|
|
|
|
PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16
|
|
|
|
PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16
|
|
}
|
|
|
|
|
|
|
|
|
|
### # VPBROADCASTD gpr/mem
|
|
|
|
|
|
{
|
|
ICLASS : VPBROADCASTD
|
|
COMMENT : gpr 128/256
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
|
|
PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32
|
|
|
|
PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32
|
|
|
|
|
|
PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32
|
|
|
|
PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32
|
|
}
|
|
|
|
|
|
|
|
### # VPBROADCASTQ gpr/mem
|
|
|
|
{
|
|
ICLASS : VPBROADCASTQ
|
|
COMMENT : gpr 128/256
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
|
|
PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64
|
|
|
|
PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64
|
|
|
|
PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64
|
|
|
|
PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VBROADCASTSS
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
COMMENT : xmm,xmm and ymm,xmm
|
|
PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32
|
|
|
|
PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : VBROADCASTSD
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
COMMENT : ymm,xmm only
|
|
PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VBROADCASTI128
|
|
CPL : 3
|
|
CATEGORY : BROADCAST
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-6
|
|
COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1?
|
|
PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/hsw-vshift-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
|
|
|
|
|
|
{
|
|
ICLASS : VPSLLVD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
|
|
}
|
|
{
|
|
ICLASS : VPSLLVQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRLVD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
|
|
}
|
|
{
|
|
ICLASS : VPSRLVQ
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : VPSRAVD
|
|
CPL : 3
|
|
CATEGORY : AVX2
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-4
|
|
PATTERN : VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
|
|
|
|
PATTERN : VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq
|
|
|
|
PATTERN : VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq
|
|
|
|
PATTERN : VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/movnt-load-isa.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
|
|
{
|
|
ICLASS : VMOVNTDQA
|
|
CPL : 3
|
|
CATEGORY : DATAXFER
|
|
EXTENSION : AVX2
|
|
EXCEPTIONS: avx-type-1
|
|
ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL
|
|
|
|
PATTERN : VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/hsw-bmi-vex-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
AVX_INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : PDEP
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
|
|
#32b
|
|
PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
|
|
}
|
|
|
|
{
|
|
ICLASS : PEXT
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
|
|
|
|
#32b
|
|
PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : ANDN
|
|
CPL : 3
|
|
CATEGORY : BMI1
|
|
EXTENSION : BMI1
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ]
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
|
|
|
|
PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q
|
|
|
|
PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q
|
|
}
|
|
|
|
{
|
|
ICLASS : BLSR
|
|
CPL : 3
|
|
CATEGORY : BMI1
|
|
EXTENSION : BMI1
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ]
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q
|
|
|
|
}
|
|
|
|
{
|
|
ICLASS : BLSMSK
|
|
CPL : 3
|
|
CATEGORY : BMI1
|
|
EXTENSION : BMI1
|
|
FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ]
|
|
|
|
#32b
|
|
PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
|
|
#64b
|
|
PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q
|
|
}
|
|
|
|
{
|
|
ICLASS : BLSI
|
|
CPL : 3
|
|
CATEGORY : BMI1
|
|
EXTENSION : BMI1
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ]
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q
|
|
|
|
PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q
|
|
}
|
|
|
|
{
|
|
ICLASS : BZHI
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ]
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q
|
|
|
|
PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q
|
|
}
|
|
|
|
{
|
|
ICLASS : BEXTR
|
|
CPL : 3
|
|
CATEGORY : BMI1
|
|
EXTENSION : BMI1
|
|
FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : SHLX
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q
|
|
|
|
PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q
|
|
}
|
|
{
|
|
ICLASS : SARX
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q
|
|
}
|
|
{
|
|
ICLASS : SHRX
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q
|
|
|
|
PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : MULX
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
|
|
# reg:w vvvv:w rm:r rdx:r
|
|
# 32b
|
|
PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP
|
|
PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP
|
|
|
|
PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP
|
|
PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : RORX
|
|
CPL : 3
|
|
CATEGORY : BMI2
|
|
EXTENSION : BMI2
|
|
|
|
# reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change
|
|
|
|
# 32b
|
|
PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b
|
|
|
|
PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b
|
|
PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b
|
|
|
|
PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b
|
|
|
|
# 64b
|
|
PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()
|
|
OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b
|
|
PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()
|
|
OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/tzcnt-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : TZCNT
|
|
CPL : 3
|
|
CATEGORY : BMI1
|
|
EXTENSION : BMI1
|
|
FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ]
|
|
PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r
|
|
}
|
|
|
|
{
|
|
ICLASS : BSF
|
|
VERSION : 1
|
|
COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
|
|
|
|
PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
|
|
PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/vmfunc-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : VMFUNC
|
|
CPL : 3
|
|
CATEGORY : VTX
|
|
EXTENSION : VMFUNC
|
|
ISA_SET : VMFUNC
|
|
ATTRIBUTES :
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix
|
|
OPERANDS : REG0=XED_REG_EAX:r:SUPP
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/invpcid-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
|
|
{
|
|
ICLASS : INVPCID
|
|
CPL : 0
|
|
CATEGORY : MISC
|
|
EXTENSION : INVPCID
|
|
ISA_SET : INVPCID
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR64_R():r MEM0:r:dq
|
|
PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()
|
|
OPERANDS : REG0=GPR32_R():r MEM0:r:dq
|
|
COMMENT :
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/lzcnt-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
# LZCNT reg16, reg/mem16 F30FBD /r
|
|
# LZCNT reg32, reg/mem32 F30FBD /r
|
|
# LZCNT reg64, reg/mem64 F30FBD /r
|
|
|
|
{
|
|
ICLASS : LZCNT
|
|
# This replace the AMD version in LZCNT builds
|
|
VERSION : 2
|
|
CPL : 3
|
|
CATEGORY : LZCNT
|
|
EXTENSION : LZCNT
|
|
COMMENT : These next one WAS introduced first by AMD circa SSE4a.
|
|
FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ]
|
|
PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():w:v MEM0:r:v
|
|
PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : BSR
|
|
VERSION : 2
|
|
COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR
|
|
CPL : 3
|
|
CATEGORY : BITBYTE
|
|
EXTENSION : BASE
|
|
ISA_SET : I386
|
|
FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ]
|
|
PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
|
|
PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS : REG0=GPRv_R():cw MEM0:r:v
|
|
|
|
PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/rtm-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : XBEGIN
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : RTM
|
|
COMMENT : Not always a branch. If aborts, then branches & eax is written
|
|
|
|
PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz()
|
|
OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP
|
|
}
|
|
|
|
{
|
|
ICLASS : XEND
|
|
CPL : 3
|
|
CATEGORY : COND_BR
|
|
EXTENSION : RTM
|
|
COMMENT : Transaction end. may branch
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
|
|
{
|
|
ICLASS : XABORT
|
|
CPL : 3
|
|
CATEGORY : UNCOND_BR
|
|
EXTENSION : RTM
|
|
COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw.
|
|
PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8()
|
|
OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS : XTEST
|
|
CPL : 3
|
|
CATEGORY : LOGICAL
|
|
EXTENSION : RTM
|
|
COMMENT : test if in RTM transaction mode
|
|
FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ]
|
|
PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/bdw/adox-adcx-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS : ADCX
|
|
CPL : 3
|
|
CATEGORY : ADOX_ADCX
|
|
EXTENSION : ADOX_ADCX
|
|
ISA_SET : ADOX_ADCX
|
|
|
|
FLAGS : MUST [ cf-tst cf-mod ]
|
|
|
|
# reg:rw rm:r
|
|
# 32b
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66()
|
|
OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66()
|
|
OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d
|
|
|
|
# 64b
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() mode64
|
|
OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() mode64
|
|
OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q
|
|
}
|
|
|
|
|
|
|
|
{
|
|
ICLASS : ADOX
|
|
CPL : 3
|
|
CATEGORY : ADOX_ADCX
|
|
EXTENSION : ADOX_ADCX
|
|
ISA_SET : ADOX_ADCX
|
|
|
|
FLAGS : MUST [ of-tst of-mod ]
|
|
|
|
# reg:rw rm:r
|
|
# 32b
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66()
|
|
OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66()
|
|
OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d
|
|
|
|
# 64b
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() mode64
|
|
OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q
|
|
PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() mode64
|
|
OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/pku/pku-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS: RDPKRU
|
|
CPL: 3
|
|
CATEGORY: PKU
|
|
EXTENSION: PKU
|
|
ISA_SET: PKU
|
|
ATTRIBUTES:
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix
|
|
OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP
|
|
}
|
|
|
|
|
|
{
|
|
ICLASS: WRPKRU
|
|
CPL: 3
|
|
CATEGORY: PKU
|
|
EXTENSION: PKU
|
|
ISA_SET: PKU
|
|
ATTRIBUTES:
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix
|
|
OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP
|
|
}
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/clwb/clwb.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
|
|
{
|
|
ICLASS: CLWB
|
|
CPL: 3
|
|
CATEGORY: CLWB
|
|
EXTENSION: CLWB
|
|
ISA_SET: CLWB
|
|
ATTRIBUTES: PREFETCH # check TSX-friendlyness
|
|
PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()
|
|
OPERANDS : MEM0:r:mprefetch
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/vnni/vnni-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPDPBUSD (VPDPBUSD-128-1)
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSD (VPDPBUSD-256-1)
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSD (VPDPBUSD-512-1)
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSDS (VPDPBUSDS-128-1)
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSDS (VPDPBUSDS-256-1)
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSDS (VPDPBUSDS-512-1)
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSD (VPDPWSSD-128-1)
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSD (VPDPWSSD-256-1)
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSD (VPDPWSSD-512-1)
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSDS (VPDPWSSDS-128-1)
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSDS (VPDPWSSDS-256-1)
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSDS (VPDPWSSDS-512-1)
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VNNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-128-1)
|
|
{
|
|
ICLASS: VCVTNE2PS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTNE2PS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-256-1)
|
|
{
|
|
ICLASS: VCVTNE2PS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTNE2PS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-512-1)
|
|
{
|
|
ICLASS: VCVTNE2PS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTNE2PS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-128-1)
|
|
{
|
|
ICLASS: VCVTNEPS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTNEPS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-256-1)
|
|
{
|
|
ICLASS: VCVTNEPS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTNEPS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-512-1)
|
|
{
|
|
ICLASS: VCVTNEPS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTNEPS2BF16
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VDPBF16PS (VDPBF16PS-128-1)
|
|
{
|
|
ICLASS: VDPBF16PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDPBF16PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDPBF16PS (VDPBF16PS-256-1)
|
|
{
|
|
ICLASS: VDPBF16PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDPBF16PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDPBF16PS (VDPBF16PS-512-1)
|
|
{
|
|
ICLASS: VDPBF16PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDPBF16PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BF16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-fixup.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
UDELETE : PREFETCH_RESERVED_0F0Dr2
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VEXP2PD (VEXP2PD-512-1)
|
|
{
|
|
ICLASS: VEXP2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VEXP2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VEXP2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VEXP2PS (VEXP2PS-512-1)
|
|
{
|
|
ICLASS: VEXP2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VEXP2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VEXP2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1)
|
|
{
|
|
ICLASS: VGATHERPF0DPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1)
|
|
{
|
|
ICLASS: VGATHERPF0DPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1)
|
|
{
|
|
ICLASS: VGATHERPF0QPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1)
|
|
{
|
|
ICLASS: VGATHERPF0QPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1)
|
|
{
|
|
ICLASS: VGATHERPF1DPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1)
|
|
{
|
|
ICLASS: VGATHERPF1DPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1)
|
|
{
|
|
ICLASS: VGATHERPF1QPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1)
|
|
{
|
|
ICLASS: VGATHERPF1QPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP28PD (VRCP28PD-512-1)
|
|
{
|
|
ICLASS: VRCP28PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VRCP28PS (VRCP28PS-512-1)
|
|
{
|
|
ICLASS: VRCP28PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VRCP28SD (VRCP28SD-128-1)
|
|
{
|
|
ICLASS: VRCP28SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VRCP28SS (VRCP28SS-128-1)
|
|
{
|
|
ICLASS: VRCP28SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP28SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT28PD (VRSQRT28PD-512-1)
|
|
{
|
|
ICLASS: VRSQRT28PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT28PS (VRSQRT28PS-512-1)
|
|
{
|
|
ICLASS: VRSQRT28PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT28SD (VRSQRT28SD-128-1)
|
|
{
|
|
ICLASS: VRSQRT28SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT28SS (VRSQRT28SS-128-1)
|
|
{
|
|
ICLASS: VRSQRT28SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX
|
|
PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT28SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512ER_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR
|
|
PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF0DPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF0DPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF0QPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF0QPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF1DPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF1DPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF1QPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1)
|
|
{
|
|
ICLASS: VSCATTERPF1QPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512PF_512
|
|
EXCEPTIONS: AVX512-E12NP
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT
|
|
PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw
|
|
IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512
|
|
}
|
|
|
|
|
|
INSTRUCTIONS()::
|
|
# EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1)
|
|
{
|
|
ICLASS: PREFETCHWT1
|
|
CPL: 3
|
|
CATEGORY: PREFETCHWT1
|
|
EXTENSION: PREFETCHWT1
|
|
ISA_SET: PREFETCHWT1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: PREFETCH
|
|
PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()
|
|
OPERANDS: MEM0:r:b:u8
|
|
IFORM: PREFETCHWT1_MEMu8
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING V4FMADDPS (V4FMADDPS-512-1)
|
|
{
|
|
ICLASS: V4FMADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512_4FMAPS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_4FMAPS_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32
|
|
IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING V4FMADDSS (V4FMADDSS-128-1)
|
|
{
|
|
ICLASS: V4FMADDSS
|
|
CPL: 3
|
|
CATEGORY: AVX512_4FMAPS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_4FMAPS_SCALAR
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32
|
|
IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING V4FNMADDPS (V4FNMADDPS-512-1)
|
|
{
|
|
ICLASS: V4FNMADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512_4FMAPS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_4FMAPS_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX
|
|
PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32
|
|
IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING V4FNMADDSS (V4FNMADDSS-128-1)
|
|
{
|
|
ICLASS: V4FNMADDSS
|
|
CPL: 3
|
|
CATEGORY: AVX512_4FMAPS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_4FMAPS_SCALAR
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32
|
|
IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VP4DPWSSD (VP4DPWSSD-512-1)
|
|
{
|
|
ICLASS: VP4DPWSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512_4VNNIW
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_4VNNIW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX
|
|
PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32
|
|
IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1)
|
|
{
|
|
ICLASS: VP4DPWSSDS
|
|
CPL: 3
|
|
CATEGORY: AVX512_4VNNIW
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_4VNNIW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX
|
|
PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()
|
|
OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32
|
|
IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPOPCNTD (VPOPCNTD-512-1)
|
|
{
|
|
ICLASS: VPOPCNTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTQ (VPOPCNTQ-512-1)
|
|
{
|
|
ICLASS: VPOPCNTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-foundation-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VADDPD (VADDPD-512-1)
|
|
{
|
|
ICLASS: VADDPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDPS (VADDPS-512-1)
|
|
{
|
|
ICLASS: VADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDSD (VADDSD-128-1)
|
|
{
|
|
ICLASS: VADDSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDSS (VADDSS-128-1)
|
|
{
|
|
ICLASS: VADDSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VALIGND (VALIGND-512-1)
|
|
{
|
|
ICLASS: VALIGND
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VALIGND
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VALIGNQ (VALIGNQ-512-1)
|
|
{
|
|
ICLASS: VALIGNQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VALIGNQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPD (VBLENDMPD-512-1)
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPS (VBLENDMPS-512-1)
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32
|
|
IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF64X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64
|
|
IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32
|
|
IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI64X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64
|
|
IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSD (VBROADCASTSD-512-1)
|
|
{
|
|
ICLASS: VBROADCASTSD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64
|
|
IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSD (VBROADCASTSD-512-2)
|
|
{
|
|
ICLASS: VBROADCASTSD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64
|
|
IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-512-1)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32
|
|
IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-512-2)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32
|
|
IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPD (VCMPPD-512-1)
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPS (VCMPPS-512-1)
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPSD (VCMPSD-128-1)
|
|
{
|
|
ICLASS: VCMPSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPSS (VCMPSS-128-1)
|
|
{
|
|
ICLASS: VCMPSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMISD (VCOMISD-128-1)
|
|
{
|
|
ICLASS: VCOMISD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCOMISD_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCOMISD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCOMISD_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCOMISD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VCOMISD_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMISS (VCOMISS-128-1)
|
|
{
|
|
ICLASS: VCOMISS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCOMISS_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCOMISS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCOMISS_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCOMISS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VCOMISS_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
|
|
IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64
|
|
IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
|
|
IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32
|
|
IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1)
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512
|
|
COMMENT: ignores rc/sae. need to adjust VL to 512
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1)
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
|
|
IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
|
|
IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1)
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PS (VCVTPD2PS-512-1)
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1)
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PS (VCVTPH2PS-512-1)
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16
|
|
IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1)
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PD (VCVTPS2PD-512-1)
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-512-1)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-512-2)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1)
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSD2SI (VCVTSD2SI-128-1)
|
|
{
|
|
ICLASS: VCVTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSD2SI (VCVTSD2SI-128-2)
|
|
{
|
|
ICLASS: VCVTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
|
|
IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSD2SS (VCVTSD2SS-128-1)
|
|
{
|
|
ICLASS: VCVTSD2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSD2USI (VCVTSD2USI-128-1)
|
|
{
|
|
ICLASS: VCVTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
|
|
IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
|
|
IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSD2USI (VCVTSD2USI-128-2)
|
|
{
|
|
ICLASS: VCVTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
|
|
IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSI2SD (VCVTSI2SD-128-1)
|
|
{
|
|
ICLASS: VCVTSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: SIMD_SCALAR
|
|
COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding
|
|
PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
|
|
PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32
|
|
IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
|
|
PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32
|
|
IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSI2SD (VCVTSI2SD-128-2)
|
|
{
|
|
ICLASS: VCVTSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
|
|
IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64
|
|
IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64
|
|
IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSI2SS (VCVTSI2SS-128-1)
|
|
{
|
|
ICLASS: VCVTSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSI2SS (VCVTSI2SS-128-2)
|
|
{
|
|
ICLASS: VCVTSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64
|
|
IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512
|
|
}
|
|
# EMITTING VCVTSS2SD (VCVTSS2SD-128-1)
|
|
{
|
|
ICLASS: VCVTSS2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSS2SI (VCVTSS2SI-128-1)
|
|
{
|
|
ICLASS: VCVTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSS2SI (VCVTSS2SI-128-2)
|
|
{
|
|
ICLASS: VCVTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
|
|
IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSS2USI (VCVTSS2USI-128-1)
|
|
{
|
|
ICLASS: VCVTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
|
|
IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
|
|
IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSS2USI (VCVTSS2USI-128-2)
|
|
{
|
|
ICLASS: VCVTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
|
|
IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1)
|
|
{
|
|
ICLASS: VCVTTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
|
|
IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2)
|
|
{
|
|
ICLASS: VCVTTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
|
|
IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1)
|
|
{
|
|
ICLASS: VCVTTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
|
|
IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64
|
|
IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2)
|
|
{
|
|
ICLASS: VCVTTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSD2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q
|
|
PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64
|
|
IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1)
|
|
{
|
|
ICLASS: VCVTTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32
|
|
IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2)
|
|
{
|
|
ICLASS: VCVTTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32
|
|
IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1)
|
|
{
|
|
ICLASS: VCVTTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
|
|
IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32
|
|
IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2)
|
|
{
|
|
ICLASS: VCVTTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSS2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32
|
|
IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512
|
|
COMMENT: ignores rc/sae. need to adjust VL to 512
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1)
|
|
{
|
|
ICLASS: VCVTUSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
|
|
PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32
|
|
IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
|
|
PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32
|
|
IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2)
|
|
{
|
|
ICLASS: VCVTUSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
|
|
IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64
|
|
IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64
|
|
IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1)
|
|
{
|
|
ICLASS: VCVTUSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2)
|
|
{
|
|
ICLASS: VCVTUSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER
|
|
PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64
|
|
IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPD (VDIVPD-512-1)
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPS (VDIVPS-512-1)
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVSD (VDIVSD-128-1)
|
|
{
|
|
ICLASS: VDIVSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVSS (VDIVSS-128-1)
|
|
{
|
|
ICLASS: VDIVSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-512-1)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
|
|
IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-512-2)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-512-1)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
|
|
IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-512-2)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1)
|
|
{
|
|
ICLASS: VEXTRACTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2)
|
|
{
|
|
ICLASS: VEXTRACTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1)
|
|
{
|
|
ICLASS: VEXTRACTF64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2)
|
|
{
|
|
ICLASS: VEXTRACTF64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1)
|
|
{
|
|
ICLASS: VEXTRACTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2)
|
|
{
|
|
ICLASS: VEXTRACTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1)
|
|
{
|
|
ICLASS: VEXTRACTI64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2)
|
|
{
|
|
ICLASS: VEXTRACTI64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTPS (VEXTRACTPS-128-1)
|
|
{
|
|
ICLASS: VEXTRACTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b
|
|
IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VEXTRACTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b
|
|
IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1)
|
|
{
|
|
ICLASS: VFIXUPIMMSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1)
|
|
{
|
|
ICLASS: VFIXUPIMMSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PD (VFMADD132PD-512-1)
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PS (VFMADD132PS-512-1)
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132SD (VFMADD132SD-128-1)
|
|
{
|
|
ICLASS: VFMADD132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132SS (VFMADD132SS-128-1)
|
|
{
|
|
ICLASS: VFMADD132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PD (VFMADD213PD-512-1)
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PS (VFMADD213PS-512-1)
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213SD (VFMADD213SD-128-1)
|
|
{
|
|
ICLASS: VFMADD213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213SS (VFMADD213SS-128-1)
|
|
{
|
|
ICLASS: VFMADD213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PD (VFMADD231PD-512-1)
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PS (VFMADD231PS-512-1)
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231SD (VFMADD231SD-128-1)
|
|
{
|
|
ICLASS: VFMADD231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231SS (VFMADD231SS-128-1)
|
|
{
|
|
ICLASS: VFMADD231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PD (VFMSUB132PD-512-1)
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PS (VFMSUB132PS-512-1)
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132SD (VFMSUB132SD-128-1)
|
|
{
|
|
ICLASS: VFMSUB132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132SS (VFMSUB132SS-128-1)
|
|
{
|
|
ICLASS: VFMSUB132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PD (VFMSUB213PD-512-1)
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PS (VFMSUB213PS-512-1)
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213SD (VFMSUB213SD-128-1)
|
|
{
|
|
ICLASS: VFMSUB213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213SS (VFMSUB213SS-128-1)
|
|
{
|
|
ICLASS: VFMSUB213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PD (VFMSUB231PD-512-1)
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PS (VFMSUB231PS-512-1)
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231SD (VFMSUB231SD-128-1)
|
|
{
|
|
ICLASS: VFMSUB231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231SS (VFMSUB231SS-128-1)
|
|
{
|
|
ICLASS: VFMSUB231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PD (VFNMADD132PD-512-1)
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PS (VFNMADD132PS-512-1)
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132SD (VFNMADD132SD-128-1)
|
|
{
|
|
ICLASS: VFNMADD132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132SS (VFNMADD132SS-128-1)
|
|
{
|
|
ICLASS: VFNMADD132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PD (VFNMADD213PD-512-1)
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PS (VFNMADD213PS-512-1)
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213SD (VFNMADD213SD-128-1)
|
|
{
|
|
ICLASS: VFNMADD213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213SS (VFNMADD213SS-128-1)
|
|
{
|
|
ICLASS: VFNMADD213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PD (VFNMADD231PD-512-1)
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PS (VFNMADD231PS-512-1)
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231SD (VFNMADD231SD-128-1)
|
|
{
|
|
ICLASS: VFNMADD231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231SS (VFNMADD231SS-128-1)
|
|
{
|
|
ICLASS: VFNMADD231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1)
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1)
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1)
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1)
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1)
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1)
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231SD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231SS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPD (VGATHERDPD-512-1)
|
|
{
|
|
ICLASS: VGATHERDPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
|
|
IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPS (VGATHERDPS-512-1)
|
|
{
|
|
ICLASS: VGATHERDPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
|
|
IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPD (VGATHERQPD-512-1)
|
|
{
|
|
ICLASS: VGATHERQPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
|
|
IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPS (VGATHERQPS-512-1)
|
|
{
|
|
ICLASS: VGATHERQPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
|
|
IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPD (VGETEXPPD-512-1)
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPS (VGETEXPPS-512-1)
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPSD (VGETEXPSD-128-1)
|
|
{
|
|
ICLASS: VGETEXPSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPSS (VGETEXPSS-128-1)
|
|
{
|
|
ICLASS: VGETEXPSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPD (VGETMANTPD-512-1)
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPS (VGETMANTPS-512-1)
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTSD (VGETMANTSD-128-1)
|
|
{
|
|
ICLASS: VGETMANTSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTSS (VGETMANTSS-128-1)
|
|
{
|
|
ICLASS: VGETMANTSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF32X4 (VINSERTF32X4-512-1)
|
|
{
|
|
ICLASS: VINSERTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF64X4 (VINSERTF64X4-512-1)
|
|
{
|
|
ICLASS: VINSERTF64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI32X4 (VINSERTI32X4-512-1)
|
|
{
|
|
ICLASS: VINSERTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI64X4 (VINSERTI64X4-512-1)
|
|
{
|
|
ICLASS: VINSERTI64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI64X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTPS (VINSERTPS-128-1)
|
|
{
|
|
ICLASS: VINSERTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_TUPLE1
|
|
PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPD (VMAXPD-512-1)
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPS (VMAXPS-512-1)
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXSD (VMAXSD-128-1)
|
|
{
|
|
ICLASS: VMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXSS (VMAXSS-128-1)
|
|
{
|
|
ICLASS: VMAXSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPD (VMINPD-512-1)
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPS (VMINPS-512-1)
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINSD (VMINSD-128-1)
|
|
{
|
|
ICLASS: VMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINSS (VMINSS-128-1)
|
|
{
|
|
ICLASS: VMINSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-512-1)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
|
|
IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-512-2)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64
|
|
IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-512-3)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
|
|
IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-512-1)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
|
|
IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-512-2)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32
|
|
IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-512-3)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
|
|
IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVD (VMOVD-128-1)
|
|
{
|
|
ICLASS: VMOVD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32
|
|
IFORM: VMOVD_XMMu32_GPR32u32_AVX512
|
|
PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32
|
|
IFORM: VMOVD_XMMu32_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER
|
|
PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32
|
|
IFORM: VMOVD_XMMu32_MEMu32_AVX512
|
|
PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32
|
|
IFORM: VMOVD_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVD (VMOVD-128-2)
|
|
{
|
|
ICLASS: VMOVD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32
|
|
IFORM: VMOVD_GPR32u32_XMMu32_AVX512
|
|
PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32
|
|
IFORM: VMOVD_GPR32u32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32
|
|
IFORM: VMOVD_MEMu32_XMMu32_AVX512
|
|
PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32
|
|
IFORM: VMOVD_MEMu32_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDDUP (VMOVDDUP-512-1)
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
|
|
IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-512-1)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
|
|
IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-512-2)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
|
|
IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-512-3)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-512-1)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
|
|
IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-512-2)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-512-3)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-512-1)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
|
|
IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-512-2)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
|
|
IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-512-3)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-512-1)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
|
|
IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-512-2)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-512-3)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVHLPS (VMOVHLPS-128-1)
|
|
{
|
|
ICLASS: VMOVHLPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E7NM128
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVHPD (VMOVHPD-128-1)
|
|
{
|
|
ICLASS: VMOVHPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR
|
|
PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64
|
|
IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVHPD (VMOVHPD-128-2)
|
|
{
|
|
ICLASS: VMOVHPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR
|
|
PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64
|
|
IFORM: VMOVHPD_MEMf64_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVHPS (VMOVHPS-128-1)
|
|
{
|
|
ICLASS: VMOVHPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_TUPLE2
|
|
PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32
|
|
IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVHPS (VMOVHPS-128-2)
|
|
{
|
|
ICLASS: VMOVHPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_TUPLE2
|
|
PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32
|
|
IFORM: VMOVHPS_MEMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVLHPS (VMOVLHPS-128-1)
|
|
{
|
|
ICLASS: VMOVLHPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E7NM128
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32
|
|
IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVLPD (VMOVLPD-128-1)
|
|
{
|
|
ICLASS: VMOVLPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR
|
|
PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVLPD (VMOVLPD-128-2)
|
|
{
|
|
ICLASS: VMOVLPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR
|
|
PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64
|
|
IFORM: VMOVLPD_MEMf64_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVLPS (VMOVLPS-128-1)
|
|
{
|
|
ICLASS: VMOVLPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_TUPLE2
|
|
PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32
|
|
IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVLPS (VMOVLPS-128-2)
|
|
{
|
|
ICLASS: VMOVLPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_TUPLE2
|
|
PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32
|
|
IFORM: VMOVLPS_MEMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQ (VMOVNTDQ-512-1)
|
|
{
|
|
ICLASS: VMOVNTDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32
|
|
IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQA (VMOVNTDQA-512-1)
|
|
{
|
|
ICLASS: VMOVNTDQA
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32
|
|
IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPD (VMOVNTPD-512-1)
|
|
{
|
|
ICLASS: VMOVNTPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64
|
|
IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPS (VMOVNTPS-512-1)
|
|
{
|
|
ICLASS: VMOVNTPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32
|
|
IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVQ (VMOVQ-128-1)
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64
|
|
IFORM: VMOVQ_XMMu64_GPR64u64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER
|
|
PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64
|
|
IFORM: VMOVQ_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVQ (VMOVQ-128-2)
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64
|
|
IFORM: VMOVQ_GPR64u64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64
|
|
IFORM: VMOVQ_MEMu64_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVQ (VMOVQ-128-3)
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64
|
|
IFORM: VMOVQ_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR
|
|
PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64
|
|
IFORM: VMOVQ_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVQ (VMOVQ-128-4)
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64
|
|
IFORM: VMOVQ_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR
|
|
PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64
|
|
IFORM: VMOVQ_MEMu64_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSD (VMOVSD-128-1)
|
|
{
|
|
ICLASS: VMOVSD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64
|
|
IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSD (VMOVSD-128-2)
|
|
{
|
|
ICLASS: VMOVSD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSD (VMOVSD-128-3)
|
|
{
|
|
ICLASS: VMOVSD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSD (VMOVSD-128-4)
|
|
{
|
|
ICLASS: VMOVSD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64
|
|
IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSHDUP (VMOVSHDUP-512-1)
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
|
|
IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSLDUP (VMOVSLDUP-512-1)
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
|
|
IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSS (VMOVSS-128-1)
|
|
{
|
|
ICLASS: VMOVSS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32
|
|
IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSS (VMOVSS-128-2)
|
|
{
|
|
ICLASS: VMOVSS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSS (VMOVSS-128-3)
|
|
{
|
|
ICLASS: VMOVSS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSS (VMOVSS-128-4)
|
|
{
|
|
ICLASS: VMOVSS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32
|
|
IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-512-1)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
|
|
IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-512-2)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64
|
|
IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-512-3)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
|
|
IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-512-1)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32
|
|
IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-512-2)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32
|
|
IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-512-3)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32
|
|
IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPD (VMULPD-512-1)
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPS (VMULPS-512-1)
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULSD (VMULSD-128-1)
|
|
{
|
|
ICLASS: VMULSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULSS (VMULSS-128-1)
|
|
{
|
|
ICLASS: VMULSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSD (VPABSD-512-1)
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
|
|
IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSQ (VPABSQ-512-1)
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64
|
|
IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDD (VPADDD-512-1)
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDQ (VPADDQ-512-1)
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDD (VPANDD-512-1)
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDND (VPANDND-512-1)
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDNQ (VPANDNQ-512-1)
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDQ (VPANDQ-512-1)
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMD (VPBLENDMD-512-1)
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMQ (VPBLENDMQ-512-1)
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32
|
|
IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-512-2)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32
|
|
IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-512-3)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
|
|
IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32
|
|
IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64
|
|
IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64
|
|
IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64
|
|
IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPD (VPCMPD-512-1)
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQD (VPCMPEQD-512-1)
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQQ (VPCMPEQQ-512-1)
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTD (VPCMPGTD-512-1)
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTQ (VPCMPGTQ-512-1)
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPQ (VPCMPQ-512-1)
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUD (VPCMPUD-512-1)
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUQ (VPCMPUQ-512-1)
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
|
|
IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMD (VPERMD-512-1)
|
|
{
|
|
ICLASS: VPERMD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2D (VPERMI2D-512-1)
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PD (VPERMI2PD-512-1)
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PS (VPERMI2PS-512-1)
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2Q (VPERMI2Q-512-1)
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-512-1)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-512-2)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-512-1)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-512-2)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPD (VPERMPD-512-1)
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPD (VPERMPD-512-2)
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPS (VPERMPS-512-1)
|
|
{
|
|
ICLASS: VPERMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMQ (VPERMQ-512-1)
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMQ (VPERMQ-512-2)
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2D (VPERMT2D-512-1)
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PD (VPERMT2PD-512-1)
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PS (VPERMT2PS-512-1)
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2Q (VPERMT2Q-512-1)
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-512-1)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32
|
|
IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-512-2)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-512-1)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64
|
|
IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-512-2)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDD (VPGATHERDD-512-1)
|
|
{
|
|
ICLASS: VPGATHERDD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
|
|
IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDQ (VPGATHERDQ-512-1)
|
|
{
|
|
ICLASS: VPGATHERDQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
|
|
IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQD (VPGATHERQD-512-1)
|
|
{
|
|
ICLASS: VPGATHERQD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
|
|
IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQQ (VPGATHERQQ-512-1)
|
|
{
|
|
ICLASS: VPGATHERQQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
|
|
IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSD (VPMAXSD-512-1)
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
|
|
IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSQ (VPMAXSQ-512-1)
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
|
|
IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUD (VPMAXUD-512-1)
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUQ (VPMAXUQ-512-1)
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSD (VPMINSD-512-1)
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
|
|
IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSQ (VPMINSQ-512-1)
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
|
|
IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUD (VPMINUD-512-1)
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUQ (VPMINUQ-512-1)
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-512-1)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
|
|
IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-512-2)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-512-1)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
|
|
IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-512-2)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-512-1)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-512-2)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-512-1)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-512-2)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-512-1)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-512-2)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-512-1)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32
|
|
IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-512-2)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32
|
|
IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-512-1)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32
|
|
IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-512-2)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32
|
|
IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-512-1)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64
|
|
IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-512-2)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64
|
|
IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-512-1)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64
|
|
IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-512-2)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64
|
|
IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-512-1)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64
|
|
IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-512-2)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64
|
|
IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBD (VPMOVSXBD-512-1)
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1)
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1)
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32
|
|
IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWD (VPMOVSXWD-512-1)
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
|
|
IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16
|
|
IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1)
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-512-1)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
|
|
IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-512-2)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-512-1)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32
|
|
IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-512-2)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-512-1)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-512-2)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-512-1)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-512-2)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-512-1)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64
|
|
IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-512-2)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBD (VPMOVZXBD-512-1)
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1)
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1)
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32
|
|
IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWD (VPMOVZXWD-512-1)
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
|
|
IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16
|
|
IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1)
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULDQ (VPMULDQ-512-1)
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64
|
|
IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLD (VPMULLD-512-1)
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULUDQ (VPMULUDQ-512-1)
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORD (VPORD-512-1)
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORQ (VPORQ-512-1)
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLD (VPROLD-512-1)
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLQ (VPROLQ-512-1)
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVD (VPROLVD-512-1)
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVQ (VPROLVQ-512-1)
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORD (VPRORD-512-1)
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORQ (VPRORQ-512-1)
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVD (VPRORVD-512-1)
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVQ (VPRORVQ-512-1)
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDD (VPSCATTERDD-512-1)
|
|
{
|
|
ICLASS: VPSCATTERDD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32
|
|
IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1)
|
|
{
|
|
ICLASS: VPSCATTERDQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQD (VPSCATTERQD-512-1)
|
|
{
|
|
ICLASS: VPSCATTERQD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1)
|
|
{
|
|
ICLASS: VPSCATTERQQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64
|
|
IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFD (VPSHUFD-512-1)
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-512-1)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32
|
|
IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-512-2)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-512-1)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
|
|
IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-512-2)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVD (VPSLLVD-512-1)
|
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{
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ICLASS: VPSLLVD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
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OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
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IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
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}
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{
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ICLASS: VPSLLVD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
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OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
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IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
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}
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# EMITTING VPSLLVQ (VPSLLVQ-512-1)
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{
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ICLASS: VPSLLVQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
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OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
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IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
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}
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{
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ICLASS: VPSLLVQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
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IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
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}
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# EMITTING VPSRAD (VPSRAD-512-1)
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{
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ICLASS: VPSRAD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
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OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32
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IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
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}
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{
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ICLASS: VPSRAD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
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PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128()
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OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32
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IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
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}
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# EMITTING VPSRAD (VPSRAD-512-2)
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{
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ICLASS: VPSRAD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8()
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OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
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IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
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}
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|
|
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{
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ICLASS: VPSRAD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
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OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
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IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
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}
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# EMITTING VPSRAQ (VPSRAQ-512-1)
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{
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ICLASS: VPSRAQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4NF
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
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OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64
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IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
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}
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|
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{
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ICLASS: VPSRAQ
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|
CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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|
ISA_SET: AVX512F_512
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|
EXCEPTIONS: AVX512-E4NF
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|
REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
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PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128()
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OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
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IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
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}
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|
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# EMITTING VPSRAQ (VPSRAQ-512-2)
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{
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ICLASS: VPSRAQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8()
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OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
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IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
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}
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|
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{
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ICLASS: VPSRAQ
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
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PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
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OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
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IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
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}
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|
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# EMITTING VPSRAVD (VPSRAVD-512-1)
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{
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ICLASS: VPSRAVD
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CPL: 3
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CATEGORY: AVX512
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EXTENSION: AVX512EVEX
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ISA_SET: AVX512F_512
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EXCEPTIONS: AVX512-E4
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REAL_OPCODE: Y
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ATTRIBUTES: MASKOP_EVEX
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PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
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OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
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IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
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}
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|
|
|
{
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ICLASS: VPSRAVD
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|
CPL: 3
|
|
CATEGORY: AVX512
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|
EXTENSION: AVX512EVEX
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|
ISA_SET: AVX512F_512
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|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
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IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
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}
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|
|
|
|
|
# EMITTING VPSRAVQ (VPSRAVQ-512-1)
|
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{
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|
ICLASS: VPSRAVQ
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|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
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|
IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
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}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-512-1)
|
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{
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|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32
|
|
IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-512-2)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-512-1)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
|
|
IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-512-2)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVD (VPSRLVD-512-1)
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVQ (VPSRLVQ-512-1)
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBD (VPSUBD-512-1)
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBQ (VPSUBQ-512-1)
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGD (VPTERNLOGD-512-1)
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1)
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMD (VPTESTMD-512-1)
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMQ (VPTESTMQ-512-1)
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMD (VPTESTNMD-512-1)
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMQ (VPTESTNMQ-512-1)
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1)
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1)
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1)
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1)
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORD (VPXORD-512-1)
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORQ (VPXORQ-512-1)
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PD (VRCP14PD-512-1)
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PS (VRCP14PS-512-1)
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14SD (VRCP14SD-128-1)
|
|
{
|
|
ICLASS: VRCP14SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14SS (VRCP14SS-128-1)
|
|
{
|
|
ICLASS: VRCP14SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1)
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1)
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALESD (VRNDSCALESD-128-1)
|
|
{
|
|
ICLASS: VRNDSCALESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALESS (VRNDSCALESS-128-1)
|
|
{
|
|
ICLASS: VRNDSCALESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PD (VRSQRT14PD-512-1)
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PS (VRSQRT14PS-512-1)
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14SD (VRSQRT14SD-128-1)
|
|
{
|
|
ICLASS: VRSQRT14SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14SD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14SS (VRSQRT14SS-128-1)
|
|
{
|
|
ICLASS: VRSQRT14SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14SS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPD (VSCALEFPD-512-1)
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPS (VSCALEFPS-512-1)
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFSD (VSCALEFSD-128-1)
|
|
{
|
|
ICLASS: VSCALEFSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFSS (VSCALEFSS-128-1)
|
|
{
|
|
ICLASS: VSCALEFSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPD (VSCATTERDPD-512-1)
|
|
{
|
|
ICLASS: VSCATTERDPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
|
|
IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPS (VSCATTERDPS-512-1)
|
|
{
|
|
ICLASS: VSCATTERDPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32
|
|
IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPD (VSCATTERQPD-512-1)
|
|
{
|
|
ICLASS: VSCATTERQPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64
|
|
IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPS (VSCATTERQPS-512-1)
|
|
{
|
|
ICLASS: VSCATTERQPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFF32X4 (VSHUFF32X4-512-1)
|
|
{
|
|
ICLASS: VSHUFF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFF64X2 (VSHUFF64X2-512-1)
|
|
{
|
|
ICLASS: VSHUFF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFI32X4 (VSHUFI32X4-512-1)
|
|
{
|
|
ICLASS: VSHUFI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFI64X2 (VSHUFI64X2-512-1)
|
|
{
|
|
ICLASS: VSHUFI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPD (VSHUFPD-512-1)
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPS (VSHUFPS-512-1)
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPD (VSQRTPD-512-1)
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPS (VSQRTPS-512-1)
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTSD (VSQRTSD-128-1)
|
|
{
|
|
ICLASS: VSQRTSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTSS (VSQRTSS-128-1)
|
|
{
|
|
ICLASS: VSQRTSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPD (VSUBPD-512-1)
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPS (VSUBPS-512-1)
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBSD (VSUBSD-128-1)
|
|
{
|
|
ICLASS: VSUBSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBSS (VSUBSS-128-1)
|
|
{
|
|
ICLASS: VSUBSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUCOMISD (VUCOMISD-128-1)
|
|
{
|
|
ICLASS: VUCOMISD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64
|
|
IFORM: VUCOMISD_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUCOMISD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64
|
|
IFORM: VUCOMISD_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUCOMISD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VUCOMISD_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUCOMISS (VUCOMISS-128-1)
|
|
{
|
|
ICLASS: VUCOMISS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32
|
|
IFORM: VUCOMISS_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUCOMISS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32
|
|
IFORM: VUCOMISS_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUCOMISS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32
|
|
IFORM: VUCOMISS_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPD (VUNPCKHPD-512-1)
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPS (VUNPCKHPS-512-1)
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPD (VUNPCKLPD-512-1)
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64
|
|
IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPS (VUNPCKLPS-512-1)
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32
|
|
IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
AVX_INSTRUCTIONS()::
|
|
# EMITTING KANDNW (KANDNW-256-1)
|
|
{
|
|
ICLASS: KANDNW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDW (KANDW-256-1)
|
|
{
|
|
ICLASS: KANDW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVW (KMOVW-128-1)
|
|
{
|
|
ICLASS: KMOVW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16
|
|
IFORM: KMOVW_MASKmskw_MASKu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: KMOVW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16
|
|
IFORM: KMOVW_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVW (KMOVW-128-2)
|
|
{
|
|
ICLASS: KMOVW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR
|
|
OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw
|
|
IFORM: KMOVW_MEMu16_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVW (KMOVW-128-3)
|
|
{
|
|
ICLASS: KMOVW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
|
|
IFORM: KMOVW_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVW (KMOVW-128-4)
|
|
{
|
|
ICLASS: KMOVW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVW_GPR32u32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KNOTW (KNOTW-128-1)
|
|
{
|
|
ICLASS: KNOTW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KNOTW_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORTESTW (KORTESTW-128-1)
|
|
{
|
|
ICLASS: KORTESTW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORW (KORW-256-1)
|
|
{
|
|
ICLASS: KORW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTLW (KSHIFTLW-128-1)
|
|
{
|
|
ICLASS: KSHIFTLW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTRW (KSHIFTRW-128-1)
|
|
{
|
|
ICLASS: KSHIFTRW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KUNPCKBW (KUNPCKBW-256-1)
|
|
{
|
|
ICLASS: KUNPCKBW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXNORW (KXNORW-256-1)
|
|
{
|
|
ICLASS: KXNORW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXORW (KXORW-256-1)
|
|
{
|
|
ICLASS: KXORW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512F_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512cd/vconflict-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTMB2Q
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8
|
|
IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTMW2D
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16
|
|
IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTD (VPCONFLICTD-512-1)
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1)
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTD (VPLZCNTD-512-1)
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTQ (VPLZCNTQ-512-1)
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/skx-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VADDPD (VADDPD-128-1)
|
|
{
|
|
ICLASS: VADDPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDPD (VADDPD-256-1)
|
|
{
|
|
ICLASS: VADDPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDPS (VADDPS-128-1)
|
|
{
|
|
ICLASS: VADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDPS (VADDPS-256-1)
|
|
{
|
|
ICLASS: VADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VALIGND (VALIGND-128-1)
|
|
{
|
|
ICLASS: VALIGND
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VALIGND
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VALIGND (VALIGND-256-1)
|
|
{
|
|
ICLASS: VALIGND
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VALIGND
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VALIGNQ (VALIGNQ-128-1)
|
|
{
|
|
ICLASS: VALIGNQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VALIGNQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VALIGNQ (VALIGNQ-256-1)
|
|
{
|
|
ICLASS: VALIGNQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VALIGNQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPD (VANDNPD-128-1)
|
|
{
|
|
ICLASS: VANDNPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPD (VANDNPD-256-1)
|
|
{
|
|
ICLASS: VANDNPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPD (VANDNPD-512-1)
|
|
{
|
|
ICLASS: VANDNPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPS (VANDNPS-128-1)
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPS (VANDNPS-256-1)
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDNPS (VANDNPS-512-1)
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDNPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPD (VANDPD-128-1)
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPD (VANDPD-256-1)
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPD (VANDPD-512-1)
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPS (VANDPS-128-1)
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPS (VANDPS-256-1)
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VANDPS (VANDPS-512-1)
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VANDPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPD (VBLENDMPD-128-1)
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPD (VBLENDMPD-256-1)
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPS (VBLENDMPS-128-1)
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBLENDMPS (VBLENDMPS-256-1)
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBLENDMPS
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTF32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32
|
|
IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF32X8
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32
|
|
IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTF64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64
|
|
IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTF64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64
|
|
IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32
|
|
IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32
|
|
IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32
|
|
IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VBROADCASTI32X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32
|
|
IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X4
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32
|
|
IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI32X8
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32
|
|
IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1)
|
|
{
|
|
ICLASS: VBROADCASTI64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64
|
|
IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1)
|
|
{
|
|
ICLASS: VBROADCASTI64X2
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64
|
|
IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSD (VBROADCASTSD-256-1)
|
|
{
|
|
ICLASS: VBROADCASTSD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSD (VBROADCASTSD-256-2)
|
|
{
|
|
ICLASS: VBROADCASTSD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-128-1)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-128-2)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-256-1)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VBROADCASTSS (VBROADCASTSS-256-2)
|
|
{
|
|
ICLASS: VBROADCASTSS
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPD (VCMPPD-128-1)
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPD (VCMPPD-256-1)
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPS (VCMPPS-128-1)
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPS (VCMPPS-256-1)
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64
|
|
IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2)
|
|
{
|
|
ICLASS: VCOMPRESSPD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64
|
|
IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32
|
|
IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2)
|
|
{
|
|
ICLASS: VCOMPRESSPS
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32
|
|
IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PS (VCVTPD2PS-128-1)
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PS (VCVTPD2PS-256-1)
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PS (VCVTPH2PS-128-2)
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16
|
|
IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PS (VCVTPH2PS-256-2)
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16
|
|
IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PD (VCVTPS2PD-128-1)
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PD (VCVTPS2PD-256-1)
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-128-2)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-128-3)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-256-2)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PH (VCVTPS2PH-256-3)
|
|
{
|
|
ICLASS: VCVTPS2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E11
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM
|
|
PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1)
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1)
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPD2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPS2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VDBPSADBW (VDBPSADBW-128-1)
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDBPSADBW (VDBPSADBW-256-1)
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDBPSADBW (VDBPSADBW-512-1)
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDBPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPD (VDIVPD-128-1)
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPD (VDIVPD-256-1)
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPS (VDIVPS-128-1)
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPS (VDIVPS-256-1)
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-128-1)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
|
|
IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-128-2)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-256-1)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPD (VEXPANDPD-256-2)
|
|
{
|
|
ICLASS: VEXPANDPD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-128-1)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-128-2)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-256-1)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXPANDPS (VEXPANDPS-256-2)
|
|
{
|
|
ICLASS: VEXPANDPS
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1)
|
|
{
|
|
ICLASS: VEXTRACTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2)
|
|
{
|
|
ICLASS: VEXTRACTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1)
|
|
{
|
|
ICLASS: VEXTRACTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2)
|
|
{
|
|
ICLASS: VEXTRACTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b
|
|
IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2)
|
|
{
|
|
ICLASS: VEXTRACTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b
|
|
IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1)
|
|
{
|
|
ICLASS: VEXTRACTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2)
|
|
{
|
|
ICLASS: VEXTRACTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1)
|
|
{
|
|
ICLASS: VEXTRACTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2)
|
|
{
|
|
ICLASS: VEXTRACTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b
|
|
IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2)
|
|
{
|
|
ICLASS: VEXTRACTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b
|
|
IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1)
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFIXUPIMMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PD (VFMADD132PD-128-1)
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PD (VFMADD132PD-256-1)
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PS (VFMADD132PS-128-1)
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PS (VFMADD132PS-256-1)
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PD (VFMADD213PD-128-1)
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PD (VFMADD213PD-256-1)
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PS (VFMADD213PS-128-1)
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PS (VFMADD213PS-256-1)
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PD (VFMADD231PD-128-1)
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PD (VFMADD231PD-256-1)
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PS (VFMADD231PS-128-1)
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PS (VFMADD231PS-256-1)
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PD (VFMSUB132PD-128-1)
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PD (VFMSUB132PD-256-1)
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PS (VFMSUB132PS-128-1)
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PS (VFMSUB132PS-256-1)
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PD (VFMSUB213PD-128-1)
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PD (VFMSUB213PD-256-1)
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PS (VFMSUB213PS-128-1)
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PS (VFMSUB213PS-256-1)
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PD (VFMSUB231PD-128-1)
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PD (VFMSUB231PD-256-1)
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PS (VFMSUB231PS-128-1)
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PS (VFMSUB231PS-256-1)
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PD (VFNMADD132PD-128-1)
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PD (VFNMADD132PD-256-1)
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PS (VFNMADD132PS-128-1)
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PS (VFNMADD132PS-256-1)
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PD (VFNMADD213PD-128-1)
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PD (VFNMADD213PD-256-1)
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PS (VFNMADD213PS-128-1)
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PS (VFNMADD213PS-256-1)
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PD (VFNMADD231PD-128-1)
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PD (VFNMADD231PD-256-1)
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PS (VFNMADD231PS-128-1)
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PS (VFNMADD231PS-256-1)
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1)
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1)
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1)
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1)
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1)
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PD
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1)
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PS
|
|
CPL: 3
|
|
CATEGORY: VFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPD (VFPCLASSPD-128-1)
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPD (VFPCLASSPD-256-1)
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPD (VFPCLASSPD-512-1)
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPS (VFPCLASSPS-128-1)
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPS (VFPCLASSPS-256-1)
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPS (VFPCLASSPS-512-1)
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSSD (VFPCLASSSD-128-1)
|
|
{
|
|
ICLASS: VFPCLASSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSSS (VFPCLASSSS-128-1)
|
|
{
|
|
ICLASS: VFPCLASSSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSSS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPD (VGATHERDPD-128-2)
|
|
{
|
|
ICLASS: VGATHERDPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
|
|
IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPD (VGATHERDPD-256-2)
|
|
{
|
|
ICLASS: VGATHERDPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
|
|
IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPS (VGATHERDPS-128-2)
|
|
{
|
|
ICLASS: VGATHERDPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
|
|
IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERDPS (VGATHERDPS-256-2)
|
|
{
|
|
ICLASS: VGATHERDPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
|
|
IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPD (VGATHERQPD-128-2)
|
|
{
|
|
ICLASS: VGATHERQPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
|
|
IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPD (VGATHERQPD-256-2)
|
|
{
|
|
ICLASS: VGATHERQPD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64
|
|
IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPS (VGATHERQPS-128-2)
|
|
{
|
|
ICLASS: VGATHERQPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
|
|
IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VGATHERQPS (VGATHERQPS-256-2)
|
|
{
|
|
ICLASS: VGATHERQPS
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32
|
|
IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPD (VGETEXPPD-128-1)
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPD (VGETEXPPD-256-1)
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPS (VGETEXPPS-128-1)
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPS (VGETEXPPS-256-1)
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPD (VGETMANTPD-128-1)
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPD (VGETMANTPD-256-1)
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPS (VGETMANTPS-128-1)
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPS (VGETMANTPS-256-1)
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF32X4 (VINSERTF32X4-256-1)
|
|
{
|
|
ICLASS: VINSERTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF32X8 (VINSERTF32X8-512-1)
|
|
{
|
|
ICLASS: VINSERTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b
|
|
IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF64X2 (VINSERTF64X2-256-1)
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTF64X2 (VINSERTF64X2-512-1)
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b
|
|
IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI32X4 (VINSERTI32X4-256-1)
|
|
{
|
|
ICLASS: VINSERTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI32X8 (VINSERTI32X8-512-1)
|
|
{
|
|
ICLASS: VINSERTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI32X8
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8
|
|
PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b
|
|
IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI64X2 (VINSERTI64X2-256-1)
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VINSERTI64X2 (VINSERTI64X2-512-1)
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VINSERTI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2
|
|
PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPD (VMAXPD-128-1)
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPD (VMAXPD-256-1)
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPS (VMAXPS-128-1)
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPS (VMAXPS-256-1)
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPD (VMINPD-128-1)
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPD (VMINPD-256-1)
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPS (VMINPS-128-1)
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPS (VMINPS-256-1)
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-128-1)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
|
|
IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-128-2)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64
|
|
IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-128-3)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-256-1)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-256-2)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64
|
|
IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPD (VMOVAPD-256-3)
|
|
{
|
|
ICLASS: VMOVAPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-128-1)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-128-2)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32
|
|
IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-128-3)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-256-1)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-256-2)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32
|
|
IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVAPS (VMOVAPS-256-3)
|
|
{
|
|
ICLASS: VMOVAPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDDUP (VMOVDDUP-128-1)
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64
|
|
IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDDUP (VMOVDDUP-256-1)
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP
|
|
PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-128-1)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
|
|
IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-128-2)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-128-3)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-256-1)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
|
|
IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-256-2)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA32 (VMOVDQA32-256-3)
|
|
{
|
|
ICLASS: VMOVDQA32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-128-1)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
|
|
IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-128-2)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-128-3)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-256-1)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
|
|
IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-256-2)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQA64 (VMOVDQA64-256-3)
|
|
{
|
|
ICLASS: VMOVDQA64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-128-1)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
|
|
IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
|
|
IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-128-2)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
|
|
IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-128-3)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
|
|
IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-256-1)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
|
|
IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
|
|
IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-256-2)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
|
|
IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-256-3)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
|
|
IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-512-1)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
|
|
IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
|
|
IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-512-2)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
|
|
IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU16 (VMOVDQU16-512-3)
|
|
{
|
|
ICLASS: VMOVDQU16
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
|
|
IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-128-1)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
|
|
IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-128-2)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-128-3)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-256-1)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
|
|
IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-256-2)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU32 (VMOVDQU32-256-3)
|
|
{
|
|
ICLASS: VMOVDQU32
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-128-1)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
|
|
IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-128-2)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-128-3)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-256-1)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
|
|
IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-256-2)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU64 (VMOVDQU64-256-3)
|
|
{
|
|
ICLASS: VMOVDQU64
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-128-1)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
|
|
IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
|
|
IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-128-2)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8
|
|
IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-128-3)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8
|
|
IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-256-1)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
|
|
IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
|
|
IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-256-2)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8
|
|
IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-256-3)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8
|
|
IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-512-1)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
|
|
IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
|
|
IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-512-2)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8
|
|
IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVDQU8 (VMOVDQU8-512-3)
|
|
{
|
|
ICLASS: VMOVDQU8
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8
|
|
IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQ (VMOVNTDQ-128-1)
|
|
{
|
|
ICLASS: VMOVNTDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32
|
|
IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQ (VMOVNTDQ-256-1)
|
|
{
|
|
ICLASS: VMOVNTDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32
|
|
IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQA (VMOVNTDQA-128-1)
|
|
{
|
|
ICLASS: VMOVNTDQA
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTDQA (VMOVNTDQA-256-1)
|
|
{
|
|
ICLASS: VMOVNTDQA
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32
|
|
IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPD (VMOVNTPD-128-1)
|
|
{
|
|
ICLASS: VMOVNTPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64
|
|
IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPD (VMOVNTPD-256-1)
|
|
{
|
|
ICLASS: VMOVNTPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64
|
|
IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPS (VMOVNTPS-128-1)
|
|
{
|
|
ICLASS: VMOVNTPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32
|
|
IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVNTPS (VMOVNTPS-256-1)
|
|
{
|
|
ICLASS: VMOVNTPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E1NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL
|
|
PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32
|
|
IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSHDUP (VMOVSHDUP-128-1)
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSHDUP (VMOVSHDUP-256-1)
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSHDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSLDUP (VMOVSLDUP-128-1)
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSLDUP (VMOVSLDUP-256-1)
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVSLDUP
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-128-1)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
|
|
IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-128-2)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64
|
|
IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-128-3)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-256-1)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
|
|
IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-256-2)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64
|
|
IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPD (VMOVUPD-256-3)
|
|
{
|
|
ICLASS: VMOVUPD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-128-1)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32
|
|
IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-128-2)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32
|
|
IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-128-3)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-256-1)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32
|
|
IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-256-2)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32
|
|
IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVUPS (VMOVUPS-256-3)
|
|
{
|
|
ICLASS: VMOVUPS
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()
|
|
OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPD (VMULPD-128-1)
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPD (VMULPD-256-1)
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPS (VMULPS-128-1)
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPS (VMULPS-256-1)
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPD (VORPD-128-1)
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPD (VORPD-256-1)
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPD (VORPD-512-1)
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPS (VORPS-128-1)
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPS (VORPS-256-1)
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VORPS (VORPS-512-1)
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSB (VPABSB-128-1)
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSB (VPABSB-256-1)
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8
|
|
IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
|
|
IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSB (VPABSB-512-1)
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8
|
|
IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8
|
|
IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSD (VPABSD-128-1)
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSD (VPABSD-256-1)
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSQ (VPABSQ-128-1)
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64
|
|
IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSQ (VPABSQ-256-1)
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64
|
|
IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSW (VPABSW-128-1)
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSW (VPABSW-256-1)
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
|
|
IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16
|
|
IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPABSW (VPABSW-512-1)
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16
|
|
IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPABSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16
|
|
IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSDW (VPACKSSDW-128-1)
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSDW (VPACKSSDW-256-1)
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSDW (VPACKSSDW-512-1)
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32
|
|
IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSWB (VPACKSSWB-128-1)
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSWB (VPACKSSWB-256-1)
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKSSWB (VPACKSSWB-512-1)
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKSSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSDW (VPACKUSDW-128-1)
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSDW (VPACKUSDW-256-1)
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSDW (VPACKUSDW-512-1)
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSWB (VPACKUSWB-128-1)
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSWB (VPACKUSWB-256-1)
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPACKUSWB (VPACKUSWB-512-1)
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPACKUSWB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDB (VPADDB-128-1)
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDB (VPADDB-256-1)
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDB (VPADDB-512-1)
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDD (VPADDD-128-1)
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDD (VPADDD-256-1)
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDQ (VPADDQ-128-1)
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDQ (VPADDQ-256-1)
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSB (VPADDSB-128-1)
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSB (VPADDSB-256-1)
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSB (VPADDSB-512-1)
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSW (VPADDSW-128-1)
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSW (VPADDSW-256-1)
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDSW (VPADDSW-512-1)
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSB (VPADDUSB-128-1)
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSB (VPADDUSB-256-1)
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSB (VPADDUSB-512-1)
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSW (VPADDUSW-128-1)
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSW (VPADDUSW-256-1)
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDUSW (VPADDUSW-512-1)
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDW (VPADDW-128-1)
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDW (VPADDW-256-1)
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPADDW (VPADDW-512-1)
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPADDW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPALIGNR (VPALIGNR-128-1)
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPALIGNR (VPALIGNR-256-1)
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPALIGNR (VPALIGNR-512-1)
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPALIGNR
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDD (VPANDD-128-1)
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDD (VPANDD-256-1)
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDND (VPANDND-128-1)
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDND (VPANDND-256-1)
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDND
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDNQ (VPANDNQ-128-1)
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDNQ (VPANDNQ-256-1)
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDNQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDQ (VPANDQ-128-1)
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPANDQ (VPANDQ-256-1)
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPANDQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGB (VPAVGB-128-1)
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGB (VPAVGB-256-1)
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGB (VPAVGB-512-1)
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGW (VPAVGW-128-1)
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGW (VPAVGW-256-1)
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPAVGW (VPAVGW-512-1)
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPAVGW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMB (VPBLENDMB-128-1)
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMB (VPBLENDMB-256-1)
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMB (VPBLENDMB-512-1)
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMB
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMD (VPBLENDMD-128-1)
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMD (VPBLENDMD-256-1)
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMD
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMQ (VPBLENDMQ-128-1)
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMQ (VPBLENDMQ-256-1)
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMQ
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL
|
|
PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMW (VPBLENDMW-128-1)
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMW (VPBLENDMW-256-1)
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBLENDMW (VPBLENDMW-512-1)
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBLENDMW
|
|
CPL: 3
|
|
CATEGORY: BLEND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL
|
|
PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8
|
|
IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8
|
|
IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8
|
|
IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8
|
|
IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8
|
|
IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8
|
|
IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8
|
|
IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE
|
|
PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8
|
|
IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTB (VPBROADCASTB-512-2)
|
|
{
|
|
ICLASS: VPBROADCASTB
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8
|
|
IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-128-3)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32
|
|
IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTD (VPBROADCASTD-256-3)
|
|
{
|
|
ICLASS: VPBROADCASTD
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32
|
|
IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTMB2Q
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8
|
|
IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTMB2Q
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8
|
|
IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTMW2D
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16
|
|
IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTMW2D
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64
|
|
IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64
|
|
IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64
|
|
IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3)
|
|
{
|
|
ICLASS: VPBROADCASTQ
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64
|
|
IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-128-1)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-128-2)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16
|
|
IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-256-1)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16
|
|
IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16
|
|
IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-256-2)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16
|
|
IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-512-1)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16
|
|
IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD
|
|
PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16
|
|
IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPBROADCASTW (VPBROADCASTW-512-2)
|
|
{
|
|
ICLASS: VPBROADCASTW
|
|
CPL: 3
|
|
CATEGORY: BROADCAST
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16
|
|
IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPB (VPCMPB-128-1)
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPB (VPCMPB-256-1)
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPB (VPCMPB-512-1)
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b
|
|
IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPD (VPCMPD-128-1)
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPD (VPCMPD-256-1)
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQB (VPCMPEQB-128-1)
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQB (VPCMPEQB-256-1)
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQB (VPCMPEQB-512-1)
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQD (VPCMPEQD-128-1)
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQD (VPCMPEQD-256-1)
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQQ (VPCMPEQQ-128-1)
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQQ (VPCMPEQQ-256-1)
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQW (VPCMPEQW-128-1)
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQW (VPCMPEQW-256-1)
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPEQW (VPCMPEQW-512-1)
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPEQW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTB (VPCMPGTB-128-1)
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTB (VPCMPGTB-256-1)
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTB (VPCMPGTB-512-1)
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTD (VPCMPGTD-128-1)
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTD (VPCMPGTD-256-1)
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTQ (VPCMPGTQ-128-1)
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTQ (VPCMPGTQ-256-1)
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTW (VPCMPGTW-128-1)
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTW (VPCMPGTW-256-1)
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPGTW (VPCMPGTW-512-1)
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPGTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPQ (VPCMPQ-128-1)
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPQ (VPCMPQ-256-1)
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUB (VPCMPUB-128-1)
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUB (VPCMPUB-256-1)
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUB (VPCMPUB-512-1)
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUD (VPCMPUD-128-1)
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUD (VPCMPUD-256-1)
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUQ (VPCMPUQ-128-1)
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUQ (VPCMPUQ-256-1)
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUW (VPCMPUW-128-1)
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUW (VPCMPUW-256-1)
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPUW (VPCMPUW-512-1)
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPW (VPCMPW-128-1)
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPW (VPCMPW-256-1)
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCMPW (VPCMPW-512-1)
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCMPW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b
|
|
IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2)
|
|
{
|
|
ICLASS: VPCOMPRESSD
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2)
|
|
{
|
|
ICLASS: VPCOMPRESSQ
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTD (VPCONFLICTD-128-1)
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTD (VPCONFLICTD-256-1)
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1)
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1)
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCONFLICTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMD (VPERMD-256-1)
|
|
{
|
|
ICLASS: VPERMD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2D (VPERMI2D-128-1)
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2D (VPERMI2D-256-1)
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PD (VPERMI2PD-128-1)
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PD (VPERMI2PD-256-1)
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PS (VPERMI2PS-128-1)
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2PS (VPERMI2PS-256-1)
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2Q (VPERMI2Q-128-1)
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2Q (VPERMI2Q-256-1)
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2W (VPERMI2W-128-1)
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2W (VPERMI2W-256-1)
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2W (VPERMI2W-512-1)
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-128-1)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-128-2)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-256-1)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPD (VPERMILPD-256-2)
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-128-1)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-128-2)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-256-1)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMILPS (VPERMILPS-256-2)
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMILPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPD (VPERMPD-256-1)
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPD (VPERMPD-256-2)
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMPS (VPERMPS-256-1)
|
|
{
|
|
ICLASS: VPERMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMQ (VPERMQ-256-1)
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMQ (VPERMQ-256-2)
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2D (VPERMT2D-128-1)
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2D (VPERMT2D-256-1)
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2D
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PD (VPERMT2PD-128-1)
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PD (VPERMT2PD-256-1)
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PS (VPERMT2PS-128-1)
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2PS (VPERMT2PS-256-1)
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2Q (VPERMT2Q-128-1)
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2Q (VPERMT2Q-256-1)
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2Q
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2W (VPERMT2W-128-1)
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2W (VPERMT2W-256-1)
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2W (VPERMT2W-512-1)
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2W
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMW (VPERMW-128-1)
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMW (VPERMW-256-1)
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMW (VPERMW-512-1)
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-128-1)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32
|
|
IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-128-2)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-256-1)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32
|
|
IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDD (VPEXPANDD-256-2)
|
|
{
|
|
ICLASS: VPEXPANDD
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-128-1)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64
|
|
IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-128-2)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-256-1)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64
|
|
IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDQ (VPEXPANDQ-256-2)
|
|
{
|
|
ICLASS: VPEXPANDQ
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRB (VPEXTRB-128-1)
|
|
{
|
|
ICLASS: VPEXTRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE
|
|
PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE()
|
|
OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRD (VPEXTRD-128-1)
|
|
{
|
|
ICLASS: VPEXTRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRQ (VPEXTRQ-128-1)
|
|
{
|
|
ICLASS: VPEXTRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRW (VPEXTRW-128-1)
|
|
{
|
|
ICLASS: VPEXTRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPEXTRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD
|
|
PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD()
|
|
OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXTRW (VPEXTRW-128-2)
|
|
{
|
|
ICLASS: VPEXTRW_C5
|
|
DISASM: vpextrw
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
|
|
PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64
|
|
OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5
|
|
|
|
PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDD (VPGATHERDD-128-2)
|
|
{
|
|
ICLASS: VPGATHERDD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
|
|
IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDD (VPGATHERDD-256-2)
|
|
{
|
|
ICLASS: VPGATHERDD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
|
|
IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDQ (VPGATHERDQ-128-2)
|
|
{
|
|
ICLASS: VPGATHERDQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
|
|
IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERDQ (VPGATHERDQ-256-2)
|
|
{
|
|
ICLASS: VPGATHERDQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
|
|
IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQD (VPGATHERQD-128-2)
|
|
{
|
|
ICLASS: VPGATHERQD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
|
|
IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQD (VPGATHERQD-256-2)
|
|
{
|
|
ICLASS: VPGATHERQD
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32
|
|
IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQQ (VPGATHERQQ-128-2)
|
|
{
|
|
ICLASS: VPGATHERQQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
|
|
IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPGATHERQQ (VPGATHERQQ-256-2)
|
|
{
|
|
ICLASS: VPGATHERQQ
|
|
CPL: 3
|
|
CATEGORY: GATHER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64
|
|
IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRB (VPINSRB-128-1)
|
|
{
|
|
ICLASS: VPINSRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b
|
|
IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER_BYTE
|
|
PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b
|
|
IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRD (VPINSRD-128-1)
|
|
{
|
|
ICLASS: VPINSRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
|
|
IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b
|
|
IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
|
|
IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b
|
|
IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRQ (VPINSRQ-128-1)
|
|
{
|
|
ICLASS: VPINSRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b
|
|
IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER
|
|
PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b
|
|
IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPINSRW (VPINSRW-128-1)
|
|
{
|
|
ICLASS: VPINSRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b
|
|
IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPINSRW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER_WORD
|
|
PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b
|
|
IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTD (VPLZCNTD-128-1)
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTD (VPLZCNTD-256-1)
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTD
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTQ (VPLZCNTQ-128-1)
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPLZCNTQ (VPLZCNTQ-256-1)
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPLZCNTQ
|
|
CPL: 3
|
|
CATEGORY: CONFLICT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512CD_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDUBSW (VPMADDUBSW-128-1)
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDUBSW (VPMADDUBSW-256-1)
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDUBSW (VPMADDUBSW-512-1)
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDWD (VPMADDWD-128-1)
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDWD (VPMADDWD-256-1)
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADDWD (VPMADDWD-512-1)
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADDWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSB (VPMAXSB-128-1)
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSB (VPMAXSB-256-1)
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSB (VPMAXSB-512-1)
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSD (VPMAXSD-128-1)
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSD (VPMAXSD-256-1)
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSQ (VPMAXSQ-128-1)
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
|
|
IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSQ (VPMAXSQ-256-1)
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
|
|
IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSW (VPMAXSW-128-1)
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSW (VPMAXSW-256-1)
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXSW (VPMAXSW-512-1)
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUB (VPMAXUB-128-1)
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUB (VPMAXUB-256-1)
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUB (VPMAXUB-512-1)
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUD (VPMAXUD-128-1)
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUD (VPMAXUD-256-1)
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUQ (VPMAXUQ-128-1)
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUQ (VPMAXUQ-256-1)
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUW (VPMAXUW-128-1)
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUW (VPMAXUW-256-1)
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMAXUW (VPMAXUW-512-1)
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMAXUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSB (VPMINSB-128-1)
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSB (VPMINSB-256-1)
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSB (VPMINSB-512-1)
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSD (VPMINSD-128-1)
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32
|
|
IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSD (VPMINSD-256-1)
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32
|
|
IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSQ (VPMINSQ-128-1)
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
|
|
IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSQ (VPMINSQ-256-1)
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
|
|
IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSW (VPMINSW-128-1)
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSW (VPMINSW-256-1)
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINSW (VPMINSW-512-1)
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUB (VPMINUB-128-1)
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUB (VPMINUB-256-1)
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUB (VPMINUB-512-1)
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUD (VPMINUD-128-1)
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUD (VPMINUD-256-1)
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUQ (VPMINUQ-128-1)
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUQ (VPMINUQ-256-1)
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUW (VPMINUW-128-1)
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUW (VPMINUW-256-1)
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMINUW (VPMINUW-512-1)
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMINUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVB2M (VPMOVB2M-128-1)
|
|
{
|
|
ICLASS: VPMOVB2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8
|
|
IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVB2M (VPMOVB2M-256-1)
|
|
{
|
|
ICLASS: VPMOVB2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8
|
|
IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVB2M (VPMOVB2M-512-1)
|
|
{
|
|
ICLASS: VPMOVB2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8
|
|
IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVD2M (VPMOVD2M-128-1)
|
|
{
|
|
ICLASS: VPMOVD2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32
|
|
IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVD2M (VPMOVD2M-256-1)
|
|
{
|
|
ICLASS: VPMOVD2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32
|
|
IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVD2M (VPMOVD2M-512-1)
|
|
{
|
|
ICLASS: VPMOVD2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32
|
|
IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-128-1)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-128-2)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-256-1)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDB (VPMOVDB-256-2)
|
|
{
|
|
ICLASS: VPMOVDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-128-1)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-128-2)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-256-1)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVDW (VPMOVDW-256-2)
|
|
{
|
|
ICLASS: VPMOVDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2B (VPMOVM2B-128-1)
|
|
{
|
|
ICLASS: VPMOVM2B
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2B (VPMOVM2B-256-1)
|
|
{
|
|
ICLASS: VPMOVM2B
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2B (VPMOVM2B-512-1)
|
|
{
|
|
ICLASS: VPMOVM2B
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2D (VPMOVM2D-128-1)
|
|
{
|
|
ICLASS: VPMOVM2D
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2D (VPMOVM2D-256-1)
|
|
{
|
|
ICLASS: VPMOVM2D
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2D (VPMOVM2D-512-1)
|
|
{
|
|
ICLASS: VPMOVM2D
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2Q (VPMOVM2Q-128-1)
|
|
{
|
|
ICLASS: VPMOVM2Q
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2Q (VPMOVM2Q-256-1)
|
|
{
|
|
ICLASS: VPMOVM2Q
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2Q (VPMOVM2Q-512-1)
|
|
{
|
|
ICLASS: VPMOVM2Q
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2W (VPMOVM2W-128-1)
|
|
{
|
|
ICLASS: VPMOVM2W
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2W (VPMOVM2W-256-1)
|
|
{
|
|
ICLASS: VPMOVM2W
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVM2W (VPMOVM2W-512-1)
|
|
{
|
|
ICLASS: VPMOVM2W
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw
|
|
IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQ2M (VPMOVQ2M-128-1)
|
|
{
|
|
ICLASS: VPMOVQ2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64
|
|
IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQ2M (VPMOVQ2M-256-1)
|
|
{
|
|
ICLASS: VPMOVQ2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64
|
|
IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQ2M (VPMOVQ2M-512-1)
|
|
{
|
|
ICLASS: VPMOVQ2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64
|
|
IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-128-1)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-128-2)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-256-1)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQB (VPMOVQB-256-2)
|
|
{
|
|
ICLASS: VPMOVQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-128-1)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-128-2)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-256-1)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQD (VPMOVQD-256-2)
|
|
{
|
|
ICLASS: VPMOVQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-128-1)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-128-2)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-256-1)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVQW (VPMOVQW-256-2)
|
|
{
|
|
ICLASS: VPMOVQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-128-1)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-128-2)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-256-1)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDB (VPMOVSDB-256-2)
|
|
{
|
|
ICLASS: VPMOVSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-128-1)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-128-2)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32
|
|
IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-256-1)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSDW (VPMOVSDW-256-2)
|
|
{
|
|
ICLASS: VPMOVSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32
|
|
IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-128-1)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-128-2)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-256-1)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQB (VPMOVSQB-256-2)
|
|
{
|
|
ICLASS: VPMOVSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-128-1)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-128-2)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-256-1)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQD (VPMOVSQD-256-2)
|
|
{
|
|
ICLASS: VPMOVSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-128-1)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-128-2)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64
|
|
IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-256-1)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSQW (VPMOVSQW-256-2)
|
|
{
|
|
ICLASS: VPMOVSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64
|
|
IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-128-1)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16
|
|
IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-128-2)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16
|
|
IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-256-1)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16
|
|
IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-256-2)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16
|
|
IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-512-1)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16
|
|
IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSWB (VPMOVSWB-512-2)
|
|
{
|
|
ICLASS: VPMOVSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16
|
|
IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBD (VPMOVSXBD-128-1)
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBD (VPMOVSXBD-256-1)
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1)
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8
|
|
IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1)
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBW (VPMOVSXBW-128-1)
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBW (VPMOVSXBW-256-1)
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXBW (VPMOVSXBW-512-1)
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8
|
|
IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
|
|
IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1)
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32
|
|
IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1)
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32
|
|
IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWD (VPMOVSXWD-128-1)
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWD (VPMOVSXWD-256-1)
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1)
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16
|
|
IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1)
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVSXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-128-1)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-128-2)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-256-1)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDB (VPMOVUSDB-256-2)
|
|
{
|
|
ICLASS: VPMOVUSDB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-128-1)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-128-2)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-256-1)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSDW (VPMOVUSDW-256-2)
|
|
{
|
|
ICLASS: VPMOVUSDW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-128-1)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-128-2)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-256-1)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQB (VPMOVUSQB-256-2)
|
|
{
|
|
ICLASS: VPMOVUSQB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-128-1)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-128-2)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-256-1)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQD (VPMOVUSQD-256-2)
|
|
{
|
|
ICLASS: VPMOVUSQD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-128-1)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-128-2)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-256-1)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSQW (VPMOVUSQW-256-2)
|
|
{
|
|
ICLASS: VPMOVUSQW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-128-1)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-128-2)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-256-1)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-256-2)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-512-1)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
|
|
IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVUSWB (VPMOVUSWB-512-2)
|
|
{
|
|
ICLASS: VPMOVUSWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
|
|
IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVW2M (VPMOVW2M-128-1)
|
|
{
|
|
ICLASS: VPMOVW2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16
|
|
IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVW2M (VPMOVW2M-256-1)
|
|
{
|
|
ICLASS: VPMOVW2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16
|
|
IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVW2M (VPMOVW2M-512-1)
|
|
{
|
|
ICLASS: VPMOVW2M
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E7NM
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16
|
|
IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-128-1)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-128-2)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
|
|
IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-256-1)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-256-2)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
|
|
IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-512-1)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
|
|
IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVWB (VPMOVWB-512-2)
|
|
{
|
|
ICLASS: VPMOVWB
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
|
|
IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBD (VPMOVZXBD-128-1)
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBD (VPMOVZXBD-256-1)
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1)
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8
|
|
IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1)
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM
|
|
PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8
|
|
IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBW (VPMOVZXBW-128-1)
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8
|
|
IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBW (VPMOVZXBW-256-1)
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8
|
|
IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8
|
|
IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXBW (VPMOVZXBW-512-1)
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8
|
|
IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXBW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8
|
|
IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1)
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32
|
|
IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1)
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXDQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32
|
|
IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWD (VPMOVZXWD-128-1)
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWD (VPMOVZXWD-256-1)
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWD
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM
|
|
PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
|
|
IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1)
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16
|
|
IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1)
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMOVZXWQ
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM
|
|
PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
|
|
IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULDQ (VPMULDQ-128-1)
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64
|
|
IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULDQ (VPMULDQ-256-1)
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64
|
|
IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
|
|
PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR
|
|
IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHRSW (VPMULHRSW-128-1)
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHRSW (VPMULHRSW-256-1)
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHRSW (VPMULHRSW-512-1)
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHRSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHUW (VPMULHUW-128-1)
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHUW (VPMULHUW-256-1)
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHUW (VPMULHUW-512-1)
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHUW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHW (VPMULHW-128-1)
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHW (VPMULHW-256-1)
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULHW (VPMULHW-512-1)
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLD (VPMULLD-128-1)
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLD (VPMULLD-256-1)
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLQ (VPMULLQ-128-1)
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLQ (VPMULLQ-256-1)
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLQ (VPMULLQ-512-1)
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLW (VPMULLW-128-1)
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLW (VPMULLW-256-1)
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULLW (VPMULLW-512-1)
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULUDQ (VPMULUDQ-128-1)
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULUDQ (VPMULUDQ-256-1)
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULUDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
COMMENT: Strange instruction that uses 32b of each 64b input element
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX
|
|
PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORD (VPORD-128-1)
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORD (VPORD-256-1)
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORQ (VPORQ-128-1)
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPORQ (VPORQ-256-1)
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLD (VPROLD-128-1)
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLD (VPROLD-256-1)
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLQ (VPROLQ-128-1)
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLQ (VPROLQ-256-1)
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVD (VPROLVD-128-1)
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVD (VPROLVD-256-1)
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVQ (VPROLVQ-128-1)
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPROLVQ (VPROLVQ-256-1)
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPROLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORD (VPRORD-128-1)
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORD (VPRORD-256-1)
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORQ (VPRORQ-128-1)
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORQ (VPRORQ-256-1)
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVD (VPRORVD-128-1)
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVD (VPRORVD-256-1)
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVQ (VPRORVQ-128-1)
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPRORVQ (VPRORVQ-256-1)
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPRORVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSADBW (VPSADBW-128-1)
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8
|
|
IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSADBW (VPSADBW-256-1)
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8
|
|
IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSADBW (VPSADBW-512-1)
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8
|
|
IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSADBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDD (VPSCATTERDD-128-1)
|
|
{
|
|
ICLASS: VPSCATTERDD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDD (VPSCATTERDD-256-1)
|
|
{
|
|
ICLASS: VPSCATTERDD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32
|
|
IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1)
|
|
{
|
|
ICLASS: VPSCATTERDQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1)
|
|
{
|
|
ICLASS: VPSCATTERDQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQD (VPSCATTERQD-128-1)
|
|
{
|
|
ICLASS: VPSCATTERQD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQD (VPSCATTERQD-256-1)
|
|
{
|
|
ICLASS: VPSCATTERQD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32
|
|
IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1)
|
|
{
|
|
ICLASS: VPSCATTERQQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64
|
|
IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1)
|
|
{
|
|
ICLASS: VPSCATTERQQ
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64
|
|
IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFB (VPSHUFB-128-1)
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFB (VPSHUFB-256-1)
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFB (VPSHUFB-512-1)
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFD (VPSHUFD-128-1)
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFD (VPSHUFD-256-1)
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFHW (VPSHUFHW-128-1)
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFHW (VPSHUFHW-256-1)
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFHW (VPSHUFHW-512-1)
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFHW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFLW (VPSHUFLW-128-1)
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFLW (VPSHUFLW-256-1)
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFLW (VPSHUFLW-512-1)
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-128-1)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-128-3)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-256-1)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLD (VPSLLD-256-3)
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLDQ (VPSLLDQ-128-2)
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLDQ (VPSLLDQ-256-2)
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLDQ (VPSLLDQ-512-1)
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-128-1)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-128-3)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-256-1)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLQ (VPSLLQ-256-3)
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVD (VPSLLVD-128-1)
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVD (VPSLLVD-256-1)
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVQ (VPSLLVQ-128-1)
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVQ (VPSLLVQ-256-1)
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVW (VPSLLVW-128-1)
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVW (VPSLLVW-256-1)
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLVW (VPSLLVW-512-1)
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-128-1)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-128-3)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-256-1)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-256-3)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-512-1)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSLLW (VPSLLW-512-2)
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSLLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-128-1)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-128-3)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-256-1)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAD (VPSRAD-256-3)
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-128-1)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-128-2)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-256-1)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAQ (VPSRAQ-256-2)
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVD (VPSRAVD-128-1)
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVD (VPSRAVD-256-1)
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVQ (VPSRAVQ-128-1)
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVQ (VPSRAVQ-256-1)
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVW (VPSRAVW-128-1)
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVW (VPSRAVW-256-1)
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAVW (VPSRAVW-512-1)
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-128-1)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-128-2)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-256-1)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-256-2)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-512-1)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRAW (VPSRAW-512-2)
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRAW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-128-1)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-128-2)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-256-1)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLD (VPSRLD-256-2)
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLDQ (VPSRLDQ-128-1)
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLDQ (VPSRLDQ-256-1)
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLDQ (VPSRLDQ-512-1)
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b
|
|
IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b
|
|
IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-128-1)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-128-2)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-256-1)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLQ (VPSRLQ-256-2)
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVD (VPSRLVD-128-1)
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVD (VPSRLVD-256-1)
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVQ (VPSRLVQ-128-1)
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVQ (VPSRLVQ-256-1)
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVW (VPSRLVW-128-1)
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVW (VPSRLVW-256-1)
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLVW (VPSRLVW-512-1)
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLVW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-128-1)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-128-2)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-256-1)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-256-2)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-512-1)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_MEM128
|
|
PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSRLW (VPSRLW-512-2)
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSRLW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBB (VPSUBB-128-1)
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBB (VPSUBB-256-1)
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBB (VPSUBB-512-1)
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBD (VPSUBD-128-1)
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBD (VPSUBD-256-1)
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBQ (VPSUBQ-128-1)
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBQ (VPSUBQ-256-1)
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSB (VPSUBSB-128-1)
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8
|
|
IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8
|
|
IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSB (VPSUBSB-256-1)
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8
|
|
IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8
|
|
IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSB (VPSUBSB-512-1)
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8
|
|
IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8
|
|
IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSW (VPSUBSW-128-1)
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16
|
|
IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16
|
|
IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSW (VPSUBSW-256-1)
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16
|
|
IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16
|
|
IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBSW (VPSUBSW-512-1)
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16
|
|
IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16
|
|
IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSB (VPSUBUSB-128-1)
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSB (VPSUBUSB-256-1)
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSB (VPSUBUSB-512-1)
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSW (VPSUBUSW-128-1)
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSW (VPSUBUSW-256-1)
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBUSW (VPSUBUSW-512-1)
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBUSW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBW (VPSUBW-128-1)
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBW (VPSUBW-256-1)
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSUBW (VPSUBW-512-1)
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSUBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGD (VPTERNLOGD-128-1)
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGD (VPTERNLOGD-256-1)
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1)
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1)
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTERNLOGQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMB (VPTESTMB-128-1)
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMB (VPTESTMB-256-1)
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMB (VPTESTMB-512-1)
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMD (VPTESTMD-128-1)
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMD (VPTESTMD-256-1)
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMQ (VPTESTMQ-128-1)
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMQ (VPTESTMQ-256-1)
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMW (VPTESTMW-128-1)
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMW (VPTESTMW-256-1)
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTMW (VPTESTMW-512-1)
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMB (VPTESTNMB-128-1)
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMB (VPTESTNMB-256-1)
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMB (VPTESTNMB-512-1)
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMB
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMD (VPTESTNMD-128-1)
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMD (VPTESTNMD-256-1)
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMQ (VPTESTNMQ-128-1)
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMQ (VPTESTNMQ-256-1)
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMW (VPTESTNMW-128-1)
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMW (VPTESTNMW-256-1)
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPTESTNMW (VPTESTNMW-512-1)
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPTESTNMW
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1)
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1)
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1)
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1)
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKHWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1)
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLBW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLQDQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1)
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1)
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1)
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPUNPCKLWD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512BW_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORD (VPXORD-128-1)
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORD (VPXORD-256-1)
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORQ (VPXORQ-128-1)
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPXORQ (VPXORQ-256-1)
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPXORQ
|
|
CPL: 3
|
|
CATEGORY: LOGICAL
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPD (VRANGEPD-128-1)
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPD (VRANGEPD-256-1)
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPD (VRANGEPD-512-1)
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPS (VRANGEPS-128-1)
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPS (VRANGEPS-256-1)
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGEPS (VRANGEPS-512-1)
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGESD (VRANGESD-128-1)
|
|
{
|
|
ICLASS: VRANGESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRANGESS (VRANGESS-128-1)
|
|
{
|
|
ICLASS: VRANGESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRANGESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PD (VRCP14PD-128-1)
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PD (VRCP14PD-256-1)
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PS (VRCP14PS-128-1)
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCP14PS (VRCP14PS-256-1)
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCP14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPD (VREDUCEPD-128-1)
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPD (VREDUCEPD-256-1)
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPD (VREDUCEPD-512-1)
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b
|
|
IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPS (VREDUCEPS-128-1)
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPS (VREDUCEPS-256-1)
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPS (VREDUCEPS-512-1)
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b
|
|
IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCESD (VREDUCESD-128-1)
|
|
{
|
|
ICLASS: VREDUCESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b
|
|
IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCESS (VREDUCESS-128-1)
|
|
{
|
|
ICLASS: VREDUCESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR
|
|
PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b
|
|
IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1)
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1)
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1)
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1)
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PD (VRSQRT14PD-128-1)
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PD (VRSQRT14PD-256-1)
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PS (VRSQRT14PS-128-1)
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRT14PS (VRSQRT14PS-256-1)
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRT14PS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPD (VSCALEFPD-128-1)
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPD (VSCALEFPD-256-1)
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPS (VSCALEFPS-128-1)
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPS (VSCALEFPS-256-1)
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPD (VSCATTERDPD-128-1)
|
|
{
|
|
ICLASS: VSCATTERDPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPD (VSCATTERDPD-256-1)
|
|
{
|
|
ICLASS: VSCATTERDPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPS (VSCATTERDPS-128-1)
|
|
{
|
|
ICLASS: VSCATTERDPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERDPS (VSCATTERDPS-256-1)
|
|
{
|
|
ICLASS: VSCATTERDPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32
|
|
IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPD (VSCATTERQPD-128-1)
|
|
{
|
|
ICLASS: VSCATTERQPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64
|
|
IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPD (VSCATTERQPD-256-1)
|
|
{
|
|
ICLASS: VSCATTERQPD
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64
|
|
IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPS (VSCATTERQPS-128-1)
|
|
{
|
|
ICLASS: VSCATTERQPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VSCATTERQPS (VSCATTERQPS-256-1)
|
|
{
|
|
ICLASS: VSCATTERQPS
|
|
CPL: 3
|
|
CATEGORY: SCATTER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E12
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER
|
|
PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32
|
|
IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFF32X4 (VSHUFF32X4-256-1)
|
|
{
|
|
ICLASS: VSHUFF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFF32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFF64X2 (VSHUFF64X2-256-1)
|
|
{
|
|
ICLASS: VSHUFF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFF64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFI32X4 (VSHUFI32X4-256-1)
|
|
{
|
|
ICLASS: VSHUFI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFI32X4
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFI64X2 (VSHUFI64X2-256-1)
|
|
{
|
|
ICLASS: VSHUFI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFI64X2
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPD (VSHUFPD-128-1)
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b
|
|
IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPD (VSHUFPD-256-1)
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b
|
|
IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPS (VSHUFPS-128-1)
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b
|
|
IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSHUFPS (VSHUFPS-256-1)
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b
|
|
IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSHUFPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPD (VSQRTPD-128-1)
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPD (VSQRTPD-256-1)
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPS (VSQRTPS-128-1)
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPS (VSQRTPS-256-1)
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPD (VSUBPD-128-1)
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPD (VSUBPD-256-1)
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPS (VSUBPS-128-1)
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPS (VSUBPS-256-1)
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED
|
|
PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPD (VUNPCKHPD-128-1)
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPD (VUNPCKHPD-256-1)
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPS (VUNPCKHPS-128-1)
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKHPS (VUNPCKHPS-256-1)
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKHPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPD (VUNPCKLPD-128-1)
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPD (VUNPCKLPD-256-1)
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64
|
|
IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPS (VUNPCKLPS-128-1)
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUNPCKLPS (VUNPCKLPS-256-1)
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32
|
|
IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUNPCKLPS
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512F_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPD (VXORPD-128-1)
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPD (VXORPD-256-1)
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPD (VXORPD-512-1)
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPD
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPS (VXORPS-128-1)
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPS (VXORPS-256-1)
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VXORPS (VXORPS-512-1)
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VXORPS
|
|
CPL: 3
|
|
CATEGORY: LOGICAL_FP
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512DQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
AVX_INSTRUCTIONS()::
|
|
# EMITTING KADDB (KADDB-256-1)
|
|
{
|
|
ICLASS: KADDB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KADDD (KADDD-256-1)
|
|
{
|
|
ICLASS: KADDD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KADDQ (KADDQ-256-1)
|
|
{
|
|
ICLASS: KADDQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KADDW (KADDW-256-1)
|
|
{
|
|
ICLASS: KADDW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDB (KANDB-256-1)
|
|
{
|
|
ICLASS: KANDB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDD (KANDD-256-1)
|
|
{
|
|
ICLASS: KANDD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDNB (KANDNB-256-1)
|
|
{
|
|
ICLASS: KANDNB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDND (KANDND-256-1)
|
|
{
|
|
ICLASS: KANDND
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDNQ (KANDNQ-256-1)
|
|
{
|
|
ICLASS: KANDNQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KANDQ (KANDQ-256-1)
|
|
{
|
|
ICLASS: KANDQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-1)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8
|
|
IFORM: KMOVB_MASKmskw_MASKu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8
|
|
IFORM: KMOVB_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-2)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR
|
|
OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw
|
|
IFORM: KMOVB_MEMu8_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-3)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
|
|
IFORM: KMOVB_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVB (KMOVB-128-4)
|
|
{
|
|
ICLASS: KMOVB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVB_GPR32u32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-1)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32
|
|
IFORM: KMOVD_MASKmskw_MASKu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32
|
|
IFORM: KMOVD_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-2)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR
|
|
OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw
|
|
IFORM: KMOVD_MEMu32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-3)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored.
|
|
PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
|
|
IFORM: KMOVD_MASKmskw_GPR32u32_AVX512
|
|
|
|
PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
|
|
IFORM: KMOVD_MASKmskw_GPR32u32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVD (KMOVD-128-4)
|
|
{
|
|
ICLASS: KMOVD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored.
|
|
PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVD_GPR32u32_MASKmskw_AVX512
|
|
|
|
PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVD_GPR32u32_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-1)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64
|
|
IFORM: KMOVQ_MASKmskw_MASKu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64
|
|
IFORM: KMOVQ_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-2)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K21
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR
|
|
OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw
|
|
IFORM: KMOVQ_MEMu64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-3)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64
|
|
IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KMOVQ (KMOVQ-128-4)
|
|
{
|
|
ICLASS: KMOVQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw
|
|
IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KNOTB (KNOTB-128-1)
|
|
{
|
|
ICLASS: KNOTB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KNOTB_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KNOTD (KNOTD-128-1)
|
|
{
|
|
ICLASS: KNOTD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KNOTD_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KNOTQ (KNOTQ-128-1)
|
|
{
|
|
ICLASS: KNOTQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORB (KORB-256-1)
|
|
{
|
|
ICLASS: KORB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORD (KORD-256-1)
|
|
{
|
|
ICLASS: KORD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORQ (KORQ-256-1)
|
|
{
|
|
ICLASS: KORQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORTESTB (KORTESTB-128-1)
|
|
{
|
|
ICLASS: KORTESTB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORTESTD (KORTESTD-128-1)
|
|
{
|
|
ICLASS: KORTESTD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KORTESTQ (KORTESTQ-128-1)
|
|
{
|
|
ICLASS: KORTESTQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTLB (KSHIFTLB-128-1)
|
|
{
|
|
ICLASS: KSHIFTLB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTLD (KSHIFTLD-128-1)
|
|
{
|
|
ICLASS: KSHIFTLD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTLQ (KSHIFTLQ-128-1)
|
|
{
|
|
ICLASS: KSHIFTLQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTRB (KSHIFTRB-128-1)
|
|
{
|
|
ICLASS: KSHIFTRB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTRD (KSHIFTRD-128-1)
|
|
{
|
|
ICLASS: KSHIFTRD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KSHIFTRQ (KSHIFTRQ-128-1)
|
|
{
|
|
ICLASS: KSHIFTRQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b
|
|
IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTB (KTESTB-128-1)
|
|
{
|
|
ICLASS: KTESTB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTB_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTD (KTESTD-128-1)
|
|
{
|
|
ICLASS: KTESTD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTD_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTQ (KTESTQ-128-1)
|
|
{
|
|
ICLASS: KTESTQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KTESTW (KTESTW-128-1)
|
|
{
|
|
ICLASS: KTESTW
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ]
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR
|
|
OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw
|
|
IFORM: KTESTW_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KUNPCKDQ (KUNPCKDQ-256-1)
|
|
{
|
|
ICLASS: KUNPCKDQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KUNPCKWD (KUNPCKWD-256-1)
|
|
{
|
|
ICLASS: KUNPCKWD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXNORB (KXNORB-256-1)
|
|
{
|
|
ICLASS: KXNORB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXNORD (KXNORD-256-1)
|
|
{
|
|
ICLASS: KXNORD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXNORQ (KXNORQ-256-1)
|
|
{
|
|
ICLASS: KXNORQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXORB (KXORB-256-1)
|
|
{
|
|
ICLASS: KXORB
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512DQ_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXORD (KXORD-256-1)
|
|
{
|
|
ICLASS: KXORD
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING KXORQ (KXORQ-256-1)
|
|
{
|
|
ICLASS: KXORQ
|
|
CPL: 3
|
|
CATEGORY: KMASK
|
|
EXTENSION: AVX512VEX
|
|
ISA_SET: AVX512BW_KOP
|
|
EXCEPTIONS: AVX512-K20
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: KMASK
|
|
PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw
|
|
IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512ifma/ifma-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1)
|
|
{
|
|
ICLASS: VPMADD52HUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADD52HUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1)
|
|
{
|
|
ICLASS: VPMADD52HUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADD52HUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1)
|
|
{
|
|
ICLASS: VPMADD52HUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADD52HUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1)
|
|
{
|
|
ICLASS: VPMADD52LUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADD52LUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1)
|
|
{
|
|
ICLASS: VPMADD52LUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADD52LUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1)
|
|
{
|
|
ICLASS: VPMADD52LUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMADD52LUQ
|
|
CPL: 3
|
|
CATEGORY: IFMA
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_IFMA_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512vbmi/vbmi-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPERMB (VPERMB-128-1)
|
|
{
|
|
ICLASS: VPERMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMB (VPERMB-256-1)
|
|
{
|
|
ICLASS: VPERMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMB (VPERMB-512-1)
|
|
{
|
|
ICLASS: VPERMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2B (VPERMI2B-128-1)
|
|
{
|
|
ICLASS: VPERMI2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2B (VPERMI2B-256-1)
|
|
{
|
|
ICLASS: VPERMI2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMI2B (VPERMI2B-512-1)
|
|
{
|
|
ICLASS: VPERMI2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMI2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2B (VPERMT2B-128-1)
|
|
{
|
|
ICLASS: VPERMT2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2B (VPERMT2B-256-1)
|
|
{
|
|
ICLASS: VPERMT2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPERMT2B (VPERMT2B-512-1)
|
|
{
|
|
ICLASS: VPERMT2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPERMT2B
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1)
|
|
{
|
|
ICLASS: VPMULTISHIFTQB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULTISHIFTQB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_128
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1)
|
|
{
|
|
ICLASS: VPMULTISHIFTQB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULTISHIFTQB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_256
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1)
|
|
{
|
|
ICLASS: VPMULTISHIFTQB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPMULTISHIFTQB
|
|
CPL: 3
|
|
CATEGORY: AVX512_VBMI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI_512
|
|
EXCEPTIONS: AVX512-E4NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/wbnoinvd/wbnoinvd-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
{
|
|
ICLASS : WBINVD
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : BASE
|
|
ISA_SET : I486REAL
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x09 WBNOINVD=0
|
|
OPERANDS :
|
|
PATTERN : 0x0F 0x09 WBNOINVD=1 REP!=3
|
|
OPERANDS :
|
|
VERSION : 2
|
|
}
|
|
|
|
{
|
|
ICLASS : WBNOINVD
|
|
CPL : 0
|
|
CATEGORY : SYSTEM
|
|
EXTENSION : WBNOINVD
|
|
ISA_SET : WBNOINVD
|
|
ATTRIBUTES : RING0 NOTSX
|
|
PATTERN : 0x0F 0x09 WBNOINVD=1 f3_refining_prefix
|
|
OPERANDS :
|
|
}
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/pconfig/pconfig-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING PCONFIG (PCONFIG-N/A-1)
|
|
{
|
|
ICLASS: PCONFIG
|
|
CPL: 0
|
|
CATEGORY: PCONFIG
|
|
EXTENSION: PCONFIG
|
|
ISA_SET: PCONFIG
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ]
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64
|
|
OPERANDS: REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_EBX:crw:SUPP:d:u32 REG2=XED_REG_ECX:crw:SUPP:d:u32 REG3=XED_REG_EDX:crw:SUPP:d:u32
|
|
IFORM: PCONFIG
|
|
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix mode64
|
|
OPERANDS: REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64
|
|
IFORM: PCONFIG64
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/bitalg/bitalg-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPOPCNTB (VPOPCNTB-128-1)
|
|
{
|
|
ICLASS: VPOPCNTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
|
|
IFORM: VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
|
|
IFORM: VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTB (VPOPCNTB-256-1)
|
|
{
|
|
ICLASS: VPOPCNTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
|
|
IFORM: VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
|
|
IFORM: VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTB (VPOPCNTB-512-1)
|
|
{
|
|
ICLASS: VPOPCNTB
|
|
CPL: 3
|
|
CATEGORY: AVX512_BITALG
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
|
|
IFORM: VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTB
|
|
CPL: 3
|
|
CATEGORY: AVX512_BITALG
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
|
|
IFORM: VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTW (VPOPCNTW-128-1)
|
|
{
|
|
ICLASS: VPOPCNTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
|
|
IFORM: VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
|
|
IFORM: VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTW (VPOPCNTW-256-1)
|
|
{
|
|
ICLASS: VPOPCNTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
|
|
IFORM: VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTW
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
|
|
IFORM: VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTW (VPOPCNTW-512-1)
|
|
{
|
|
ICLASS: VPOPCNTW
|
|
CPL: 3
|
|
CATEGORY: AVX512_BITALG
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
|
|
IFORM: VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTW
|
|
CPL: 3
|
|
CATEGORY: AVX512_BITALG
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
|
|
IFORM: VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-128-1)
|
|
{
|
|
ICLASS: VPSHUFBITQMB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFBITQMB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8
|
|
IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-256-1)
|
|
{
|
|
ICLASS: VPSHUFBITQMB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFBITQMB
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8
|
|
IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-512-1)
|
|
{
|
|
ICLASS: VPSHUFBITQMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_BITALG
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8
|
|
IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHUFBITQMB
|
|
CPL: 3
|
|
CATEGORY: AVX512_BITALG
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_BITALG_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8
|
|
IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/vbmi2/vbmi2-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-1)
|
|
{
|
|
ICLASS: VPCOMPRESSB
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8
|
|
IFORM: VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-2)
|
|
{
|
|
ICLASS: VPCOMPRESSB
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8
|
|
IFORM: VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-1)
|
|
{
|
|
ICLASS: VPCOMPRESSB
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8
|
|
IFORM: VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-2)
|
|
{
|
|
ICLASS: VPCOMPRESSB
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8
|
|
IFORM: VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-1)
|
|
{
|
|
ICLASS: VPCOMPRESSB
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8
|
|
IFORM: VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-2)
|
|
{
|
|
ICLASS: VPCOMPRESSB
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8
|
|
IFORM: VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-1)
|
|
{
|
|
ICLASS: VPCOMPRESSW
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16
|
|
IFORM: VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-2)
|
|
{
|
|
ICLASS: VPCOMPRESSW
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16
|
|
IFORM: VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-1)
|
|
{
|
|
ICLASS: VPCOMPRESSW
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16
|
|
IFORM: VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-2)
|
|
{
|
|
ICLASS: VPCOMPRESSW
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16
|
|
IFORM: VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-1)
|
|
{
|
|
ICLASS: VPCOMPRESSW
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT()
|
|
OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16
|
|
IFORM: VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-2)
|
|
{
|
|
ICLASS: VPCOMPRESSW
|
|
CPL: 3
|
|
CATEGORY: COMPRESS
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16
|
|
IFORM: VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDB (VPEXPANDB-128-1)
|
|
{
|
|
ICLASS: VPEXPANDB
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8
|
|
IFORM: VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDB (VPEXPANDB-128-2)
|
|
{
|
|
ICLASS: VPEXPANDB
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8
|
|
IFORM: VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDB (VPEXPANDB-256-1)
|
|
{
|
|
ICLASS: VPEXPANDB
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8
|
|
IFORM: VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDB (VPEXPANDB-256-2)
|
|
{
|
|
ICLASS: VPEXPANDB
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8
|
|
IFORM: VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDB (VPEXPANDB-512-1)
|
|
{
|
|
ICLASS: VPEXPANDB
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8
|
|
IFORM: VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDB (VPEXPANDB-512-2)
|
|
{
|
|
ICLASS: VPEXPANDB
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8
|
|
IFORM: VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDW (VPEXPANDW-128-1)
|
|
{
|
|
ICLASS: VPEXPANDW
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16
|
|
IFORM: VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDW (VPEXPANDW-128-2)
|
|
{
|
|
ICLASS: VPEXPANDW
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
|
|
IFORM: VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDW (VPEXPANDW-256-1)
|
|
{
|
|
ICLASS: VPEXPANDW
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16
|
|
IFORM: VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDW (VPEXPANDW-256-2)
|
|
{
|
|
ICLASS: VPEXPANDW
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
|
|
IFORM: VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDW (VPEXPANDW-512-1)
|
|
{
|
|
ICLASS: VPEXPANDW
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16
|
|
IFORM: VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPEXPANDW (VPEXPANDW-512-2)
|
|
{
|
|
ICLASS: VPEXPANDW
|
|
CPL: 3
|
|
CATEGORY: EXPAND
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
|
|
IFORM: VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDD (VPSHLDD-128-1)
|
|
{
|
|
ICLASS: VPSHLDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDD (VPSHLDD-256-1)
|
|
{
|
|
ICLASS: VPSHLDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDD (VPSHLDD-512-1)
|
|
{
|
|
ICLASS: VPSHLDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDQ (VPSHLDQ-128-1)
|
|
{
|
|
ICLASS: VPSHLDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDQ (VPSHLDQ-256-1)
|
|
{
|
|
ICLASS: VPSHLDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDQ (VPSHLDQ-512-1)
|
|
{
|
|
ICLASS: VPSHLDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVD (VPSHLDVD-128-1)
|
|
{
|
|
ICLASS: VPSHLDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVD (VPSHLDVD-256-1)
|
|
{
|
|
ICLASS: VPSHLDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVD (VPSHLDVD-512-1)
|
|
{
|
|
ICLASS: VPSHLDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVQ (VPSHLDVQ-128-1)
|
|
{
|
|
ICLASS: VPSHLDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVQ (VPSHLDVQ-256-1)
|
|
{
|
|
ICLASS: VPSHLDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVQ (VPSHLDVQ-512-1)
|
|
{
|
|
ICLASS: VPSHLDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVW (VPSHLDVW-128-1)
|
|
{
|
|
ICLASS: VPSHLDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVW (VPSHLDVW-256-1)
|
|
{
|
|
ICLASS: VPSHLDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDVW (VPSHLDVW-512-1)
|
|
{
|
|
ICLASS: VPSHLDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDW (VPSHLDW-128-1)
|
|
{
|
|
ICLASS: VPSHLDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDW (VPSHLDW-256-1)
|
|
{
|
|
ICLASS: VPSHLDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHLDW (VPSHLDW-512-1)
|
|
{
|
|
ICLASS: VPSHLDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHLDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDD (VPSHRDD-128-1)
|
|
{
|
|
ICLASS: VPSHRDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b
|
|
IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDD (VPSHRDD-256-1)
|
|
{
|
|
ICLASS: VPSHRDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b
|
|
IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDD (VPSHRDD-512-1)
|
|
{
|
|
ICLASS: VPSHRDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b
|
|
IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDQ (VPSHRDQ-128-1)
|
|
{
|
|
ICLASS: VPSHRDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDQ (VPSHRDQ-256-1)
|
|
{
|
|
ICLASS: VPSHRDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDQ (VPSHRDQ-512-1)
|
|
{
|
|
ICLASS: VPSHRDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVD (VPSHRDVD-128-1)
|
|
{
|
|
ICLASS: VPSHRDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
|
|
IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVD (VPSHRDVD-256-1)
|
|
{
|
|
ICLASS: VPSHRDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
|
|
IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVD (VPSHRDVD-512-1)
|
|
{
|
|
ICLASS: VPSHRDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32
|
|
IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVD
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVQ (VPSHRDVQ-128-1)
|
|
{
|
|
ICLASS: VPSHRDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
|
|
IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVQ (VPSHRDVQ-256-1)
|
|
{
|
|
ICLASS: VPSHRDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
|
|
IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVQ (VPSHRDVQ-512-1)
|
|
{
|
|
ICLASS: VPSHRDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
|
|
IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVQ
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVW (VPSHRDVW-128-1)
|
|
{
|
|
ICLASS: VPSHRDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
|
|
IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
|
|
IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVW (VPSHRDVW-256-1)
|
|
{
|
|
ICLASS: VPSHRDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
|
|
IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
|
|
IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDVW (VPSHRDVW-512-1)
|
|
{
|
|
ICLASS: VPSHRDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
|
|
IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDVW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
|
|
IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDW (VPSHRDW-128-1)
|
|
{
|
|
ICLASS: VPSHRDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b
|
|
IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDW (VPSHRDW-256-1)
|
|
{
|
|
ICLASS: VPSHRDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b
|
|
IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPSHRDW (VPSHRDW-512-1)
|
|
{
|
|
ICLASS: VPSHRDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b
|
|
IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPSHRDW
|
|
CPL: 3
|
|
CATEGORY: VBMI2
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VBMI2_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b
|
|
IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-sse-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING GF2P8AFFINEINVQB (GF2P8AFFINEINVQB-N/A-1)
|
|
{
|
|
ICLASS: GF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: GFNI
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x3A 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b
|
|
IFORM: GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8
|
|
}
|
|
|
|
{
|
|
ICLASS: GF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: GFNI
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8
|
|
}
|
|
|
|
|
|
# EMITTING GF2P8AFFINEQB (GF2P8AFFINEQB-N/A-1)
|
|
{
|
|
ICLASS: GF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: GFNI
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x3A 0xCE MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b
|
|
IFORM: GF2P8AFFINEQB_XMMu8_XMMu64_IMM8
|
|
}
|
|
|
|
{
|
|
ICLASS: GF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: GFNI
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: GF2P8AFFINEQB_XMMu8_MEMu64_IMM8
|
|
}
|
|
|
|
|
|
# EMITTING GF2P8MULB (GF2P8MULB-N/A-1)
|
|
{
|
|
ICLASS: GF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: GFNI
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x38 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8
|
|
IFORM: GF2P8MULB_XMMu8_XMMu8
|
|
}
|
|
|
|
{
|
|
ICLASS: GF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: GFNI
|
|
EXCEPTIONS: SSE_TYPE_4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: REQUIRES_ALIGNMENT
|
|
PATTERN: 0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8
|
|
IFORM: GF2P8MULB_XMMu8_MEMu8
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-evex-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-1)
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-1)
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-512-1)
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-1)
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-1)
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-512-1)
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8MULB (VGF2P8MULB-128-1)
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8
|
|
IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8MULB (VGF2P8MULB-256-1)
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8
|
|
IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8MULB (VGF2P8MULB-512-1)
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8
|
|
IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_GFNI_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM
|
|
PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8
|
|
IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-vex-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
AVX_INSTRUCTIONS()::
|
|
# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-2)
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-2)
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEINVQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-2)
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8()
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-2)
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8AFFINEQB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b
|
|
IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8MULB (VGF2P8MULB-128-2)
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8
|
|
IFORM: VGF2P8MULB_XMMu8_XMMu8_XMMu8
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0
|
|
OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8
|
|
IFORM: VGF2P8MULB_XMMu8_XMMu8_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING VGF2P8MULB (VGF2P8MULB-256-2)
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8
|
|
IFORM: VGF2P8MULB_YMMu8_YMMu8_YMMu8
|
|
}
|
|
|
|
{
|
|
ICLASS: VGF2P8MULB
|
|
CPL: 3
|
|
CATEGORY: GFNI
|
|
EXTENSION: GFNI
|
|
ISA_SET: AVX_GFNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0
|
|
OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8
|
|
IFORM: VGF2P8MULB_YMMu8_YMMu8_MEMu8
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/vaes-evex-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VAESDEC (VAESDEC-128-1)
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
|
|
IFORM: VAESDEC_XMMu128_XMMu128_XMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
|
|
IFORM: VAESDEC_XMMu128_XMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESDEC (VAESDEC-256-1)
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
|
|
IFORM: VAESDEC_YMMu128_YMMu128_YMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESDEC_YMMu128_YMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESDEC (VAESDEC-512-1)
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
|
|
IFORM: VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
|
|
IFORM: VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESDECLAST (VAESDECLAST-128-1)
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
|
|
IFORM: VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
|
|
IFORM: VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESDECLAST (VAESDECLAST-256-1)
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
|
|
IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESDECLAST (VAESDECLAST-512-1)
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
|
|
IFORM: VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
|
|
IFORM: VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESENC (VAESENC-128-1)
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
|
|
IFORM: VAESENC_XMMu128_XMMu128_XMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
|
|
IFORM: VAESENC_XMMu128_XMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESENC (VAESENC-256-1)
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
|
|
IFORM: VAESENC_YMMu128_YMMu128_YMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESENC_YMMu128_YMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESENC (VAESENC-512-1)
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
|
|
IFORM: VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
|
|
IFORM: VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESENCLAST (VAESENCLAST-128-1)
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
|
|
IFORM: VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
|
|
IFORM: VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESENCLAST (VAESENCLAST-256-1)
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
|
|
IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VAESENCLAST (VAESENCLAST-512-1)
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128
|
|
IFORM: VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VAES_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
|
|
IFORM: VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCLMULQDQ (VPCLMULQDQ-128-1)
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPCLMULQDQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPCLMULQDQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-1)
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPCLMULQDQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPCLMULQDQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPCLMULQDQ (VPCLMULQDQ-512-1)
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPCLMULQDQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPCLMULQDQ_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULLMEM
|
|
PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()
|
|
OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/vaes-vex-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
AVX_INSTRUCTIONS()::
|
|
# EMITTING VAESDEC (VAESDEC-256-2)
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
|
|
IFORM: VAESDEC_YMMu128_YMMu128_YMMu128
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDEC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESDEC_YMMu128_YMMu128_MEMu128
|
|
}
|
|
|
|
|
|
# EMITTING VAESDECLAST (VAESDECLAST-256-2)
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
|
|
IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESDECLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128
|
|
}
|
|
|
|
|
|
# EMITTING VAESENC (VAESENC-256-2)
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
|
|
IFORM: VAESENC_YMMu128_YMMu128_YMMu128
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENC
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESENC_YMMu128_YMMu128_MEMu128
|
|
}
|
|
|
|
|
|
# EMITTING VAESENCLAST (VAESENCLAST-256-2)
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
|
|
IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128
|
|
}
|
|
|
|
{
|
|
ICLASS: VAESENCLAST
|
|
CPL: 3
|
|
CATEGORY: VAES
|
|
EXTENSION: VAES
|
|
ISA_SET: VAES
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
|
|
IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128
|
|
}
|
|
|
|
|
|
# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-2)
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: VPCLMULQDQ
|
|
ISA_SET: VPCLMULQDQ
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8
|
|
}
|
|
|
|
{
|
|
ICLASS: VPCLMULQDQ
|
|
CPL: 3
|
|
CATEGORY: VPCLMULQDQ
|
|
EXTENSION: VPCLMULQDQ
|
|
ISA_SET: VPCLMULQDQ
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 UIMM8()
|
|
OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b
|
|
IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-vl/vpopcntdq-vl-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VPOPCNTD (VPOPCNTD-128-1)
|
|
{
|
|
ICLASS: VPOPCNTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTD (VPOPCNTD-256-1)
|
|
{
|
|
ICLASS: VPOPCNTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTD
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTQ (VPOPCNTQ-128-1)
|
|
{
|
|
ICLASS: VPOPCNTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VPOPCNTQ (VPOPCNTQ-256-1)
|
|
{
|
|
ICLASS: VPOPCNTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VPOPCNTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VPOPCNTDQ_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
|
|
PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/vp2intersect/vp2intersect-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VP2INTERSECTD (VP2INTERSECTD-128-1)
|
|
{
|
|
ICLASS: VP2INTERSECTD
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MULTIDEST2
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32
|
|
IFORM: VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VP2INTERSECTD
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VP2INTERSECTD (VP2INTERSECTD-256-1)
|
|
{
|
|
ICLASS: VP2INTERSECTD
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MULTIDEST2
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32
|
|
IFORM: VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VP2INTERSECTD
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VP2INTERSECTD (VP2INTERSECTD-512-1)
|
|
{
|
|
ICLASS: VP2INTERSECTD
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MULTIDEST2
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32
|
|
IFORM: VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VP2INTERSECTD
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-128-1)
|
|
{
|
|
ICLASS: VP2INTERSECTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MULTIDEST2
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64
|
|
IFORM: VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VP2INTERSECTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-256-1)
|
|
{
|
|
ICLASS: VP2INTERSECTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MULTIDEST2
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64
|
|
IFORM: VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VP2INTERSECTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-512-1)
|
|
{
|
|
ICLASS: VP2INTERSECTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MULTIDEST2
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64
|
|
IFORM: VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VP2INTERSECTQ
|
|
CPL: 3
|
|
CATEGORY: AVX512_VP2INTERSECT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_VP2INTERSECT_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED
|
|
PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/keylocker/keylocker-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING AESDEC128KL (AESDEC128KL-N/A-1)
|
|
{
|
|
ICLASS: AESDEC128KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER
|
|
EXTENSION: KEYLOCKER
|
|
ISA_SET: KEYLOCKER
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xDD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:m384:u8
|
|
IFORM: AESDEC128KL_XMMu8_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING AESDEC256KL (AESDEC256KL-N/A-1)
|
|
{
|
|
ICLASS: AESDEC256KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER
|
|
EXTENSION: KEYLOCKER
|
|
ISA_SET: KEYLOCKER
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xDF f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:zd:u8
|
|
IFORM: AESDEC256KL_XMMu8_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING AESDECWIDE128KL (AESDECWIDE128KL-N/A-1)
|
|
{
|
|
ICLASS: AESDECWIDE128KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER_WIDE
|
|
EXTENSION: KEYLOCKER_WIDE
|
|
ISA_SET: KEYLOCKER_WIDE
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: MEM0:r:m384:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8
|
|
IFORM: AESDECWIDE128KL_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING AESDECWIDE256KL (AESDECWIDE256KL-N/A-1)
|
|
{
|
|
ICLASS: AESDECWIDE256KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER_WIDE
|
|
EXTENSION: KEYLOCKER_WIDE
|
|
ISA_SET: KEYLOCKER_WIDE
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: MEM0:r:zd:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8
|
|
IFORM: AESDECWIDE256KL_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING AESENC128KL (AESENC128KL-N/A-1)
|
|
{
|
|
ICLASS: AESENC128KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER
|
|
EXTENSION: KEYLOCKER
|
|
ISA_SET: KEYLOCKER
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xDC f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:m384:u8
|
|
IFORM: AESENC128KL_XMMu8_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING AESENC256KL (AESENC256KL-N/A-1)
|
|
{
|
|
ICLASS: AESENC256KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER
|
|
EXTENSION: KEYLOCKER
|
|
ISA_SET: KEYLOCKER
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xDE f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()
|
|
OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:zd:u8
|
|
IFORM: AESENC256KL_XMMu8_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING AESENCWIDE128KL (AESENCWIDE128KL-N/A-1)
|
|
{
|
|
ICLASS: AESENCWIDE128KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER_WIDE
|
|
EXTENSION: KEYLOCKER_WIDE
|
|
ISA_SET: KEYLOCKER_WIDE
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: MEM0:r:m384:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8
|
|
IFORM: AESENCWIDE128KL_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING AESENCWIDE256KL (AESENCWIDE256KL-N/A-1)
|
|
{
|
|
ICLASS: AESENCWIDE256KL
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER_WIDE
|
|
EXTENSION: KEYLOCKER_WIDE
|
|
ISA_SET: KEYLOCKER_WIDE
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: MEM0:r:zd:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8
|
|
IFORM: AESENCWIDE256KL_MEMu8
|
|
}
|
|
|
|
|
|
# EMITTING ENCODEKEY128 (ENCODEKEY128-N/A-1)
|
|
{
|
|
ICLASS: ENCODEKEY128
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER
|
|
EXTENSION: KEYLOCKER
|
|
ISA_SET: KEYLOCKER
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-0 of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xFA MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix
|
|
OPERANDS: REG0=GPR32_R():w:d:u8 REG1=GPR32_B():r:d:u8 REG2=XED_REG_XMM0:rw:SUPP:dq:u8 REG3=XED_REG_XMM1:w:SUPP:dq:u8 REG4=XED_REG_XMM2:w:SUPP:dq:u8 REG5=XED_REG_XMM4:w:SUPP:dq:u8 REG6=XED_REG_XMM5:w:SUPP:dq:u8 REG7=XED_REG_XMM6:w:SUPP:dq:u8
|
|
IFORM: ENCODEKEY128_GPR32u8_GPR32u8
|
|
}
|
|
|
|
|
|
# EMITTING ENCODEKEY256 (ENCODEKEY256-N/A-1)
|
|
{
|
|
ICLASS: ENCODEKEY256
|
|
CPL: 3
|
|
CATEGORY: KEYLOCKER
|
|
EXTENSION: KEYLOCKER
|
|
ISA_SET: KEYLOCKER
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-0 of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xFB MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix
|
|
OPERANDS: REG0=GPR32_R():w:d:u8 REG1=GPR32_B():r:d:u8 REG2=XED_REG_XMM0:rw:SUPP:dq:u8 REG3=XED_REG_XMM1:rw:SUPP:dq:u8 REG4=XED_REG_XMM2:w:SUPP:dq:u8 REG5=XED_REG_XMM3:w:SUPP:dq:u8 REG6=XED_REG_XMM4:w:SUPP:dq:u8 REG7=XED_REG_XMM5:w:SUPP:dq:u8 REG8=XED_REG_XMM6:w:SUPP:dq:u8
|
|
IFORM: ENCODEKEY256_GPR32u8_GPR32u8
|
|
}
|
|
|
|
|
|
# EMITTING LOADIWKEY (LOADIWKEY-N/A-1)
|
|
{
|
|
ICLASS: LOADIWKEY
|
|
CPL: 0
|
|
CATEGORY: KEYLOCKER
|
|
EXTENSION: KEYLOCKER
|
|
ISA_SET: KEYLOCKER
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ]
|
|
PATTERN: 0x0F 0x38 0xDC f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]
|
|
OPERANDS: REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XED_REG_EAX:r:SUPP:d:u32 REG3=XED_REG_XMM0:r:SUPP:dq:u8
|
|
IFORM: LOADIWKEY_XMMu8_XMMu8
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/hreset/hreset-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING HRESET (HRESET-N/A-1)
|
|
{
|
|
ICLASS: HRESET
|
|
CPL: 0
|
|
CATEGORY: HRESET
|
|
EXTENSION: HRESET
|
|
ISA_SET: HRESET
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x3A 0xF0 MOD[0b11] MOD=3 REG[0b000] RM[0b000] f3_refining_prefix UIMM8()
|
|
OPERANDS: IMM0:r:b REG0=XED_REG_EAX:r:SUPP:d:u32
|
|
IFORM: HRESET_IMM8
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx-vnni/avx-vnni-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
AVX_INSTRUCTIONS()::
|
|
# EMITTING VPDPBUSD (VPDPBUSD-128-2)
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
IFORM: VPDPBUSD_XMMi32_XMMu32_XMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPDPBUSD_XMMi32_XMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSD (VPDPBUSD-256-2)
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
IFORM: VPDPBUSD_YMMi32_YMMu32_YMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
IFORM: VPDPBUSD_YMMi32_YMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSDS (VPDPBUSDS-128-2)
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
IFORM: VPDPBUSDS_XMMi32_XMMu32_XMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPDPBUSDS_XMMi32_XMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING VPDPBUSDS (VPDPBUSDS-256-2)
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
IFORM: VPDPBUSDS_YMMi32_YMMu32_YMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPBUSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
IFORM: VPDPBUSDS_YMMi32_YMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSD (VPDPWSSD-128-2)
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
IFORM: VPDPWSSD_XMMi32_XMMu32_XMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPDPWSSD_XMMi32_XMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSD (VPDPWSSD-256-2)
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
IFORM: VPDPWSSD_YMMi32_YMMu32_YMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSD
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
IFORM: VPDPWSSD_YMMi32_YMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSDS (VPDPWSSDS-128-2)
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
|
|
IFORM: VPDPWSSDS_XMMi32_XMMu32_XMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0
|
|
OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
|
|
IFORM: VPDPWSSDS_XMMi32_XMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING VPDPWSSDS (VPDPWSSDS-256-2)
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
|
|
IFORM: VPDPWSSDS_YMMi32_YMMu32_YMMu32
|
|
}
|
|
|
|
{
|
|
ICLASS: VPDPWSSDS
|
|
CPL: 3
|
|
CATEGORY: VEX
|
|
EXTENSION: AVX_VNNI
|
|
ISA_SET: AVX_VNNI
|
|
EXCEPTIONS: avx-type-4
|
|
REAL_OPCODE: Y
|
|
PATTERN: VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0
|
|
OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
|
|
IFORM: VPDPWSSDS_YMMi32_YMMu32_MEMu32
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/uintr/uintr-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING CLUI (CLUI-N/A-1)
|
|
{
|
|
ICLASS: CLUI
|
|
CPL: 3
|
|
CATEGORY: UINTR
|
|
EXTENSION: UINTR
|
|
ISA_SET: UINTR
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64
|
|
OPERANDS: REG0=XED_REG_UIF:w:SUPP:i1
|
|
IFORM: CLUI
|
|
}
|
|
|
|
|
|
# EMITTING SENDUIPI (SENDUIPI-N/A-1)
|
|
{
|
|
ICLASS: SENDUIPI
|
|
CPL: 3
|
|
CATEGORY: UINTR
|
|
EXTENSION: UINTR
|
|
ISA_SET: UINTR
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64
|
|
OPERANDS: REG0=GPR32_B():r:d:u32
|
|
IFORM: SENDUIPI_GPR32u32
|
|
}
|
|
|
|
|
|
# EMITTING STUI (STUI-N/A-1)
|
|
{
|
|
ICLASS: STUI
|
|
CPL: 3
|
|
CATEGORY: UINTR
|
|
EXTENSION: UINTR
|
|
ISA_SET: UINTR
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64
|
|
OPERANDS: REG0=XED_REG_UIF:w:SUPP:i1
|
|
IFORM: STUI
|
|
}
|
|
|
|
|
|
# EMITTING TESTUI (TESTUI-N/A-1)
|
|
{
|
|
ICLASS: TESTUI
|
|
CPL: 3
|
|
CATEGORY: UINTR
|
|
EXTENSION: UINTR
|
|
ISA_SET: UINTR
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ cf-mod ]
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64
|
|
OPERANDS: REG0=XED_REG_UIF:r:SUPP:i1
|
|
IFORM: TESTUI
|
|
}
|
|
|
|
|
|
# EMITTING UIRET (UIRET-N/A-1)
|
|
{
|
|
ICLASS: UIRET
|
|
CPL: 3
|
|
CATEGORY: UINTR
|
|
EXTENSION: UINTR
|
|
ISA_SET: UINTR
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ]
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64
|
|
OPERANDS: REG0=rIP():w:SUPP REG1=XED_REG_STACKPOP:r:SUPP:spw
|
|
IFORM: UIRET
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-spr-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
AVX_INSTRUCTIONS()::
|
|
# EMITTING LDTILECFG (LDTILECFG-128-1)
|
|
{
|
|
ICLASS: LDTILECFG
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_TILE
|
|
ISA_SET: AMX_TILE
|
|
EXCEPTIONS: AMX-E1
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR
|
|
OPERANDS: MEM0:r:zd
|
|
IFORM: LDTILECFG_MEM
|
|
}
|
|
|
|
|
|
# EMITTING STTILECFG (STTILECFG-128-1)
|
|
{
|
|
ICLASS: STTILECFG
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_TILE
|
|
ISA_SET: AMX_TILE
|
|
EXCEPTIONS: AMX-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR
|
|
OPERANDS: MEM0:w:zd
|
|
IFORM: STTILECFG_MEM
|
|
}
|
|
|
|
|
|
# EMITTING TDPBF16PS (TDPBF16PS-128-1)
|
|
{
|
|
ICLASS: TDPBF16PS
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_BF16
|
|
ISA_SET: AMX_BF16
|
|
EXCEPTIONS: AMX-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x5C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64
|
|
OPERANDS: REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32
|
|
IFORM: TDPBF16PS_TMMf32_TMMu32_TMMu32
|
|
}
|
|
|
|
|
|
# EMITTING TDPBSSD (TDPBSSD-128-1)
|
|
{
|
|
ICLASS: TDPBSSD
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_INT8
|
|
ISA_SET: AMX_INT8
|
|
EXCEPTIONS: AMX-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x5E VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64
|
|
OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32
|
|
IFORM: TDPBSSD_TMMi32_TMMu32_TMMu32
|
|
}
|
|
|
|
|
|
# EMITTING TDPBSUD (TDPBSUD-128-1)
|
|
{
|
|
ICLASS: TDPBSUD
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_INT8
|
|
ISA_SET: AMX_INT8
|
|
EXCEPTIONS: AMX-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x5E VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64
|
|
OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32
|
|
IFORM: TDPBSUD_TMMi32_TMMu32_TMMu32
|
|
}
|
|
|
|
|
|
# EMITTING TDPBUSD (TDPBUSD-128-1)
|
|
{
|
|
ICLASS: TDPBUSD
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_INT8
|
|
ISA_SET: AMX_INT8
|
|
EXCEPTIONS: AMX-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x5E V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64
|
|
OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32
|
|
IFORM: TDPBUSD_TMMi32_TMMu32_TMMu32
|
|
}
|
|
|
|
|
|
# EMITTING TDPBUUD (TDPBUUD-128-1)
|
|
{
|
|
ICLASS: TDPBUUD
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_INT8
|
|
ISA_SET: AMX_INT8
|
|
EXCEPTIONS: AMX-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x5E VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64
|
|
OPERANDS: REG0=TMM_R():rw:tv:u32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32
|
|
IFORM: TDPBUUD_TMMu32_TMMu32_TMMu32
|
|
}
|
|
|
|
|
|
# EMITTING TILELOADD (TILELOADD-128-1)
|
|
{
|
|
ICLASS: TILELOADD
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_TILE
|
|
ISA_SET: AMX_TILE
|
|
EXCEPTIONS: AMX-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR
|
|
OPERANDS: REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
|
|
IFORM: TILELOADD_TMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING TILELOADDT1 (TILELOADDT1-128-1)
|
|
{
|
|
ICLASS: TILELOADDT1
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_TILE
|
|
ISA_SET: AMX_TILE
|
|
EXCEPTIONS: AMX-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR
|
|
OPERANDS: REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
|
|
IFORM: TILELOADDT1_TMMu32_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING TILERELEASE (TILERELEASE-128-1)
|
|
{
|
|
ICLASS: TILERELEASE
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_TILE
|
|
ISA_SET: AMX_TILE
|
|
EXCEPTIONS: AMX-E6
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x49 VNP V0F38 MOD[0b11] MOD=3 REG[0b000] RM[0b000] VL128 W0 mode64 NOVSR
|
|
OPERANDS:
|
|
IFORM: TILERELEASE
|
|
}
|
|
|
|
|
|
# EMITTING TILESTORED (TILESTORED-128-1)
|
|
{
|
|
ICLASS: TILESTORED
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_TILE
|
|
ISA_SET: AMX_TILE
|
|
EXCEPTIONS: AMX-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED
|
|
PATTERN: VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR
|
|
OPERANDS: MEM0:w:ptr:u32 REG0=TMM_R():r:tv:u32
|
|
IFORM: TILESTORED_MEMu32_TMMu32
|
|
}
|
|
|
|
|
|
# EMITTING TILEZERO (TILEZERO-128-1)
|
|
{
|
|
ICLASS: TILEZERO
|
|
CPL: 3
|
|
CATEGORY: AMX_TILE
|
|
EXTENSION: AMX_TILE
|
|
ISA_SET: AMX_TILE
|
|
EXCEPTIONS: AMX-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR
|
|
OPERANDS: REG0=TMM_R():w:tv:u32
|
|
IFORM: TILEZERO_TMMu32
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/enqcmd/enqcmd-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2019 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING ENQCMD (ENQCMD-N/A-1)
|
|
{
|
|
ICLASS: ENQCMD
|
|
CPL: 3
|
|
CATEGORY: ENQCMD
|
|
EXTENSION: ENQCMD
|
|
ISA_SET: ENQCMD
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ]
|
|
PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix
|
|
OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32
|
|
IFORM: ENQCMD_GPRa_MEMu32
|
|
}
|
|
|
|
|
|
# EMITTING ENQCMDS (ENQCMDS-N/A-1)
|
|
{
|
|
ICLASS: ENQCMDS
|
|
CPL: 3
|
|
CATEGORY: ENQCMD
|
|
EXTENSION: ENQCMD
|
|
ISA_SET: ENQCMD
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ]
|
|
PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix
|
|
OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32
|
|
IFORM: ENQCMDS_GPRa_MEMu32
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/tsx-ldtrk/tsx-ldtrk-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
|
|
INSTRUCTIONS()::
|
|
# EMITTING XRESLDTRK (XRESLDTRK-N/A-1)
|
|
{
|
|
ICLASS: XRESLDTRK
|
|
CPL: 3
|
|
CATEGORY: TSX_LDTRK
|
|
EXTENSION: TSX_LDTRK
|
|
ISA_SET: TSX_LDTRK
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix
|
|
OPERANDS:
|
|
IFORM: XRESLDTRK
|
|
}
|
|
|
|
|
|
# EMITTING XSUSLDTRK (XSUSLDTRK-N/A-1)
|
|
{
|
|
ICLASS: XSUSLDTRK
|
|
CPL: 3
|
|
CATEGORY: TSX_LDTRK
|
|
EXTENSION: TSX_LDTRK
|
|
ISA_SET: TSX_LDTRK
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix
|
|
OPERANDS:
|
|
IFORM: XSUSLDTRK
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/serialize/serialize-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING SERIALIZE (SERIALIZE-N/A-1)
|
|
{
|
|
ICLASS: SERIALIZE
|
|
CPL: 3
|
|
CATEGORY: SERIALIZE
|
|
EXTENSION: SERIALIZE
|
|
ISA_SET: SERIALIZE
|
|
REAL_OPCODE: Y
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix
|
|
OPERANDS:
|
|
IFORM: SERIALIZE
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/tdx/tdx-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2020 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
INSTRUCTIONS()::
|
|
# EMITTING SEAMCALL (SEAMCALL-N/A-1)
|
|
{
|
|
ICLASS: SEAMCALL
|
|
CPL: 0
|
|
CATEGORY: LEGACY
|
|
EXTENSION: TDX
|
|
ISA_SET: TDX
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] osz_refining_prefix mode64
|
|
OPERANDS: REG0=XED_REG_RAX:rw:SUPP:q:u64
|
|
IFORM: SEAMCALL
|
|
}
|
|
|
|
|
|
# EMITTING SEAMOPS (SEAMOPS-N/A-1)
|
|
{
|
|
ICLASS: SEAMOPS
|
|
CPL: 0
|
|
CATEGORY: LEGACY
|
|
EXTENSION: TDX
|
|
ISA_SET: TDX
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b110] osz_refining_prefix mode64
|
|
OPERANDS: REG0=XED_REG_RAX:rw:SUPP:q:u64
|
|
IFORM: SEAMOPS
|
|
}
|
|
|
|
|
|
# EMITTING SEAMRET (SEAMRET-N/A-1)
|
|
{
|
|
ICLASS: SEAMRET
|
|
CPL: 0
|
|
CATEGORY: LEGACY
|
|
EXTENSION: TDX
|
|
ISA_SET: TDX
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b101] osz_refining_prefix mode64
|
|
OPERANDS:
|
|
IFORM: SEAMRET
|
|
}
|
|
|
|
|
|
# EMITTING TDCALL (TDCALL-N/A-1)
|
|
{
|
|
ICLASS: TDCALL
|
|
CPL: 0
|
|
CATEGORY: LEGACY
|
|
EXTENSION: TDX
|
|
ISA_SET: TDX
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix mode64
|
|
OPERANDS: REG0=XED_REG_RCX:r:SUPP:q:u64
|
|
IFORM: TDCALL
|
|
}
|
|
|
|
|
|
# EMITTING TDCALL (TDCALL-N/A-2)
|
|
{
|
|
ICLASS: TDCALL
|
|
CPL: 0
|
|
CATEGORY: LEGACY
|
|
EXTENSION: TDX
|
|
ISA_SET: TDX
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: NOTSX
|
|
PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64
|
|
OPERANDS: REG0=XED_REG_ECX:r:SUPP:d:u32
|
|
IFORM: TDCALL
|
|
}
|
|
|
|
|
|
|
|
|
|
###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-fp16-isa.xed.txt
|
|
|
|
#BEGIN_LEGAL
|
|
#
|
|
#Copyright (c) 2021 Intel Corporation
|
|
#
|
|
# Licensed under the Apache License, Version 2.0 (the "License");
|
|
# you may not use this file except in compliance with the License.
|
|
# You may obtain a copy of the License at
|
|
#
|
|
# http://www.apache.org/licenses/LICENSE-2.0
|
|
#
|
|
# Unless required by applicable law or agreed to in writing, software
|
|
# distributed under the License is distributed on an "AS IS" BASIS,
|
|
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
# See the License for the specific language governing permissions and
|
|
# limitations under the License.
|
|
#
|
|
#END_LEGAL
|
|
#
|
|
#
|
|
#
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
# ***** GENERATED FILE -- DO NOT EDIT! *****
|
|
#
|
|
#
|
|
#
|
|
EVEX_INSTRUCTIONS()::
|
|
# EMITTING VADDPH (VADDPH-128-1)
|
|
{
|
|
ICLASS: VADDPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDPH (VADDPH-256-1)
|
|
{
|
|
ICLASS: VADDPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDPH (VADDPH-512-1)
|
|
{
|
|
ICLASS: VADDPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VADDSH (VADDSH-128-1)
|
|
{
|
|
ICLASS: VADDSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VADDSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPH (VCMPPH-128-1)
|
|
{
|
|
ICLASS: VCMPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPH (VCMPPH-256-1)
|
|
{
|
|
ICLASS: VCMPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b
|
|
IFORM: VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPPH (VCMPPH-512-1)
|
|
{
|
|
ICLASS: VCMPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCMPSH (VCMPSH-128-1)
|
|
{
|
|
ICLASS: VCMPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCMPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
|
|
IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCOMISH (VCOMISH-128-1)
|
|
{
|
|
ICLASS: VCOMISH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCOMISH_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCOMISH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCOMISH_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCOMISH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: DISP8_SCALAR MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VCOMISH_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PH (VCVTDQ2PH-128-1)
|
|
{
|
|
ICLASS: VCVTDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32
|
|
IFORM: VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PH (VCVTDQ2PH-256-1)
|
|
{
|
|
ICLASS: VCVTDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
|
|
IFORM: VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTDQ2PH (VCVTDQ2PH-512-1)
|
|
{
|
|
ICLASS: VCVTDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
|
|
IFORM: VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32
|
|
IFORM: VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR
|
|
IFORM: VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PH (VCVTPD2PH-128-1)
|
|
{
|
|
ICLASS: VCVTPD2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
|
|
IFORM: VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ
|
|
PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PH (VCVTPD2PH-256-1)
|
|
{
|
|
ICLASS: VCVTPD2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
|
|
IFORM: VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ
|
|
PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPD2PH (VCVTPD2PH-512-1)
|
|
{
|
|
ICLASS: VCVTPD2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
|
|
IFORM: VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPD2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ
|
|
PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
|
|
IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2DQ (VCVTPH2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2DQ (VCVTPH2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2DQ (VCVTPH2DQ-512-1)
|
|
{
|
|
ICLASS: VCVTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PD (VCVTPH2PD-128-1)
|
|
{
|
|
ICLASS: VCVTPH2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ
|
|
PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PD (VCVTPH2PD-256-1)
|
|
{
|
|
ICLASS: VCVTPH2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ
|
|
PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PD (VCVTPH2PD-512-1)
|
|
{
|
|
ICLASS: VCVTPH2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ
|
|
PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PSX (VCVTPH2PSX-128-1)
|
|
{
|
|
ICLASS: VCVTPH2PSX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PSX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ
|
|
PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PSX (VCVTPH2PSX-256-1)
|
|
{
|
|
ICLASS: VCVTPH2PSX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PSX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ
|
|
PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2PSX (VCVTPH2PSX-512-1)
|
|
{
|
|
ICLASS: VCVTPH2PSX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PSX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ
|
|
PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2PSX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ
|
|
PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2QQ (VCVTPH2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2QQ (VCVTPH2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2QQ (VCVTPH2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-512-1)
|
|
{
|
|
ICLASS: VCVTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UW (VCVTPH2UW-128-1)
|
|
{
|
|
ICLASS: VCVTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UW (VCVTPH2UW-256-1)
|
|
{
|
|
ICLASS: VCVTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2UW (VCVTPH2UW-512-1)
|
|
{
|
|
ICLASS: VCVTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2W (VCVTPH2W-128-1)
|
|
{
|
|
ICLASS: VCVTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2W (VCVTPH2W-256-1)
|
|
{
|
|
ICLASS: VCVTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPH2W (VCVTPH2W-512-1)
|
|
{
|
|
ICLASS: VCVTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PHX (VCVTPS2PHX-128-1)
|
|
{
|
|
ICLASS: VCVTPS2PHX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32
|
|
IFORM: VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PHX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ
|
|
PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PHX (VCVTPS2PHX-256-1)
|
|
{
|
|
ICLASS: VCVTPS2PHX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32
|
|
IFORM: VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PHX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ
|
|
PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTPS2PHX (VCVTPS2PHX-512-1)
|
|
{
|
|
ICLASS: VCVTPS2PHX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PHX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ
|
|
PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
|
|
IFORM: VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTPS2PHX
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ
|
|
PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
|
|
IFORM: VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PH (VCVTQQ2PH-128-1)
|
|
{
|
|
ICLASS: VCVTQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PH (VCVTQQ2PH-256-1)
|
|
{
|
|
ICLASS: VCVTQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTQQ2PH (VCVTQQ2PH-512-1)
|
|
{
|
|
ICLASS: VCVTQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSD2SH (VCVTSD2SH-128-1)
|
|
{
|
|
ICLASS: VCVTSD2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ
|
|
PATTERN: EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ
|
|
PATTERN: EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64
|
|
IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSD2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ
|
|
PATTERN: EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64
|
|
IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2SD (VCVTSH2SD-128-1)
|
|
{
|
|
ICLASS: VCVTSH2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ
|
|
PATTERN: EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ
|
|
PATTERN: EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SD
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ
|
|
PATTERN: EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-mode64)
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2SI_GPR32i32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-not64)
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2SI_GPR32i32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2SI (VCVTSH2SI-128-2)
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SI_GPR64i64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SI_GPR64i64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2SI_GPR64i64_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2SS (VCVTSH2SS-128-1)
|
|
{
|
|
ICLASS: VCVTSH2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ
|
|
PATTERN: EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ
|
|
PATTERN: EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2SS
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ
|
|
PATTERN: EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-mode64)
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2USI_GPR32u32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-not64)
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2USI_GPR32u32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSH2USI (VCVTSH2USI-128-2)
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2USI_GPR64u64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTSH2USI_GPR64u64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16
|
|
IFORM: VCVTSH2USI_GPR64u64_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-mode64)
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-not64)
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSI2SH (VCVTSI2SH-128-2)
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:i64
|
|
IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTSS2SH (VCVTSS2SH-128-1)
|
|
{
|
|
ICLASS: VCVTSS2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ
|
|
PATTERN: EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ
|
|
PATTERN: EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32
|
|
IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTSS2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ
|
|
PATTERN: EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:d:f32
|
|
IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2DQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2QQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UDQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()
|
|
OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-128-1)
|
|
{
|
|
ICLASS: VCVTTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-256-1)
|
|
{
|
|
ICLASS: VCVTTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-512-1)
|
|
{
|
|
ICLASS: VCVTTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UQQ
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()
|
|
OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UW (VCVTTPH2UW-128-1)
|
|
{
|
|
ICLASS: VCVTTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UW (VCVTTPH2UW-256-1)
|
|
{
|
|
ICLASS: VCVTTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2UW (VCVTTPH2UW-512-1)
|
|
{
|
|
ICLASS: VCVTTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zu16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2UW
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2W (VCVTTPH2W-128-1)
|
|
{
|
|
ICLASS: VCVTTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2W (VCVTTPH2W-256-1)
|
|
{
|
|
ICLASS: VCVTTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTPH2W (VCVTTPH2W-512-1)
|
|
{
|
|
ICLASS: VCVTTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zi16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTPH2W
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-mode64)
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
|
|
IFORM: VCVTTSH2SI_GPR32i32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-not64)
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16
|
|
IFORM: VCVTTSH2SI_GPR32i32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-2)
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2SI_GPR64i64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2SI_GPR64i64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2SI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16
|
|
IFORM: VCVTTSH2SI_GPR64i64_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-mode64)
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
|
|
IFORM: VCVTTSH2USI_GPR32u32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-not64)
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16
|
|
IFORM: VCVTTSH2USI_GPR32u32_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-2)
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2USI_GPR64u64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VCVTTSH2USI_GPR64u64_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTTSH2USI
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE
|
|
OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16
|
|
IFORM: VCVTTSH2USI_GPR64u64_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-128-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32
|
|
IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-256-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
|
|
IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-512-1)
|
|
{
|
|
ICLASS: VCVTUDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32
|
|
IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUDQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR
|
|
IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-128-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64
|
|
IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-256-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64
|
|
IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-512-1)
|
|
{
|
|
ICLASS: VCVTUQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
|
|
IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUQQ2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR
|
|
IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-mode64)
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-not64)
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-2)
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUSI2SH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:u64
|
|
IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUW2PH (VCVTUW2PH-128-1)
|
|
{
|
|
ICLASS: VCVTUW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16
|
|
IFORM: VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
|
|
IFORM: VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUW2PH (VCVTUW2PH-256-1)
|
|
{
|
|
ICLASS: VCVTUW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16
|
|
IFORM: VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
|
|
IFORM: VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTUW2PH (VCVTUW2PH-512-1)
|
|
{
|
|
ICLASS: VCVTUW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
|
|
IFORM: VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16
|
|
IFORM: VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTUW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR
|
|
IFORM: VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTW2PH (VCVTW2PH-128-1)
|
|
{
|
|
ICLASS: VCVTW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
|
|
IFORM: VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR
|
|
IFORM: VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTW2PH (VCVTW2PH-256-1)
|
|
{
|
|
ICLASS: VCVTW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16
|
|
IFORM: VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR
|
|
IFORM: VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VCVTW2PH (VCVTW2PH-512-1)
|
|
{
|
|
ICLASS: VCVTW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16
|
|
IFORM: VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16
|
|
IFORM: VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VCVTW2PH
|
|
CPL: 3
|
|
CATEGORY: CONVERT
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR
|
|
IFORM: VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPH (VDIVPH-128-1)
|
|
{
|
|
ICLASS: VDIVPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPH (VDIVPH-256-1)
|
|
{
|
|
ICLASS: VDIVPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVPH (VDIVPH-512-1)
|
|
{
|
|
ICLASS: VDIVPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VDIVSH (VDIVSH-128-1)
|
|
{
|
|
ICLASS: VDIVSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VDIVSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMADDCPH (VFCMADDCPH-128-1)
|
|
{
|
|
ICLASS: VFCMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMADDCPH (VFCMADDCPH-256-1)
|
|
{
|
|
ICLASS: VFCMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
|
|
IFORM: VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMADDCPH (VFCMADDCPH-512-1)
|
|
{
|
|
ICLASS: VFCMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMADDCSH (VFCMADDCSH-128-1)
|
|
{
|
|
ICLASS: VFCMADDCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMADDCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMADDCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
|
|
IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMULCPH (VFCMULCPH-128-1)
|
|
{
|
|
ICLASS: VFCMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMULCPH (VFCMULCPH-256-1)
|
|
{
|
|
ICLASS: VFCMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
|
|
IFORM: VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMULCPH (VFCMULCPH-512-1)
|
|
{
|
|
ICLASS: VFCMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFCMULCSH (VFCMULCSH-128-1)
|
|
{
|
|
ICLASS: VFCMULCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMULCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFCMULCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0xD7 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
|
|
IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PH (VFMADD132PH-128-1)
|
|
{
|
|
ICLASS: VFMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PH (VFMADD132PH-256-1)
|
|
{
|
|
ICLASS: VFMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132PH (VFMADD132PH-512-1)
|
|
{
|
|
ICLASS: VFMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD132SH (VFMADD132SH-128-1)
|
|
{
|
|
ICLASS: VFMADD132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x99 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PH (VFMADD213PH-128-1)
|
|
{
|
|
ICLASS: VFMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PH (VFMADD213PH-256-1)
|
|
{
|
|
ICLASS: VFMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213PH (VFMADD213PH-512-1)
|
|
{
|
|
ICLASS: VFMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD213SH (VFMADD213SH-128-1)
|
|
{
|
|
ICLASS: VFMADD213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xA9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PH (VFMADD231PH-128-1)
|
|
{
|
|
ICLASS: VFMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PH (VFMADD231PH-256-1)
|
|
{
|
|
ICLASS: VFMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231PH (VFMADD231PH-512-1)
|
|
{
|
|
ICLASS: VFMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADD231SH (VFMADD231SH-128-1)
|
|
{
|
|
ICLASS: VFMADD231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADD231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xB9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDCPH (VFMADDCPH-128-1)
|
|
{
|
|
ICLASS: VFMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDCPH (VFMADDCPH-256-1)
|
|
{
|
|
ICLASS: VFMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
|
|
IFORM: VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDCPH (VFMADDCPH-512-1)
|
|
{
|
|
ICLASS: VFMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDCSH (VFMADDCSH-128-1)
|
|
{
|
|
ICLASS: VFMADDCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
|
|
IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-128-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-256-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-512-1)
|
|
{
|
|
ICLASS: VFMADDSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMADDSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PH (VFMSUB132PH-128-1)
|
|
{
|
|
ICLASS: VFMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PH (VFMSUB132PH-256-1)
|
|
{
|
|
ICLASS: VFMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132PH (VFMSUB132PH-512-1)
|
|
{
|
|
ICLASS: VFMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB132SH (VFMSUB132SH-128-1)
|
|
{
|
|
ICLASS: VFMSUB132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9B V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PH (VFMSUB213PH-128-1)
|
|
{
|
|
ICLASS: VFMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PH (VFMSUB213PH-256-1)
|
|
{
|
|
ICLASS: VFMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213PH (VFMSUB213PH-512-1)
|
|
{
|
|
ICLASS: VFMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB213SH (VFMSUB213SH-128-1)
|
|
{
|
|
ICLASS: VFMSUB213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PH (VFMSUB231PH-128-1)
|
|
{
|
|
ICLASS: VFMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PH (VFMSUB231PH-256-1)
|
|
{
|
|
ICLASS: VFMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231PH (VFMSUB231PH-512-1)
|
|
{
|
|
ICLASS: VFMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUB231SH (VFMSUB231SH-128-1)
|
|
{
|
|
ICLASS: VFMSUB231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUB231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-128-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-256-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-512-1)
|
|
{
|
|
ICLASS: VFMSUBADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMSUBADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMULCPH (VFMULCPH-128-1)
|
|
{
|
|
ICLASS: VFMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMULCPH (VFMULCPH-256-1)
|
|
{
|
|
ICLASS: VFMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16
|
|
IFORM: VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMULCPH (VFMULCPH-512-1)
|
|
{
|
|
ICLASS: VFMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16
|
|
IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMULCPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH
|
|
PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR
|
|
IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFMULCSH (VFMULCSH-128-1)
|
|
{
|
|
ICLASS: VFMULCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMULCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16
|
|
IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFMULCSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR
|
|
PATTERN: EVV 0xD7 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16
|
|
IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PH (VFNMADD132PH-128-1)
|
|
{
|
|
ICLASS: VFNMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PH (VFNMADD132PH-256-1)
|
|
{
|
|
ICLASS: VFNMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132PH (VFNMADD132PH-512-1)
|
|
{
|
|
ICLASS: VFNMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD132SH (VFNMADD132SH-128-1)
|
|
{
|
|
ICLASS: VFNMADD132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PH (VFNMADD213PH-128-1)
|
|
{
|
|
ICLASS: VFNMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PH (VFNMADD213PH-256-1)
|
|
{
|
|
ICLASS: VFNMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213PH (VFNMADD213PH-512-1)
|
|
{
|
|
ICLASS: VFNMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD213SH (VFNMADD213SH-128-1)
|
|
{
|
|
ICLASS: VFNMADD213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PH (VFNMADD231PH-128-1)
|
|
{
|
|
ICLASS: VFNMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PH (VFNMADD231PH-256-1)
|
|
{
|
|
ICLASS: VFNMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231PH (VFNMADD231PH-512-1)
|
|
{
|
|
ICLASS: VFNMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMADD231SH (VFNMADD231SH-128-1)
|
|
{
|
|
ICLASS: VFNMADD231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMADD231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PH (VFNMSUB132PH-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PH (VFNMSUB132PH-256-1)
|
|
{
|
|
ICLASS: VFNMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132PH (VFNMSUB132PH-512-1)
|
|
{
|
|
ICLASS: VFNMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB132SH (VFNMSUB132SH-128-1)
|
|
{
|
|
ICLASS: VFNMSUB132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB132SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x9F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PH (VFNMSUB213PH-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PH (VFNMSUB213PH-256-1)
|
|
{
|
|
ICLASS: VFNMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213PH (VFNMSUB213PH-512-1)
|
|
{
|
|
ICLASS: VFNMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB213SH (VFNMSUB213SH-128-1)
|
|
{
|
|
ICLASS: VFNMSUB213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB213SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xAF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PH (VFNMSUB231PH-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PH (VFNMSUB231PH-256-1)
|
|
{
|
|
ICLASS: VFNMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231PH (VFNMSUB231PH-512-1)
|
|
{
|
|
ICLASS: VFNMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231PH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFNMSUB231SH (VFNMSUB231SH-128-1)
|
|
{
|
|
ICLASS: VFNMSUB231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFNMSUB231SH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0xBF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPH (VFPCLASSPH-128-1)
|
|
{
|
|
ICLASS: VFPCLASSPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPH (VFPCLASSPH-256-1)
|
|
{
|
|
ICLASS: VFPCLASSPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f16 IMM0:r:b
|
|
IFORM: VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSPH (VFPCLASSPH-512-1)
|
|
{
|
|
ICLASS: VFPCLASSPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512
|
|
}
|
|
|
|
|
|
# EMITTING VFPCLASSSH (VFPCLASSSH-128-1)
|
|
{
|
|
ICLASS: VFPCLASSSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x67 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VFPCLASSSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR
|
|
PATTERN: EVV 0x67 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:wrd:f16 IMM0:r:b
|
|
IFORM: VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPH (VGETEXPPH-128-1)
|
|
{
|
|
ICLASS: VGETEXPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPH (VGETEXPPH-256-1)
|
|
{
|
|
ICLASS: VGETEXPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPPH (VGETEXPPH-512-1)
|
|
{
|
|
ICLASS: VGETEXPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETEXPSH (VGETEXPSH-128-1)
|
|
{
|
|
ICLASS: VGETEXPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETEXPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x43 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPH (VGETMANTPH-128-1)
|
|
{
|
|
ICLASS: VGETMANTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPH (VGETMANTPH-256-1)
|
|
{
|
|
ICLASS: VGETMANTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
|
|
IFORM: VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTPH (VGETMANTPH-512-1)
|
|
{
|
|
ICLASS: VGETMANTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VGETMANTSH (VGETMANTSH-128-1)
|
|
{
|
|
ICLASS: VGETMANTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VGETMANTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x27 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
|
|
IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPH (VMAXPH-128-1)
|
|
{
|
|
ICLASS: VMAXPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPH (VMAXPH-256-1)
|
|
{
|
|
ICLASS: VMAXPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXPH (VMAXPH-512-1)
|
|
{
|
|
ICLASS: VMAXPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMAXSH (VMAXSH-128-1)
|
|
{
|
|
ICLASS: VMAXSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMAXSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPH (VMINPH-128-1)
|
|
{
|
|
ICLASS: VMINPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPH (VMINPH-256-1)
|
|
{
|
|
ICLASS: VMINPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINPH (VMINPH-512-1)
|
|
{
|
|
ICLASS: VMINPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMINSH (VMINSH-128-1)
|
|
{
|
|
ICLASS: VMINSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMINSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSH (VMOVSH-128-1)
|
|
{
|
|
ICLASS: VMOVSH
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR
|
|
PATTERN: EVV 0x10 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:f16
|
|
IFORM: VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSH (VMOVSH-128-5)
|
|
{
|
|
ICLASS: VMOVSH
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR
|
|
PATTERN: EVV 0x11 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: MEM0:w:wrd:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f16
|
|
IFORM: VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSH (VMOVSH-128-6)
|
|
{
|
|
ICLASS: VMOVSH
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVSH (VMOVSH-128-7)
|
|
{
|
|
ICLASS: VMOVSH
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E5
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_R3():r:dq:f16
|
|
IFORM: VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVW (VMOVW-128-1)
|
|
{
|
|
ICLASS: VMOVW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x6E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=GPR32_B():r:d:f16
|
|
IFORM: VMOVW_XMMf16_GPR32f16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_READER
|
|
PATTERN: EVV 0x6E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_READER()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VMOVW_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMOVW (VMOVW-128-2)
|
|
{
|
|
ICLASS: VMOVW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
PATTERN: EVV 0x7E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=GPR32_B():w:d:f16 REG1=XMM_R3():r:dq:f16
|
|
IFORM: VMOVW_GPR32f16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMOVW
|
|
CPL: 3
|
|
CATEGORY: DATAXFER
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128N
|
|
EXCEPTIONS: AVX512-E9NF
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_GPR_WRITER_STORE
|
|
PATTERN: EVV 0x7E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_STORE()
|
|
OPERANDS: MEM0:w:wrd:f16 REG0=XMM_R3():r:dq:f16
|
|
IFORM: VMOVW_MEMf16_XMMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPH (VMULPH-128-1)
|
|
{
|
|
ICLASS: VMULPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPH (VMULPH-256-1)
|
|
{
|
|
ICLASS: VMULPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULPH (VMULPH-512-1)
|
|
{
|
|
ICLASS: VMULPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VMULSH (VMULSH-128-1)
|
|
{
|
|
ICLASS: VMULSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VMULSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCPPH (VRCPPH-128-1)
|
|
{
|
|
ICLASS: VRCPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCPPH (VRCPPH-256-1)
|
|
{
|
|
ICLASS: VRCPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCPPH (VRCPPH-512-1)
|
|
{
|
|
ICLASS: VRCPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCPPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRCPSH (VRCPSH-128-1)
|
|
{
|
|
ICLASS: VRCPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x4D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRCPSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR
|
|
PATTERN: EVV 0x4D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPH (VREDUCEPH-128-1)
|
|
{
|
|
ICLASS: VREDUCEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPH (VREDUCEPH-256-1)
|
|
{
|
|
ICLASS: VREDUCEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
|
|
IFORM: VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCEPH (VREDUCEPH-512-1)
|
|
{
|
|
ICLASS: VREDUCEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VREDUCESH (VREDUCESH-128-1)
|
|
{
|
|
ICLASS: VREDUCESH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VREDUCESH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x57 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
|
|
IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPH (VRNDSCALEPH-128-1)
|
|
{
|
|
ICLASS: VRNDSCALEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPH (VRNDSCALEPH-256-1)
|
|
{
|
|
ICLASS: VRNDSCALEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b
|
|
IFORM: VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALEPH (VRNDSCALEPH-512-1)
|
|
{
|
|
ICLASS: VRNDSCALEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b
|
|
IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALEPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b
|
|
IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRNDSCALESH (VRNDSCALESH-128-1)
|
|
{
|
|
ICLASS: VRNDSCALESH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALESH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b
|
|
IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRNDSCALESH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x0A VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b
|
|
IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRTPH (VRSQRTPH-128-1)
|
|
{
|
|
ICLASS: VRSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRTPH (VRSQRTPH-256-1)
|
|
{
|
|
ICLASS: VRSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRTPH (VRSQRTPH-512-1)
|
|
{
|
|
ICLASS: VRSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX
|
|
PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E4
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION
|
|
PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VRSQRTSH (VRSQRTSH-128-1)
|
|
{
|
|
ICLASS: VRSQRTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR
|
|
PATTERN: EVV 0x4F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VRSQRTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E10
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR
|
|
PATTERN: EVV 0x4F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPH (VSCALEFPH-128-1)
|
|
{
|
|
ICLASS: VSCALEFPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPH (VSCALEFPH-256-1)
|
|
{
|
|
ICLASS: VSCALEFPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFPH (VSCALEFPH-512-1)
|
|
{
|
|
ICLASS: VSCALEFPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSCALEFSH (VSCALEFSH-128-1)
|
|
{
|
|
ICLASS: VSCALEFSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSCALEFSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPH (VSQRTPH-128-1)
|
|
{
|
|
ICLASS: VSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
|
|
IFORM: VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPH (VSQRTPH-256-1)
|
|
{
|
|
ICLASS: VSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16
|
|
IFORM: VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTPH (VSQRTPH-512-1)
|
|
{
|
|
ICLASS: VSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16
|
|
IFORM: VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSQRTSH (VSQRTSH-128-1)
|
|
{
|
|
ICLASS: VSQRTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSQRTSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPH (VSUBPH-128-1)
|
|
{
|
|
ICLASS: VSUBPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_128
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPH (VSUBPH-256-1)
|
|
{
|
|
ICLASS: VSUBPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16
|
|
IFORM: VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_256
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBPH (VSUBPH-512-1)
|
|
{
|
|
ICLASS: VSUBPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR
|
|
PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0
|
|
OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16
|
|
IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBPH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_512
|
|
EXCEPTIONS: AVX512-E2
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR
|
|
PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()
|
|
OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR
|
|
IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VSUBSH (VSUBSH-128-1)
|
|
{
|
|
ICLASS: VSUBSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16
|
|
IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VSUBSH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3
|
|
REAL_OPCODE: Y
|
|
ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|
|
# EMITTING VUCOMISH (VUCOMISH-128-1)
|
|
{
|
|
ICLASS: VUCOMISH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16
|
|
IFORM: VUCOMISH_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUCOMISH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0
|
|
OPERANDS: REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16
|
|
IFORM: VUCOMISH_XMMf16_XMMf16_AVX512
|
|
}
|
|
|
|
{
|
|
ICLASS: VUCOMISH
|
|
CPL: 3
|
|
CATEGORY: FP16
|
|
EXTENSION: AVX512EVEX
|
|
ISA_SET: AVX512_FP16_SCALAR
|
|
EXCEPTIONS: AVX512-E3NF
|
|
REAL_OPCODE: Y
|
|
FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ]
|
|
ATTRIBUTES: DISP8_SCALAR MXCSR SIMD_SCALAR
|
|
PATTERN: EVV 0x2E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR()
|
|
OPERANDS: REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16
|
|
IFORM: VUCOMISH_XMMf16_MEMf16_AVX512
|
|
}
|
|
|
|
|