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2121 lines
85 KiB
2121 lines
85 KiB
nt: SEGMENT_DEFAULT_ENCODE
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working rule:
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BASE0=rIPa() -> nothing
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inlining rule: rIPa()::
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OUTREG=XED_REG_EIP EASZ=2 -> nothing
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OUTREG=XED_REG_RIP EASZ=3 -> nothing
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new rule BASE0=XED_REG_EIP EASZ=2 -> nothing
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new rule BASE0=XED_REG_RIP EASZ=3 -> nothing
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working rule:
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BASE0=ArSP() -> FB DEFAULT_SEG=1 value=0x1
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inlining rule: ArSP()::
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OUTREG=XED_REG_SP EASZ=1 -> nothing
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OUTREG=XED_REG_ESP EASZ=2 -> nothing
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OUTREG=XED_REG_RSP EASZ=3 -> nothing
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new rule BASE0=XED_REG_SP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1
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new rule BASE0=XED_REG_ESP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1
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new rule BASE0=XED_REG_RSP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1
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working rule:
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BASE0=ArBP() -> FB DEFAULT_SEG=1 value=0x1
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inlining rule: ArBP()::
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OUTREG=XED_REG_BP EASZ=1 -> nothing
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OUTREG=XED_REG_EBP EASZ=2 -> nothing
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OUTREG=XED_REG_RBP EASZ=3 -> nothing
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new rule BASE0=XED_REG_BP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1
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new rule BASE0=XED_REG_EBP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1
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new rule BASE0=XED_REG_RBP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1
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working rule:
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BASE0=ArAX() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: ArAX()::
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OUTREG=XED_REG_AX EASZ=1 -> nothing
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OUTREG=XED_REG_EAX EASZ=2 -> nothing
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OUTREG=XED_REG_RAX EASZ=3 -> nothing
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new rule BASE0=XED_REG_AX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_EAX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_RAX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=ArCX() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: ArCX()::
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OUTREG=XED_REG_CX EASZ=1 -> nothing
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OUTREG=XED_REG_ECX EASZ=2 -> nothing
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OUTREG=XED_REG_RCX EASZ=3 -> nothing
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new rule BASE0=XED_REG_CX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_ECX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_RCX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=ArDX() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: ArDX()::
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OUTREG=XED_REG_DX EASZ=1 -> nothing
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OUTREG=XED_REG_EDX EASZ=2 -> nothing
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OUTREG=XED_REG_RDX EASZ=3 -> nothing
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new rule BASE0=XED_REG_DX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_EDX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_RDX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=ArBX() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: ArBX()::
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OUTREG=XED_REG_BX EASZ=1 -> nothing
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OUTREG=XED_REG_EBX EASZ=2 -> nothing
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OUTREG=XED_REG_RBX EASZ=3 -> nothing
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new rule BASE0=XED_REG_BX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_EBX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_RBX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=ArSI() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: ArSI()::
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OUTREG=XED_REG_SI EASZ=1 -> nothing
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OUTREG=XED_REG_ESI EASZ=2 -> nothing
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OUTREG=XED_REG_RSI EASZ=3 -> nothing
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new rule BASE0=XED_REG_SI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_ESI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_RSI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=ArDI() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: ArDI()::
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OUTREG=XED_REG_DI EASZ=1 -> nothing
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OUTREG=XED_REG_EDI EASZ=2 -> nothing
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OUTREG=XED_REG_RDI EASZ=3 -> nothing
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new rule BASE0=XED_REG_DI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_EDI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_RDI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar8() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar8()::
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OUTREG=XED_REG_R8W EASZ=1 -> nothing
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OUTREG=XED_REG_R8D EASZ=2 -> nothing
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OUTREG=XED_REG_R8 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R8W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R8D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R8 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar9() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar9()::
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OUTREG=XED_REG_R9W EASZ=1 -> nothing
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OUTREG=XED_REG_R9D EASZ=2 -> nothing
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OUTREG=XED_REG_R9 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R9W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R9D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R9 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar10() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar10()::
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OUTREG=XED_REG_R10W EASZ=1 -> nothing
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OUTREG=XED_REG_R10D EASZ=2 -> nothing
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OUTREG=XED_REG_R10 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R10W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R10D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R10 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar11() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar11()::
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OUTREG=XED_REG_R11W EASZ=1 -> nothing
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OUTREG=XED_REG_R11D EASZ=2 -> nothing
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OUTREG=XED_REG_R11 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R11W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R11D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R11 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar12() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar12()::
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OUTREG=XED_REG_R12W EASZ=1 -> nothing
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OUTREG=XED_REG_R12D EASZ=2 -> nothing
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OUTREG=XED_REG_R12 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R12W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R12D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R12 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar13() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar13()::
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OUTREG=XED_REG_R13W EASZ=1 -> nothing
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OUTREG=XED_REG_R13D EASZ=2 -> nothing
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OUTREG=XED_REG_R13 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R13W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R13D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R13 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar14() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar14()::
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OUTREG=XED_REG_R14W EASZ=1 -> nothing
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OUTREG=XED_REG_R14D EASZ=2 -> nothing
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OUTREG=XED_REG_R14 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R14W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R14D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R14 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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working rule:
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BASE0=Ar15() -> FB DEFAULT_SEG=0 value=0x0
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inlining rule: Ar15()::
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OUTREG=XED_REG_R15W EASZ=1 -> nothing
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OUTREG=XED_REG_R15D EASZ=2 -> nothing
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OUTREG=XED_REG_R15 EASZ=3 -> nothing
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new rule BASE0=XED_REG_R15W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R15D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0
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new rule BASE0=XED_REG_R15 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0
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nt: SEGMENT_ENCODE
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nt: SIB_REQUIRED_ENCODE
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working rule:
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EASZ=2 INDEX=GPR32e() -> FB NEED_SIB=1 value=0x1
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inlining rule: GPR32e()::
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MODE=1 OUTREG=GPR32e_m32() -> nothing
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MODE=2 OUTREG=GPR32e_m64() -> nothing
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new rule EASZ=2 MODE=1 INDEX=GPR32e_m32() -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=GPR32e_m64() -> FB NEED_SIB=1 value=0x1
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working rule:
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EASZ=3 INDEX=GPR64e() -> FB NEED_SIB=1 value=0x1
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inlining rule: GPR64e()::
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OUTREG=XED_REG_RAX -> nothing
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OUTREG=XED_REG_RBX -> nothing
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OUTREG=XED_REG_RCX -> nothing
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OUTREG=XED_REG_RDX -> nothing
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OUTREG=XED_REG_RSP -> nothing
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OUTREG=XED_REG_RBP -> nothing
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OUTREG=XED_REG_RSI -> nothing
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OUTREG=XED_REG_RDI -> nothing
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OUTREG=XED_REG_R8 -> nothing
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OUTREG=XED_REG_R9 -> nothing
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OUTREG=XED_REG_R10 -> nothing
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OUTREG=XED_REG_R11 -> nothing
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OUTREG=XED_REG_R12 -> nothing
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OUTREG=XED_REG_R13 -> nothing
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OUTREG=XED_REG_R14 -> nothing
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OUTREG=XED_REG_R15 -> nothing
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new rule EASZ=3 INDEX=XED_REG_RAX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_RBX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_RCX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_RDX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_RSP -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_RBP -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_RSI -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_RDI -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R8 -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R9 -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R10 -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R11 -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R12 -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R13 -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R14 -> FB NEED_SIB=1 value=0x1
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new rule EASZ=3 INDEX=XED_REG_R15 -> FB NEED_SIB=1 value=0x1
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working rule:
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EASZ!=1 BASE0=ArSP() -> FB NEED_SIB=1 value=0x1
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inlining rule: ArSP()::
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OUTREG=XED_REG_SP EASZ=1 -> nothing
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OUTREG=XED_REG_ESP EASZ=2 -> nothing
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OUTREG=XED_REG_RSP EASZ=3 -> nothing
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new rule EASZ!=1 BASE0=XED_REG_SP EASZ=1 -> FB NEED_SIB=1 value=0x1
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new rule EASZ!=1 BASE0=XED_REG_ESP EASZ=2 -> FB NEED_SIB=1 value=0x1
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new rule EASZ!=1 BASE0=XED_REG_RSP EASZ=3 -> FB NEED_SIB=1 value=0x1
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working rule:
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EASZ!=1 BASE0=Ar12() -> FB NEED_SIB=1 value=0x1
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inlining rule: Ar12()::
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OUTREG=XED_REG_R12W EASZ=1 -> nothing
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OUTREG=XED_REG_R12D EASZ=2 -> nothing
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OUTREG=XED_REG_R12 EASZ=3 -> nothing
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new rule EASZ!=1 BASE0=XED_REG_R12W EASZ=1 -> FB NEED_SIB=1 value=0x1
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new rule EASZ!=1 BASE0=XED_REG_R12D EASZ=2 -> FB NEED_SIB=1 value=0x1
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new rule EASZ!=1 BASE0=XED_REG_R12 EASZ=3 -> FB NEED_SIB=1 value=0x1
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working rule:
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EASZ=2 MODE=1 INDEX=GPR32e_m32() -> FB NEED_SIB=1 value=0x1
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inlining rule: GPR32e_m32()::
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OUTREG=XED_REG_EAX -> nothing
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OUTREG=XED_REG_EBX -> nothing
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OUTREG=XED_REG_ECX -> nothing
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OUTREG=XED_REG_EDX -> nothing
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OUTREG=XED_REG_ESP -> nothing
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OUTREG=XED_REG_EBP -> nothing
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OUTREG=XED_REG_ESI -> nothing
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OUTREG=XED_REG_EDI -> nothing
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new rule EASZ=2 MODE=1 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=1 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=1 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=1 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=1 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=1 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=1 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=1 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1
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working rule:
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EASZ=2 MODE=2 INDEX=GPR32e_m64() -> FB NEED_SIB=1 value=0x1
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inlining rule: GPR32e_m64()::
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OUTREG=XED_REG_EAX -> nothing
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OUTREG=XED_REG_EBX -> nothing
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OUTREG=XED_REG_ECX -> nothing
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OUTREG=XED_REG_EDX -> nothing
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OUTREG=XED_REG_ESP -> nothing
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OUTREG=XED_REG_EBP -> nothing
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OUTREG=XED_REG_ESI -> nothing
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OUTREG=XED_REG_EDI -> nothing
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OUTREG=XED_REG_R8D -> nothing
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OUTREG=XED_REG_R9D -> nothing
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OUTREG=XED_REG_R10D -> nothing
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OUTREG=XED_REG_R11D -> nothing
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OUTREG=XED_REG_R12D -> nothing
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OUTREG=XED_REG_R13D -> nothing
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OUTREG=XED_REG_R14D -> nothing
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OUTREG=XED_REG_R15D -> nothing
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new rule EASZ=2 MODE=2 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R8D -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R9D -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R10D -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R11D -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R12D -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R13D -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R14D -> FB NEED_SIB=1 value=0x1
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new rule EASZ=2 MODE=2 INDEX=XED_REG_R15D -> FB NEED_SIB=1 value=0x1
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nt: SIBBASE_ENCODE
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nt: SIBBASE_ENCODE_SIB1
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working rule:
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BASE0=ArAX() -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0
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inlining rule: ArAX()::
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OUTREG=XED_REG_AX EASZ=1 -> nothing
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OUTREG=XED_REG_EAX EASZ=2 -> nothing
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OUTREG=XED_REG_RAX EASZ=3 -> nothing
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new rule BASE0=XED_REG_AX EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0
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new rule BASE0=XED_REG_EAX EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0
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new rule BASE0=XED_REG_RAX EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0
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working rule:
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BASE0=Ar8() -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1
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inlining rule: Ar8()::
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OUTREG=XED_REG_R8W EASZ=1 -> nothing
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OUTREG=XED_REG_R8D EASZ=2 -> nothing
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OUTREG=XED_REG_R8 EASZ=3 -> nothing
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|
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new rule BASE0=XED_REG_R8W EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R8D EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R8 EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1
|
|
working rule:
|
|
BASE0=ArCX() -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_CX EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_ECX EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_RCX EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar9() -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R9W EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R9D EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R9 EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1
|
|
working rule:
|
|
BASE0=ArDX() -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_DX EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_EDX EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_RDX EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar10() -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R10W EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R10D EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R10 EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1
|
|
working rule:
|
|
BASE0=ArBX() -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_BX EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_EBX EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_RBX EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar11() -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R11W EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R11D EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R11 EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1
|
|
working rule:
|
|
BASE0=ArSP() -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0
|
|
inlining rule: ArSP()::
|
|
OUTREG=XED_REG_SP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSP EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_SP EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_ESP EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_RSP EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar12() -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R12W EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R12D EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R12 EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1
|
|
working rule:
|
|
BASE0=ArBP() -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar13() -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1
|
|
working rule:
|
|
BASE0=ArSI() -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_SI EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_ESI EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_RSI EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar14() -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R14W EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R14D EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R14 EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1
|
|
working rule:
|
|
BASE0=ArDI() -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_DI EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_EDI EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0
|
|
new rule BASE0=XED_REG_RDI EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar15() -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R15W EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R15D EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1
|
|
new rule BASE0=XED_REG_R15 EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1
|
|
nt: SIBINDEX_ENCODE
|
|
nt: SIBINDEX_ENCODE_SIB1
|
|
working rule:
|
|
INDEX=ArAX() -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0
|
|
inlining rule: ArAX()::
|
|
OUTREG=XED_REG_AX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EAX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RAX EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_AX EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_EAX EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_RAX EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0
|
|
working rule:
|
|
INDEX=Ar8() -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1
|
|
inlining rule: Ar8()::
|
|
OUTREG=XED_REG_R8W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R8D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R8 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R8W EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R8D EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R8 EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1
|
|
working rule:
|
|
INDEX=ArCX() -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_CX EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_ECX EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_RCX EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0
|
|
working rule:
|
|
INDEX=Ar9() -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R9W EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R9D EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R9 EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1
|
|
working rule:
|
|
INDEX=ArDX() -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_DX EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_EDX EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_RDX EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0
|
|
working rule:
|
|
INDEX=Ar10() -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R10W EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R10D EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R10 EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1
|
|
working rule:
|
|
INDEX=ArBX() -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_BX EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_EBX EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_RBX EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0
|
|
working rule:
|
|
INDEX=Ar11() -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R11W EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R11D EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R11 EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1
|
|
working rule:
|
|
INDEX=Ar12() -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R12W EASZ=1 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R12D EASZ=2 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R12 EASZ=3 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1
|
|
working rule:
|
|
INDEX=ArBP() -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_BP EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_EBP EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_RBP EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0
|
|
working rule:
|
|
INDEX=Ar13() -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R13W EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R13D EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R13 EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1
|
|
working rule:
|
|
INDEX=ArSI() -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_SI EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_ESI EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_RSI EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0
|
|
working rule:
|
|
INDEX=Ar14() -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R14W EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R14D EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R14 EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1
|
|
working rule:
|
|
INDEX=ArDI() -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_DI EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_EDI EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0
|
|
new rule INDEX=XED_REG_RDI EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0
|
|
working rule:
|
|
INDEX=Ar15() -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule INDEX=XED_REG_R15W EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R15D EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1
|
|
new rule INDEX=XED_REG_R15 EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1
|
|
nt: SIBSCALE_ENCODE
|
|
nt: MODRM_MOD_ENCODE
|
|
nt: MODRM_MOD_EA16_DISP0
|
|
nt: MODRM_MOD_EA16_DISP8
|
|
nt: MODRM_MOD_EA16_DISP16
|
|
nt: MODRM_MOD_EA32_DISP0
|
|
nt: MODRM_MOD_EA32_DISP8
|
|
nt: MODRM_MOD_EA32_DISP32
|
|
working rule:
|
|
BASE0=GPR32e() -> FB MOD=2 value=0x2
|
|
inlining rule: GPR32e()::
|
|
MODE=1 OUTREG=GPR32e_m32() -> nothing
|
|
MODE=2 OUTREG=GPR32e_m64() -> nothing
|
|
|
|
new rule MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2
|
|
working rule:
|
|
BASE0=rIPa() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: rIPa()::
|
|
OUTREG=XED_REG_EIP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RIP EASZ=3 -> nothing
|
|
|
|
new rule MODE=2 BASE0=XED_REG_EIP EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule MODE=2 BASE0=XED_REG_RIP EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2
|
|
inlining rule: GPR32e_m32()::
|
|
OUTREG=XED_REG_EAX -> nothing
|
|
OUTREG=XED_REG_EBX -> nothing
|
|
OUTREG=XED_REG_ECX -> nothing
|
|
OUTREG=XED_REG_EDX -> nothing
|
|
OUTREG=XED_REG_ESP -> nothing
|
|
OUTREG=XED_REG_EBP -> nothing
|
|
OUTREG=XED_REG_ESI -> nothing
|
|
OUTREG=XED_REG_EDI -> nothing
|
|
|
|
new rule MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2
|
|
new rule MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2
|
|
new rule MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2
|
|
new rule MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2
|
|
new rule MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2
|
|
new rule MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2
|
|
new rule MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2
|
|
new rule MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2
|
|
working rule:
|
|
MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2
|
|
inlining rule: GPR32e_m64()::
|
|
OUTREG=XED_REG_EAX -> nothing
|
|
OUTREG=XED_REG_EBX -> nothing
|
|
OUTREG=XED_REG_ECX -> nothing
|
|
OUTREG=XED_REG_EDX -> nothing
|
|
OUTREG=XED_REG_ESP -> nothing
|
|
OUTREG=XED_REG_EBP -> nothing
|
|
OUTREG=XED_REG_ESI -> nothing
|
|
OUTREG=XED_REG_EDI -> nothing
|
|
OUTREG=XED_REG_R8D -> nothing
|
|
OUTREG=XED_REG_R9D -> nothing
|
|
OUTREG=XED_REG_R10D -> nothing
|
|
OUTREG=XED_REG_R11D -> nothing
|
|
OUTREG=XED_REG_R12D -> nothing
|
|
OUTREG=XED_REG_R13D -> nothing
|
|
OUTREG=XED_REG_R14D -> nothing
|
|
OUTREG=XED_REG_R15D -> nothing
|
|
|
|
new rule MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2
|
|
new rule MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2
|
|
nt: MODRM_MOD_EA64_DISP0
|
|
nt: MODRM_MOD_EA64_DISP8
|
|
working rule:
|
|
BASE0=GPR64e() -> FB MOD=1 value=0x1
|
|
inlining rule: GPR64e()::
|
|
OUTREG=XED_REG_RAX -> nothing
|
|
OUTREG=XED_REG_RBX -> nothing
|
|
OUTREG=XED_REG_RCX -> nothing
|
|
OUTREG=XED_REG_RDX -> nothing
|
|
OUTREG=XED_REG_RSP -> nothing
|
|
OUTREG=XED_REG_RBP -> nothing
|
|
OUTREG=XED_REG_RSI -> nothing
|
|
OUTREG=XED_REG_RDI -> nothing
|
|
OUTREG=XED_REG_R8 -> nothing
|
|
OUTREG=XED_REG_R9 -> nothing
|
|
OUTREG=XED_REG_R10 -> nothing
|
|
OUTREG=XED_REG_R11 -> nothing
|
|
OUTREG=XED_REG_R12 -> nothing
|
|
OUTREG=XED_REG_R13 -> nothing
|
|
OUTREG=XED_REG_R14 -> nothing
|
|
OUTREG=XED_REG_R15 -> nothing
|
|
|
|
new rule BASE0=XED_REG_RAX -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_RBX -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_RCX -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_RDX -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_RSP -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_RBP -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_RSI -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_RDI -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R8 -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R9 -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R10 -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R11 -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R12 -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R13 -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R14 -> FB MOD=1 value=0x1
|
|
new rule BASE0=XED_REG_R15 -> FB MOD=1 value=0x1
|
|
nt: MODRM_MOD_EA64_DISP32
|
|
nt: MODRM_RM_ENCODE
|
|
nt: MODRM_RM_ENCODE_EA16_SIB0
|
|
nt: MODRM_RM_ENCODE_EA64_SIB0
|
|
nt: MODRM_RM_ENCODE_EA32_SIB0
|
|
nt: MODRM_RM_ENCODE_EANOT16_SIB1
|
|
nt: SIB_NT
|
|
nt: DISP_NT
|
|
nt: ERROR
|
|
nt: DISP_WIDTH_0
|
|
nt: DISP_WIDTH_8
|
|
nt: DISP_WIDTH_16
|
|
nt: DISP_WIDTH_32
|
|
nt: DISP_WIDTH_0_8_16
|
|
nt: DISP_WIDTH_0_8_32
|
|
nt: FIXUP_EOSZ_ENC
|
|
nt: FIXUP_EASZ_ENC
|
|
nt: FIXUP_SMODE_ENC
|
|
nt: REMOVE_SEGMENT
|
|
nt: REMOVE_SEGMENT_AGEN1
|
|
working rule:
|
|
SEG0=SEGe() -> FB ERROR=XED_ERROR_GENERAL_ERROR
|
|
inlining rule: SEGe()::
|
|
OUTREG=XED_REG_DS -> nothing
|
|
OUTREG=XED_REG_CS -> nothing
|
|
OUTREG=XED_REG_ES -> nothing
|
|
OUTREG=XED_REG_FS -> nothing
|
|
OUTREG=XED_REG_GS -> nothing
|
|
OUTREG=XED_REG_SS -> nothing
|
|
|
|
new rule SEG0=XED_REG_DS -> FB ERROR=XED_ERROR_GENERAL_ERROR
|
|
new rule SEG0=XED_REG_CS -> FB ERROR=XED_ERROR_GENERAL_ERROR
|
|
new rule SEG0=XED_REG_ES -> FB ERROR=XED_ERROR_GENERAL_ERROR
|
|
new rule SEG0=XED_REG_FS -> FB ERROR=XED_ERROR_GENERAL_ERROR
|
|
new rule SEG0=XED_REG_GS -> FB ERROR=XED_ERROR_GENERAL_ERROR
|
|
new rule SEG0=XED_REG_SS -> FB ERROR=XED_ERROR_GENERAL_ERROR
|
|
nt: OVERRIDE_SEG0
|
|
nt: OVERRIDE_SEG1
|
|
nt: REX_PREFIX_ENC
|
|
nt: PREFIX_ENC
|
|
nt: DF64
|
|
nt: OSZ_NONTERM_ENC
|
|
nt: REFINING66
|
|
nt: IGNORE66
|
|
nt: IMMUNE66
|
|
nt: IMMUNE66_LOOP64
|
|
nt: IMMUNE_REXW
|
|
nt: CR_WIDTH
|
|
nt: FORCE64
|
|
nt: BRANCH_HINT
|
|
nt: CET_NO_TRACK
|
|
nt: VEXED_REX
|
|
nt: XOP_TYPE_ENC
|
|
nt: XOP_MAP_ENC
|
|
nt: XOP_REXXB_ENC
|
|
nt: BND_R_CHECK
|
|
nt: BND_B_CHECK
|
|
nt: VEX_TYPE_ENC
|
|
nt: VEX_REXR_ENC
|
|
nt: VEX_REXXB_ENC
|
|
nt: VEX_MAP_ENC
|
|
nt: VEX_REG_ENC
|
|
nt: VEX_ESCVL_ENC
|
|
nt: SE_IMM8
|
|
nt: VMODRM_MOD_ENCODE
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArBP() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar13() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArBP() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar13() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArAX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArAX()::
|
|
OUTREG=XED_REG_AX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EAX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RAX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArBX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArCX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArDX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArSI() -> FB MOD=0 value=0x0
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArDI() -> FB MOD=0 value=0x0
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=ArSP() -> FB MOD=0 value=0x0
|
|
inlining rule: ArSP()::
|
|
OUTREG=XED_REG_SP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSP EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar8() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: Ar8()::
|
|
OUTREG=XED_REG_R8W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R8D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R8 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar9() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar10() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar11() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar12() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar14() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=0 BASE0=Ar15() MODE=2 -> FB MOD=0 value=0x0
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArAX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArAX()::
|
|
OUTREG=XED_REG_AX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EAX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RAX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArBX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArCX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArDX() -> FB MOD=0 value=0x0
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArSI() -> FB MOD=0 value=0x0
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArDI() -> FB MOD=0 value=0x0
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=ArSP() -> FB MOD=0 value=0x0
|
|
inlining rule: ArSP()::
|
|
OUTREG=XED_REG_SP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSP EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar8() -> FB MOD=0 value=0x0
|
|
inlining rule: Ar8()::
|
|
OUTREG=XED_REG_R8W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R8D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R8 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar9() -> FB MOD=0 value=0x0
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar10() -> FB MOD=0 value=0x0
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar11() -> FB MOD=0 value=0x0
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar12() -> FB MOD=0 value=0x0
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar14() -> FB MOD=0 value=0x0
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=0 BASE0=Ar15() -> FB MOD=0 value=0x0
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0
|
|
new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=8 BASE0=GPR64e() -> FB MOD=1 value=0x1
|
|
inlining rule: GPR64e()::
|
|
OUTREG=XED_REG_RAX -> nothing
|
|
OUTREG=XED_REG_RBX -> nothing
|
|
OUTREG=XED_REG_RCX -> nothing
|
|
OUTREG=XED_REG_RDX -> nothing
|
|
OUTREG=XED_REG_RSP -> nothing
|
|
OUTREG=XED_REG_RBP -> nothing
|
|
OUTREG=XED_REG_RSI -> nothing
|
|
OUTREG=XED_REG_RDI -> nothing
|
|
OUTREG=XED_REG_R8 -> nothing
|
|
OUTREG=XED_REG_R9 -> nothing
|
|
OUTREG=XED_REG_R10 -> nothing
|
|
OUTREG=XED_REG_R11 -> nothing
|
|
OUTREG=XED_REG_R12 -> nothing
|
|
OUTREG=XED_REG_R13 -> nothing
|
|
OUTREG=XED_REG_R14 -> nothing
|
|
OUTREG=XED_REG_R15 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RAX -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBX -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RCX -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDX -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSP -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBP -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSI -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDI -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R8 -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R9 -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R10 -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R11 -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R12 -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R13 -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R14 -> FB MOD=1 value=0x1
|
|
new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R15 -> FB MOD=1 value=0x1
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=32 BASE0=GPR32e() -> FB MOD=2 value=0x2
|
|
inlining rule: GPR32e()::
|
|
MODE=1 OUTREG=GPR32e_m32() -> nothing
|
|
MODE=2 OUTREG=GPR32e_m64() -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArAX() -> FB MOD=2 value=0x2
|
|
inlining rule: ArAX()::
|
|
OUTREG=XED_REG_AX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EAX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RAX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_AX EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArBX() -> FB MOD=2 value=0x2
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BX EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArCX() -> FB MOD=2 value=0x2
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_CX EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArDX() -> FB MOD=2 value=0x2
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DX EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArSI() -> FB MOD=2 value=0x2
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SI EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArDI() -> FB MOD=2 value=0x2
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DI EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArSP() -> FB MOD=2 value=0x2
|
|
inlining rule: ArSP()::
|
|
OUTREG=XED_REG_SP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSP EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SP EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=ArBP() -> FB MOD=2 value=0x2
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BP EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar8() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar8()::
|
|
OUTREG=XED_REG_R8W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R8D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R8 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar9() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar10() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar11() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar12() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar13() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar14() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=3 DISP_WIDTH=32 BASE0=Ar15() -> FB MOD=2 value=0x2
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=2 value=0x2
|
|
new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2
|
|
inlining rule: GPR32e_m32()::
|
|
OUTREG=XED_REG_EAX -> nothing
|
|
OUTREG=XED_REG_EBX -> nothing
|
|
OUTREG=XED_REG_ECX -> nothing
|
|
OUTREG=XED_REG_EDX -> nothing
|
|
OUTREG=XED_REG_ESP -> nothing
|
|
OUTREG=XED_REG_EBP -> nothing
|
|
OUTREG=XED_REG_ESI -> nothing
|
|
OUTREG=XED_REG_EDI -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2
|
|
working rule:
|
|
EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2
|
|
inlining rule: GPR32e_m64()::
|
|
OUTREG=XED_REG_EAX -> nothing
|
|
OUTREG=XED_REG_EBX -> nothing
|
|
OUTREG=XED_REG_ECX -> nothing
|
|
OUTREG=XED_REG_EDX -> nothing
|
|
OUTREG=XED_REG_ESP -> nothing
|
|
OUTREG=XED_REG_EBP -> nothing
|
|
OUTREG=XED_REG_ESI -> nothing
|
|
OUTREG=XED_REG_EDI -> nothing
|
|
OUTREG=XED_REG_R8D -> nothing
|
|
OUTREG=XED_REG_R9D -> nothing
|
|
OUTREG=XED_REG_R10D -> nothing
|
|
OUTREG=XED_REG_R11D -> nothing
|
|
OUTREG=XED_REG_R12D -> nothing
|
|
OUTREG=XED_REG_R13D -> nothing
|
|
OUTREG=XED_REG_R14D -> nothing
|
|
OUTREG=XED_REG_R15D -> nothing
|
|
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2
|
|
new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2
|
|
nt: VSIB_ENC_BASE
|
|
working rule:
|
|
BASE0=ArAX() -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0
|
|
inlining rule: ArAX()::
|
|
OUTREG=XED_REG_AX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EAX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RAX EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_AX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0
|
|
new rule BASE0=XED_REG_EAX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0
|
|
new rule BASE0=XED_REG_RAX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0
|
|
working rule:
|
|
BASE0=ArCX() -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_CX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1
|
|
new rule BASE0=XED_REG_ECX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1
|
|
new rule BASE0=XED_REG_RCX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1
|
|
working rule:
|
|
BASE0=ArDX() -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_DX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2
|
|
new rule BASE0=XED_REG_EDX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2
|
|
new rule BASE0=XED_REG_RDX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2
|
|
working rule:
|
|
BASE0=ArBX() -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_BX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3
|
|
new rule BASE0=XED_REG_EBX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3
|
|
new rule BASE0=XED_REG_RBX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3
|
|
working rule:
|
|
BASE0=ArSP() -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4
|
|
inlining rule: ArSP()::
|
|
OUTREG=XED_REG_SP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSP EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_SP EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4
|
|
new rule BASE0=XED_REG_ESP EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4
|
|
new rule BASE0=XED_REG_RSP EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4
|
|
working rule:
|
|
BASE0=ArBP() -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5
|
|
new rule BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5
|
|
new rule BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5
|
|
working rule:
|
|
BASE0=Ar13() -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5
|
|
new rule BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5
|
|
new rule BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5
|
|
working rule:
|
|
BASE0=ArSI() -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_SI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6
|
|
new rule BASE0=XED_REG_ESI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6
|
|
new rule BASE0=XED_REG_RSI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6
|
|
working rule:
|
|
BASE0=ArDI() -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_DI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7
|
|
new rule BASE0=XED_REG_EDI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7
|
|
new rule BASE0=XED_REG_RDI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7
|
|
working rule:
|
|
BASE0=Ar8() -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0
|
|
inlining rule: Ar8()::
|
|
OUTREG=XED_REG_R8W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R8D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R8 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R8W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0
|
|
new rule BASE0=XED_REG_R8D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0
|
|
new rule BASE0=XED_REG_R8 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0
|
|
working rule:
|
|
BASE0=Ar9() -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R9W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1
|
|
new rule BASE0=XED_REG_R9D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1
|
|
new rule BASE0=XED_REG_R9 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1
|
|
working rule:
|
|
BASE0=Ar10() -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R10W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2
|
|
new rule BASE0=XED_REG_R10D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2
|
|
new rule BASE0=XED_REG_R10 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2
|
|
working rule:
|
|
BASE0=Ar11() -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R11W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3
|
|
new rule BASE0=XED_REG_R11D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3
|
|
new rule BASE0=XED_REG_R11 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3
|
|
working rule:
|
|
BASE0=Ar12() -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R12W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4
|
|
new rule BASE0=XED_REG_R12D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4
|
|
new rule BASE0=XED_REG_R12 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4
|
|
working rule:
|
|
BASE0=Ar14() -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R14W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6
|
|
new rule BASE0=XED_REG_R14D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6
|
|
new rule BASE0=XED_REG_R14 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6
|
|
working rule:
|
|
BASE0=Ar15() -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule BASE0=XED_REG_R15W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7
|
|
new rule BASE0=XED_REG_R15D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7
|
|
new rule BASE0=XED_REG_R15 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7
|
|
nt: VSIB_ENC_SCALE
|
|
nt: VSIB_ENC
|
|
nt: VSIB_ENC_INDEX_XMM
|
|
nt: VSIB_ENC_INDEX_YMM
|
|
nt: DISP_WIDTH_8_32
|
|
nt: NELEM_TUPLE1_4X
|
|
nt: EVEX_62_REXR_ENC
|
|
nt: EVEX_REXX_ENC
|
|
nt: EVEX_REXB_ENC
|
|
nt: EVEX_REXRR_ENC
|
|
nt: EVEX_MAP_ENC
|
|
nt: EVEX_REXW_VVVV_ENC
|
|
nt: EVEX_UPP_ENC
|
|
nt: EVEX_LL_ENC
|
|
nt: AVX512_EVEX_BYTE3_ENC
|
|
nt: AVX512_ROUND
|
|
nt: SAE
|
|
nt: ESIZE_128_BITS
|
|
nt: ESIZE_64_BITS
|
|
nt: ESIZE_32_BITS
|
|
nt: ESIZE_16_BITS
|
|
nt: ESIZE_8_BITS
|
|
nt: ESIZE_4_BITS
|
|
nt: ESIZE_2_BITS
|
|
nt: ESIZE_1_BITS
|
|
nt: NELEM_MOVDDUP
|
|
nt: NELEM_FULLMEM
|
|
nt: NELEM_HALFMEM
|
|
nt: NELEM_QUARTERMEM
|
|
nt: NELEM_EIGHTHMEM
|
|
nt: NELEM_GPR_READER_BYTE
|
|
nt: NELEM_GPR_READER_WORD
|
|
nt: NELEM_GPR_WRITER_LDOP_D
|
|
nt: NELEM_GPR_WRITER_LDOP_Q
|
|
nt: NELEM_GPR_WRITER_STORE_BYTE
|
|
nt: NELEM_GPR_WRITER_STORE_WORD
|
|
nt: NELEM_TUPLE1_BYTE
|
|
nt: NELEM_TUPLE1_WORD
|
|
nt: NELEM_SCALAR
|
|
nt: NELEM_TUPLE1_SUBDWORD
|
|
nt: NELEM_GPR_READER
|
|
nt: NELEM_GPR_READER_SUBDWORD
|
|
nt: NELEM_GPR_WRITER_LDOP
|
|
nt: NELEM_GPR_WRITER_STORE
|
|
nt: NELEM_GPR_WRITER_STORE_SUBDWORD
|
|
nt: NELEM_MEM128
|
|
nt: NELEM_TUPLE1
|
|
nt: NELEM_GSCAT
|
|
nt: NELEM_TUPLE2
|
|
nt: NELEM_TUPLE4
|
|
nt: NELEM_TUPLE8
|
|
nt: NELEM_FULL
|
|
nt: NELEM_HALF
|
|
nt: FIX_ROUND_LEN512
|
|
nt: FIX_ROUND_LEN128
|
|
nt: UISA_ENC_INDEX_ZMM
|
|
nt: UISA_ENC_INDEX_YMM
|
|
nt: UISA_ENC_INDEX_XMM
|
|
nt: NELEM_QUARTER
|
|
nt: GPR8_R
|
|
nt: GPR8_B
|
|
nt: GPR8_SB
|
|
nt: SEGe
|
|
nt: GPR16e
|
|
nt: GPR32e
|
|
working rule:
|
|
MODE=1 OUTREG=GPR32e_m32() -> nothing
|
|
inlining rule: GPR32e_m32()::
|
|
OUTREG=XED_REG_EAX -> nothing
|
|
OUTREG=XED_REG_EBX -> nothing
|
|
OUTREG=XED_REG_ECX -> nothing
|
|
OUTREG=XED_REG_EDX -> nothing
|
|
OUTREG=XED_REG_ESP -> nothing
|
|
OUTREG=XED_REG_EBP -> nothing
|
|
OUTREG=XED_REG_ESI -> nothing
|
|
OUTREG=XED_REG_EDI -> nothing
|
|
|
|
new rule MODE=1 OUTREG=XED_REG_EAX -> nothing
|
|
new rule MODE=1 OUTREG=XED_REG_EBX -> nothing
|
|
new rule MODE=1 OUTREG=XED_REG_ECX -> nothing
|
|
new rule MODE=1 OUTREG=XED_REG_EDX -> nothing
|
|
new rule MODE=1 OUTREG=XED_REG_ESP -> nothing
|
|
new rule MODE=1 OUTREG=XED_REG_EBP -> nothing
|
|
new rule MODE=1 OUTREG=XED_REG_ESI -> nothing
|
|
new rule MODE=1 OUTREG=XED_REG_EDI -> nothing
|
|
working rule:
|
|
MODE=2 OUTREG=GPR32e_m64() -> nothing
|
|
inlining rule: GPR32e_m64()::
|
|
OUTREG=XED_REG_EAX -> nothing
|
|
OUTREG=XED_REG_EBX -> nothing
|
|
OUTREG=XED_REG_ECX -> nothing
|
|
OUTREG=XED_REG_EDX -> nothing
|
|
OUTREG=XED_REG_ESP -> nothing
|
|
OUTREG=XED_REG_EBP -> nothing
|
|
OUTREG=XED_REG_ESI -> nothing
|
|
OUTREG=XED_REG_EDI -> nothing
|
|
OUTREG=XED_REG_R8D -> nothing
|
|
OUTREG=XED_REG_R9D -> nothing
|
|
OUTREG=XED_REG_R10D -> nothing
|
|
OUTREG=XED_REG_R11D -> nothing
|
|
OUTREG=XED_REG_R12D -> nothing
|
|
OUTREG=XED_REG_R13D -> nothing
|
|
OUTREG=XED_REG_R14D -> nothing
|
|
OUTREG=XED_REG_R15D -> nothing
|
|
|
|
new rule MODE=2 OUTREG=XED_REG_EAX -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_EBX -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_ECX -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_EDX -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_ESP -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_EBP -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_ESI -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_EDI -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R8D -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R9D -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R10D -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R11D -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R12D -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R13D -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R14D -> nothing
|
|
new rule MODE=2 OUTREG=XED_REG_R15D -> nothing
|
|
nt: GPR32e_m32
|
|
nt: GPR32e_m64
|
|
nt: GPR64e
|
|
nt: ArAX
|
|
nt: ArBX
|
|
nt: ArCX
|
|
nt: ArDX
|
|
nt: ArSI
|
|
nt: ArDI
|
|
nt: ArSP
|
|
nt: ArBP
|
|
nt: SrSP
|
|
nt: SrBP
|
|
nt: Ar8
|
|
nt: Ar9
|
|
nt: Ar10
|
|
nt: Ar11
|
|
nt: Ar12
|
|
nt: Ar13
|
|
nt: Ar14
|
|
nt: Ar15
|
|
nt: rIP
|
|
nt: rIPa
|
|
nt: OeAX
|
|
nt: OrAX
|
|
nt: OrDX
|
|
nt: OrCX
|
|
nt: OrBX
|
|
nt: OrSP
|
|
nt: OrBP
|
|
nt: rFLAGS
|
|
nt: MMX_R
|
|
nt: MMX_B
|
|
nt: GPRv_R
|
|
nt: GPRv_SB
|
|
nt: GPRz_R
|
|
nt: GPRv_B
|
|
nt: GPRz_B
|
|
nt: GPRy_B
|
|
nt: GPRy_R
|
|
nt: GPR64_R
|
|
nt: GPR64_B
|
|
nt: GPR64_SB
|
|
nt: GPR64_X
|
|
nt: GPR32_R
|
|
nt: GPR32_B
|
|
nt: GPR32_SB
|
|
nt: GPR32_X
|
|
nt: GPR16_R
|
|
nt: GPR16_B
|
|
nt: GPR16_SB
|
|
nt: CR_R
|
|
nt: CR_B
|
|
nt: DR_R
|
|
nt: X87
|
|
nt: SEG
|
|
nt: SEG_MOV
|
|
nt: FINAL_DSEG
|
|
nt: FINAL_DSEG_NOT64
|
|
nt: FINAL_DSEG_MODE64
|
|
nt: FINAL_DSEG1
|
|
nt: FINAL_DSEG1_NOT64
|
|
nt: FINAL_DSEG1_MODE64
|
|
nt: FINAL_ESEG
|
|
nt: FINAL_ESEG1
|
|
nt: FINAL_SSEG1
|
|
nt: FINAL_SSEG0
|
|
nt: FINAL_SSEG
|
|
nt: FINAL_SSEG_NOT64
|
|
nt: FINAL_SSEG_MODE64
|
|
nt: XMM_R
|
|
nt: XMM_R_32
|
|
nt: XMM_R_64
|
|
nt: XMM_B
|
|
nt: XMM_B_32
|
|
nt: XMM_B_64
|
|
nt: BND_R
|
|
nt: BND_B
|
|
nt: A_GPR_R
|
|
working rule:
|
|
OUTREG=ArAX() -> FB REXR=0 value=0x0 FB REG=0 value=0x0
|
|
inlining rule: ArAX()::
|
|
OUTREG=XED_REG_AX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EAX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RAX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_AX EASZ=1 -> FB REXR=0 value=0x0 FB REG=0 value=0x0
|
|
new rule OUTREG=XED_REG_EAX EASZ=2 -> FB REXR=0 value=0x0 FB REG=0 value=0x0
|
|
new rule OUTREG=XED_REG_RAX EASZ=3 -> FB REXR=0 value=0x0 FB REG=0 value=0x0
|
|
working rule:
|
|
OUTREG=ArCX() -> FB REXR=0 value=0x0 FB REG=1 value=0x1
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_CX EASZ=1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1
|
|
new rule OUTREG=XED_REG_ECX EASZ=2 -> FB REXR=0 value=0x0 FB REG=1 value=0x1
|
|
new rule OUTREG=XED_REG_RCX EASZ=3 -> FB REXR=0 value=0x0 FB REG=1 value=0x1
|
|
working rule:
|
|
OUTREG=ArDX() -> FB REXR=0 value=0x0 FB REG=2 value=0x2
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_DX EASZ=1 -> FB REXR=0 value=0x0 FB REG=2 value=0x2
|
|
new rule OUTREG=XED_REG_EDX EASZ=2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2
|
|
new rule OUTREG=XED_REG_RDX EASZ=3 -> FB REXR=0 value=0x0 FB REG=2 value=0x2
|
|
working rule:
|
|
OUTREG=ArBX() -> FB REXR=0 value=0x0 FB REG=3 value=0x3
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_BX EASZ=1 -> FB REXR=0 value=0x0 FB REG=3 value=0x3
|
|
new rule OUTREG=XED_REG_EBX EASZ=2 -> FB REXR=0 value=0x0 FB REG=3 value=0x3
|
|
new rule OUTREG=XED_REG_RBX EASZ=3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3
|
|
working rule:
|
|
OUTREG=ArSP() -> FB REXR=0 value=0x0 FB REG=4 value=0x4
|
|
inlining rule: ArSP()::
|
|
OUTREG=XED_REG_SP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSP EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_SP EASZ=1 -> FB REXR=0 value=0x0 FB REG=4 value=0x4
|
|
new rule OUTREG=XED_REG_ESP EASZ=2 -> FB REXR=0 value=0x0 FB REG=4 value=0x4
|
|
new rule OUTREG=XED_REG_RSP EASZ=3 -> FB REXR=0 value=0x0 FB REG=4 value=0x4
|
|
working rule:
|
|
OUTREG=ArBP() -> FB REXR=0 value=0x0 FB REG=5 value=0x5
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_BP EASZ=1 -> FB REXR=0 value=0x0 FB REG=5 value=0x5
|
|
new rule OUTREG=XED_REG_EBP EASZ=2 -> FB REXR=0 value=0x0 FB REG=5 value=0x5
|
|
new rule OUTREG=XED_REG_RBP EASZ=3 -> FB REXR=0 value=0x0 FB REG=5 value=0x5
|
|
working rule:
|
|
OUTREG=ArSI() -> FB REXR=0 value=0x0 FB REG=6 value=0x6
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_SI EASZ=1 -> FB REXR=0 value=0x0 FB REG=6 value=0x6
|
|
new rule OUTREG=XED_REG_ESI EASZ=2 -> FB REXR=0 value=0x0 FB REG=6 value=0x6
|
|
new rule OUTREG=XED_REG_RSI EASZ=3 -> FB REXR=0 value=0x0 FB REG=6 value=0x6
|
|
working rule:
|
|
OUTREG=ArDI() -> FB REXR=0 value=0x0 FB REG=7 value=0x7
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_DI EASZ=1 -> FB REXR=0 value=0x0 FB REG=7 value=0x7
|
|
new rule OUTREG=XED_REG_EDI EASZ=2 -> FB REXR=0 value=0x0 FB REG=7 value=0x7
|
|
new rule OUTREG=XED_REG_RDI EASZ=3 -> FB REXR=0 value=0x0 FB REG=7 value=0x7
|
|
working rule:
|
|
OUTREG=Ar8() -> FB REXR=1 value=0x1 FB REG=0 value=0x0
|
|
inlining rule: Ar8()::
|
|
OUTREG=XED_REG_R8W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R8D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R8 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R8W EASZ=1 -> FB REXR=1 value=0x1 FB REG=0 value=0x0
|
|
new rule OUTREG=XED_REG_R8D EASZ=2 -> FB REXR=1 value=0x1 FB REG=0 value=0x0
|
|
new rule OUTREG=XED_REG_R8 EASZ=3 -> FB REXR=1 value=0x1 FB REG=0 value=0x0
|
|
working rule:
|
|
OUTREG=Ar9() -> FB REXR=1 value=0x1 FB REG=1 value=0x1
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R9W EASZ=1 -> FB REXR=1 value=0x1 FB REG=1 value=0x1
|
|
new rule OUTREG=XED_REG_R9D EASZ=2 -> FB REXR=1 value=0x1 FB REG=1 value=0x1
|
|
new rule OUTREG=XED_REG_R9 EASZ=3 -> FB REXR=1 value=0x1 FB REG=1 value=0x1
|
|
working rule:
|
|
OUTREG=Ar10() -> FB REXR=1 value=0x1 FB REG=2 value=0x2
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R10W EASZ=1 -> FB REXR=1 value=0x1 FB REG=2 value=0x2
|
|
new rule OUTREG=XED_REG_R10D EASZ=2 -> FB REXR=1 value=0x1 FB REG=2 value=0x2
|
|
new rule OUTREG=XED_REG_R10 EASZ=3 -> FB REXR=1 value=0x1 FB REG=2 value=0x2
|
|
working rule:
|
|
OUTREG=Ar11() -> FB REXR=1 value=0x1 FB REG=3 value=0x3
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R11W EASZ=1 -> FB REXR=1 value=0x1 FB REG=3 value=0x3
|
|
new rule OUTREG=XED_REG_R11D EASZ=2 -> FB REXR=1 value=0x1 FB REG=3 value=0x3
|
|
new rule OUTREG=XED_REG_R11 EASZ=3 -> FB REXR=1 value=0x1 FB REG=3 value=0x3
|
|
working rule:
|
|
OUTREG=Ar12() -> FB REXR=1 value=0x1 FB REG=4 value=0x4
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R12W EASZ=1 -> FB REXR=1 value=0x1 FB REG=4 value=0x4
|
|
new rule OUTREG=XED_REG_R12D EASZ=2 -> FB REXR=1 value=0x1 FB REG=4 value=0x4
|
|
new rule OUTREG=XED_REG_R12 EASZ=3 -> FB REXR=1 value=0x1 FB REG=4 value=0x4
|
|
working rule:
|
|
OUTREG=Ar13() -> FB REXR=1 value=0x1 FB REG=5 value=0x5
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R13W EASZ=1 -> FB REXR=1 value=0x1 FB REG=5 value=0x5
|
|
new rule OUTREG=XED_REG_R13D EASZ=2 -> FB REXR=1 value=0x1 FB REG=5 value=0x5
|
|
new rule OUTREG=XED_REG_R13 EASZ=3 -> FB REXR=1 value=0x1 FB REG=5 value=0x5
|
|
working rule:
|
|
OUTREG=Ar14() -> FB REXR=1 value=0x1 FB REG=6 value=0x6
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R14W EASZ=1 -> FB REXR=1 value=0x1 FB REG=6 value=0x6
|
|
new rule OUTREG=XED_REG_R14D EASZ=2 -> FB REXR=1 value=0x1 FB REG=6 value=0x6
|
|
new rule OUTREG=XED_REG_R14 EASZ=3 -> FB REXR=1 value=0x1 FB REG=6 value=0x6
|
|
working rule:
|
|
OUTREG=Ar15() -> FB REXR=1 value=0x1 FB REG=7 value=0x7
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R15W EASZ=1 -> FB REXR=1 value=0x1 FB REG=7 value=0x7
|
|
new rule OUTREG=XED_REG_R15D EASZ=2 -> FB REXR=1 value=0x1 FB REG=7 value=0x7
|
|
new rule OUTREG=XED_REG_R15 EASZ=3 -> FB REXR=1 value=0x1 FB REG=7 value=0x7
|
|
nt: A_GPR_B
|
|
working rule:
|
|
OUTREG=ArAX() -> FB REXB=0 value=0x0 FB RM=0 value=0x0
|
|
inlining rule: ArAX()::
|
|
OUTREG=XED_REG_AX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EAX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RAX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_AX EASZ=1 -> FB REXB=0 value=0x0 FB RM=0 value=0x0
|
|
new rule OUTREG=XED_REG_EAX EASZ=2 -> FB REXB=0 value=0x0 FB RM=0 value=0x0
|
|
new rule OUTREG=XED_REG_RAX EASZ=3 -> FB REXB=0 value=0x0 FB RM=0 value=0x0
|
|
working rule:
|
|
OUTREG=ArCX() -> FB REXB=0 value=0x0 FB RM=1 value=0x1
|
|
inlining rule: ArCX()::
|
|
OUTREG=XED_REG_CX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ECX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RCX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_CX EASZ=1 -> FB REXB=0 value=0x0 FB RM=1 value=0x1
|
|
new rule OUTREG=XED_REG_ECX EASZ=2 -> FB REXB=0 value=0x0 FB RM=1 value=0x1
|
|
new rule OUTREG=XED_REG_RCX EASZ=3 -> FB REXB=0 value=0x0 FB RM=1 value=0x1
|
|
working rule:
|
|
OUTREG=ArDX() -> FB REXB=0 value=0x0 FB RM=2 value=0x2
|
|
inlining rule: ArDX()::
|
|
OUTREG=XED_REG_DX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_DX EASZ=1 -> FB REXB=0 value=0x0 FB RM=2 value=0x2
|
|
new rule OUTREG=XED_REG_EDX EASZ=2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2
|
|
new rule OUTREG=XED_REG_RDX EASZ=3 -> FB REXB=0 value=0x0 FB RM=2 value=0x2
|
|
working rule:
|
|
OUTREG=ArBX() -> FB REXB=0 value=0x0 FB RM=3 value=0x3
|
|
inlining rule: ArBX()::
|
|
OUTREG=XED_REG_BX EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBX EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBX EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_BX EASZ=1 -> FB REXB=0 value=0x0 FB RM=3 value=0x3
|
|
new rule OUTREG=XED_REG_EBX EASZ=2 -> FB REXB=0 value=0x0 FB RM=3 value=0x3
|
|
new rule OUTREG=XED_REG_RBX EASZ=3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3
|
|
working rule:
|
|
OUTREG=ArSP() -> FB REXB=0 value=0x0 FB RM=4 value=0x4
|
|
inlining rule: ArSP()::
|
|
OUTREG=XED_REG_SP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSP EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_SP EASZ=1 -> FB REXB=0 value=0x0 FB RM=4 value=0x4
|
|
new rule OUTREG=XED_REG_ESP EASZ=2 -> FB REXB=0 value=0x0 FB RM=4 value=0x4
|
|
new rule OUTREG=XED_REG_RSP EASZ=3 -> FB REXB=0 value=0x0 FB RM=4 value=0x4
|
|
working rule:
|
|
OUTREG=ArBP() -> FB REXB=0 value=0x0 FB RM=5 value=0x5
|
|
inlining rule: ArBP()::
|
|
OUTREG=XED_REG_BP EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EBP EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RBP EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_BP EASZ=1 -> FB REXB=0 value=0x0 FB RM=5 value=0x5
|
|
new rule OUTREG=XED_REG_EBP EASZ=2 -> FB REXB=0 value=0x0 FB RM=5 value=0x5
|
|
new rule OUTREG=XED_REG_RBP EASZ=3 -> FB REXB=0 value=0x0 FB RM=5 value=0x5
|
|
working rule:
|
|
OUTREG=ArSI() -> FB REXB=0 value=0x0 FB RM=6 value=0x6
|
|
inlining rule: ArSI()::
|
|
OUTREG=XED_REG_SI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_ESI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RSI EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_SI EASZ=1 -> FB REXB=0 value=0x0 FB RM=6 value=0x6
|
|
new rule OUTREG=XED_REG_ESI EASZ=2 -> FB REXB=0 value=0x0 FB RM=6 value=0x6
|
|
new rule OUTREG=XED_REG_RSI EASZ=3 -> FB REXB=0 value=0x0 FB RM=6 value=0x6
|
|
working rule:
|
|
OUTREG=ArDI() -> FB REXB=0 value=0x0 FB RM=7 value=0x7
|
|
inlining rule: ArDI()::
|
|
OUTREG=XED_REG_DI EASZ=1 -> nothing
|
|
OUTREG=XED_REG_EDI EASZ=2 -> nothing
|
|
OUTREG=XED_REG_RDI EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_DI EASZ=1 -> FB REXB=0 value=0x0 FB RM=7 value=0x7
|
|
new rule OUTREG=XED_REG_EDI EASZ=2 -> FB REXB=0 value=0x0 FB RM=7 value=0x7
|
|
new rule OUTREG=XED_REG_RDI EASZ=3 -> FB REXB=0 value=0x0 FB RM=7 value=0x7
|
|
working rule:
|
|
OUTREG=Ar8() -> FB REXB=1 value=0x1 FB RM=0 value=0x0
|
|
inlining rule: Ar8()::
|
|
OUTREG=XED_REG_R8W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R8D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R8 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R8W EASZ=1 -> FB REXB=1 value=0x1 FB RM=0 value=0x0
|
|
new rule OUTREG=XED_REG_R8D EASZ=2 -> FB REXB=1 value=0x1 FB RM=0 value=0x0
|
|
new rule OUTREG=XED_REG_R8 EASZ=3 -> FB REXB=1 value=0x1 FB RM=0 value=0x0
|
|
working rule:
|
|
OUTREG=Ar9() -> FB REXB=1 value=0x1 FB RM=1 value=0x1
|
|
inlining rule: Ar9()::
|
|
OUTREG=XED_REG_R9W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R9D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R9 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R9W EASZ=1 -> FB REXB=1 value=0x1 FB RM=1 value=0x1
|
|
new rule OUTREG=XED_REG_R9D EASZ=2 -> FB REXB=1 value=0x1 FB RM=1 value=0x1
|
|
new rule OUTREG=XED_REG_R9 EASZ=3 -> FB REXB=1 value=0x1 FB RM=1 value=0x1
|
|
working rule:
|
|
OUTREG=Ar10() -> FB REXB=1 value=0x1 FB RM=2 value=0x2
|
|
inlining rule: Ar10()::
|
|
OUTREG=XED_REG_R10W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R10D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R10 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R10W EASZ=1 -> FB REXB=1 value=0x1 FB RM=2 value=0x2
|
|
new rule OUTREG=XED_REG_R10D EASZ=2 -> FB REXB=1 value=0x1 FB RM=2 value=0x2
|
|
new rule OUTREG=XED_REG_R10 EASZ=3 -> FB REXB=1 value=0x1 FB RM=2 value=0x2
|
|
working rule:
|
|
OUTREG=Ar11() -> FB REXB=1 value=0x1 FB RM=3 value=0x3
|
|
inlining rule: Ar11()::
|
|
OUTREG=XED_REG_R11W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R11D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R11 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R11W EASZ=1 -> FB REXB=1 value=0x1 FB RM=3 value=0x3
|
|
new rule OUTREG=XED_REG_R11D EASZ=2 -> FB REXB=1 value=0x1 FB RM=3 value=0x3
|
|
new rule OUTREG=XED_REG_R11 EASZ=3 -> FB REXB=1 value=0x1 FB RM=3 value=0x3
|
|
working rule:
|
|
OUTREG=Ar12() -> FB REXB=1 value=0x1 FB RM=4 value=0x4
|
|
inlining rule: Ar12()::
|
|
OUTREG=XED_REG_R12W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R12D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R12 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R12W EASZ=1 -> FB REXB=1 value=0x1 FB RM=4 value=0x4
|
|
new rule OUTREG=XED_REG_R12D EASZ=2 -> FB REXB=1 value=0x1 FB RM=4 value=0x4
|
|
new rule OUTREG=XED_REG_R12 EASZ=3 -> FB REXB=1 value=0x1 FB RM=4 value=0x4
|
|
working rule:
|
|
OUTREG=Ar13() -> FB REXB=1 value=0x1 FB RM=5 value=0x5
|
|
inlining rule: Ar13()::
|
|
OUTREG=XED_REG_R13W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R13D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R13 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R13W EASZ=1 -> FB REXB=1 value=0x1 FB RM=5 value=0x5
|
|
new rule OUTREG=XED_REG_R13D EASZ=2 -> FB REXB=1 value=0x1 FB RM=5 value=0x5
|
|
new rule OUTREG=XED_REG_R13 EASZ=3 -> FB REXB=1 value=0x1 FB RM=5 value=0x5
|
|
working rule:
|
|
OUTREG=Ar14() -> FB REXB=1 value=0x1 FB RM=6 value=0x6
|
|
inlining rule: Ar14()::
|
|
OUTREG=XED_REG_R14W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R14D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R14 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R14W EASZ=1 -> FB REXB=1 value=0x1 FB RM=6 value=0x6
|
|
new rule OUTREG=XED_REG_R14D EASZ=2 -> FB REXB=1 value=0x1 FB RM=6 value=0x6
|
|
new rule OUTREG=XED_REG_R14 EASZ=3 -> FB REXB=1 value=0x1 FB RM=6 value=0x6
|
|
working rule:
|
|
OUTREG=Ar15() -> FB REXB=1 value=0x1 FB RM=7 value=0x7
|
|
inlining rule: Ar15()::
|
|
OUTREG=XED_REG_R15W EASZ=1 -> nothing
|
|
OUTREG=XED_REG_R15D EASZ=2 -> nothing
|
|
OUTREG=XED_REG_R15 EASZ=3 -> nothing
|
|
|
|
new rule OUTREG=XED_REG_R15W EASZ=1 -> FB REXB=1 value=0x1 FB RM=7 value=0x7
|
|
new rule OUTREG=XED_REG_R15D EASZ=2 -> FB REXB=1 value=0x1 FB RM=7 value=0x7
|
|
new rule OUTREG=XED_REG_R15 EASZ=3 -> FB REXB=1 value=0x1 FB RM=7 value=0x7
|
|
nt: XMM_SE
|
|
nt: XMM_SE64
|
|
nt: XMM_SE32
|
|
nt: YMM_SE
|
|
nt: YMM_SE64
|
|
nt: YMM_SE32
|
|
nt: XMM_N
|
|
nt: XMM_N_32
|
|
nt: XMM_N_64
|
|
nt: YMM_N
|
|
nt: YMM_N_32
|
|
nt: YMM_N_64
|
|
nt: YMM_R
|
|
nt: YMM_R_32
|
|
nt: YMM_R_64
|
|
nt: YMM_B
|
|
nt: YMM_B_32
|
|
nt: YMM_B_64
|
|
nt: VGPRy_R
|
|
nt: VGPRy_B
|
|
nt: VGPRy_N
|
|
nt: VGPR32_N
|
|
nt: VGPR32_B
|
|
nt: VGPR32_R
|
|
nt: VGPR32_N_32
|
|
nt: VGPR32_N_64
|
|
nt: VGPR64_N
|
|
nt: VGPR32_R_32
|
|
nt: VGPR32_R_64
|
|
nt: VGPR64_R
|
|
nt: VGPR32_B_32
|
|
nt: VGPR32_B_64
|
|
nt: VGPR64_B
|
|
nt: MASK1
|
|
nt: MASKNOT0
|
|
nt: MASK_R
|
|
nt: MASK_B
|
|
nt: MASK_N
|
|
nt: MASK_N64
|
|
nt: MASK_N32
|
|
nt: XMM_R3
|
|
nt: XMM_R3_32
|
|
nt: XMM_R3_64
|
|
nt: YMM_R3
|
|
nt: YMM_R3_32
|
|
nt: YMM_R3_64
|
|
nt: ZMM_R3
|
|
nt: ZMM_R3_32
|
|
nt: ZMM_R3_64
|
|
nt: XMM_B3
|
|
nt: XMM_B3_32
|
|
nt: XMM_B3_64
|
|
nt: YMM_B3
|
|
nt: YMM_B3_32
|
|
nt: YMM_B3_64
|
|
nt: ZMM_B3
|
|
nt: ZMM_B3_32
|
|
nt: ZMM_B3_64
|
|
nt: XMM_N3
|
|
nt: XMM_N3_32
|
|
nt: XMM_N3_64
|
|
nt: YMM_N3
|
|
nt: YMM_N3_32
|
|
nt: YMM_N3_64
|
|
nt: ZMM_N3
|
|
nt: ZMM_N3_32
|
|
nt: ZMM_N3_64
|
|
nt: TMM_R
|
|
nt: TMM_B
|
|
nt: TMM_N
|