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439 lines
12 KiB
439 lines
12 KiB
#pragma once
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#include <unicorn/unicorn.h>
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#include <vmutils.hpp>
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#define VIRTUAL_REGISTER_COUNT 24
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#define VIRTUAL_SEH_REGISTER 24
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namespace vm::instrs {
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/// <summary>
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/// mnemonic representation of supported virtual instructions...
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/// </summary>
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enum class mnemonic_t {
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unknown,
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sreg,
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lreg,
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lconst,
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add,
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div,
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idiv,
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mul,
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imul,
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nand,
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nor,
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read,
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write,
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shl,
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shld,
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shr,
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shrd,
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lvsp,
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svsp,
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writecr3,
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readcr3,
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writecr8,
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readcr8,
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cpuid,
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rdtsc,
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call,
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jmp,
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vmexit
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};
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/// <summary>
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/// the main virtual instruction structure which is returned by profilers...
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/// </summary>
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struct vinstr_t {
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/// <summary>
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/// mnemonic of the virtual instruction...
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/// </summary>
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mnemonic_t mnemonic;
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/// <summary>
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/// size varient of the virtual instruction... I.E SREGQ would have a value of
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/// "64" here...where the SREGDW varient would have a "32" here... this is the
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/// stack disposition essentially, or the value on the stack...
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/// </summary>
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u8 stack_size;
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struct {
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/// <summary>
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/// true if the virtual instruction has an imm false if not...
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/// </summary>
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bool has_imm;
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/// <summary>
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/// size in bits of the imm... 8, 16, 32, 64...
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/// </summary>
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u8 size;
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/// <summary>
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/// imm value...
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/// </summary>
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u64 val;
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} imm;
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};
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/// <summary>
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/// virtual branch type...
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/// </summary>
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enum class vbranch_type {
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/// <summary>
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/// vmexit
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/// </summary>
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none,
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/// <summary>
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/// virtual jcc
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/// </summary>
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jcc,
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/// <summary>
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/// absolute jmp...
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/// </summary>
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absolute,
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/// <summary>
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/// jmp table, either indirect or direct...
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/// </summary>
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table
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};
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/// <summary>
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/// virtual code block
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/// </summary>
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struct vblk_t {
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/// <summary>
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/// start address VIP of this basic block...
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/// </summary>
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struct {
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/// <summary>
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/// relative virtual address...
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/// </summary>
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std::uint32_t rva;
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/// <summary>
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/// image based relative virtual address...
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/// </summary>
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std::uintptr_t img_base;
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} m_vip;
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/// <summary>
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/// virtual instruction pointer and virtual stack pointer used for this basic
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/// block...
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/// </summary>
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struct {
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zydis_reg_t vip;
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zydis_reg_t vsp;
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} m_vm;
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struct {
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/// <summary>
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/// unicorn-engine cpu context of the first instruction of the jmp
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/// handler...
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/// </summary>
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uc_context* ctx;
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/// <summary>
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/// unicorn-engine stack of the first instruction of the jmp handler...
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/// </summary>
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std::uint8_t* stack;
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struct {
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zydis_reg_t vip;
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zydis_reg_t vsp;
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} m_vm;
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} m_jmp;
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/// <summary>
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/// vector of virtual instructions for this basic block...
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/// </summary>
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std::vector<vm::instrs::vinstr_t> m_vinstrs;
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/// <summary>
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/// virtual branch type...
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/// </summary>
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vbranch_type branch_type;
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/// <summary>
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/// vector of virtual instruction pointers. one for each branch...
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/// </summary>
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std::vector<std::uintptr_t> branches;
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};
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/// <summary>
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/// virtual routine structure
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/// </summary>
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struct vrtn_t {
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/// <summary>
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/// relative virtual address to the first instruction of the vm enter...
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/// </summary>
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std::uint32_t m_rva;
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/// <summary>
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/// vector of virtual code blocks... these virtual code blocks contain virtual
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/// instructions...
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/// </summary>
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std::vector<vblk_t> m_blks;
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};
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/// <summary>
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/// emu instruction containing current cpu register values and such...
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/// </summary>
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struct emu_instr_t {
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/// <summary>
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/// decoded instruction...
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/// </summary>
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zydis_decoded_instr_t m_instr;
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/// <summary>
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/// cpu context before execution of this instruction...
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/// </summary>
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uc_context* m_cpu;
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};
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/// <summary>
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/// handler trace containing information about a stream of instructions... also
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/// contains some information about the virtual machine such as vip and vsp...
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/// </summary>
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struct hndlr_trace_t {
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/// <summary>
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/// pointer to the unicorn-engine... used by profilers...
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/// </summary>
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uc_engine* m_uc;
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/// <summary>
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/// copy of the stack at the very first instruction of the virtual machine
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/// handler...
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/// </summary>
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std::uint8_t* m_stack;
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/// <summary>
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/// native register used for virtual instruction pointer...
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/// </summary>
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zydis_reg_t m_vip;
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/// <summary>
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/// native register used for the virtual stack pointer...
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/// </summary>
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zydis_reg_t m_vsp;
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/// <summary>
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/// vector of emulated, diassembled instructions...
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/// </summary>
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std::vector<emu_instr_t> m_instrs;
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};
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/// <summary>
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/// matcher function which returns true if an instruction matches a desired
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/// one...
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/// </summary>
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using matcher_t = std::function<bool(const zydis_reg_t vip,
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const zydis_reg_t vsp,
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const zydis_decoded_instr_t& instr)>;
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/// <summary>
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/// virtual instruction structure generator... this can update the vip and vsp
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/// argument... it cannot update the instruction stream (hndlr)...
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/// </summary>
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using vinstr_gen_t =
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std::function<std::optional<vinstr_t>(zydis_reg_t& vip,
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zydis_reg_t& vsp,
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hndlr_trace_t& hndlr)>;
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/// <summary>
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/// each virtual instruction has its own profiler_t structure which can generate
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/// all varients of the virtual instruction for each size...
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/// </summary>
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struct profiler_t {
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/// <summary>
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/// string name of the virtual instruction that this profile generates for...
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/// </summary>
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std::string name;
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/// <summary>
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/// mnemonic representation of the virtual instruction...
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/// </summary>
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mnemonic_t mnemonic;
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/// <summary>
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/// vector of matcher lambda's which return true if a given instruction
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/// matches...
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/// </summary>
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std::vector<matcher_t> matchers;
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/// <summary>
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/// generates a virtual instruction structure...
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/// </summary>
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vinstr_gen_t generate;
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};
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/// <summary>
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/// list of all profiles here...
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/// </summary>
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extern profiler_t jmp;
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extern profiler_t sreg;
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extern profiler_t lreg;
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extern profiler_t lconst;
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extern profiler_t add;
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extern profiler_t lvsp;
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extern profiler_t svsp;
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extern profiler_t nand;
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extern profiler_t nor;
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extern profiler_t read;
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extern profiler_t write;
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extern profiler_t imul;
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extern profiler_t shr;
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extern profiler_t vmexit;
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/// <summary>
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/// unsorted vector of profiles... they get sorted once at runtime...
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/// </summary>
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inline std::vector<profiler_t*> profiles = {
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&vmexit, &shr, &imul, &nor, &write, &svsp, &read,
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&nand, &lvsp, &add, &jmp, &sreg, &lreg, &lconst};
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/// <summary>
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/// no i did not make this by hand, you cannot clown upon me!
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/// </summary>
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inline std::map<zydis_reg_t, uc_x86_reg> reg_map = {
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{ZYDIS_REGISTER_AL, UC_X86_REG_AL},
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{ZYDIS_REGISTER_CL, UC_X86_REG_CL},
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{ZYDIS_REGISTER_DL, UC_X86_REG_DL},
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{ZYDIS_REGISTER_BL, UC_X86_REG_BL},
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{ZYDIS_REGISTER_AH, UC_X86_REG_AH},
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{ZYDIS_REGISTER_CH, UC_X86_REG_CH},
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{ZYDIS_REGISTER_DH, UC_X86_REG_DH},
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{ZYDIS_REGISTER_BH, UC_X86_REG_BH},
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{ZYDIS_REGISTER_SPL, UC_X86_REG_SPL},
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{ZYDIS_REGISTER_BPL, UC_X86_REG_BPL},
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{ZYDIS_REGISTER_SIL, UC_X86_REG_SIL},
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{ZYDIS_REGISTER_DIL, UC_X86_REG_DIL},
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{ZYDIS_REGISTER_R8B, UC_X86_REG_R8B},
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{ZYDIS_REGISTER_R9B, UC_X86_REG_R9B},
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{ZYDIS_REGISTER_R10B, UC_X86_REG_R10B},
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{ZYDIS_REGISTER_R11B, UC_X86_REG_R11B},
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{ZYDIS_REGISTER_R12B, UC_X86_REG_R12B},
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{ZYDIS_REGISTER_R13B, UC_X86_REG_R13B},
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{ZYDIS_REGISTER_R14B, UC_X86_REG_R14B},
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{ZYDIS_REGISTER_R15B, UC_X86_REG_R15B},
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{ZYDIS_REGISTER_AX, UC_X86_REG_AX},
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{ZYDIS_REGISTER_CX, UC_X86_REG_CX},
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{ZYDIS_REGISTER_DX, UC_X86_REG_DX},
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{ZYDIS_REGISTER_BX, UC_X86_REG_BX},
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{ZYDIS_REGISTER_SP, UC_X86_REG_SP},
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{ZYDIS_REGISTER_BP, UC_X86_REG_BP},
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{ZYDIS_REGISTER_SI, UC_X86_REG_SI},
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{ZYDIS_REGISTER_DI, UC_X86_REG_DI},
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{ZYDIS_REGISTER_R8W, UC_X86_REG_R8W},
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{ZYDIS_REGISTER_R9W, UC_X86_REG_R9W},
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{ZYDIS_REGISTER_R10W, UC_X86_REG_R10W},
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{ZYDIS_REGISTER_R11W, UC_X86_REG_R11W},
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{ZYDIS_REGISTER_R12W, UC_X86_REG_R12W},
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{ZYDIS_REGISTER_R13W, UC_X86_REG_R13W},
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{ZYDIS_REGISTER_R14W, UC_X86_REG_R14W},
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{ZYDIS_REGISTER_R15W, UC_X86_REG_R15W},
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{ZYDIS_REGISTER_EAX, UC_X86_REG_EAX},
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{ZYDIS_REGISTER_ECX, UC_X86_REG_ECX},
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{ZYDIS_REGISTER_EDX, UC_X86_REG_EDX},
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{ZYDIS_REGISTER_EBX, UC_X86_REG_EBX},
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{ZYDIS_REGISTER_ESP, UC_X86_REG_ESP},
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{ZYDIS_REGISTER_EBP, UC_X86_REG_EBP},
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{ZYDIS_REGISTER_ESI, UC_X86_REG_ESI},
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{ZYDIS_REGISTER_EDI, UC_X86_REG_EDI},
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{ZYDIS_REGISTER_R8D, UC_X86_REG_R8D},
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{ZYDIS_REGISTER_R9D, UC_X86_REG_R9D},
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{ZYDIS_REGISTER_R10D, UC_X86_REG_R10D},
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{ZYDIS_REGISTER_R11D, UC_X86_REG_R11D},
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{ZYDIS_REGISTER_R12D, UC_X86_REG_R12D},
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{ZYDIS_REGISTER_R13D, UC_X86_REG_R13D},
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{ZYDIS_REGISTER_R14D, UC_X86_REG_R14D},
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{ZYDIS_REGISTER_R15D, UC_X86_REG_R15D},
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{ZYDIS_REGISTER_RAX, UC_X86_REG_RAX},
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{ZYDIS_REGISTER_RCX, UC_X86_REG_RCX},
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{ZYDIS_REGISTER_RDX, UC_X86_REG_RDX},
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{ZYDIS_REGISTER_RBX, UC_X86_REG_RBX},
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{ZYDIS_REGISTER_RSP, UC_X86_REG_RSP},
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{ZYDIS_REGISTER_RBP, UC_X86_REG_RBP},
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{ZYDIS_REGISTER_RSI, UC_X86_REG_RSI},
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{ZYDIS_REGISTER_RDI, UC_X86_REG_RDI},
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{ZYDIS_REGISTER_R8, UC_X86_REG_R8},
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{ZYDIS_REGISTER_R9, UC_X86_REG_R9},
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{ZYDIS_REGISTER_R10, UC_X86_REG_R10},
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{ZYDIS_REGISTER_R11, UC_X86_REG_R11},
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{ZYDIS_REGISTER_R12, UC_X86_REG_R12},
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{ZYDIS_REGISTER_R13, UC_X86_REG_R13},
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{ZYDIS_REGISTER_R14, UC_X86_REG_R14},
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{ZYDIS_REGISTER_R15, UC_X86_REG_R15}};
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/// <summary>
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/// deadstore and opaque branch removal from unicorn engine trace... this is the
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/// same algorithm as the one in vm::utils::deobfuscate...
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/// </summary>
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/// <param name="trace"></param>
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void deobfuscate(hndlr_trace_t& trace);
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/// <summary>
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/// sorts the profiles by descending order of matchers... this will prevent a
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/// smaller profiler with less matchers from being used when it should not be...
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///
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/// this function can be called multiple times...
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/// </summary>
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void init();
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/// <summary>
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/// determines the virtual instruction for the vm handler given vsp and vip...
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/// </summary>
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/// <param name="vip">vip native register...</param>
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/// <param name="vsp">vsp native register...</param>
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/// <param name="hndlr"></param>
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/// <returns>returns vinstr_t structure...</returns>
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vinstr_t determine(hndlr_trace_t& hndlr);
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/// <summary>
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/// get profile from mnemonic...
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/// </summary>
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/// <param name="mnemonic">mnemonic of the profile to get...</param>
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/// <returns>pointer to the profile...</returns>
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profiler_t* get_profile(mnemonic_t mnemonic);
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} // namespace vm::instrs
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// MOV REG, [VIP]
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#define IMM_FETCH \
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[&](const zydis_reg_t vip, const zydis_reg_t vsp, \
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const zydis_decoded_instr_t& instr) -> bool { \
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return vm::utils::is_mov(instr) && \
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instr.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER && \
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instr.operands[1].type == ZYDIS_OPERAND_TYPE_MEMORY && \
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instr.operands[1].mem.base == vip; \
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}
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// MOV [VSP], REG
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#define STR_VALUE \
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[&](const zydis_reg_t vip, const zydis_reg_t vsp, \
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const zydis_decoded_instr_t& instr) -> bool { \
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return instr.mnemonic == ZYDIS_MNEMONIC_MOV && \
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instr.operands[0].type == ZYDIS_OPERAND_TYPE_MEMORY && \
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instr.operands[0].mem.base == vsp && \
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instr.operands[1].type == ZYDIS_OPERAND_TYPE_REGISTER; \
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}
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// MOV REG, [VSP]
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#define LOAD_VALUE \
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[&](const zydis_reg_t vip, const zydis_reg_t vsp, \
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const zydis_decoded_instr_t& instr) -> bool { \
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return instr.mnemonic == ZYDIS_MNEMONIC_MOV && \
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instr.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER && \
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instr.operands[1].type == ZYDIS_OPERAND_TYPE_MEMORY && \
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instr.operands[1].mem.base == vsp; \
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}
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// SUB VSP, OFFSET
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#define SUB_VSP \
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[&](const zydis_reg_t vip, const zydis_reg_t vsp, \
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const zydis_decoded_instr_t& instr) -> bool { \
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return instr.mnemonic == ZYDIS_MNEMONIC_SUB && \
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instr.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER && \
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instr.operands[0].reg.value == vsp && \
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instr.operands[1].type == ZYDIS_OPERAND_TYPE_IMMEDIATE; \
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} |