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149 lines
4.0 KiB
149 lines
4.0 KiB
#ifndef CAPSTONE_MOS65XX_H
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#define CAPSTONE_MOS65XX_H
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/* Capstone Disassembly Engine */
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/* By Sebastian Macke <sebastian@macke.de, 2018 */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "platform.h"
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/// MOS65XX registers and special registers
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typedef enum mos65xx_reg {
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MOS65XX_REG_INVALID = 0,
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MOS65XX_REG_ACC, ///< accumulator
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MOS65XX_REG_X, ///< X index register
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MOS65XX_REG_Y, ///< Y index register
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MOS65XX_REG_P, ///< status register
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MOS65XX_REG_SP, ///< stack pointer register
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MOS65XX_REG_ENDING, // <-- mark the end of the list of registers
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} mos65xx_reg;
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/// MOS65XX Addressing Modes
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typedef enum mos65xx_address_mode {
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MOS65XX_AM_NONE = 0, ///< No address mode.
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MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)
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MOS65XX_AM_ACC, ///< accumulator addressing
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MOS65XX_AM_ABS, ///< absolute addressing
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MOS65XX_AM_ZP, ///< zeropage addressing
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MOS65XX_AM_IMM, ///< 8 Bit immediate value
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MOS65XX_AM_ABSX, ///< indexed absolute addressing by the X index register
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MOS65XX_AM_ABSY, ///< indexed absolute addressing by the Y index register
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MOS65XX_AM_INDX, ///< indexed indirect addressing by the X index register
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MOS65XX_AM_INDY, ///< indirect indexed addressing by the Y index register
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MOS65XX_AM_ZPX, ///< indexed zeropage addressing by the X index register
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MOS65XX_AM_ZPY, ///< indexed zeropage addressing by the Y index register
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MOS65XX_AM_REL, ///< relative addressing used by branches
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MOS65XX_AM_IND, ///< absolute indirect addressing
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} mos65xx_address_mode;
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/// MOS65XX instruction
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typedef enum mos65xx_insn {
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MOS65XX_INS_INVALID = 0,
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MOS65XX_INS_ADC,
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MOS65XX_INS_AND,
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MOS65XX_INS_ASL,
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MOS65XX_INS_BCC,
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MOS65XX_INS_BCS,
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MOS65XX_INS_BEQ,
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MOS65XX_INS_BIT,
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MOS65XX_INS_BMI,
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MOS65XX_INS_BNE,
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MOS65XX_INS_BPL,
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MOS65XX_INS_BRK,
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MOS65XX_INS_BVC,
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MOS65XX_INS_BVS,
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MOS65XX_INS_CLC,
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MOS65XX_INS_CLD,
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MOS65XX_INS_CLI,
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MOS65XX_INS_CLV,
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MOS65XX_INS_CMP,
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MOS65XX_INS_CPX,
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MOS65XX_INS_CPY,
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MOS65XX_INS_DEC,
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MOS65XX_INS_DEX,
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MOS65XX_INS_DEY,
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MOS65XX_INS_EOR,
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MOS65XX_INS_INC,
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MOS65XX_INS_INX,
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MOS65XX_INS_INY,
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MOS65XX_INS_JMP,
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MOS65XX_INS_JSR,
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MOS65XX_INS_LDA,
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MOS65XX_INS_LDX,
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MOS65XX_INS_LDY,
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MOS65XX_INS_LSR,
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MOS65XX_INS_NOP,
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MOS65XX_INS_ORA,
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MOS65XX_INS_PHA,
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MOS65XX_INS_PLA,
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MOS65XX_INS_PHP,
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MOS65XX_INS_PLP,
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MOS65XX_INS_ROL,
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MOS65XX_INS_ROR,
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MOS65XX_INS_RTI,
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MOS65XX_INS_RTS,
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MOS65XX_INS_SBC,
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MOS65XX_INS_SEC,
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MOS65XX_INS_SED,
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MOS65XX_INS_SEI,
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MOS65XX_INS_STA,
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MOS65XX_INS_STX,
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MOS65XX_INS_STY,
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MOS65XX_INS_TAX,
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MOS65XX_INS_TAY,
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MOS65XX_INS_TSX,
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MOS65XX_INS_TXA,
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MOS65XX_INS_TXS,
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MOS65XX_INS_TYA,
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MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions
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} mos65xx_insn;
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/// Group of MOS65XX instructions
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typedef enum mos65xx_group_type {
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MOS65XX_GRP_INVALID = 0, ///< CS_GRP_INVALID
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MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP
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MOS65XX_GRP_CALL, ///< = CS_GRP_RET
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MOS65XX_GRP_RET, ///< = CS_GRP_RET
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MOS65XX_GRP_IRET = 5, ///< = CS_GRP_IRET
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MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE
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MOS65XX_GRP_ENDING,// <-- mark the end of the list of groups
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} mos65xx_group_type;
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/// Operand type for instruction's operands
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typedef enum mos65xx_op_type {
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MOS65XX_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
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MOS65XX_OP_REG, ///< = CS_OP_REG (Register operand).
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MOS65XX_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
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MOS65XX_OP_MEM, ///< = CS_OP_MEM (Memory operand).
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} mos65xx_op_type;
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/// Instruction operand
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typedef struct cs_mos65xx_op {
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mos65xx_op_type type; ///< operand type
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union {
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mos65xx_reg reg; ///< register value for REG operand
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uint8_t imm; ///< immediate value for IMM operand
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uint16_t mem; ///< base/index/scale/disp value for MEM operand
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};
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} cs_mos65xx_op;
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/// The MOS65XX address mode and it's operands
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typedef struct cs_mos65xx {
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mos65xx_address_mode am;
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bool modifies_flags;
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/// Number of operands of this instruction,
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/// or 0 when instruction has no operand.
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uint8_t op_count;
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cs_mos65xx_op operands[3]; ///< operands for this instruction.
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} cs_mos65xx;
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#ifdef __cplusplus
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}
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#endif
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#endif //CAPSTONE_MOS65XX_H
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