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360 lines
8.1 KiB
360 lines
8.1 KiB
/* Capstone Disassembly Engine */
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/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
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#ifndef CAPSTONE_TMS320C64X_H
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#define CAPSTONE_TMS320C64X_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include "platform.h"
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#ifdef _MSC_VER
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#pragma warning(disable:4201)
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#endif
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typedef enum tms320c64x_op_type {
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TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
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TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand).
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TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
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TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand).
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TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops
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} tms320c64x_op_type;
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typedef enum tms320c64x_mem_disp {
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TMS320C64X_MEM_DISP_INVALID = 0,
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TMS320C64X_MEM_DISP_CONSTANT,
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TMS320C64X_MEM_DISP_REGISTER,
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} tms320c64x_mem_disp;
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typedef enum tms320c64x_mem_dir {
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TMS320C64X_MEM_DIR_INVALID = 0,
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TMS320C64X_MEM_DIR_FW,
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TMS320C64X_MEM_DIR_BW,
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} tms320c64x_mem_dir;
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typedef enum tms320c64x_mem_mod {
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TMS320C64X_MEM_MOD_INVALID = 0,
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TMS320C64X_MEM_MOD_NO,
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TMS320C64X_MEM_MOD_PRE,
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TMS320C64X_MEM_MOD_POST,
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} tms320c64x_mem_mod;
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typedef struct tms320c64x_op_mem {
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unsigned int base; ///< base register
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unsigned int disp; ///< displacement/offset value
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unsigned int unit; ///< unit of base and offset register
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unsigned int scaled; ///< offset scaled
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unsigned int disptype; ///< displacement type
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unsigned int direction; ///< direction
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unsigned int modify; ///< modification
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} tms320c64x_op_mem;
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typedef struct cs_tms320c64x_op {
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tms320c64x_op_type type; ///< operand type
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union {
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unsigned int reg; ///< register value for REG operand or first register for REGPAIR operand
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int32_t imm; ///< immediate value for IMM operand
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tms320c64x_op_mem mem; ///< base/disp value for MEM operand
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};
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} cs_tms320c64x_op;
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typedef struct cs_tms320c64x {
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uint8_t op_count;
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cs_tms320c64x_op operands[8]; ///< operands for this instruction.
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struct {
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unsigned int reg;
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unsigned int zero;
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} condition;
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struct {
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unsigned int unit;
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unsigned int side;
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unsigned int crosspath;
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} funit;
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unsigned int parallel;
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} cs_tms320c64x;
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typedef enum tms320c64x_reg {
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TMS320C64X_REG_INVALID = 0,
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TMS320C64X_REG_AMR,
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TMS320C64X_REG_CSR,
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TMS320C64X_REG_DIER,
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TMS320C64X_REG_DNUM,
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TMS320C64X_REG_ECR,
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TMS320C64X_REG_GFPGFR,
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TMS320C64X_REG_GPLYA,
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TMS320C64X_REG_GPLYB,
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TMS320C64X_REG_ICR,
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TMS320C64X_REG_IER,
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TMS320C64X_REG_IERR,
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TMS320C64X_REG_ILC,
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TMS320C64X_REG_IRP,
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TMS320C64X_REG_ISR,
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TMS320C64X_REG_ISTP,
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TMS320C64X_REG_ITSR,
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TMS320C64X_REG_NRP,
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TMS320C64X_REG_NTSR,
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TMS320C64X_REG_REP,
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TMS320C64X_REG_RILC,
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TMS320C64X_REG_SSR,
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TMS320C64X_REG_TSCH,
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TMS320C64X_REG_TSCL,
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TMS320C64X_REG_TSR,
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TMS320C64X_REG_A0,
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TMS320C64X_REG_A1,
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TMS320C64X_REG_A2,
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TMS320C64X_REG_A3,
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TMS320C64X_REG_A4,
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TMS320C64X_REG_A5,
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TMS320C64X_REG_A6,
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TMS320C64X_REG_A7,
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TMS320C64X_REG_A8,
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TMS320C64X_REG_A9,
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TMS320C64X_REG_A10,
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TMS320C64X_REG_A11,
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TMS320C64X_REG_A12,
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TMS320C64X_REG_A13,
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TMS320C64X_REG_A14,
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TMS320C64X_REG_A15,
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TMS320C64X_REG_A16,
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TMS320C64X_REG_A17,
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TMS320C64X_REG_A18,
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TMS320C64X_REG_A19,
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TMS320C64X_REG_A20,
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TMS320C64X_REG_A21,
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TMS320C64X_REG_A22,
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TMS320C64X_REG_A23,
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TMS320C64X_REG_A24,
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TMS320C64X_REG_A25,
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TMS320C64X_REG_A26,
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TMS320C64X_REG_A27,
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TMS320C64X_REG_A28,
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TMS320C64X_REG_A29,
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TMS320C64X_REG_A30,
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TMS320C64X_REG_A31,
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TMS320C64X_REG_B0,
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TMS320C64X_REG_B1,
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TMS320C64X_REG_B2,
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TMS320C64X_REG_B3,
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TMS320C64X_REG_B4,
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TMS320C64X_REG_B5,
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TMS320C64X_REG_B6,
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TMS320C64X_REG_B7,
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TMS320C64X_REG_B8,
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TMS320C64X_REG_B9,
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TMS320C64X_REG_B10,
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TMS320C64X_REG_B11,
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TMS320C64X_REG_B12,
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TMS320C64X_REG_B13,
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TMS320C64X_REG_B14,
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TMS320C64X_REG_B15,
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TMS320C64X_REG_B16,
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TMS320C64X_REG_B17,
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TMS320C64X_REG_B18,
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TMS320C64X_REG_B19,
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TMS320C64X_REG_B20,
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TMS320C64X_REG_B21,
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TMS320C64X_REG_B22,
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TMS320C64X_REG_B23,
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TMS320C64X_REG_B24,
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TMS320C64X_REG_B25,
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TMS320C64X_REG_B26,
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TMS320C64X_REG_B27,
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TMS320C64X_REG_B28,
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TMS320C64X_REG_B29,
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TMS320C64X_REG_B30,
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TMS320C64X_REG_B31,
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TMS320C64X_REG_PCE1,
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TMS320C64X_REG_ENDING, // <-- mark the end of the list of registers
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// Alias registers
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TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
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TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
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} tms320c64x_reg;
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typedef enum tms320c64x_insn {
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TMS320C64X_INS_INVALID = 0,
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TMS320C64X_INS_ABS,
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TMS320C64X_INS_ABS2,
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TMS320C64X_INS_ADD,
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TMS320C64X_INS_ADD2,
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TMS320C64X_INS_ADD4,
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TMS320C64X_INS_ADDAB,
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TMS320C64X_INS_ADDAD,
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TMS320C64X_INS_ADDAH,
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TMS320C64X_INS_ADDAW,
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TMS320C64X_INS_ADDK,
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TMS320C64X_INS_ADDKPC,
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TMS320C64X_INS_ADDU,
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TMS320C64X_INS_AND,
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TMS320C64X_INS_ANDN,
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TMS320C64X_INS_AVG2,
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TMS320C64X_INS_AVGU4,
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TMS320C64X_INS_B,
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TMS320C64X_INS_BDEC,
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TMS320C64X_INS_BITC4,
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TMS320C64X_INS_BNOP,
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TMS320C64X_INS_BPOS,
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TMS320C64X_INS_CLR,
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TMS320C64X_INS_CMPEQ,
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TMS320C64X_INS_CMPEQ2,
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TMS320C64X_INS_CMPEQ4,
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TMS320C64X_INS_CMPGT,
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TMS320C64X_INS_CMPGT2,
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TMS320C64X_INS_CMPGTU4,
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TMS320C64X_INS_CMPLT,
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TMS320C64X_INS_CMPLTU,
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TMS320C64X_INS_DEAL,
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TMS320C64X_INS_DOTP2,
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TMS320C64X_INS_DOTPN2,
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TMS320C64X_INS_DOTPNRSU2,
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TMS320C64X_INS_DOTPRSU2,
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TMS320C64X_INS_DOTPSU4,
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TMS320C64X_INS_DOTPU4,
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TMS320C64X_INS_EXT,
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TMS320C64X_INS_EXTU,
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TMS320C64X_INS_GMPGTU,
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TMS320C64X_INS_GMPY4,
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TMS320C64X_INS_LDB,
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TMS320C64X_INS_LDBU,
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TMS320C64X_INS_LDDW,
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TMS320C64X_INS_LDH,
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TMS320C64X_INS_LDHU,
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TMS320C64X_INS_LDNDW,
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TMS320C64X_INS_LDNW,
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TMS320C64X_INS_LDW,
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TMS320C64X_INS_LMBD,
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TMS320C64X_INS_MAX2,
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TMS320C64X_INS_MAXU4,
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TMS320C64X_INS_MIN2,
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TMS320C64X_INS_MINU4,
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TMS320C64X_INS_MPY,
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TMS320C64X_INS_MPY2,
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TMS320C64X_INS_MPYH,
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TMS320C64X_INS_MPYHI,
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TMS320C64X_INS_MPYHIR,
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TMS320C64X_INS_MPYHL,
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TMS320C64X_INS_MPYHLU,
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TMS320C64X_INS_MPYHSLU,
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TMS320C64X_INS_MPYHSU,
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TMS320C64X_INS_MPYHU,
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TMS320C64X_INS_MPYHULS,
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TMS320C64X_INS_MPYHUS,
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TMS320C64X_INS_MPYLH,
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TMS320C64X_INS_MPYLHU,
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TMS320C64X_INS_MPYLI,
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TMS320C64X_INS_MPYLIR,
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TMS320C64X_INS_MPYLSHU,
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TMS320C64X_INS_MPYLUHS,
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TMS320C64X_INS_MPYSU,
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TMS320C64X_INS_MPYSU4,
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TMS320C64X_INS_MPYU,
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TMS320C64X_INS_MPYU4,
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TMS320C64X_INS_MPYUS,
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TMS320C64X_INS_MVC,
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TMS320C64X_INS_MVD,
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TMS320C64X_INS_MVK,
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TMS320C64X_INS_MVKL,
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TMS320C64X_INS_MVKLH,
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TMS320C64X_INS_NOP,
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TMS320C64X_INS_NORM,
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TMS320C64X_INS_OR,
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TMS320C64X_INS_PACK2,
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TMS320C64X_INS_PACKH2,
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TMS320C64X_INS_PACKH4,
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TMS320C64X_INS_PACKHL2,
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TMS320C64X_INS_PACKL4,
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TMS320C64X_INS_PACKLH2,
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TMS320C64X_INS_ROTL,
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TMS320C64X_INS_SADD,
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TMS320C64X_INS_SADD2,
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TMS320C64X_INS_SADDU4,
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TMS320C64X_INS_SADDUS2,
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TMS320C64X_INS_SAT,
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TMS320C64X_INS_SET,
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TMS320C64X_INS_SHFL,
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TMS320C64X_INS_SHL,
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TMS320C64X_INS_SHLMB,
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TMS320C64X_INS_SHR,
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TMS320C64X_INS_SHR2,
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TMS320C64X_INS_SHRMB,
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TMS320C64X_INS_SHRU,
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TMS320C64X_INS_SHRU2,
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TMS320C64X_INS_SMPY,
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TMS320C64X_INS_SMPY2,
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TMS320C64X_INS_SMPYH,
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TMS320C64X_INS_SMPYHL,
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TMS320C64X_INS_SMPYLH,
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TMS320C64X_INS_SPACK2,
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TMS320C64X_INS_SPACKU4,
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TMS320C64X_INS_SSHL,
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TMS320C64X_INS_SSHVL,
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TMS320C64X_INS_SSHVR,
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TMS320C64X_INS_SSUB,
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TMS320C64X_INS_STB,
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TMS320C64X_INS_STDW,
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TMS320C64X_INS_STH,
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TMS320C64X_INS_STNDW,
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TMS320C64X_INS_STNW,
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TMS320C64X_INS_STW,
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TMS320C64X_INS_SUB,
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TMS320C64X_INS_SUB2,
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TMS320C64X_INS_SUB4,
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TMS320C64X_INS_SUBAB,
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TMS320C64X_INS_SUBABS4,
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TMS320C64X_INS_SUBAH,
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TMS320C64X_INS_SUBAW,
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TMS320C64X_INS_SUBC,
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TMS320C64X_INS_SUBU,
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TMS320C64X_INS_SWAP4,
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TMS320C64X_INS_UNPKHU4,
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TMS320C64X_INS_UNPKLU4,
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TMS320C64X_INS_XOR,
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TMS320C64X_INS_XPND2,
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TMS320C64X_INS_XPND4,
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// Aliases
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TMS320C64X_INS_IDLE,
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TMS320C64X_INS_MV,
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TMS320C64X_INS_NEG,
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TMS320C64X_INS_NOT,
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TMS320C64X_INS_SWAP2,
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TMS320C64X_INS_ZERO,
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TMS320C64X_INS_ENDING, // <-- mark the end of the list of instructions
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} tms320c64x_insn;
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typedef enum tms320c64x_insn_group {
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TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
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TMS320C64X_GRP_JUMP, ///< = CS_GRP_JUMP
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TMS320C64X_GRP_FUNIT_D = 128,
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TMS320C64X_GRP_FUNIT_L,
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TMS320C64X_GRP_FUNIT_M,
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TMS320C64X_GRP_FUNIT_S,
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TMS320C64X_GRP_FUNIT_NO,
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TMS320C64X_GRP_ENDING, // <-- mark the end of the list of groups
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} tms320c64x_insn_group;
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typedef enum tms320c64x_funit {
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TMS320C64X_FUNIT_INVALID = 0,
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TMS320C64X_FUNIT_D,
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TMS320C64X_FUNIT_L,
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TMS320C64X_FUNIT_M,
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TMS320C64X_FUNIT_S,
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TMS320C64X_FUNIT_NO
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} tms320c64x_funit;
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#ifdef __cplusplus
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}
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#endif
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#endif
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