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426 lines
10 KiB
426 lines
10 KiB
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#include "snes9x.h"
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#include "memmap.h"
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#include "cpuops.h"
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#include "dma.h"
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#include "apu/apu.h"
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#include "fxemu.h"
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#include "snapshot.h"
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#include "movie.h"
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#ifdef DEBUGGER
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#include "debug.h"
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#include "missing.h"
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#endif
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static inline void S9xReschedule (void);
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void S9xMainLoop (void)
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{
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#define CHECK_FOR_IRQ_CHANGE() \
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if (Timings.IRQFlagChanging) \
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{ \
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if (Timings.IRQFlagChanging & IRQ_TRIGGER_NMI) \
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{ \
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CPU.NMIPending = TRUE; \
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Timings.NMITriggerPos = CPU.Cycles + 6; \
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} \
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if (Timings.IRQFlagChanging & IRQ_CLEAR_FLAG) \
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ClearIRQ(); \
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else if (Timings.IRQFlagChanging & IRQ_SET_FLAG) \
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SetIRQ(); \
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Timings.IRQFlagChanging = IRQ_NONE; \
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}
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if (CPU.Flags & SCAN_KEYS_FLAG)
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{
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CPU.Flags &= ~SCAN_KEYS_FLAG;
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S9xMovieUpdate();
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}
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for (;;)
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{
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if (CPU.NMIPending)
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{
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage ("Comparing %d to %d\n", Timings.NMITriggerPos, CPU.Cycles);
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#endif
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if (Timings.NMITriggerPos <= CPU.Cycles)
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{
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CPU.NMIPending = FALSE;
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Timings.NMITriggerPos = 0xffff;
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if (CPU.WaitingForInterrupt)
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{
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CPU.WaitingForInterrupt = FALSE;
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Registers.PCw++;
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CPU.Cycles += TWO_CYCLES + ONE_DOT_CYCLE / 2;
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while (CPU.Cycles >= CPU.NextEvent)
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S9xDoHEventProcessing();
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}
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CHECK_FOR_IRQ_CHANGE();
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S9xOpcode_NMI();
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}
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}
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if (CPU.Cycles >= Timings.NextIRQTimer)
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{
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#ifdef DEBUGGER
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S9xTraceMessage ("Timer triggered\n");
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#endif
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S9xUpdateIRQPositions(false);
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CPU.IRQLine = TRUE;
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}
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if (CPU.IRQLine || CPU.IRQExternal)
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{
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if (CPU.WaitingForInterrupt)
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{
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CPU.WaitingForInterrupt = FALSE;
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Registers.PCw++;
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CPU.Cycles += TWO_CYCLES + ONE_DOT_CYCLE / 2;
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while (CPU.Cycles >= CPU.NextEvent)
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S9xDoHEventProcessing();
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}
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if (!CheckFlag(IRQ))
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{
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/* The flag pushed onto the stack is the new value */
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CHECK_FOR_IRQ_CHANGE();
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S9xOpcode_IRQ();
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}
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}
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/* Change IRQ flag for instructions that set it only on last cycle */
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CHECK_FOR_IRQ_CHANGE();
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#ifdef DEBUGGER
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if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
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{
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for (int Break = 0; Break != 6; Break++)
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{
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if (S9xBreakpoint[Break].Enabled &&
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S9xBreakpoint[Break].Bank == Registers.PB &&
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S9xBreakpoint[Break].Address == Registers.PCw)
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{
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if (S9xBreakpoint[Break].Enabled == 2)
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S9xBreakpoint[Break].Enabled = TRUE;
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else
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CPU.Flags |= DEBUG_MODE_FLAG;
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}
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}
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}
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if (CPU.Flags & DEBUG_MODE_FLAG)
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break;
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if (CPU.Flags & TRACE_FLAG)
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S9xTrace();
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if (CPU.Flags & SINGLE_STEP_FLAG)
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{
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CPU.Flags &= ~SINGLE_STEP_FLAG;
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CPU.Flags |= DEBUG_MODE_FLAG;
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}
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#endif
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if (CPU.Flags & SCAN_KEYS_FLAG)
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{
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#ifdef DEBUGGER
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if (!(CPU.Flags & FRAME_ADVANCE_FLAG))
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#endif
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{
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S9xSyncSpeed();
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}
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break;
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}
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uint8 Op;
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struct SOpcodes *Opcodes;
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if (CPU.PCBase)
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{
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Op = CPU.PCBase[Registers.PCw];
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CPU.Cycles += CPU.MemSpeed;
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Opcodes = ICPU.S9xOpcodes;
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}
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else
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{
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Op = S9xGetByte(Registers.PBPC);
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OpenBus = Op;
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Opcodes = S9xOpcodesSlow;
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}
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if ((Registers.PCw & MEMMAP_MASK) + ICPU.S9xOpLengths[Op] >= MEMMAP_BLOCK_SIZE)
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{
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uint8 *oldPCBase = CPU.PCBase;
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CPU.PCBase = S9xGetBasePointer(ICPU.ShiftedPB + ((uint16) (Registers.PCw + 4)));
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if (oldPCBase != CPU.PCBase || (Registers.PCw & ~MEMMAP_MASK) == (0xffff & ~MEMMAP_MASK))
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Opcodes = S9xOpcodesSlow;
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}
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Registers.PCw++;
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(*Opcodes[Op].S9xOpcode)();
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if (Settings.SA1)
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S9xSA1MainLoop();
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}
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S9xPackStatus();
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}
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static inline void S9xReschedule (void)
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{
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switch (CPU.WhichEvent)
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{
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case HC_HBLANK_START_EVENT:
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CPU.WhichEvent = HC_HDMA_START_EVENT;
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CPU.NextEvent = Timings.HDMAStart;
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break;
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case HC_HDMA_START_EVENT:
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CPU.WhichEvent = HC_HCOUNTER_MAX_EVENT;
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CPU.NextEvent = Timings.H_Max;
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break;
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case HC_HCOUNTER_MAX_EVENT:
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CPU.WhichEvent = HC_HDMA_INIT_EVENT;
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CPU.NextEvent = Timings.HDMAInit;
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break;
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case HC_HDMA_INIT_EVENT:
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CPU.WhichEvent = HC_RENDER_EVENT;
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CPU.NextEvent = Timings.RenderPos;
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break;
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case HC_RENDER_EVENT:
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CPU.WhichEvent = HC_WRAM_REFRESH_EVENT;
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CPU.NextEvent = Timings.WRAMRefreshPos;
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break;
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case HC_WRAM_REFRESH_EVENT:
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CPU.WhichEvent = HC_HBLANK_START_EVENT;
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CPU.NextEvent = Timings.HBlankStart;
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break;
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}
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}
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void S9xDoHEventProcessing (void)
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{
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#ifdef DEBUGGER
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static char eventname[7][32] =
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{
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"",
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"HC_HBLANK_START_EVENT",
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"HC_HDMA_START_EVENT ",
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"HC_HCOUNTER_MAX_EVENT",
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"HC_HDMA_INIT_EVENT ",
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"HC_RENDER_EVENT ",
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"HC_WRAM_REFRESH_EVENT"
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};
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#endif
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage("--- HC event processing (%s) expected HC:%04d executed HC:%04d VC:%04d",
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eventname[CPU.WhichEvent], CPU.NextEvent, CPU.Cycles, CPU.V_Counter);
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#endif
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switch (CPU.WhichEvent)
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{
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case HC_HBLANK_START_EVENT:
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S9xReschedule();
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break;
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case HC_HDMA_START_EVENT:
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S9xReschedule();
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if (PPU.HDMA && CPU.V_Counter <= PPU.ScreenHeight)
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{
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#ifdef DEBUGGER
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S9xTraceFormattedMessage("*** HDMA Transfer HC:%04d, Channel:%02x", CPU.Cycles, PPU.HDMA);
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#endif
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PPU.HDMA = S9xDoHDMA(PPU.HDMA);
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}
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break;
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case HC_HCOUNTER_MAX_EVENT:
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if (Settings.SuperFX)
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{
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if (!SuperFX.oneLineDone)
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S9xSuperFXExec();
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SuperFX.oneLineDone = FALSE;
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}
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S9xAPUEndScanline();
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CPU.Cycles -= Timings.H_Max;
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if (Timings.NMITriggerPos != 0xffff)
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Timings.NMITriggerPos -= Timings.H_Max;
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if (Timings.NextIRQTimer != 0x0fffffff)
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Timings.NextIRQTimer -= Timings.H_Max;
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S9xAPUSetReferenceTime(CPU.Cycles);
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if (Settings.SA1)
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SA1.Cycles -= Timings.H_Max * 3;
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CPU.V_Counter++;
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if (CPU.V_Counter >= Timings.V_Max) // V ranges from 0 to Timings.V_Max - 1
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{
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CPU.V_Counter = 0;
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Timings.InterlaceField ^= 1;
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// From byuu:
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// [NTSC]
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// interlace mode has 525 scanlines: 263 on the even frame, and 262 on the odd.
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// non-interlace mode has 524 scanlines: 262 scanlines on both even and odd frames.
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// [PAL] <PAL info is unverified on hardware>
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// interlace mode has 625 scanlines: 313 on the even frame, and 312 on the odd.
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// non-interlace mode has 624 scanlines: 312 scanlines on both even and odd frames.
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if (IPPU.Interlace && !Timings.InterlaceField)
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Timings.V_Max = Timings.V_Max_Master + 1; // 263 (NTSC), 313?(PAL)
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else
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Timings.V_Max = Timings.V_Max_Master; // 262 (NTSC), 312?(PAL)
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Memory.FillRAM[0x213F] ^= 0x80;
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PPU.RangeTimeOver = 0;
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// FIXME: reading $4210 will wait 2 cycles, then perform reading, then wait 4 more cycles.
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Memory.FillRAM[0x4210] = Model->_5A22;
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ICPU.Frame++;
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PPU.HVBeamCounterLatched = 0;
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}
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// From byuu:
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// In non-interlace mode, there are 341 dots per scanline, and 262 scanlines per frame.
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// On odd frames, scanline 240 is one dot short.
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// In interlace mode, there are always 341 dots per scanline. Even frames have 263 scanlines,
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// and odd frames have 262 scanlines.
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// Interlace mode scanline 240 on odd frames is not missing a dot.
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if (CPU.V_Counter == 240 && !IPPU.Interlace && Timings.InterlaceField) // V=240
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Timings.H_Max = Timings.H_Max_Master - ONE_DOT_CYCLE; // HC=1360
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else
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Timings.H_Max = Timings.H_Max_Master; // HC=1364
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if (Model->_5A22 == 2)
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{
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if (CPU.V_Counter != 240 || IPPU.Interlace || !Timings.InterlaceField) // V=240
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{
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if (Timings.WRAMRefreshPos == SNES_WRAM_REFRESH_HC_v2 - ONE_DOT_CYCLE) // HC=534
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Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v2; // HC=538
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else
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Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v2 - ONE_DOT_CYCLE; // HC=534
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}
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}
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else
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Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v1;
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if (CPU.V_Counter == PPU.ScreenHeight + FIRST_VISIBLE_LINE) // VBlank starts from V=225(240).
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{
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S9xEndScreenRefresh();
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CPU.Flags |= SCAN_KEYS_FLAG;
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PPU.HDMA = 0;
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// Bits 7 and 6 of $4212 are computed when read in S9xGetPPU.
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#ifdef DEBUGGER
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missing.dma_this_frame = 0;
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#endif
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IPPU.MaxBrightness = PPU.Brightness;
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PPU.ForcedBlanking = (Memory.FillRAM[0x2100] >> 7) & 1;
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if (!PPU.ForcedBlanking)
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{
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PPU.OAMAddr = PPU.SavedOAMAddr;
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uint8 tmp = 0;
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if (PPU.OAMPriorityRotation)
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tmp = (PPU.OAMAddr & 0xFE) >> 1;
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if ((PPU.OAMFlip & 1) || PPU.FirstSprite != tmp)
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{
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PPU.FirstSprite = tmp;
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IPPU.OBJChanged = TRUE;
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}
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PPU.OAMFlip = 0;
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}
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// FIXME: writing to $4210 will wait 6 cycles.
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Memory.FillRAM[0x4210] = 0x80 | Model->_5A22;
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if (Memory.FillRAM[0x4200] & 0x80)
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{
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage ("NMI Scheduled for next scanline.");
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#endif
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// FIXME: triggered at HC=6, checked just before the final CPU cycle,
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// then, when to call S9xOpcode_NMI()?
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CPU.NMIPending = TRUE;
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Timings.NMITriggerPos = 6 + 6;
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}
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}
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if (CPU.V_Counter == PPU.ScreenHeight + 3) // FIXME: not true
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{
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if (Memory.FillRAM[0x4200] & 1)
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S9xDoAutoJoypad();
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}
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if (CPU.V_Counter == FIRST_VISIBLE_LINE) // V=1
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S9xStartScreenRefresh();
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S9xReschedule();
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break;
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case HC_HDMA_INIT_EVENT:
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S9xReschedule();
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if (CPU.V_Counter == 0)
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{
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#ifdef DEBUGGER
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S9xTraceFormattedMessage("*** HDMA Init HC:%04d, Channel:%02x", CPU.Cycles, PPU.HDMA);
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#endif
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S9xStartHDMA();
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}
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break;
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case HC_RENDER_EVENT:
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if (CPU.V_Counter >= FIRST_VISIBLE_LINE && CPU.V_Counter <= PPU.ScreenHeight)
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RenderLine((uint8) (CPU.V_Counter - FIRST_VISIBLE_LINE));
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S9xReschedule();
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break;
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case HC_WRAM_REFRESH_EVENT:
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#ifdef DEBUGGER
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S9xTraceFormattedMessage("*** WRAM Refresh HC:%04d", CPU.Cycles);
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#endif
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CPU.Cycles += SNES_WRAM_REFRESH_CYCLES;
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S9xReschedule();
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break;
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}
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#ifdef DEBUGGER
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if (Settings.TraceHCEvent)
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S9xTraceFormattedMessage("--- HC event rescheduled (%s) expected HC:%04d current HC:%04d",
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eventname[CPU.WhichEvent], CPU.NextEvent, CPU.Cycles);
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#endif
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}
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