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1636 lines
39 KiB
1636 lines
39 KiB
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#include "snes9x.h"
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#include "memmap.h"
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#include "dma.h"
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#include "apu/apu.h"
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#include "sdd1emu.h"
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#include "spc7110emu.h"
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#ifdef DEBUGGER
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#include "missing.h"
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#endif
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#define ADD_CYCLES(n) { CPU.Cycles += (n); }
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extern uint8 *HDMAMemPointers[8];
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extern int HDMA_ModeByteCounts[8];
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extern SPC7110 s7emu;
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static uint8 sdd1_decode_buffer[0x10000];
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static inline bool8 addCyclesInDMA (uint8);
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static inline bool8 HDMAReadLineCount (int);
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static inline bool8 addCyclesInDMA (uint8 dma_channel)
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{
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// Add 8 cycles per byte, sync APU, and do HC related events.
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// If HDMA was done in S9xDoHEventProcessing(), check if it used the same channel as DMA.
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ADD_CYCLES(SLOW_ONE_CYCLE);
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while (CPU.Cycles >= CPU.NextEvent)
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S9xDoHEventProcessing();
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if (CPU.HDMARanInDMA & (1 << dma_channel))
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{
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CPU.HDMARanInDMA = 0;
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#ifdef DEBUGGER
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printf("HDMA and DMA use the same channel %d!\n", dma_channel);
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#endif
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// If HDMA triggers in the middle of DMA transfer and it uses the same channel,
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// it kills the DMA transfer immediately. $43x2 and $43x5 stop updating.
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return (FALSE);
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}
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CPU.HDMARanInDMA = 0;
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return (TRUE);
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}
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bool8 S9xDoDMA (uint8 Channel)
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{
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CPU.InDMA = TRUE;
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CPU.InDMAorHDMA = TRUE;
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CPU.CurrentDMAorHDMAChannel = Channel;
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SDMA *d = &DMA[Channel];
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// Check invalid DMA first
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if ((d->ABank == 0x7E || d->ABank == 0x7F) && d->BAddress == 0x80 && !d->ReverseTransfer)
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{
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// Attempting a DMA from WRAM to $2180 will not work, WRAM will not be written.
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// Attempting a DMA from $2180 to WRAM will similarly not work,
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// the value written is (initially) the OpenBus value.
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// In either case, the address in $2181-3 is not incremented.
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// Does an invalid DMA actually take time?
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// I'd say yes, since 'invalid' is probably just the WRAM chip
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// not being able to read and write itself at the same time
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// And no, PPU.WRAM should not be updated.
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int32 c = d->TransferBytes;
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// Writing $0000 to $43x5 actually results in a transfer of $10000 bytes, not 0.
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if (c == 0)
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c = 0x10000;
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// 8 cycles per channel
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ADD_CYCLES(SLOW_ONE_CYCLE);
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// 8 cycles per byte
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while (c)
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{
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d->TransferBytes--;
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d->AAddress++;
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c--;
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if (!addCyclesInDMA(Channel))
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{
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CPU.InDMA = FALSE;
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CPU.InDMAorHDMA = FALSE;
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CPU.CurrentDMAorHDMAChannel = -1;
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return (FALSE);
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}
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}
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#ifdef DEBUGGER
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if (Settings.TraceDMA)
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{
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sprintf(String, "DMA[%d]: WRAM Bank:%02X->$2180", Channel, d->ABank);
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S9xMessage(S9X_TRACE, S9X_DMA_TRACE, String);
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}
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#endif
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CPU.InDMA = FALSE;
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CPU.InDMAorHDMA = FALSE;
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CPU.CurrentDMAorHDMAChannel = -1;
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return (TRUE);
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}
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// Prepare for accessing $2118-2119
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switch (d->BAddress)
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{
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case 0x18:
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case 0x19:
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if (IPPU.RenderThisFrame)
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FLUSH_REDRAW();
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break;
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}
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int32 inc = d->AAddressFixed ? 0 : (!d->AAddressDecrement ? 1 : -1);
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int32 count = d->TransferBytes;
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// Writing $0000 to $43x5 actually results in a transfer of $10000 bytes, not 0.
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if (count == 0)
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count = 0x10000;
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// Prepare for custom chip DMA
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// S-DD1
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uint8 *in_sdd1_dma = NULL;
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if (Settings.SDD1)
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{
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if (d->AAddressFixed && Memory.FillRAM[0x4801] > 0)
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{
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// XXX: Should probably verify that we're DMAing from ROM?
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// And somewhere we should make sure we're not running across a mapping boundary too.
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// Hacky support for pre-decompressed S-DD1 data
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inc = !d->AAddressDecrement ? 1 : -1;
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uint8 *in_ptr = S9xGetBasePointer(((d->ABank << 16) | d->AAddress));
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if (in_ptr)
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{
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in_ptr += d->AAddress;
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SDD1_decompress(sdd1_decode_buffer, in_ptr, d->TransferBytes);
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}
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#ifdef DEBUGGER
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else
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{
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sprintf(String, "S-DD1: DMA from non-block address $%02X:%04X", d->ABank, d->AAddress);
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S9xMessage(S9X_WARNING, S9X_DMA_TRACE, String);
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}
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#endif
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in_sdd1_dma = sdd1_decode_buffer;
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}
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Memory.FillRAM[0x4801] = 0;
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}
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// SPC7110
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uint8 *spc7110_dma = NULL;
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if (Settings.SPC7110)
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{
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if (d->AAddress == 0x4800 || d->ABank == 0x50)
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{
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spc7110_dma = new uint8[d->TransferBytes];
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for (int i = 0; i < d->TransferBytes; i++)
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spc7110_dma[i] = s7emu.decomp.read();
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int32 icount = s7emu.r4809 | (s7emu.r480a << 8);
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icount -= d->TransferBytes;
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s7emu.r4809 = icount & 0x00ff;
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s7emu.r480a = (icount & 0xff00) >> 8;
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inc = 1;
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d->AAddress -= count;
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}
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}
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// SA-1
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bool8 in_sa1_dma = FALSE;
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if (Settings.SA1)
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{
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if (SA1.in_char_dma && d->BAddress == 0x18 && (d->ABank & 0xf0) == 0x40)
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{
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// Perform packed bitmap to PPU character format conversion on the data
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// before transmitting it to V-RAM via-DMA.
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int32 num_chars = 1 << ((Memory.FillRAM[0x2231] >> 2) & 7);
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int32 depth = (Memory.FillRAM[0x2231] & 3) == 0 ? 8 : (Memory.FillRAM[0x2231] & 3) == 1 ? 4 : 2;
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int32 bytes_per_char = 8 * depth;
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int32 bytes_per_line = depth * num_chars;
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int32 char_line_bytes = bytes_per_char * num_chars;
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uint32 addr = (d->AAddress / char_line_bytes) * char_line_bytes;
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uint8 *base = S9xGetBasePointer((d->ABank << 16) + addr);
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if (!base)
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{
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sprintf(String, "SA-1: DMA from non-block address $%02X:%04X", d->ABank, addr);
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S9xMessage(S9X_WARNING, S9X_DMA_TRACE, String);
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base = Memory.ROM;
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}
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base += addr;
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uint8 *buffer = &Memory.ROM[CMemory::MAX_ROM_SIZE - 0x10000];
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uint8 *p = buffer;
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uint32 inc_sa1 = char_line_bytes - (d->AAddress % char_line_bytes);
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uint32 char_count = inc_sa1 / bytes_per_char;
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in_sa1_dma = TRUE;
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#if 0
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printf("SA-1 DMA: %08x,", base);
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printf("depth = %d, count = %d, bytes_per_char = %d, bytes_per_line = %d, num_chars = %d, char_line_bytes = %d\n",
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depth, count, bytes_per_char, bytes_per_line, num_chars, char_line_bytes);
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#endif
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switch (depth)
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{
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case 2:
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for (int32 i = 0; i < count; i += inc_sa1, base += char_line_bytes, inc_sa1 = char_line_bytes, char_count = num_chars)
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{
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uint8 *line = base + (num_chars - char_count) * 2;
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for (uint32 j = 0; j < char_count && p - buffer < count; j++, line += 2)
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{
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uint8 *q = line;
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for (int32 l = 0; l < 8; l++, q += bytes_per_line)
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{
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for (int32 b = 0; b < 2; b++)
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{
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uint8 r = *(q + b);
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*(p + 0) = (*(p + 0) << 1) | ((r >> 0) & 1);
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*(p + 1) = (*(p + 1) << 1) | ((r >> 1) & 1);
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*(p + 0) = (*(p + 0) << 1) | ((r >> 2) & 1);
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*(p + 1) = (*(p + 1) << 1) | ((r >> 3) & 1);
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*(p + 0) = (*(p + 0) << 1) | ((r >> 4) & 1);
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*(p + 1) = (*(p + 1) << 1) | ((r >> 5) & 1);
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*(p + 0) = (*(p + 0) << 1) | ((r >> 6) & 1);
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*(p + 1) = (*(p + 1) << 1) | ((r >> 7) & 1);
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}
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p += 2;
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}
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}
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}
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break;
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case 4:
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for (int32 i = 0; i < count; i += inc_sa1, base += char_line_bytes, inc_sa1 = char_line_bytes, char_count = num_chars)
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{
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uint8 *line = base + (num_chars - char_count) * 4;
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for (uint32 j = 0; j < char_count && p - buffer < count; j++, line += 4)
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{
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uint8 *q = line;
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for (int32 l = 0; l < 8; l++, q += bytes_per_line)
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{
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for (int32 b = 0; b < 4; b++)
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{
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uint8 r = *(q + b);
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*(p + 0) = (*(p + 0) << 1) | ((r >> 0) & 1);
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*(p + 1) = (*(p + 1) << 1) | ((r >> 1) & 1);
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*(p + 16) = (*(p + 16) << 1) | ((r >> 2) & 1);
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*(p + 17) = (*(p + 17) << 1) | ((r >> 3) & 1);
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*(p + 0) = (*(p + 0) << 1) | ((r >> 4) & 1);
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*(p + 1) = (*(p + 1) << 1) | ((r >> 5) & 1);
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*(p + 16) = (*(p + 16) << 1) | ((r >> 6) & 1);
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*(p + 17) = (*(p + 17) << 1) | ((r >> 7) & 1);
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}
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p += 2;
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}
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p += 32 - 16;
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}
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}
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break;
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case 8:
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for (int32 i = 0; i < count; i += inc_sa1, base += char_line_bytes, inc_sa1 = char_line_bytes, char_count = num_chars)
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{
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uint8 *line = base + (num_chars - char_count) * 8;
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for (uint32 j = 0; j < char_count && p - buffer < count; j++, line += 8)
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{
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uint8 *q = line;
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for (int32 l = 0; l < 8; l++, q += bytes_per_line)
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{
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for (int32 b = 0; b < 8; b++)
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{
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uint8 r = *(q + b);
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*(p + 0) = (*(p + 0) << 1) | ((r >> 0) & 1);
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*(p + 1) = (*(p + 1) << 1) | ((r >> 1) & 1);
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*(p + 16) = (*(p + 16) << 1) | ((r >> 2) & 1);
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*(p + 17) = (*(p + 17) << 1) | ((r >> 3) & 1);
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*(p + 32) = (*(p + 32) << 1) | ((r >> 4) & 1);
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*(p + 33) = (*(p + 33) << 1) | ((r >> 5) & 1);
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*(p + 48) = (*(p + 48) << 1) | ((r >> 6) & 1);
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*(p + 49) = (*(p + 49) << 1) | ((r >> 7) & 1);
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}
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p += 2;
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}
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p += 64 - 16;
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}
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}
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break;
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}
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}
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}
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#ifdef DEBUGGER
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if (Settings.TraceDMA)
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{
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sprintf(String, "DMA[%d]: %s Mode:%d 0x%02X%04X->0x21%02X Bytes:%d (%s) V:%03d",
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Channel, d->ReverseTransfer ? "PPU->CPU" : "CPU->PPU", d->TransferMode, d->ABank, d->AAddress, d->BAddress,
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d->TransferBytes, d->AAddressFixed ? "fixed" : (d->AAddressDecrement ? "dec" : "inc"), CPU.V_Counter);
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if (d->BAddress == 0x18 || d->BAddress == 0x19 || d->BAddress == 0x39 || d->BAddress == 0x3a)
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sprintf(String, "%s VRAM: %04X (%d,%d) %s", String,
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PPU.VMA.Address, PPU.VMA.Increment, PPU.VMA.FullGraphicCount, PPU.VMA.High ? "word" : "byte");
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else
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if (d->BAddress == 0x22 || d->BAddress == 0x3b)
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sprintf(String, "%s CGRAM: %02X (%x)", String, PPU.CGADD, PPU.CGFLIP);
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else
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if (d->BAddress == 0x04 || d->BAddress == 0x38)
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sprintf(String, "%s OBJADDR: %04X", String, PPU.OAMAddr);
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S9xMessage(S9X_TRACE, S9X_DMA_TRACE, String);
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}
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#endif
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// Do Transfer
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uint8 Work;
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// 8 cycles per channel
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ADD_CYCLES(SLOW_ONE_CYCLE);
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if (!d->ReverseTransfer)
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{
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// CPU -> PPU
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int32 b = 0;
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uint16 p = d->AAddress;
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uint8 *base = S9xGetBasePointer((d->ABank << 16) + d->AAddress);
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bool8 inWRAM_DMA;
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int32 rem = count;
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// Transfer per block if d->AAdressFixed is FALSE
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count = d->AAddressFixed ? rem : (d->AAddressDecrement ? ((p & MEMMAP_MASK) + 1) : (MEMMAP_BLOCK_SIZE - (p & MEMMAP_MASK)));
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// Settings for custom chip DMA
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if (in_sa1_dma)
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{
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base = &Memory.ROM[CMemory::MAX_ROM_SIZE - 0x10000];
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p = 0;
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count = rem;
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}
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else
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if (in_sdd1_dma)
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{
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base = in_sdd1_dma;
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p = 0;
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count = rem;
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}
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else
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if (spc7110_dma)
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{
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base = spc7110_dma;
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p = 0;
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count = rem;
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}
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inWRAM_DMA = ((!in_sa1_dma && !in_sdd1_dma && !spc7110_dma) &&
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(d->ABank == 0x7e || d->ABank == 0x7f || (!(d->ABank & 0x40) && d->AAddress < 0x2000)));
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// 8 cycles per byte
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#define UPDATE_COUNTERS \
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d->TransferBytes--; \
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d->AAddress += inc; \
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p += inc; \
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if (!addCyclesInDMA(Channel)) \
|
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{ \
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CPU.InDMA = FALSE; \
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CPU.InDMAorHDMA = FALSE; \
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CPU.InWRAMDMAorHDMA = FALSE; \
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CPU.CurrentDMAorHDMAChannel = -1; \
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return (FALSE); \
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}
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|
|
while (1)
|
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{
|
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if (count > rem)
|
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count = rem;
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rem -= count;
|
|
|
|
CPU.InWRAMDMAorHDMA = inWRAM_DMA;
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|
|
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if (!base)
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{
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// DMA SLOW PATH
|
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if (d->TransferMode == 0 || d->TransferMode == 2 || d->TransferMode == 6)
|
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{
|
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do
|
|
{
|
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Work = S9xGetByte((d->ABank << 16) + p);
|
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S9xSetPPU(Work, 0x2100 + d->BAddress);
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UPDATE_COUNTERS;
|
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} while (--count > 0);
|
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}
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else
|
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if (d->TransferMode == 1 || d->TransferMode == 5)
|
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{
|
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// This is a variation on Duff's Device. It is legal C/C++.
|
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switch (b)
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{
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default:
|
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while (count > 1)
|
|
{
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Work = S9xGetByte((d->ABank << 16) + p);
|
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S9xSetPPU(Work, 0x2100 + d->BAddress);
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UPDATE_COUNTERS;
|
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count--;
|
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// Fall through
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case 1:
|
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Work = S9xGetByte((d->ABank << 16) + p);
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S9xSetPPU(Work, 0x2101 + d->BAddress);
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UPDATE_COUNTERS;
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count--;
|
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}
|
|
}
|
|
|
|
if (count == 1)
|
|
{
|
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Work = S9xGetByte((d->ABank << 16) + p);
|
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S9xSetPPU(Work, 0x2100 + d->BAddress);
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UPDATE_COUNTERS;
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b = 1;
|
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}
|
|
else
|
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b = 0;
|
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}
|
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else
|
|
if (d->TransferMode == 3 || d->TransferMode == 7)
|
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{
|
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switch (b)
|
|
{
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default:
|
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do
|
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{
|
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Work = S9xGetByte((d->ABank << 16) + p);
|
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S9xSetPPU(Work, 0x2100 + d->BAddress);
|
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UPDATE_COUNTERS;
|
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if (--count <= 0)
|
|
{
|
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b = 1;
|
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break;
|
|
}
|
|
// Fall through
|
|
case 1:
|
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Work = S9xGetByte((d->ABank << 16) + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
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b = 2;
|
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break;
|
|
}
|
|
// Fall through
|
|
case 2:
|
|
Work = S9xGetByte((d->ABank << 16) + p);
|
|
S9xSetPPU(Work, 0x2101 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 3;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 3:
|
|
Work = S9xGetByte((d->ABank << 16) + p);
|
|
S9xSetPPU(Work, 0x2101 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 0;
|
|
break;
|
|
}
|
|
} while (1);
|
|
}
|
|
}
|
|
else
|
|
if (d->TransferMode == 4)
|
|
{
|
|
switch (b)
|
|
{
|
|
default:
|
|
do
|
|
{
|
|
Work = S9xGetByte((d->ABank << 16) + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 1;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 1:
|
|
Work = S9xGetByte((d->ABank << 16) + p);
|
|
S9xSetPPU(Work, 0x2101 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 2;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 2:
|
|
Work = S9xGetByte((d->ABank << 16) + p);
|
|
S9xSetPPU(Work, 0x2102 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 3;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 3:
|
|
Work = S9xGetByte((d->ABank << 16) + p);
|
|
S9xSetPPU(Work, 0x2103 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 0;
|
|
break;
|
|
}
|
|
} while (1);
|
|
}
|
|
}
|
|
#ifdef DEBUGGER
|
|
else
|
|
{
|
|
sprintf(String, "Unknown DMA transfer mode: %d on channel %d\n", d->TransferMode, Channel);
|
|
S9xMessage(S9X_TRACE, S9X_DMA_TRACE, String);
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
// DMA FAST PATH
|
|
if (d->TransferMode == 0 || d->TransferMode == 2 || d->TransferMode == 6)
|
|
{
|
|
switch (d->BAddress)
|
|
{
|
|
case 0x04: // OAMDATA
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2104(Work);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
|
|
break;
|
|
|
|
case 0x18: // VMDATAL
|
|
if (!PPU.VMA.FullGraphicCount)
|
|
{
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2118_linear(Work);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
}
|
|
else
|
|
{
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2118_tile(Work);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x19: // VMDATAH
|
|
if (!PPU.VMA.FullGraphicCount)
|
|
{
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2119_linear(Work);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
}
|
|
else
|
|
{
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2119_tile(Work);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x22: // CGDATA
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2122(Work);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
|
|
break;
|
|
|
|
case 0x80: // WMDATA
|
|
if (!CPU.InWRAMDMAorHDMA)
|
|
{
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2180(Work);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
}
|
|
else
|
|
{
|
|
do
|
|
{
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
} while (--count > 0);
|
|
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
if (d->TransferMode == 1 || d->TransferMode == 5)
|
|
{
|
|
if (d->BAddress == 0x18)
|
|
{
|
|
// VMDATAL
|
|
if (!PPU.VMA.FullGraphicCount)
|
|
{
|
|
switch (b)
|
|
{
|
|
default:
|
|
while (count > 1)
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2118_linear(Work);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
// Fall through
|
|
case 1:
|
|
OpenBus = *(base + p);
|
|
REGISTER_2119_linear(OpenBus);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
}
|
|
}
|
|
|
|
if (count == 1)
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2118_linear(Work);
|
|
UPDATE_COUNTERS;
|
|
b = 1;
|
|
}
|
|
else
|
|
b = 0;
|
|
}
|
|
else
|
|
{
|
|
switch (b)
|
|
{
|
|
default:
|
|
while (count > 1)
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2118_tile(Work);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
// Fall through
|
|
case 1:
|
|
Work = *(base + p);
|
|
REGISTER_2119_tile(Work);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
}
|
|
}
|
|
|
|
if (count == 1)
|
|
{
|
|
Work = *(base + p);
|
|
REGISTER_2118_tile(Work);
|
|
UPDATE_COUNTERS;
|
|
b = 1;
|
|
}
|
|
else
|
|
b = 0;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// DMA mode 1 general case
|
|
switch (b)
|
|
{
|
|
default:
|
|
while (count > 1)
|
|
{
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
// Fall through
|
|
case 1:
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2101 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
}
|
|
}
|
|
|
|
if (count == 1)
|
|
{
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
b = 1;
|
|
}
|
|
else
|
|
b = 0;
|
|
}
|
|
}
|
|
else
|
|
if (d->TransferMode == 3 || d->TransferMode == 7)
|
|
{
|
|
switch (b)
|
|
{
|
|
default:
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 1;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 1:
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 2;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 2:
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2101 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 3;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 3:
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2101 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 0;
|
|
break;
|
|
}
|
|
} while (1);
|
|
}
|
|
}
|
|
else
|
|
if (d->TransferMode == 4)
|
|
{
|
|
switch (b)
|
|
{
|
|
default:
|
|
do
|
|
{
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2100 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 1;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 1:
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2101 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 2;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 2:
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2102 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 3;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case 3:
|
|
Work = *(base + p);
|
|
S9xSetPPU(Work, 0x2103 + d->BAddress);
|
|
UPDATE_COUNTERS;
|
|
if (--count <= 0)
|
|
{
|
|
b = 0;
|
|
break;
|
|
}
|
|
} while (1);
|
|
}
|
|
}
|
|
#ifdef DEBUGGER
|
|
else
|
|
{
|
|
sprintf(String, "Unknown DMA transfer mode: %d on channel %d\n", d->TransferMode, Channel);
|
|
S9xMessage(S9X_TRACE, S9X_DMA_TRACE, String);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
if (rem <= 0)
|
|
break;
|
|
|
|
base = S9xGetBasePointer((d->ABank << 16) + d->AAddress);
|
|
count = MEMMAP_BLOCK_SIZE;
|
|
inWRAM_DMA = ((!in_sa1_dma && !in_sdd1_dma && !spc7110_dma) &&
|
|
(d->ABank == 0x7e || d->ABank == 0x7f || (!(d->ABank & 0x40) && d->AAddress < 0x2000)));
|
|
}
|
|
|
|
#undef UPDATE_COUNTERS
|
|
}
|
|
else
|
|
{
|
|
// PPU -> CPU
|
|
|
|
// 8 cycles per byte
|
|
#define UPDATE_COUNTERS \
|
|
d->TransferBytes--; \
|
|
d->AAddress += inc; \
|
|
if (!addCyclesInDMA(Channel)) \
|
|
{ \
|
|
CPU.InDMA = FALSE; \
|
|
CPU.InDMAorHDMA = FALSE; \
|
|
CPU.InWRAMDMAorHDMA = FALSE; \
|
|
CPU.CurrentDMAorHDMAChannel = -1; \
|
|
return (FALSE); \
|
|
}
|
|
|
|
if (d->BAddress > 0x80 - 4 && d->BAddress <= 0x83 && !(d->ABank & 0x40))
|
|
{
|
|
// REVERSE-DMA REALLY-SLOW PATH
|
|
do
|
|
{
|
|
switch (d->TransferMode)
|
|
{
|
|
case 0:
|
|
case 2:
|
|
case 6:
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
case 5:
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
case 7:
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2102 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
CPU.InWRAMDMAorHDMA = (d->AAddress < 0x2000);
|
|
Work = S9xGetPPU(0x2103 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
default:
|
|
#ifdef DEBUGGER
|
|
sprintf(String, "Unknown DMA transfer mode: %d on channel %d\n", d->TransferMode, Channel);
|
|
S9xMessage(S9X_TRACE, S9X_DMA_TRACE, String);
|
|
#endif
|
|
while (count)
|
|
{
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
}
|
|
|
|
break;
|
|
}
|
|
} while (count);
|
|
}
|
|
else
|
|
{
|
|
// REVERSE-DMA FASTER PATH
|
|
CPU.InWRAMDMAorHDMA = (d->ABank == 0x7e || d->ABank == 0x7f);
|
|
do
|
|
{
|
|
switch (d->TransferMode)
|
|
{
|
|
case 0:
|
|
case 2:
|
|
case 6:
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
case 5:
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
case 7:
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
Work = S9xGetPPU(0x2100 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
Work = S9xGetPPU(0x2101 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
Work = S9xGetPPU(0x2102 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
if (!--count)
|
|
break;
|
|
|
|
Work = S9xGetPPU(0x2103 + d->BAddress);
|
|
S9xSetByte(Work, (d->ABank << 16) + d->AAddress);
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
|
|
break;
|
|
|
|
default:
|
|
#ifdef DEBUGGER
|
|
sprintf(String, "Unknown DMA transfer mode: %d on channel %d\n", d->TransferMode, Channel);
|
|
S9xMessage(S9X_TRACE, S9X_DMA_TRACE, String);
|
|
#endif
|
|
while (count)
|
|
{
|
|
UPDATE_COUNTERS;
|
|
count--;
|
|
}
|
|
|
|
break;
|
|
}
|
|
} while (count);
|
|
}
|
|
}
|
|
|
|
if (CPU.NMIPending && (Timings.NMITriggerPos != 0xffff))
|
|
{
|
|
Timings.NMITriggerPos = CPU.Cycles + Timings.NMIDMADelay;
|
|
}
|
|
|
|
// Release the memory used in SPC7110 DMA
|
|
if (Settings.SPC7110)
|
|
{
|
|
if (spc7110_dma)
|
|
delete [] spc7110_dma;
|
|
}
|
|
|
|
#if 0
|
|
// sanity check
|
|
if (d->TransferBytes != 0)
|
|
fprintf(stderr,"DMA[%d] TransferBytes not 0! $21%02x Reverse:%d %04x\n", Channel, d->BAddress, d->ReverseTransfer, d->TransferBytes);
|
|
#endif
|
|
|
|
CPU.InDMA = FALSE;
|
|
CPU.InDMAorHDMA = FALSE;
|
|
CPU.InWRAMDMAorHDMA = FALSE;
|
|
CPU.CurrentDMAorHDMAChannel = -1;
|
|
|
|
return (TRUE);
|
|
}
|
|
|
|
static inline bool8 HDMAReadLineCount (int d)
|
|
{
|
|
// CPU.InDMA is set, so S9xGetXXX() / S9xSetXXX() incur no charges.
|
|
|
|
uint8 line;
|
|
|
|
line = S9xGetByte((DMA[d].ABank << 16) + DMA[d].Address);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
|
|
if (!line)
|
|
{
|
|
DMA[d].Repeat = FALSE;
|
|
DMA[d].LineCount = 128;
|
|
|
|
if (DMA[d].HDMAIndirectAddressing)
|
|
{
|
|
if (PPU.HDMA & (0xfe << d))
|
|
{
|
|
DMA[d].Address++;
|
|
ADD_CYCLES(SLOW_ONE_CYCLE << 1);
|
|
}
|
|
else
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
|
|
DMA[d].IndirectAddress = S9xGetWord((DMA[d].ABank << 16) + DMA[d].Address);
|
|
DMA[d].Address++;
|
|
}
|
|
|
|
DMA[d].Address++;
|
|
HDMAMemPointers[d] = NULL;
|
|
|
|
return (FALSE);
|
|
}
|
|
else
|
|
if (line == 0x80)
|
|
{
|
|
DMA[d].Repeat = TRUE;
|
|
DMA[d].LineCount = 128;
|
|
}
|
|
else
|
|
{
|
|
DMA[d].Repeat = !(line & 0x80);
|
|
DMA[d].LineCount = line & 0x7f;
|
|
}
|
|
|
|
DMA[d].Address++;
|
|
DMA[d].DoTransfer = TRUE;
|
|
|
|
if (DMA[d].HDMAIndirectAddressing)
|
|
{
|
|
ADD_CYCLES(SLOW_ONE_CYCLE << 1);
|
|
DMA[d].IndirectAddress = S9xGetWord((DMA[d].ABank << 16) + DMA[d].Address);
|
|
DMA[d].Address += 2;
|
|
HDMAMemPointers[d] = S9xGetMemPointer((DMA[d].IndirectBank << 16) + DMA[d].IndirectAddress);
|
|
}
|
|
else
|
|
HDMAMemPointers[d] = S9xGetMemPointer((DMA[d].ABank << 16) + DMA[d].Address);
|
|
|
|
return (TRUE);
|
|
}
|
|
|
|
void S9xStartHDMA (void)
|
|
{
|
|
PPU.HDMA = Memory.FillRAM[0x420c];
|
|
|
|
#ifdef DEBUGGER
|
|
missing.hdma_this_frame = PPU.HDMA;
|
|
#endif
|
|
|
|
PPU.HDMAEnded = 0;
|
|
|
|
int32 tmpch;
|
|
|
|
CPU.InHDMA = TRUE;
|
|
CPU.InDMAorHDMA = TRUE;
|
|
tmpch = CPU.CurrentDMAorHDMAChannel;
|
|
|
|
// XXX: Not quite right...
|
|
if (PPU.HDMA != 0)
|
|
ADD_CYCLES(Timings.DMACPUSync);
|
|
|
|
for (uint8 i = 0; i < 8; i++)
|
|
{
|
|
if (PPU.HDMA & (1 << i))
|
|
{
|
|
CPU.CurrentDMAorHDMAChannel = i;
|
|
|
|
DMA[i].Address = DMA[i].AAddress;
|
|
|
|
if (!HDMAReadLineCount(i))
|
|
{
|
|
PPU.HDMA &= ~(1 << i);
|
|
PPU.HDMAEnded |= (1 << i);
|
|
}
|
|
}
|
|
else
|
|
DMA[i].DoTransfer = FALSE;
|
|
}
|
|
|
|
CPU.InHDMA = FALSE;
|
|
CPU.InDMAorHDMA = CPU.InDMA;
|
|
CPU.HDMARanInDMA = CPU.InDMA ? PPU.HDMA : 0;
|
|
CPU.CurrentDMAorHDMAChannel = tmpch;
|
|
}
|
|
|
|
uint8 S9xDoHDMA (uint8 byte)
|
|
{
|
|
struct SDMA *p;
|
|
|
|
uint32 ShiftedIBank;
|
|
uint16 IAddr;
|
|
bool8 temp;
|
|
int32 tmpch;
|
|
int d;
|
|
uint8 mask;
|
|
|
|
CPU.InHDMA = TRUE;
|
|
CPU.InDMAorHDMA = TRUE;
|
|
CPU.HDMARanInDMA = CPU.InDMA ? byte : 0;
|
|
temp = CPU.InWRAMDMAorHDMA;
|
|
tmpch = CPU.CurrentDMAorHDMAChannel;
|
|
|
|
// XXX: Not quite right...
|
|
ADD_CYCLES(Timings.DMACPUSync);
|
|
|
|
for (mask = 1, p = &DMA[0], d = 0; mask; mask <<= 1, p++, d++)
|
|
{
|
|
if (byte & mask)
|
|
{
|
|
CPU.InWRAMDMAorHDMA = FALSE;
|
|
CPU.CurrentDMAorHDMAChannel = d;
|
|
|
|
if (p->HDMAIndirectAddressing)
|
|
{
|
|
ShiftedIBank = (p->IndirectBank << 16);
|
|
IAddr = p->IndirectAddress;
|
|
}
|
|
else
|
|
{
|
|
ShiftedIBank = (p->ABank << 16);
|
|
IAddr = p->Address;
|
|
}
|
|
|
|
if (!HDMAMemPointers[d])
|
|
HDMAMemPointers[d] = S9xGetMemPointer(ShiftedIBank + IAddr);
|
|
|
|
if (p->DoTransfer)
|
|
{
|
|
// XXX: Hack for Uniracers, because we don't understand
|
|
// OAM Address Invalidation
|
|
if (p->BAddress == 0x04)
|
|
{
|
|
if (SNESGameFixes.Uniracers)
|
|
{
|
|
PPU.OAMAddr = 0x10c;
|
|
PPU.OAMFlip = 0;
|
|
}
|
|
}
|
|
|
|
#ifdef DEBUGGER
|
|
if (Settings.TraceHDMA && p->DoTransfer)
|
|
{
|
|
sprintf(String, "H-DMA[%d] %s (%d) 0x%06X->0x21%02X %s, Count: %3d, Rep: %s, V-LINE: %3ld %02X%04X",
|
|
p-DMA, p->ReverseTransfer? "read" : "write",
|
|
p->TransferMode, ShiftedIBank+IAddr, p->BAddress,
|
|
p->HDMAIndirectAddressing ? "ind" : "abs",
|
|
p->LineCount,
|
|
p->Repeat ? "yes" : "no ", (long) CPU.V_Counter,
|
|
p->ABank, p->Address);
|
|
S9xMessage(S9X_TRACE, S9X_HDMA_TRACE, String);
|
|
}
|
|
#endif
|
|
|
|
if (!p->ReverseTransfer)
|
|
{
|
|
if ((IAddr & MEMMAP_MASK) + HDMA_ModeByteCounts[p->TransferMode] >= MEMMAP_BLOCK_SIZE)
|
|
{
|
|
// HDMA REALLY-SLOW PATH
|
|
HDMAMemPointers[d] = NULL;
|
|
|
|
#define DOBYTE(Addr, RegOff) \
|
|
CPU.InWRAMDMAorHDMA = (ShiftedIBank == 0x7e0000 || ShiftedIBank == 0x7f0000 || \
|
|
(!(ShiftedIBank & 0x400000) && ((uint16) (Addr)) < 0x2000)); \
|
|
S9xSetPPU(S9xGetByte(ShiftedIBank + ((uint16) (Addr))), 0x2100 + p->BAddress + (RegOff));
|
|
|
|
switch (p->TransferMode)
|
|
{
|
|
case 0:
|
|
DOBYTE(IAddr, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 5:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 2, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 3, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 1:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 2:
|
|
case 6:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 3:
|
|
case 7:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 2, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 3, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 4:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 2, 2);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 3, 3);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
}
|
|
|
|
#undef DOBYTE
|
|
}
|
|
else
|
|
{
|
|
CPU.InWRAMDMAorHDMA = (ShiftedIBank == 0x7e0000 || ShiftedIBank == 0x7f0000 ||
|
|
(!(ShiftedIBank & 0x400000) && IAddr < 0x2000));
|
|
|
|
if (!HDMAMemPointers[d])
|
|
{
|
|
// HDMA SLOW PATH
|
|
uint32 Addr = ShiftedIBank + IAddr;
|
|
|
|
switch (p->TransferMode)
|
|
{
|
|
case 0:
|
|
S9xSetPPU(S9xGetByte(Addr), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 5:
|
|
S9xSetPPU(S9xGetByte(Addr + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 1), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
Addr += 2;
|
|
/* fall through */
|
|
case 1:
|
|
S9xSetPPU(S9xGetByte(Addr + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 1), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 2:
|
|
case 6:
|
|
S9xSetPPU(S9xGetByte(Addr + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 1), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 3:
|
|
case 7:
|
|
S9xSetPPU(S9xGetByte(Addr + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 1), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 2), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 3), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 4:
|
|
S9xSetPPU(S9xGetByte(Addr + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 1), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 2), 0x2102 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(S9xGetByte(Addr + 3), 0x2103 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// HDMA FAST PATH
|
|
switch (p->TransferMode)
|
|
{
|
|
case 0:
|
|
S9xSetPPU(*HDMAMemPointers[d]++, 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 5:
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 1), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
HDMAMemPointers[d] += 2;
|
|
/* fall through */
|
|
case 1:
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
// XXX: All HDMA should read to MDR first. This one just
|
|
// happens to fix Speedy Gonzales.
|
|
OpenBus = *(HDMAMemPointers[d] + 1);
|
|
S9xSetPPU(OpenBus, 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
HDMAMemPointers[d] += 2;
|
|
break;
|
|
|
|
case 2:
|
|
case 6:
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 1), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
HDMAMemPointers[d] += 2;
|
|
break;
|
|
|
|
case 3:
|
|
case 7:
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 1), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 2), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 3), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
HDMAMemPointers[d] += 4;
|
|
break;
|
|
|
|
case 4:
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 0), 0x2100 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 1), 0x2101 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 2), 0x2102 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
S9xSetPPU(*(HDMAMemPointers[d] + 3), 0x2103 + p->BAddress);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
HDMAMemPointers[d] += 4;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// REVERSE HDMA REALLY-SLOW PATH
|
|
// anomie says: Since this is apparently never used
|
|
// (otherwise we would have noticed before now), let's not bother with faster paths.
|
|
HDMAMemPointers[d] = NULL;
|
|
|
|
#define DOBYTE(Addr, RegOff) \
|
|
CPU.InWRAMDMAorHDMA = (ShiftedIBank == 0x7e0000 || ShiftedIBank == 0x7f0000 || \
|
|
(!(ShiftedIBank & 0x400000) && ((uint16) (Addr)) < 0x2000)); \
|
|
S9xSetByte(S9xGetPPU(0x2100 + p->BAddress + (RegOff)), ShiftedIBank + ((uint16) (Addr)));
|
|
|
|
switch (p->TransferMode)
|
|
{
|
|
case 0:
|
|
DOBYTE(IAddr, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 5:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 2, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 3, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 1:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 2:
|
|
case 6:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 3:
|
|
case 7:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 2, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 3, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
|
|
case 4:
|
|
DOBYTE(IAddr + 0, 0);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 1, 1);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 2, 2);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
DOBYTE(IAddr + 3, 3);
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
break;
|
|
}
|
|
|
|
#undef DOBYTE
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
for (mask = 1, p = &DMA[0], d = 0; mask; mask <<= 1, p++, d++)
|
|
{
|
|
if (byte & mask)
|
|
{
|
|
if (p->DoTransfer)
|
|
{
|
|
if (p->HDMAIndirectAddressing)
|
|
p->IndirectAddress += HDMA_ModeByteCounts[p->TransferMode];
|
|
else
|
|
p->Address += HDMA_ModeByteCounts[p->TransferMode];
|
|
}
|
|
|
|
p->DoTransfer = !p->Repeat;
|
|
|
|
if (!--p->LineCount)
|
|
{
|
|
if (!HDMAReadLineCount(d))
|
|
{
|
|
byte &= ~mask;
|
|
PPU.HDMAEnded |= mask;
|
|
p->DoTransfer = FALSE;
|
|
}
|
|
}
|
|
else
|
|
ADD_CYCLES(SLOW_ONE_CYCLE);
|
|
}
|
|
}
|
|
|
|
CPU.InHDMA = FALSE;
|
|
CPU.InDMAorHDMA = CPU.InDMA;
|
|
CPU.InWRAMDMAorHDMA = temp;
|
|
CPU.CurrentDMAorHDMAChannel = tmpch;
|
|
|
|
return (byte);
|
|
}
|
|
|
|
void S9xResetDMA (void)
|
|
{
|
|
for (int d = 0; d < 8; d++)
|
|
{
|
|
DMA[d].ReverseTransfer = TRUE;
|
|
DMA[d].HDMAIndirectAddressing = TRUE;
|
|
DMA[d].AAddressFixed = TRUE;
|
|
DMA[d].AAddressDecrement = TRUE;
|
|
DMA[d].TransferMode = 7;
|
|
DMA[d].BAddress = 0xff;
|
|
DMA[d].AAddress = 0xffff;
|
|
DMA[d].ABank = 0xff;
|
|
DMA[d].DMACount_Or_HDMAIndirectAddress = 0xffff;
|
|
DMA[d].IndirectBank = 0xff;
|
|
DMA[d].Address = 0xffff;
|
|
DMA[d].Repeat = FALSE;
|
|
DMA[d].LineCount = 0x7f;
|
|
DMA[d].UnknownByte = 0xff;
|
|
DMA[d].DoTransfer = FALSE;
|
|
DMA[d].UnusedBit43x0 = 1;
|
|
}
|
|
}
|