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372 lines
11 KiB
372 lines
11 KiB
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#ifndef _FXINST_H_
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#define _FXINST_H_
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/*
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* FxChip(GSU) register space specification
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* (Register address space 3000-32ff)
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*
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* The 16 generic 16 bit registers:
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* (Some have a special function in special circumstances)
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* 3000 - R0 default source/destination register
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* 3002 - R1 pixel plot X position register
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* 3004 - R2 pixel plot Y position register
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* 3006 - R3
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* 3008 - R4 lower 16 bit result of lmult
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* 300a - R5
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* 300c - R6 multiplier for fmult and lmult
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* 300e - R7 fixed point texel X position for merge
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* 3010 - R8 fixed point texel Y position for merge
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* 3012 - R9
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* 3014 - R10
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* 3016 - R11 return address set by link
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* 3018 - R12 loop counter
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* 301a - R13 loop point address
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* 301c - R14 rom address for getb, getbh, getbl, getbs
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* 301e - R15 program counter
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*
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* 3020-302f - unused
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*
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* Other internal registers
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* 3030 - SFR status flag register (16bit)
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* 3032 - unused
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* 3033 - BRAMR Backup RAM register (8bit)
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* 3034 - PBR program bank register (8bit)
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* 3035 - unused
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* 3036 - ROMBR rom bank register (8bit)
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* 3037 - CFGR control flags register (8bit)
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* 3038 - SCBR screen base register (8bit)
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* 3039 - CLSR clock speed register (8bit)
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* 303a - SCMR screen mode register (8bit)
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* 303b - VCR version code register (8bit) (read only)
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* 303c - RAMBR ram bank register (8bit)
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* 303d - unused
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* 303e - CBR cache base register (16bit)
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*
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* 3040-30ff - unused
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*
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* 3100-32ff - CACHERAM 512 bytes of GSU cache memory
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*
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* SFR status flag register bits:
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* 0 -
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* 1 Z Zero flag
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* 2 CY Carry flag
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* 3 S Sign flag
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* 4 OV Overflow flag
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* 5 G Go flag (set to 1 when the GSU is running)
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* 6 R Set to 1 when reading ROM using R14 address
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* 7 -
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* 8 ALT1 Mode set-up flag for the next instruction
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* 9 ALT2 Mode set-up flag for the next instruction
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* 10 IL Immediate lower 8-bit flag
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* 11 IH Immediate higher 8-bit flag
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* 12 B Set to 1 when the WITH instruction is executed
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* 13 -
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* 14 -
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* 15 IRQ Set to 1 when GSU caused an interrupt
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* Set to 0 when read by 658c16
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*
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* BRAMR = 0, BackupRAM is disabled
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* BRAMR = 1, BackupRAM is enabled
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*
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* CFGR control flags register bits:
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* 0 -
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* 1 -
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* 2 -
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* 3 -
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* 4 -
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* 5 MS0 Multiplier speed, 0=standard, 1=high speed
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* 6 -
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* 7 IRQ Set to 1 when GSU interrupt request is masked
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*
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* CLSR clock speed register bits:
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* 0 CLSR clock speed, 0 = 10.7Mhz, 1 = 21.4Mhz
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*
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* SCMR screen mode register bits:
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* 0 MD0 color depth mode bit 0
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* 1 MD1 color depth mode bit 1
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* 2 HT0 screen height bit 1
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* 3 RAN RAM access control
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* 4 RON ROM access control
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* 5 HT1 screen height bit 2
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* 6 -
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* 7 -
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*
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* RON = 0 SNES CPU has ROM access
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* RON = 1 GSU has ROM access
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*
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* RAN = 0 SNES has game pak RAM access
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* RAN = 1 GSU has game pak RAM access
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*
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* HT1 HT0 Screen height mode
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* 0 0 128 pixels high
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* 0 1 160 pixels high
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* 1 0 192 pixels high
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* 1 1 OBJ mode
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*
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* MD1 MD0 Color depth mode
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* 0 0 4 color mode
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* 0 1 16 color mode
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* 1 0 not used
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* 1 1 256 color mode
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*
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* CBR cache base register bits:
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* 15-4 Specify base address for data to cache from ROM or RAM
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* 3-0 Are 0 when address is read
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*
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* Write access to the program counter (301e) from
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* the SNES-CPU will start the GSU, and it will not
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* stop until it reaches a stop instruction.
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*
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*/
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// Number of banks in GSU RAM
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#define FX_RAM_BANKS 4
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// Emulate proper R14 ROM access (slower, but safer)
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#define FX_DO_ROMBUFFER
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// Address checking (definately slow)
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//#define FX_ADDRESS_CHECK
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struct FxRegs_s
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{
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// FxChip registers
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uint32 avReg[16]; // 16 Generic registers
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uint32 vColorReg; // Internal color register
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uint32 vPlotOptionReg; // Plot option register
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uint32 vStatusReg; // Status register
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uint32 vPrgBankReg; // Program bank index register
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uint32 vRomBankReg; // Rom bank index register
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uint32 vRamBankReg; // Ram bank index register
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uint32 vCacheBaseReg; // Cache base address register
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uint32 vCacheFlags; // Saying what parts of the cache was written to
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uint32 vLastRamAdr; // Last RAM address accessed
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uint32 *pvDreg; // Pointer to current destination register
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uint32 *pvSreg; // Pointer to current source register
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uint8 vRomBuffer; // Current byte read by R14
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uint8 vPipe; // Instructionset pipe
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uint32 vPipeAdr; // The address of where the pipe was read from
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// Status register optimization stuff
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uint32 vSign; // v & 0x8000
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uint32 vZero; // v == 0
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uint32 vCarry; // a value of 1 or 0
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int32 vOverflow; // (v >= 0x8000 || v < -0x8000)
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// Other emulator variables
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int32 vErrorCode;
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uint32 vIllegalAddress;
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uint8 bBreakPoint;
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uint32 vBreakPoint;
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uint32 vStepPoint;
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uint8 *pvRegisters; // 768 bytes located in the memory at address 0x3000
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uint32 nRamBanks; // Number of 64kb-banks in FxRam (Don't confuse it with SNES-Ram!!!)
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uint8 *pvRam; // Pointer to FxRam
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uint32 nRomBanks; // Number of 32kb-banks in Cart-ROM
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uint8 *pvRom; // Pointer to Cart-ROM
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uint32 vMode; // Color depth/mode
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uint32 vPrevMode; // Previous depth
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uint8 *pvScreenBase;
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uint8 *apvScreen[32]; // Pointer to each of the 32 screen colums
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int32 x[32];
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uint32 vScreenHeight; // 128, 160, 192 or 256 (could be overriden by cmode)
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uint32 vScreenRealHeight; // 128, 160, 192 or 256
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uint32 vPrevScreenHeight;
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uint32 vScreenSize;
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void (*pfPlot) (void);
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void (*pfRpix) (void);
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uint8 *pvRamBank; // Pointer to current RAM-bank
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uint8 *pvRomBank; // Pointer to current ROM-bank
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uint8 *pvPrgBank; // Pointer to current program ROM-bank
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uint8 *apvRamBank[FX_RAM_BANKS]; // Ram bank table (max 256kb)
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uint8 *apvRomBank[256]; // Rom bank table
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uint8 bCacheActive;
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uint8 *pvCache; // Pointer to the GSU cache
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uint8 avCacheBackup[512]; // Backup of ROM when the cache has replaced it
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uint32 vCounter;
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uint32 vInstCount;
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uint32 vSCBRDirty; // If SCBR is written, our cached screen pointers need updating
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uint8 *avRegAddr; // To reference avReg in snapshot.cpp
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};
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extern struct FxRegs_s GSU;
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// GSU registers
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#define GSU_R0 0x000
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#define GSU_R1 0x002
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#define GSU_R2 0x004
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#define GSU_R3 0x006
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#define GSU_R4 0x008
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#define GSU_R5 0x00a
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#define GSU_R6 0x00c
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#define GSU_R7 0x00e
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#define GSU_R8 0x010
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#define GSU_R9 0x012
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#define GSU_R10 0x014
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#define GSU_R11 0x016
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#define GSU_R12 0x018
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#define GSU_R13 0x01a
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#define GSU_R14 0x01c
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#define GSU_R15 0x01e
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#define GSU_SFR 0x030
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#define GSU_BRAMR 0x033
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#define GSU_PBR 0x034
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#define GSU_ROMBR 0x036
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#define GSU_CFGR 0x037
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#define GSU_SCBR 0x038
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#define GSU_CLSR 0x039
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#define GSU_SCMR 0x03a
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#define GSU_VCR 0x03b
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#define GSU_RAMBR 0x03c
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#define GSU_CBR 0x03e
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#define GSU_CACHERAM 0x100
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// SFR flags
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#define FLG_Z (1 << 1)
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#define FLG_CY (1 << 2)
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#define FLG_S (1 << 3)
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#define FLG_OV (1 << 4)
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#define FLG_G (1 << 5)
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#define FLG_R (1 << 6)
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#define FLG_ALT1 (1 << 8)
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#define FLG_ALT2 (1 << 9)
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#define FLG_IL (1 << 10)
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#define FLG_IH (1 << 11)
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#define FLG_B (1 << 12)
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#define FLG_IRQ (1 << 15)
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// Test flag
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#define TF(a) (GSU.vStatusReg & FLG_##a)
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#define CF(a) (GSU.vStatusReg &= ~FLG_##a)
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#define SF(a) (GSU.vStatusReg |= FLG_##a)
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// Test and set flag if condition, clear if not
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#define TS(a, b) GSU.vStatusReg = ((GSU.vStatusReg & (~FLG_##a)) | ((!!(##b)) * FLG_##a))
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// Testing ALT1 & ALT2 bits
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#define ALT0 (!TF(ALT1) && !TF(ALT2))
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#define ALT1 ( TF(ALT1) && !TF(ALT2))
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#define ALT2 (!TF(ALT1) && TF(ALT2))
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#define ALT3 ( TF(ALT1) && TF(ALT2))
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// Sign extend from 8/16 bit to 32 bit
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#define SEX8(a) ((int32) ((int8) (a)))
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#define SEX16(a) ((int32) ((int16) (a)))
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// Unsign extend from 8/16 bit to 32 bit
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#define USEX8(a) ((uint32) ((uint8) (a)))
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#define USEX16(a) ((uint32) ((uint16) (a)))
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#define SUSEX16(a) ((int32) ((uint16) (a)))
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// Set/Clr Sign and Zero flag
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#define TSZ(num) TS(S, ((num) & 0x8000)); TS(Z, (!USEX16(num)))
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// Clear flags
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#define CLRFLAGS GSU.vStatusReg &= ~(FLG_ALT1 | FLG_ALT2 | FLG_B); GSU.pvDreg = GSU.pvSreg = &R0
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// Read current RAM-Bank
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#define RAM(adr) GSU.pvRamBank[USEX16(adr)]
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// Read current ROM-Bank
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#define ROM(idx) GSU.pvRomBank[USEX16(idx)]
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// Access the current value in the pipe
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#define PIPE GSU.vPipe
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// Access data in the current program bank
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#define PRGBANK(idx) GSU.pvPrgBank[USEX16(idx)]
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// Update pipe from ROM
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#if 0
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#define FETCHPIPE { PIPE = PRGBANK(R15); GSU.vPipeAdr = (GSU.vPrgBankReg << 16) + R15; }
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#else
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#define FETCHPIPE { PIPE = PRGBANK(R15); }
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#endif
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// ABS
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#define ABS(x) ((x) < 0 ? -(x) : (x))
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// Access source register
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#define SREG (*GSU.pvSreg)
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// Access destination register
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#define DREG (*GSU.pvDreg)
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#ifndef FX_DO_ROMBUFFER
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// Don't read R14
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#define READR14
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// Don't test and/or read R14
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#define TESTR14
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#else
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// Read R14
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#define READR14 GSU.vRomBuffer = ROM(R14)
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// Test and/or read R14
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#define TESTR14 if (GSU.pvDreg == &R14) READR14
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#endif
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// Access to registers
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#define R0 GSU.avReg[0]
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#define R1 GSU.avReg[1]
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#define R2 GSU.avReg[2]
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#define R3 GSU.avReg[3]
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#define R4 GSU.avReg[4]
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#define R5 GSU.avReg[5]
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#define R6 GSU.avReg[6]
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#define R7 GSU.avReg[7]
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#define R8 GSU.avReg[8]
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#define R9 GSU.avReg[9]
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#define R10 GSU.avReg[10]
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#define R11 GSU.avReg[11]
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#define R12 GSU.avReg[12]
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#define R13 GSU.avReg[13]
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#define R14 GSU.avReg[14]
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#define R15 GSU.avReg[15]
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#define SFR GSU.vStatusReg
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#define PBR GSU.vPrgBankReg
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#define ROMBR GSU.vRomBankReg
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#define RAMBR GSU.vRamBankReg
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#define CBR GSU.vCacheBaseReg
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#define SCBR USEX8(GSU.pvRegisters[GSU_SCBR])
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#define SCMR USEX8(GSU.pvRegisters[GSU_SCMR])
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#define COLR GSU.vColorReg
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#define POR GSU.vPlotOptionReg
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#define BRAMR USEX8(GSU.pvRegisters[GSU_BRAMR])
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#define VCR USEX8(GSU.pvRegisters[GSU_VCR])
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#define CFGR USEX8(GSU.pvRegisters[GSU_CFGR])
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#define CLSR USEX8(GSU.pvRegisters[GSU_CLSR])
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// Execute instruction from the pipe, and fetch next byte to the pipe
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#define FX_STEP \
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{ \
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uint32 vOpcode = (uint32) PIPE; \
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FETCHPIPE; \
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(*fx_OpcodeTable[(GSU.vStatusReg & 0x300) | vOpcode])(); \
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}
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extern void (*fx_PlotTable[]) (void);
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extern void (*fx_OpcodeTable[]) (void);
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// Set this define if branches are relative to the instruction in the delay slot (I think they are)
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#define BRANCH_DELAY_RELATIVE
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#endif
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