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594 lines
16 KiB
594 lines
16 KiB
/*****************************************************************************\
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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This file is licensed under the Snes9x License.
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For further information, consult the LICENSE file in the root directory.
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\*****************************************************************************/
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#ifndef _PPU_H_
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#define _PPU_H_
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#define FIRST_VISIBLE_LINE 1
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#define TILE_2BIT 0
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#define TILE_4BIT 1
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#define TILE_8BIT 2
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#define TILE_2BIT_EVEN 3
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#define TILE_2BIT_ODD 4
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#define TILE_4BIT_EVEN 5
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#define TILE_4BIT_ODD 6
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#define MAX_2BIT_TILES 4096
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#define MAX_4BIT_TILES 2048
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#define MAX_8BIT_TILES 1024
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#define CLIP_OR 0
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#define CLIP_AND 1
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#define CLIP_XOR 2
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#define CLIP_XNOR 3
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struct ClipData
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{
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uint8 Count;
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uint8 DrawMode[6];
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uint16 Left[6];
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uint16 Right[6];
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};
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struct InternalPPU
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{
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struct ClipData Clip[2][6];
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bool8 ColorsChanged;
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bool8 OBJChanged;
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uint8 *TileCache[7];
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uint8 *TileCached[7];
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bool8 Interlace;
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bool8 InterlaceOBJ;
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bool8 PseudoHires;
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bool8 DoubleWidthPixels;
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bool8 DoubleHeightPixels;
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int CurrentLine;
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int PreviousLine;
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uint8 *XB;
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uint32 Red[256];
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uint32 Green[256];
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uint32 Blue[256];
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uint16 ScreenColors[256];
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uint8 MaxBrightness;
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bool8 RenderThisFrame;
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int RenderedScreenWidth;
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int RenderedScreenHeight;
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uint32 FrameCount;
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uint32 RenderedFramesCount;
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uint32 DisplayedRenderedFrameCount;
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uint32 TotalEmulatedFrames;
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uint32 SkippedFrames;
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uint32 FrameSkip;
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};
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struct SOBJ
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{
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int16 HPos;
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uint16 VPos;
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uint8 HFlip;
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uint8 VFlip;
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uint16 Name;
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uint8 Priority;
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uint8 Palette;
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uint8 Size;
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};
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struct SPPU
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{
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struct
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{
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bool8 High;
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uint8 Increment;
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uint16 Address;
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uint16 Mask1;
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uint16 FullGraphicCount;
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uint16 Shift;
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} VMA;
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uint32 WRAM;
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struct
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{
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uint16 SCBase;
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uint16 HOffset;
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uint16 VOffset;
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uint8 BGSize;
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uint16 NameBase;
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uint16 SCSize;
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} BG[4];
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uint8 BGMode;
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uint8 BG3Priority;
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bool8 CGFLIP;
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uint8 CGFLIPRead;
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uint8 CGADD;
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uint8 CGSavedByte;
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uint16 CGDATA[256];
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struct SOBJ OBJ[128];
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bool8 OBJThroughMain;
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bool8 OBJThroughSub;
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bool8 OBJAddition;
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uint16 OBJNameBase;
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uint16 OBJNameSelect;
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uint8 OBJSizeSelect;
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uint16 OAMAddr;
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uint16 SavedOAMAddr;
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uint8 OAMPriorityRotation;
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uint8 OAMFlip;
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uint8 OAMReadFlip;
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uint16 OAMTileAddress;
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uint16 OAMWriteRegister;
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uint8 OAMData[512 + 32];
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uint8 FirstSprite;
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uint8 LastSprite;
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uint8 RangeTimeOver;
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bool8 HTimerEnabled;
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bool8 VTimerEnabled;
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short HTimerPosition;
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short VTimerPosition;
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uint16 IRQHBeamPos;
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uint16 IRQVBeamPos;
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uint8 HBeamFlip;
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uint8 VBeamFlip;
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uint16 HBeamPosLatched;
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uint16 VBeamPosLatched;
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uint16 GunHLatch;
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uint16 GunVLatch;
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uint8 HVBeamCounterLatched;
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bool8 Mode7HFlip;
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bool8 Mode7VFlip;
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uint8 Mode7Repeat;
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short MatrixA;
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short MatrixB;
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short MatrixC;
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short MatrixD;
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short CentreX;
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short CentreY;
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short M7HOFS;
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short M7VOFS;
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uint8 Mosaic;
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uint8 MosaicStart;
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bool8 BGMosaic[4];
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uint8 Window1Left;
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uint8 Window1Right;
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uint8 Window2Left;
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uint8 Window2Right;
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bool8 RecomputeClipWindows;
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uint8 ClipCounts[6];
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uint8 ClipWindowOverlapLogic[6];
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uint8 ClipWindow1Enable[6];
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uint8 ClipWindow2Enable[6];
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bool8 ClipWindow1Inside[6];
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bool8 ClipWindow2Inside[6];
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bool8 ForcedBlanking;
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uint8 FixedColourRed;
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uint8 FixedColourGreen;
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uint8 FixedColourBlue;
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uint8 Brightness;
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uint16 ScreenHeight;
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bool8 Need16x8Mulitply;
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uint8 BGnxOFSbyte;
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uint8 M7byte;
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uint8 HDMA;
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uint8 HDMAEnded;
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uint8 OpenBus1;
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uint8 OpenBus2;
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uint16 VRAMReadBuffer;
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};
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extern uint16 SignExtend[2];
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extern struct SPPU PPU;
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extern struct InternalPPU IPPU;
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void S9xResetPPU (void);
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void S9xResetPPUFast (void);
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void S9xSoftResetPPU (void);
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void S9xSetPPU (uint8, uint16);
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uint8 S9xGetPPU (uint16);
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void S9xSetCPU (uint8, uint16);
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uint8 S9xGetCPU (uint16);
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void S9xUpdateIRQPositions (bool initial);
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void S9xFixColourBrightness (void);
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void S9xDoAutoJoypad (void);
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#include "gfx.h"
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#include "memmap.h"
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typedef struct
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{
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uint8 _5C77;
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uint8 _5C78;
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uint8 _5A22;
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} SnesModel;
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extern SnesModel *Model;
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extern SnesModel M1SNES;
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extern SnesModel M2SNES;
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#define MAX_5C77_VERSION 0x01
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#define MAX_5C78_VERSION 0x03
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#define MAX_5A22_VERSION 0x02
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void S9xUpdateScreen (void);
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static inline void FLUSH_REDRAW (void)
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{
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if (IPPU.PreviousLine != IPPU.CurrentLine)
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S9xUpdateScreen();
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}
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static inline void S9xUpdateVRAMReadBuffer()
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{
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if (PPU.VMA.FullGraphicCount)
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{
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uint32 addr = PPU.VMA.Address;
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uint32 rem = addr & PPU.VMA.Mask1;
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uint32 address = (addr & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3);
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PPU.VRAMReadBuffer = READ_WORD(Memory.VRAM + ((address << 1) & 0xffff));
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}
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else
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PPU.VRAMReadBuffer = READ_WORD(Memory.VRAM + ((PPU.VMA.Address << 1) & 0xffff));
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}
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static inline void REGISTER_2104 (uint8 Byte)
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{
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if (!(PPU.OAMFlip & 1))
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{
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PPU.OAMWriteRegister &= 0xff00;
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PPU.OAMWriteRegister |= Byte;
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}
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if (PPU.OAMAddr & 0x100)
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{
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int addr = ((PPU.OAMAddr & 0x10f) << 1) + (PPU.OAMFlip & 1);
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if (Byte != PPU.OAMData[addr])
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{
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FLUSH_REDRAW();
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PPU.OAMData[addr] = Byte;
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IPPU.OBJChanged = TRUE;
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// X position high bit, and sprite size (x4)
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struct SOBJ *pObj = &PPU.OBJ[(addr & 0x1f) * 4];
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pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 0) & 1];
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pObj++->Size = Byte & 2;
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pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 2) & 1];
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pObj++->Size = Byte & 8;
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pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 4) & 1];
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pObj++->Size = Byte & 32;
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pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(Byte >> 6) & 1];
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pObj->Size = Byte & 128;
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}
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}
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else if (PPU.OAMFlip & 1)
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{
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PPU.OAMWriteRegister &= 0x00ff;
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uint8 lowbyte = (uint8) (PPU.OAMWriteRegister);
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uint8 highbyte = Byte;
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PPU.OAMWriteRegister |= Byte << 8;
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int addr = (PPU.OAMAddr << 1);
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if (lowbyte != PPU.OAMData[addr] || highbyte != PPU.OAMData[addr + 1])
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{
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FLUSH_REDRAW();
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PPU.OAMData[addr] = lowbyte;
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PPU.OAMData[addr + 1] = highbyte;
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IPPU.OBJChanged = TRUE;
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if (addr & 2)
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{
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// Tile
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PPU.OBJ[addr = PPU.OAMAddr >> 1].Name = PPU.OAMWriteRegister & 0x1ff;
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// priority, h and v flip.
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PPU.OBJ[addr].Palette = (highbyte >> 1) & 7;
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PPU.OBJ[addr].Priority = (highbyte >> 4) & 3;
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PPU.OBJ[addr].HFlip = (highbyte >> 6) & 1;
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PPU.OBJ[addr].VFlip = (highbyte >> 7) & 1;
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}
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else
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{
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// X position (low)
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PPU.OBJ[addr = PPU.OAMAddr >> 1].HPos &= 0xff00;
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PPU.OBJ[addr].HPos |= lowbyte;
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// Sprite Y position
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PPU.OBJ[addr].VPos = highbyte;
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}
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}
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}
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PPU.OAMFlip ^= 1;
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if (!(PPU.OAMFlip & 1))
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{
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++PPU.OAMAddr;
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PPU.OAMAddr &= 0x1ff;
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if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1))
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{
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PPU.FirstSprite = (PPU.OAMAddr & 0xfe) >> 1;
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IPPU.OBJChanged = TRUE;
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}
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}
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else
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{
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if (PPU.OAMPriorityRotation && (PPU.OAMAddr & 1))
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IPPU.OBJChanged = TRUE;
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}
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}
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// This code is correct, however due to Snes9x's inaccurate timings, some games might be broken by this chage. :(
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#ifdef DEBUGGER
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#define CHECK_INBLANK() \
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if (!PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
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{ \
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printf("Invalid VRAM acess at (%04d, %04d) blank:%d\n", CPU.Cycles, CPU.V_Counter, PPU.ForcedBlanking); \
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if (Settings.BlockInvalidVRAMAccess) \
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{ \
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PPU.VMA.Address += !PPU.VMA.High ? PPU.VMA.Increment : 0; \
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return; \
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} \
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}
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#else
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#define CHECK_INBLANK() \
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if (Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
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{ \
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PPU.VMA.Address += !PPU.VMA.High ? PPU.VMA.Increment : 0; \
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return; \
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}
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#endif
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static inline void REGISTER_2118 (uint8 Byte)
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{
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CHECK_INBLANK();
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uint32 address;
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if (PPU.VMA.FullGraphicCount)
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{
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uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
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address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
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Memory.VRAM[address] = Byte;
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}
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else
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Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
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IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
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IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
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IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
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IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
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IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
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IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
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IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
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IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
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if (!PPU.VMA.High)
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{
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#ifdef DEBUGGER
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if (Settings.TraceVRAM && !CPU.InDMAorHDMA)
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printf("VRAM write byte: $%04X (%d, %d)\n", PPU.VMA.Address, Memory.FillRAM[0x2115] & 3, (Memory.FillRAM[0x2115] & 0x0c) >> 2);
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#endif
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PPU.VMA.Address += PPU.VMA.Increment;
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}
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}
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static inline void REGISTER_2118_tile (uint8 Byte)
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{
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CHECK_INBLANK();
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uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
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uint32 address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
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Memory.VRAM[address] = Byte;
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IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
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IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
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IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
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IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
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IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
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IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
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IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
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IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
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if (!PPU.VMA.High)
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PPU.VMA.Address += PPU.VMA.Increment;
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}
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static inline void REGISTER_2118_linear (uint8 Byte)
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{
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CHECK_INBLANK();
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uint32 address;
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Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
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IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
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IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
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IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
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IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
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IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
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IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
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IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
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IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
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IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
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if (!PPU.VMA.High)
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PPU.VMA.Address += PPU.VMA.Increment;
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}
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#undef CHECK_INBLANK
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#ifdef DEBUGGER
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#define CHECK_INBLANK() \
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if (!PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
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{ \
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printf("Invalid VRAM acess at (%04d, %04d) blank:%d\n", CPU.Cycles, CPU.V_Counter, PPU.ForcedBlanking); \
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if (Settings.BlockInvalidVRAMAccess) \
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{ \
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PPU.VMA.Address += PPU.VMA.High ? PPU.VMA.Increment : 0; \
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return; \
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} \
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}
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#else
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#define CHECK_INBLANK() \
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if (Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
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{ \
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PPU.VMA.Address += PPU.VMA.High ? PPU.VMA.Increment : 0; \
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return; \
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}
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#endif
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static inline void REGISTER_2119 (uint8 Byte)
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{
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CHECK_INBLANK();
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uint32 address;
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if (PPU.VMA.FullGraphicCount)
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{
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uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
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address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xffff;
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Memory.VRAM[address] = Byte;
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}
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else
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Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
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IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
|
|
|
if (PPU.VMA.High)
|
|
{
|
|
#ifdef DEBUGGER
|
|
if (Settings.TraceVRAM && !CPU.InDMAorHDMA)
|
|
printf("VRAM write word: $%04X (%d, %d)\n", PPU.VMA.Address, Memory.FillRAM[0x2115] & 3, (Memory.FillRAM[0x2115] & 0x0c) >> 2);
|
|
#endif
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
}
|
|
}
|
|
|
|
static inline void REGISTER_2119_tile (uint8 Byte)
|
|
{
|
|
CHECK_INBLANK();
|
|
|
|
uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
|
|
uint32 address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xffff;
|
|
|
|
Memory.VRAM[address] = Byte;
|
|
|
|
IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
|
|
|
if (PPU.VMA.High)
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
}
|
|
|
|
static inline void REGISTER_2119_linear (uint8 Byte)
|
|
{
|
|
CHECK_INBLANK();
|
|
|
|
uint32 address;
|
|
|
|
Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xffff] = Byte;
|
|
|
|
IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
|
|
IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
|
|
IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
|
|
|
if (PPU.VMA.High)
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
}
|
|
|
|
static inline void REGISTER_2122 (uint8 Byte)
|
|
{
|
|
if (PPU.CGFLIP)
|
|
{
|
|
if ((Byte & 0x7f) != (PPU.CGDATA[PPU.CGADD] >> 8) || PPU.CGSavedByte != (uint8) (PPU.CGDATA[PPU.CGADD] & 0xff))
|
|
{
|
|
FLUSH_REDRAW();
|
|
PPU.CGDATA[PPU.CGADD] = (Byte & 0x7f) << 8 | PPU.CGSavedByte;
|
|
IPPU.ColorsChanged = TRUE;
|
|
IPPU.Red[PPU.CGADD] = IPPU.XB[PPU.CGSavedByte & 0x1f];
|
|
IPPU.Blue[PPU.CGADD] = IPPU.XB[(Byte >> 2) & 0x1f];
|
|
IPPU.Green[PPU.CGADD] = IPPU.XB[(PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f];
|
|
IPPU.ScreenColors[PPU.CGADD] = (uint16) BUILD_PIXEL(IPPU.Red[PPU.CGADD], IPPU.Green[PPU.CGADD], IPPU.Blue[PPU.CGADD]);
|
|
}
|
|
|
|
PPU.CGADD++;
|
|
}
|
|
else
|
|
{
|
|
PPU.CGSavedByte = Byte;
|
|
}
|
|
|
|
PPU.CGFLIP ^= 1;
|
|
}
|
|
|
|
static inline void REGISTER_2180 (uint8 Byte)
|
|
{
|
|
Memory.RAM[PPU.WRAM++] = Byte;
|
|
PPU.WRAM &= 0x1ffff;
|
|
}
|
|
|
|
static inline uint8 REGISTER_4212 (void)
|
|
{
|
|
uint8 byte = 0;
|
|
|
|
if ((CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE) && (CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE + 3))
|
|
byte = 1;
|
|
if ((CPU.Cycles < Timings.HBlankEnd) || (CPU.Cycles >= Timings.HBlankStart))
|
|
byte |= 0x40;
|
|
if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE)
|
|
byte |= 0x80;
|
|
|
|
return (byte);
|
|
}
|
|
|
|
#endif
|