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707 lines
10 KiB
707 lines
10 KiB
case 0x7d: {
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op_io();
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regs.B.a = regs.x;
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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break;
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}
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case 0xdd: {
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op_io();
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regs.B.a = regs.B.y;
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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break;
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}
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case 0x5d: {
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op_io();
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regs.x = regs.B.a;
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regs.p.n = !!(regs.x & 0x80);
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regs.p.z = (regs.x == 0);
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break;
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}
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case 0xfd: {
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op_io();
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regs.B.y = regs.B.a;
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regs.p.n = !!(regs.B.y & 0x80);
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regs.p.z = (regs.B.y == 0);
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break;
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}
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case 0x9d: {
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op_io();
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regs.x = regs.sp;
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regs.p.n = !!(regs.x & 0x80);
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regs.p.z = (regs.x == 0);
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break;
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}
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case 0xbd: {
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op_io();
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regs.sp = regs.x;
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break;
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}
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case 0xe8: {
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regs.B.a = op_readpc();
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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break;
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}
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case 0xcd: {
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regs.x = op_readpc();
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regs.p.n = !!(regs.x & 0x80);
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regs.p.z = (regs.x == 0);
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break;
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}
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case 0x8d: {
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regs.B.y = op_readpc();
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regs.p.n = !!(regs.B.y & 0x80);
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regs.p.z = (regs.B.y == 0);
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break;
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}
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case 0xe6: {
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switch(++opcode_cycle) {
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case 1:
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op_io();
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break;
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case 2:
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regs.B.a = op_readdp(regs.x);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xbf: {
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switch(++opcode_cycle) {
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case 1:
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op_io();
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break;
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case 2:
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regs.B.a = op_readdp(regs.x++);
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op_io();
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xe4: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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break;
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case 2:
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regs.B.a = op_readdp(sp);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xf8: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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break;
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case 2:
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regs.x = op_readdp(sp);
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regs.p.n = !!(regs.x & 0x80);
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regs.p.z = (regs.x == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xeb: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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break;
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case 2:
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regs.B.y = op_readdp(sp);
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regs.p.n = !!(regs.B.y & 0x80);
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regs.p.z = (regs.B.y == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xf4: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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op_io();
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break;
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case 2:
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regs.B.a = op_readdp(sp + regs.x);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xf9: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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op_io();
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break;
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case 2:
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regs.x = op_readdp(sp + regs.B.y);
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regs.p.n = !!(regs.x & 0x80);
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regs.p.z = (regs.x == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xfb: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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op_io();
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break;
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case 2:
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regs.B.y = op_readdp(sp + regs.x);
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regs.p.n = !!(regs.B.y & 0x80);
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regs.p.z = (regs.B.y == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xe5: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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break;
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case 2:
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sp |= op_readpc() << 8;
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break;
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case 3:
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regs.B.a = op_readaddr(sp);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xe9: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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sp |= op_readpc() << 8;
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break;
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case 2:
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regs.x = op_readaddr(sp);
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regs.p.n = !!(regs.x & 0x80);
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regs.p.z = (regs.x == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xec: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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sp |= op_readpc() << 8;
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break;
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case 2:
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regs.B.y = op_readaddr(sp);
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regs.p.n = !!(regs.B.y & 0x80);
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regs.p.z = (regs.B.y == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xf5: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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sp |= op_readpc() << 8;
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op_io();
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break;
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case 2:
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regs.B.a = op_readaddr(sp + regs.x);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xf6: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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sp |= op_readpc() << 8;
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op_io();
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break;
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case 2:
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regs.B.a = op_readaddr(sp + regs.B.y);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xe7: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc() + regs.x;
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op_io();
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break;
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case 2:
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sp = op_readdp(dp);
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break;
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case 3:
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sp |= op_readdp(dp + 1) << 8;
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break;
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case 4:
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regs.B.a = op_readaddr(sp);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xf7: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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op_io();
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break;
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case 2:
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sp = op_readdp(dp);
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break;
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case 3:
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sp |= op_readdp(dp + 1) << 8;
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break;
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case 4:
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regs.B.a = op_readaddr(sp + regs.B.y);
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regs.p.n = !!(regs.B.a & 0x80);
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regs.p.z = (regs.B.a == 0);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xfa: {
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switch(++opcode_cycle) {
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case 1:
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sp = op_readpc();
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break;
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case 2:
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rd = op_readdp(sp);
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break;
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case 3:
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dp = op_readpc();
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break;
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case 4:
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op_writedp(dp, rd);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0x8f: {
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switch(++opcode_cycle) {
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case 1:
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rd = op_readpc();
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dp = op_readpc();
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break;
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case 2:
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op_readdp(dp);
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break;
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case 3:
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op_writedp(dp, rd);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xc6: {
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switch(++opcode_cycle) {
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case 1:
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op_io();
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break;
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case 2:
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op_readdp(regs.x);
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break;
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case 3:
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op_writedp(regs.x, regs.B.a);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xaf: {
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switch(++opcode_cycle) {
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case 1:
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op_io(2);
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break;
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case 2:
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op_writedp(regs.x++, regs.B.a);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xc4: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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break;
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case 2:
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op_readdp(dp);
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break;
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case 3:
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op_writedp(dp, regs.B.a);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xd8: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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break;
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case 2:
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op_readdp(dp);
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break;
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case 3:
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op_writedp(dp, regs.x);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xcb: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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break;
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case 2:
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op_readdp(dp);
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break;
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case 3:
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op_writedp(dp, regs.B.y);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xd4: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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op_io();
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dp += regs.x;
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break;
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case 2:
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op_readdp(dp);
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break;
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case 3:
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op_writedp(dp, regs.B.a);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xd9: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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op_io();
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dp += regs.B.y;
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break;
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case 2:
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op_readdp(dp);
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break;
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case 3:
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op_writedp(dp, regs.x);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xdb: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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op_io();
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dp += regs.x;
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break;
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case 2:
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op_readdp(dp);
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break;
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case 3:
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op_writedp(dp, regs.B.y);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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case 0xc5: {
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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break;
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case 2:
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dp |= op_readpc() << 8;
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break;
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case 3:
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op_readaddr(dp);
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break;
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case 4:
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op_writeaddr(dp, regs.B.a);
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opcode_cycle = 0;
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break;
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}
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break;
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}
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|
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case 0xc9: {
|
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switch(++opcode_cycle) {
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case 1:
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dp = op_readpc();
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break;
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case 2:
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dp |= op_readpc() << 8;
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break;
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case 3:
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op_readaddr(dp);
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break;
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case 4:
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op_writeaddr(dp, regs.x);
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opcode_cycle = 0;
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break;
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}
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break;
|
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}
|
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|
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case 0xcc: {
|
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switch(++opcode_cycle) {
|
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case 1:
|
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dp = op_readpc();
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break;
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case 2:
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dp |= op_readpc() << 8;
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break;
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case 3:
|
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op_readaddr(dp);
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break;
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case 4:
|
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op_writeaddr(dp, regs.B.y);
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opcode_cycle = 0;
|
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break;
|
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}
|
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break;
|
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}
|
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|
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case 0xd5: {
|
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switch(++opcode_cycle) {
|
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case 1:
|
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dp = op_readpc();
|
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dp |= op_readpc() << 8;
|
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op_io();
|
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dp += regs.x;
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break;
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case 2:
|
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op_readaddr(dp);
|
|
break;
|
|
case 3:
|
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op_writeaddr(dp, regs.B.a);
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opcode_cycle = 0;
|
|
break;
|
|
}
|
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break;
|
|
}
|
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|
|
case 0xd6: {
|
|
switch(++opcode_cycle) {
|
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case 1:
|
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dp = op_readpc();
|
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dp |= op_readpc() << 8;
|
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op_io();
|
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dp += regs.B.y;
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break;
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case 2:
|
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op_readaddr(dp);
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break;
|
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case 3:
|
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op_writeaddr(dp, regs.B.a);
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opcode_cycle = 0;
|
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break;
|
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}
|
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break;
|
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}
|
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|
|
case 0xc7: {
|
|
switch(++opcode_cycle) {
|
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case 1:
|
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sp = op_readpc();
|
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op_io();
|
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sp += regs.x;
|
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break;
|
|
case 2:
|
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dp = op_readdp(sp);
|
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break;
|
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case 3:
|
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dp |= op_readdp(sp + 1) << 8;
|
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break;
|
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case 4:
|
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op_readaddr(dp);
|
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break;
|
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case 5:
|
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op_writeaddr(dp, regs.B.a);
|
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opcode_cycle = 0;
|
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break;
|
|
}
|
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break;
|
|
}
|
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|
|
case 0xd7: {
|
|
switch(++opcode_cycle) {
|
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case 1:
|
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sp = op_readpc();
|
|
break;
|
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case 2:
|
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dp = op_readdp(sp);
|
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break;
|
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case 3:
|
|
dp |= op_readdp(sp + 1) << 8;
|
|
op_io();
|
|
dp += regs.B.y;
|
|
break;
|
|
case 4:
|
|
op_readaddr(dp);
|
|
break;
|
|
case 5:
|
|
op_writeaddr(dp, regs.B.a);
|
|
opcode_cycle = 0;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0xba: {
|
|
switch(++opcode_cycle) {
|
|
case 1:
|
|
sp = op_readpc();
|
|
break;
|
|
case 2:
|
|
regs.B.a = op_readdp(sp);
|
|
op_io();
|
|
break;
|
|
case 3:
|
|
regs.B.y = op_readdp(sp + 1);
|
|
regs.p.n = !!(regs.ya & 0x8000);
|
|
regs.p.z = (regs.ya == 0);
|
|
opcode_cycle = 0;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0xda: {
|
|
switch(++opcode_cycle) {
|
|
case 1:
|
|
dp = op_readpc();
|
|
break;
|
|
case 2:
|
|
op_readdp(dp);
|
|
break;
|
|
case 3:
|
|
op_writedp(dp, regs.B.a);
|
|
break;
|
|
case 4:
|
|
op_writedp(dp + 1, regs.B.y);
|
|
opcode_cycle = 0;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0xaa: {
|
|
switch(++opcode_cycle) {
|
|
case 1:
|
|
sp = op_readpc();
|
|
sp |= op_readpc() << 8;
|
|
break;
|
|
case 2:
|
|
bit = sp >> 13;
|
|
sp &= 0x1fff;
|
|
rd = op_readaddr(sp);
|
|
regs.p.c = !!(rd & (1 << bit));
|
|
opcode_cycle = 0;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0xca: {
|
|
switch(++opcode_cycle) {
|
|
case 1:
|
|
dp = op_readpc();
|
|
dp |= op_readpc() << 8;
|
|
break;
|
|
case 2:
|
|
bit = dp >> 13;
|
|
dp &= 0x1fff;
|
|
rd = op_readaddr(dp);
|
|
if(regs.p.c)rd |= (1 << bit);
|
|
else rd &= ~(1 << bit);
|
|
op_io();
|
|
break;
|
|
case 3:
|
|
op_writeaddr(dp, rd);
|
|
opcode_cycle = 0;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|