John Doe
3 years ago
parent
11650b6d8a
commit
20ad0b5950
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#pragma once
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#include <vmutils.hpp>
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namespace vm::instrs {
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/// <summary>
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/// mnemonic representation of supported virtual instructions...
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/// </summary>
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enum class mnemonic_t {
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unknown,
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sreg,
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lreg,
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lconst,
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add,
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div,
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idiv,
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mul,
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imul,
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nand,
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read,
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write,
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shl,
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shld,
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shr,
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shrd,
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lvsp,
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svsp,
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writecr3,
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readcr3,
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writecr8,
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readcr8,
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cpuid,
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rdtsc,
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call,
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jmp,
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vmexit
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};
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/// <summary>
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/// the main virtual instruction structure which is returned by profilers...
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/// </summary>
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struct vinstr_t {
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/// <summary>
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/// mnemonic of the virtual instruction...
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/// </summary>
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mnemonic_t mnemonic;
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/// <summary>
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/// size varient of the virtual instruction... I.E SREGQ would have a value of
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/// "64" here...where the SREGDW varient would have a "32" here...
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/// </summary>
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u8 size;
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struct {
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/// <summary>
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/// true if the virtual instruction has an imm false if not...
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/// </summary>
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bool has_imm;
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/// <summary>
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/// size in bits of the imm... 8, 16, 32, 64...
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/// </summary>
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u8 size;
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/// <summary>
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/// imm value...
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/// </summary>
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u64 val;
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} imm;
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};
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/// <summary>
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/// matcher function which returns true if an instruction matches a desired
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/// one...
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/// </summary>
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using matcher_t = std::function<bool(const zydis_reg_t vip,
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const zydis_reg_t vsp,
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const zydis_decoded_instr_t& instr)>;
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/// <summary>
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/// virtual instruction structure generator... this can update the vip and vsp
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/// argument... it cannot update the instruction stream (hndlr)...
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/// </summary>
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using vinstr_gen_t = std::function<std::optional<vinstr_t>(zydis_reg_t& vip,
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zydis_reg_t& vsp,
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zydis_rtn_t& hndlr)>;
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/// <summary>
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/// each virtual instruction has its own profiler_t structure which can generate
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/// all varients of the virtual instruction for each size...
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/// </summary>
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struct profiler_t {
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/// <summary>
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/// string name of the virtual instruction that this profile generates for...
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/// </summary>
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std::string name;
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/// <summary>
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/// mnemonic representation of the virtual instruction...
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/// </summary>
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mnemonic_t mnemonic;
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/// <summary>
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/// vector of matcher lambda's which return true if a given instruction
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/// matches...
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/// </summary>
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std::vector<matcher_t> matchers;
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/// <summary>
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/// generates a virtual instruction structure...
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/// </summary>
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vinstr_gen_t generate;
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};
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extern profiler_t jmp;
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inline std::vector<profiler_t*> profiles = {&jmp};
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inline vinstr_t determine(zydis_reg_t& vip,
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zydis_reg_t& vsp,
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zydis_rtn_t& hndlr) {
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const auto profile = std::find_if(
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profiles.begin(), profiles.end(), [&](profiler_t* profile) -> bool {
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for (auto& matcher : profile->matchers) {
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const auto matched = std::find_if(hndlr.begin(), hndlr.end(),
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[&](zydis_instr_t& instr) -> bool {
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const auto& i = instr.instr;
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return matcher(vip, vsp, i);
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});
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if (matched == hndlr.end())
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return false;
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}
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return true;
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});
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if (profile == profiles.end())
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return vinstr_t{mnemonic_t::unknown};
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auto result = (*profile)->generate(vip, vsp, hndlr);
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return result.has_value() ? result.value() : vinstr_t{mnemonic_t::unknown};
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}
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} // namespace vm::instrs
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@ -1,4 +1,5 @@
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#pragma once
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#include <vmctx.hpp>
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#include <vmlocate.hpp>
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#include <vmutils.hpp>
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#include <vmutils.hpp>
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#include <vminstrs.hpp>
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@ -0,0 +1,127 @@
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#include <vminstrs.hpp>
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namespace vm::instrs {
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profiler_t jmp = {
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"JMP",
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mnemonic_t::jmp,
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// MOV REG, [VSP]
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{{[&](const zydis_reg_t vip,
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const zydis_reg_t vsp,
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const zydis_decoded_instr_t& instr) -> bool {
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return instr.mnemonic == ZYDIS_MNEMONIC_MOV &&
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instr.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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instr.operands[1].type == ZYDIS_OPERAND_TYPE_MEMORY &&
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instr.operands[1].mem.base == vsp;
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},
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// ADD VSP, 8
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[&](const zydis_reg_t vip,
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const zydis_reg_t vsp,
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const zydis_decoded_instr_t& instr) -> bool {
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return instr.mnemonic == ZYDIS_MNEMONIC_ADD &&
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instr.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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instr.operands[0].reg.value == vsp &&
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instr.operands[1].type == ZYDIS_OPERAND_TYPE_IMMEDIATE &&
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instr.operands[1].imm.value.u == 8;
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},
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// MOV VIP, REG
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[&](const zydis_reg_t vip,
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const zydis_reg_t vsp,
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const zydis_decoded_instr_t& instr) -> bool {
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return instr.mnemonic == ZYDIS_MNEMONIC_MOV &&
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instr.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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instr.operands[0].reg.value == vip &&
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instr.operands[1].type == ZYDIS_OPERAND_TYPE_REGISTER;
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}}},
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[&](zydis_reg_t& vip,
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zydis_reg_t& vsp,
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zydis_rtn_t& hndlr) -> std::optional<vinstr_t> {
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const auto xchg = std::find_if(
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hndlr.begin(), hndlr.end(), [&](const zydis_instr_t& instr) -> bool {
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const auto& i = instr.instr;
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return i.mnemonic == ZYDIS_MNEMONIC_XCHG &&
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i.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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// exclusive or... operand 1 or operand 2 can be VSP but they
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// both cannot be...
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((i.operands[1].reg.value == vsp ||
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i.operands[0].reg.value == vsp) &&
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!((i.operands[1].reg.value == vsp) &&
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(i.operands[0].reg.value == vsp)));
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});
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// this JMP virtual instruction changes VSP as well as VIP...
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if (xchg != hndlr.end()) {
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// grab the register that isnt VSP in the XCHG...
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// xchg reg, vsp or xchg vsp, reg...
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zydis_reg_t write_dep = xchg->instr.operands[0].reg.value != vsp
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? xchg->instr.operands[0].reg.value
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: xchg->instr.operands[1].reg.value;
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// update VIP... VSP becomes VIP... with the XCHG...
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vip = xchg->instr.operands[0].reg.value != vsp
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? xchg->instr.operands[1].reg.value
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: xchg->instr.operands[0].reg.value;
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// find the next MOV REG, write_dep... this REG will be VSP...
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const auto mov_reg_write_dep = std::find_if(
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xchg, hndlr.end(), [&](const zydis_instr_t& instr) -> bool {
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const auto& i = instr.instr;
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return i.mnemonic == ZYDIS_MNEMONIC_MOV &&
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i.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].reg.value == write_dep;
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});
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if (mov_reg_write_dep == hndlr.end())
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return {};
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vsp = mov_reg_write_dep->instr.operands[0].reg.value;
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} else {
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// find the MOV REG, [VSP] instruction...
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const auto mov_reg_deref_vsp = std::find_if(
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hndlr.begin(), hndlr.end(),
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[&](const zydis_instr_t& instr) -> bool {
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const auto& i = instr.instr;
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return i.mnemonic == ZYDIS_MNEMONIC_MOV &&
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i.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].type == ZYDIS_OPERAND_TYPE_MEMORY &&
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i.operands[1].mem.base == vsp;
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});
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if (mov_reg_deref_vsp == hndlr.end())
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return {};
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// find the MOV REG, mov_reg_deref_vsp->operands[0].reg.value
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const auto mov_vip_reg = std::find_if(
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mov_reg_deref_vsp, hndlr.end(),
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[&](const zydis_instr_t& instr) -> bool {
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const auto& i = instr.instr;
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return i.mnemonic == ZYDIS_MNEMONIC_MOV &&
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i.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].reg.value ==
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mov_reg_deref_vsp->instr.operands[0].reg.value;
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});
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if (mov_vip_reg == hndlr.end())
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return {};
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vip = mov_vip_reg->instr.operands[0].reg.value;
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// see if VSP gets updated as well...
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const auto mov_reg_vsp = std::find_if(
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mov_reg_deref_vsp, hndlr.end(),
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[&](const zydis_instr_t& instr) -> bool {
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const auto& i = instr.instr;
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return i.mnemonic == ZYDIS_MNEMONIC_MOV &&
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i.operands[0].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].type == ZYDIS_OPERAND_TYPE_REGISTER &&
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i.operands[1].reg.value == vsp;
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});
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if (mov_reg_vsp != hndlr.end())
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vsp = mov_reg_vsp->instr.operands[0].reg.value;
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}
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return vinstr_t{mnemonic_t::jmp};
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}};
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}
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