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@ -8638,6 +8638,10 @@ typedef union
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#define IA32_MTRR_PHYSBASE7 0x0000020E
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#define IA32_MTRR_PHYSBASE7 0x0000020E
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#define IA32_MTRR_PHYSBASE8 0x00000210
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#define IA32_MTRR_PHYSBASE8 0x00000210
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#define IA32_MTRR_PHYSBASE9 0x00000212
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#define IA32_MTRR_PHYSBASE9 0x00000212
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#define IA32_MTRR_PHYSBASEN(n) \
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IA32_MTRR_PHYSBASE0 + (n * 2)
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/**
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/**
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* @}
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* @}
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*/
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*/
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@ -8697,7 +8701,7 @@ typedef union
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uint64_t flags;
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uint64_t flags;
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} ia32_mtrr_physmask_register;
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} ia32_mtrr_physmask_register;
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#define IA32_MTRR_PHYSMASK0 0x00000201
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#define IA32_MTRR_PHYSMASK0 0x00000201
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#define IA32_MTRR_PHYSMASK1 0x00000203
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#define IA32_MTRR_PHYSMASK1 0x00000203
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#define IA32_MTRR_PHYSMASK2 0x00000205
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#define IA32_MTRR_PHYSMASK2 0x00000205
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@ -8708,6 +8712,10 @@ typedef union
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#define IA32_MTRR_PHYSMASK7 0x0000020F
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#define IA32_MTRR_PHYSMASK7 0x0000020F
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#define IA32_MTRR_PHYSMASK8 0x00000211
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#define IA32_MTRR_PHYSMASK8 0x00000211
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#define IA32_MTRR_PHYSMASK9 0x00000213
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#define IA32_MTRR_PHYSMASK9 0x00000213
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#define IA32_MTRR_PHYSMASKN(n) \
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IA32_MTRR_PHYSMASK0 + (n * 2)
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/**
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/**
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* @}
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* @}
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*/
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*/
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