init commit

.appveyor.yml

@@ -0,0 +1,14 @@
+version: 4.0-{build}
+
+os:
+  - Visual Studio 2015
+
+before_build:
+  - call "C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\vcvarsall.bat" amd64
+
+build_script:
+  - mkdir build
+  - cd build
+  - cmake -DCMAKE_BUILD_TYPE=RELEASE -G "NMake Makefiles" ..
+  - nmake
+

.gitattributes

@@ -0,0 +1 @@
+/arch/**/*.inc linguist-language=C

.github/workflows/coverity-scan.yml

@@ -0,0 +1,41 @@
+name: coverity-scan
+on:
+  schedule:
+    - cron: '0 18 * * 1,4' # Bi-weekly at 18:00 UTC on Monday and Thursday
+
+jobs:
+  latest:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v1
+      - name: Download Coverity Build Tool
+        run: |
+          wget -q https://scan.coverity.com/download/cxx/linux64 --post-data "token=$TOKEN&project=capstone-next" -O cov-analysis-linux64.tar.gz
+          mkdir cov-analysis-linux64
+          tar xzf cov-analysis-linux64.tar.gz --strip 1 -C cov-analysis-linux64
+        env:
+          TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+
+      - name: Fixed world writable dirs
+        run: |
+          chmod go-w $HOME
+          sudo chmod -R go-w /usr/share
+          
+      - name: Build with cov-build
+        run: |
+          export PATH=`pwd`/cov-analysis-linux64/bin:$PATH
+          cov-build --dir cov-int make
+
+      - name: Submit the result to Coverity Scan
+        run: |
+          tar czvf capstone.tgz cov-int
+          curl \
+            --form project=capstone-next \
+            --form token=$TOKEN \
+            --form email=noreply@capstone-engine.org \
+            --form file=@capstone.tgz \
+            --form version=trunk \
+            --form description="capstone" \
+            https://scan.coverity.com/builds?project=capstone-next
+        env:
+          TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}

.github/workflows/fuzz.yml

@@ -0,0 +1,23 @@
+name: CIFuzz
+on: [pull_request]
+jobs:
+  Fuzzing:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Build Fuzzers
+      uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master
+      with:
+        oss-fuzz-project-name: 'capstone'
+        dry-run: false
+    - name: Run Fuzzers
+      uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master
+      with:
+        oss-fuzz-project-name: 'capstone'
+        fuzz-seconds: 600
+        dry-run: false
+    - name: Upload Crash
+      uses: actions/upload-artifact@v1
+      if: failure()
+      with:
+        name: artifacts
+        path: ./out/artifacts

.github/workflows/python-publish.yml

@@ -0,0 +1,80 @@
+name: PyPI 📦 Distribution
+
+on: [push]
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      fail-fast: false
+      matrix:
+        os: [macos-latest, ubuntu-latest, windows-latest]
+        platform: [x32, x64]
+    steps:
+    - uses: actions/checkout@v2
+
+    - name: Set up Python
+      uses: actions/setup-python@v2
+      with:
+        python-version: '3.x'
+
+    - name: Set up MSVC x86
+      if: matrix.os == 'windows-latest' && matrix.platform == 'x32'
+      uses: ilammy/msvc-dev-cmd@v1
+      with:
+        arch: x86
+
+    - name: Set up MSVC x64
+      if: matrix.os == 'windows-latest' && matrix.platform == 'x64'
+      uses: ilammy/msvc-dev-cmd@v1
+
+    - name: Install dependencies
+      run: |
+        pip install setuptools wheel
+
+    - name: Build distribution 📦
+      shell: bash 
+      run: |
+        if [ ${{ matrix.platform }} == 'x32' ] && [ ${{ matrix.os }} == 'windows-latest' ]; then
+             cd bindings/python && python setup.py build -p win32 bdist_wheel -p win32
+        elif [ ${{ matrix.platform }} == 'x32' ] && [ ${{ matrix.os }} == 'ubuntu-latest' ]; then
+             docker run --rm -v `pwd`/:/work dockcross/manylinux1-x86 > ./dockcross
+             chmod +x ./dockcross
+             ./dockcross bindings/python/build_wheel.sh
+        elif [ ${{ matrix.platform }} == 'x64' ] && [ ${{ matrix.os }} == 'ubuntu-latest' ]; then
+             docker run --rm -v `pwd`/:/work dockcross/manylinux1-x64 > ./dockcross
+             chmod +x ./dockcross
+             ./dockcross bindings/python/build_wheel.sh
+        elif [ ${{ matrix.platform }} == 'x32' ] && [ ${{ matrix.os }} == 'macos-latest' ]; then
+             cd bindings/python && python setup.py sdist
+        else
+             cd bindings/python && python setup.py bdist_wheel
+        fi
+
+    - uses: actions/upload-artifact@v2
+      with:
+         path: ${{ github.workspace }}/bindings/python/dist/*
+
+  publish:
+    needs: [build]
+    runs-on: ubuntu-latest
+    if: startsWith(github.ref, 'refs/tags')
+    steps:
+      - uses: actions/download-artifact@v2
+        with:
+          name: artifact
+          path: dist
+
+      - name: Publish distribution 📦 to test PyPI
+        uses: pypa/gh-action-pypi-publish@master
+        with:
+          user: __token__
+          password: ${{ secrets.testpypi_pass }}
+          repository_url: https://test.pypi.org/legacy/
+
+      - name: Publish distribution 📦 to PyPI
+        if: ${{ success() }}
+        uses: pypa/gh-action-pypi-publish@master
+        with:
+          user: __token__
+          password: ${{ secrets.pypi_pass }}

.gitignore

@@ -0,0 +1,124 @@
+.DS_Store
+
+# Object files
+*.o
+*.ko
+
+# Gcc dependency-tracking files
+*.d
+
+# Libraries
+*.lib
+*.a
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+*.so
+*.so.*
+*.dylib
+
+# Executables
+*.exe
+*.out
+*.app
+
+# python
+bindings/python/build/
+bindings/python/capstone.egg-info/
+*.pyc
+
+# java
+bindings/java/capstone.jar
+
+# ocaml
+bindings/ocaml/*.cmi
+bindings/ocaml/*.cmx
+bindings/ocaml/*.cmxa
+bindings/ocaml/*.mli
+bindings/ocaml/test
+bindings/ocaml/test_arm
+bindings/ocaml/test_arm64
+bindings/ocaml/test_basic
+bindings/ocaml/test_mips
+bindings/ocaml/test_x86
+bindings/ocaml/test_detail
+bindings/ocaml/test_ppc
+bindings/ocaml/test_sparc
+bindings/ocaml/test_systemz
+bindings/ocaml/test_xcore
+bindings/ocaml/test_m680x
+
+
+# test binaries
+tests/test_basic
+tests/test_detail
+tests/test_iter
+tests/test_arm
+tests/test_arm64
+tests/test_mips
+tests/test_x86
+tests/test_ppc
+tests/test_skipdata
+tests/test_sparc
+tests/test_systemz
+tests/test_xcore
+tests/*.static
+tests/test_customized_mnem
+tests/test_m68k
+tests/test_tms320c64x
+tests/test_m680x
+tests/test_evm
+tests/test_mos65xx
+
+# regress binaries
+suite/regress/invalid_read_in_print_operand
+
+# vim tmp file
+*.swp
+*~
+
+capstone.pc
+
+# local files
+_*
+
+# freebsd ports: generated file with "make makesum" command
+packages/freebsd/ports/devel/capstone/distinfo
+
+# VisualStudio
+ProjectUpgradeLog.log
+Debug/
+Release/
+ipch/
+build*/
+*.sdf
+*.opensdf
+*.suo
+*.user
+*.backup
+*.VC.db
+*.VC.opendb
+
+# CMake build directories
+build*/
+
+# Xcode
+xcode/Capstone.xcodeproj/xcuserdata
+xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
+
+# suite/
+test_arm_regression
+test_arm_regression.o
+fuzz_harness
+test_iter_benchmark
+fuzz_bindisasm
+fuzz_disasm
+capstone_get_setup
+
+
+*.s
+
+cstool/cstool
+
+# android
+android-ndk-*

.travis.yml

@@ -0,0 +1,75 @@
+language: cpp
+sudo: false
+before_install:
+        - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
+before_script:
+        - wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip
+        - unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz
+        # TODO remove built in cmocka compile and use system cmocka (including brewfile) once xenial is default
+        - git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka
+        - chmod +x suite/cstest/build_cstest.sh
+script:
+        - ./make.sh
+        - make check
+        - sudo make install
+        - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi
+        - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi
+        - if [[ "$NOPYTEST" != "true" ]]; then cd bindings/python && make check; cd ../..; fi
+        - if [[ "$NOPYTEST" != "true" ]]; then cd suite/cstest && ./build_cstest.sh; fi
+        - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -d ../MC; fi
+        - if [[ "$NOPYTEST" != "true" ]]; then python cstest_report.py -D -t build/cstest -f issues.cs; fi
+compiler:
+        - clang
+        - gcc
+os:
+        - linux
+        - osx
+matrix:
+    include:
+        - name: xenial gcc
+          os: linux
+          dist: xenial
+          compiler: gcc
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+        - name: bionic gcc (ARM64)
+          arch: arm64
+          os: linux
+          dist: bionic
+          compiler: gcc
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+                - unzip
+        - name: bionic gcc (System Z)
+          arch: s390x
+          os: linux
+          dist: bionic
+          compiler: gcc
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+        - name: xenial clang
+          os: linux
+          dist: xenial
+          compiler: clang
+          addons:
+            apt:
+              packages:
+                - libcmocka-dev
+        - name: fuzza
+          env: ASAN_OPTIONS=detect_leaks=0 CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=address" LDFLAGS="-fsanitize=address" NOPYTEST=true
+          compiler: clang
+          os: linux
+        - name: fuzzm
+          env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=memory" LDFLAGS="-fsanitize=memory" NOPYTEST=true
+          compiler: clang
+          os: linux
+        - name: fuzzu
+          env: CXXFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined" CFLAGS="-DFUZZING_BUILD_MODE_UNSAFE_FOR_PRODUCTION -fsanitize=undefined -fno-sanitize-recover=undefined,integer" LDFLAGS="-fsanitize=undefined" NOPYTEST=true
+          compiler: clang
+          os: linux

CMakeLists.txt

@@ -0,0 +1,629 @@
+cmake_minimum_required(VERSION 2.6)
+project(capstone)
+
+set(VERSION_MAJOR 5)
+set(VERSION_MINOR 0)
+set(VERSION_PATCH 0)
+
+if(POLICY CMP0042)
+  # http://www.cmake.org/cmake/help/v3.0/policy/CMP0042.html
+  cmake_policy(SET CMP0042 NEW)
+endif(POLICY CMP0042)
+
+if (POLICY CMP0048)
+  # use old policy to honor version set using VERSION_* variables to preserve backwards
+  # compatibility. change OLD to NEW when minimum cmake version is updated to 3.* and
+  # set VERSION using project(capstone VERSION 4.0.0).
+  # http://www.cmake.org/cmake/help/v3.0/policy/CMP0048.html
+  cmake_policy (SET CMP0048 OLD)
+endif()
+
+# to configure the options specify them in in the command line or change them in the cmake UI.
+# Don't edit the makefile!
+option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ON)
+option(CAPSTONE_BUILD_STATIC "Build static library" ON)
+option(CAPSTONE_BUILD_SHARED "Build shared library" ON)
+option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
+option(CAPSTONE_BUILD_TESTS "Build tests" ON)
+option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON)
+option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
+option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON)
+option(CAPSTONE_INSTALL "Generate install target" ON)
+
+set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX)
+
+list(LENGTH SUPPORTED_ARCHITECTURES count)
+math(EXPR count "${count}-1")
+# create options controlling whether support for a particular architecture is needed
+foreach(i RANGE ${count})
+  list(GET SUPPORTED_ARCHITECTURES ${i} supported_architecture)
+  list(GET SUPPORTED_ARCHITECTURE_LABELS ${i} supported_architecture_label)
+  option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ${CAPSTONE_ARCHITECTURE_DEFAULT})
+endforeach(i)
+
+# propagate architecture support variables to preprocessor
+foreach(supported_architecture ${SUPPORTED_ARCHITECTURES})
+  set(option_name "CAPSTONE_${supported_architecture}_SUPPORT")
+  if(${option_name})
+    message("Enabling ${option_name}")
+    add_definitions("-D${option_name}")
+  endif()
+endforeach(supported_architecture)
+
+option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF)
+option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF)
+option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF)
+
+if (MSVC)
+    set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /MT")
+    set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MTd")
+endif ()
+
+enable_testing()
+
+if (CAPSTONE_BUILD_DIET)
+    add_definitions(-DCAPSTONE_DIET)
+endif ()
+
+if (CAPSTONE_USE_DEFAULT_ALLOC)
+    add_definitions(-DCAPSTONE_USE_SYS_DYN_MEM)
+endif ()
+
+if (CAPSTONE_X86_REDUCE)
+    add_definitions(-DCAPSTONE_X86_REDUCE)
+endif ()
+
+if (CAPSTONE_X86_ATT_DISABLE)
+    add_definitions(-DCAPSTONE_X86_ATT_DISABLE)
+endif ()
+
+## sources
+set(SOURCES_ENGINE
+    cs.c
+    MCInst.c
+    MCInstrDesc.c
+    MCRegisterInfo.c
+    SStream.c
+    utils.c
+)
+set(HEADERS_ENGINE
+    cs_priv.h
+    LEB128.h
+    MathExtras.h
+    MCDisassembler.h
+    MCFixedLenDisassembler.h
+    MCInst.h
+    MCInstrDesc.h
+    MCRegisterInfo.h
+    SStream.h
+    utils.h
+    )
+
+set(HEADERS_COMMON
+    include/capstone/arm64.h
+    include/capstone/arm.h
+    include/capstone/capstone.h
+    include/capstone/evm.h
+    include/capstone/mips.h
+    include/capstone/ppc.h
+    include/capstone/x86.h
+    include/capstone/sparc.h
+    include/capstone/systemz.h
+    include/capstone/xcore.h
+    include/capstone/m68k.h
+    include/capstone/tms320c64x.h
+    include/capstone/m680x.h
+    include/capstone/mos65xx.h
+    include/capstone/platform.h
+    )
+
+set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
+
+## architecture support
+if (CAPSTONE_ARM_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ARM)
+    set(SOURCES_ARM
+        arch/ARM/ARMDisassembler.c
+        arch/ARM/ARMInstPrinter.c
+        arch/ARM/ARMMapping.c
+        arch/ARM/ARMModule.c
+    )
+    set(HEADERS_ARM
+        arch/ARM/ARMAddressingModes.h
+        arch/ARM/ARMBaseInfo.h
+        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMGenAsmWriter.inc
+        arch/ARM/ARMGenDisassemblerTables.inc
+        arch/ARM/ARMGenInstrInfo.inc
+        arch/ARM/ARMGenRegisterInfo.inc
+        arch/ARM/ARMGenSubtargetInfo.inc
+        arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMMapping.h
+        arch/ARM/ARMMappingInsn.inc
+        arch/ARM/ARMMappingInsnOp.inc
+        )
+    set(HEADERS_ARM
+        arch/ARM/ARMAddressingModes.h
+        arch/ARM/ARMBaseInfo.h
+        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMGenAsmWriter.inc
+        arch/ARM/ARMGenDisassemblerTables.inc
+        arch/ARM/ARMGenInstrInfo.inc
+        arch/ARM/ARMGenRegisterInfo.inc
+        arch/ARM/ARMGenSubtargetInfo.inc
+        arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
+endif ()
+
+if (CAPSTONE_ARM64_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_ARM64)
+    set(SOURCES_ARM64
+        arch/AArch64/AArch64BaseInfo.c
+        arch/AArch64/AArch64Disassembler.c
+        arch/AArch64/AArch64InstPrinter.c
+        arch/AArch64/AArch64Mapping.c
+        arch/AArch64/AArch64Module.c
+    )
+    set(HEADERS_ARM64
+        arch/AArch64/AArch64AddressingModes.h
+        arch/AArch64/AArch64BaseInfo.h
+        arch/AArch64/AArch64Disassembler.h
+        arch/AArch64/AArch64GenAsmWriter.inc
+        arch/AArch64/AArch64GenDisassemblerTables.inc
+        arch/AArch64/AArch64GenInstrInfo.inc
+        arch/AArch64/AArch64GenRegisterInfo.inc
+        arch/AArch64/AArch64GenSubtargetInfo.inc
+        arch/AArch64/AArch64InstPrinter.h
+        arch/AArch64/AArch64Mapping.h
+        arch/AArch64/AArch64MappingInsn.inc
+        )
+    set(HEADERS_ARM64
+        arch/AArch64/AArch64AddressingModes.h
+        arch/AArch64/AArch64BaseInfo.h
+        arch/AArch64/AArch64Disassembler.h
+        arch/AArch64/AArch64GenAsmWriter.inc
+        arch/AArch64/AArch64GenDisassemblerTables.inc
+        arch/AArch64/AArch64GenInstrInfo.inc
+        arch/AArch64/AArch64GenRegisterInfo.inc
+        arch/AArch64/AArch64GenSubtargetInfo.inc
+        arch/AArch64/AArch64InstPrinter.h
+        arch/AArch64/AArch64Mapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c)
+endif ()
+
+if (CAPSTONE_MIPS_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_MIPS)
+    set(SOURCES_MIPS
+        arch/Mips/MipsDisassembler.c
+        arch/Mips/MipsInstPrinter.c
+        arch/Mips/MipsMapping.c
+        arch/Mips/MipsModule.c
+    )
+    set(HEADERS_MIPS
+        arch/Mips/MipsDisassembler.h
+        arch/Mips/MipsGenAsmWriter.inc
+        arch/Mips/MipsGenDisassemblerTables.inc
+        arch/Mips/MipsGenInstrInfo.inc
+        arch/Mips/MipsGenRegisterInfo.inc
+        arch/Mips/MipsGenSubtargetInfo.inc
+        arch/Mips/MipsInstPrinter.h
+        arch/Mips/MipsMapping.h
+        arch/Mips/MipsMappingInsn.inc
+        )
+    set(HEADERS_MIPS
+        arch/Mips/MipsDisassembler.h
+        arch/Mips/MipsGenAsmWriter.inc
+        arch/Mips/MipsGenDisassemblerTables.inc
+        arch/Mips/MipsGenInstrInfo.inc
+        arch/Mips/MipsGenRegisterInfo.inc
+        arch/Mips/MipsGenSubtargetInfo.inc
+        arch/Mips/MipsInstPrinter.h
+        arch/Mips/MipsMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_mips.c)
+endif ()
+
+if (CAPSTONE_PPC_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_POWERPC)
+    set(SOURCES_PPC
+        arch/PowerPC/PPCDisassembler.c
+        arch/PowerPC/PPCInstPrinter.c
+        arch/PowerPC/PPCMapping.c
+        arch/PowerPC/PPCModule.c
+    )
+    set(HEADERS_PPC
+        arch/PowerPC/PPCDisassembler.h
+        arch/PowerPC/PPCGenAsmWriter.inc
+        arch/PowerPC/PPCGenDisassemblerTables.inc
+        arch/PowerPC/PPCGenInstrInfo.inc
+        arch/PowerPC/PPCGenRegisterInfo.inc
+        arch/PowerPC/PPCGenSubtargetInfo.inc
+        arch/PowerPC/PPCInstPrinter.h
+        arch/PowerPC/PPCMapping.h
+        arch/PowerPC/PPCMappingInsn.inc
+        arch/PowerPC/PPCPredicates.h
+        )
+    set(HEADERS_PPC
+        arch/PowerPC/PPCDisassembler.h
+        arch/PowerPC/PPCGenAsmWriter.inc
+        arch/PowerPC/PPCGenDisassemblerTables.inc
+        arch/PowerPC/PPCGenInstrInfo.inc
+        arch/PowerPC/PPCGenRegisterInfo.inc
+        arch/PowerPC/PPCGenSubtargetInfo.inc
+        arch/PowerPC/PPCInstPrinter.h
+        arch/PowerPC/PPCMapping.h
+        arch/PowerPC/PPCPredicates.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
+endif ()
+
+if (CAPSTONE_X86_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_X86)
+    set(SOURCES_X86
+        arch/X86/X86Disassembler.c
+        arch/X86/X86DisassemblerDecoder.c
+        arch/X86/X86IntelInstPrinter.c
+        arch/X86/X86Mapping.c
+        arch/X86/X86Module.c
+    )
+    set(HEADERS_X86
+        arch/X86/X86BaseInfo.h
+        arch/X86/X86Disassembler.h
+        arch/X86/X86DisassemblerDecoder.h
+        arch/X86/X86DisassemblerDecoderCommon.h
+        arch/X86/X86GenAsmWriter.inc
+        arch/X86/X86GenAsmWriter1.inc
+        arch/X86/X86GenAsmWriter1_reduce.inc
+        arch/X86/X86GenAsmWriter_reduce.inc
+        arch/X86/X86GenDisassemblerTables.inc
+        arch/X86/X86GenDisassemblerTables_reduce.inc
+        arch/X86/X86GenInstrInfo.inc
+        arch/X86/X86GenInstrInfo_reduce.inc
+        arch/X86/X86GenRegisterInfo.inc
+        arch/X86/X86InstPrinter.h
+        arch/X86/X86Mapping.h
+        arch/X86/X86MappingInsn.inc
+        arch/X86/X86MappingInsnOp.inc
+        arch/X86/X86MappingInsnOp_reduce.inc
+        arch/X86/X86MappingInsn_reduce.inc
+        )
+    set(HEADERS_X86
+        arch/X86/X86BaseInfo.h
+        arch/X86/X86Disassembler.h
+        arch/X86/X86DisassemblerDecoder.h
+        arch/X86/X86DisassemblerDecoderCommon.h
+        arch/X86/X86GenAsmWriter.inc
+        arch/X86/X86GenAsmWriter1.inc
+        arch/X86/X86GenAsmWriter1_reduce.inc
+        arch/X86/X86GenAsmWriter_reduce.inc
+        arch/X86/X86GenDisassemblerTables.inc
+        arch/X86/X86GenDisassemblerTables_reduce.inc
+        arch/X86/X86GenInstrInfo.inc
+        arch/X86/X86GenInstrInfo_reduce.inc
+        arch/X86/X86GenRegisterInfo.inc
+        arch/X86/X86InstPrinter.h
+        arch/X86/X86Mapping.h
+        )
+    if (NOT CAPSTONE_BUILD_DIET)
+        set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
+    endif ()
+    set(TEST_SOURCES ${TEST_SOURCES} test_x86.c test_customized_mnem.c)
+endif ()
+
+if (CAPSTONE_SPARC_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_SPARC)
+    set(SOURCES_SPARC
+        arch/Sparc/SparcDisassembler.c
+        arch/Sparc/SparcInstPrinter.c
+        arch/Sparc/SparcMapping.c
+        arch/Sparc/SparcModule.c
+        )
+    set(HEADERS_SPARC
+        arch/Sparc/Sparc.h
+        arch/Sparc/SparcDisassembler.h
+        arch/Sparc/SparcGenAsmWriter.inc
+        arch/Sparc/SparcGenDisassemblerTables.inc
+        arch/Sparc/SparcGenInstrInfo.inc
+        arch/Sparc/SparcGenRegisterInfo.inc
+        arch/Sparc/SparcGenSubtargetInfo.inc
+        arch/Sparc/SparcInstPrinter.h
+        arch/Sparc/SparcMapping.h
+        arch/Sparc/SparcMappingInsn.inc
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c)
+endif ()
+
+if (CAPSTONE_SYSZ_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_SYSZ)
+    set(SOURCES_SYSZ
+        arch/SystemZ/SystemZDisassembler.c
+        arch/SystemZ/SystemZInstPrinter.c
+        arch/SystemZ/SystemZMapping.c
+        arch/SystemZ/SystemZModule.c
+        arch/SystemZ/SystemZMCTargetDesc.c
+        )
+    set(HEADERS_SYSZ
+        arch/SystemZ/SystemZDisassembler.h
+        arch/SystemZ/SystemZGenAsmWriter.inc
+        arch/SystemZ/SystemZGenDisassemblerTables.inc
+        arch/SystemZ/SystemZGenInsnNameMaps.inc
+        arch/SystemZ/SystemZGenInstrInfo.inc
+        arch/SystemZ/SystemZGenRegisterInfo.inc
+        arch/SystemZ/SystemZGenSubtargetInfo.inc
+        arch/SystemZ/SystemZInstPrinter.h
+        arch/SystemZ/SystemZMapping.h
+        arch/SystemZ/SystemZMappingInsn.inc
+        arch/SystemZ/SystemZMCTargetDesc.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c)
+endif ()
+
+if (CAPSTONE_XCORE_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_XCORE)
+    set(SOURCES_XCORE
+        arch/XCore/XCoreDisassembler.c
+        arch/XCore/XCoreInstPrinter.c
+        arch/XCore/XCoreMapping.c
+        arch/XCore/XCoreModule.c
+        )
+    set(HEADERS_XCORE
+        arch/XCore/XCoreDisassembler.h
+        arch/XCore/XCoreGenAsmWriter.inc
+        arch/XCore/XCoreGenDisassemblerTables.inc
+        arch/XCore/XCoreGenInstrInfo.inc
+        arch/XCore/XCoreGenRegisterInfo.inc
+        arch/XCore/XCoreInstPrinter.h
+        arch/XCore/XCoreMapping.h
+        arch/XCore/XCoreMappingInsn.inc
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c)
+endif ()
+
+if (CAPSTONE_M68K_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_M68K)
+    set(SOURCES_M68K
+		arch/M68K/M68KDisassembler.c
+		arch/M68K/M68KInstPrinter.c
+		arch/M68K/M68KModule.c
+    )
+    set(HEADERS_M68K
+		arch/M68K/M68KDisassembler.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c)
+endif ()
+
+if (CAPSTONE_TMS320C64X_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_TMS320C64X)
+    set(SOURCES_TMS320C64X
+        arch/TMS320C64x/TMS320C64xDisassembler.c
+        arch/TMS320C64x/TMS320C64xInstPrinter.c
+        arch/TMS320C64x/TMS320C64xMapping.c
+        arch/TMS320C64x/TMS320C64xModule.c
+        )
+    set(HEADERS_TMS320C64X
+        arch/TMS320C64x/TMS320C64xDisassembler.h
+        arch/TMS320C64x/TMS320C64xGenAsmWriter.inc
+        arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc
+        arch/TMS320C64x/TMS320C64xGenInstrInfo.inc
+        arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc
+        arch/TMS320C64x/TMS320C64xInstPrinter.h
+        arch/TMS320C64x/TMS320C64xMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_tms320c64x.c)
+endif ()
+
+if (CAPSTONE_M680X_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_M680X)
+    set(SOURCES_M680X
+		arch/M680X/M680XDisassembler.c
+		arch/M680X/M680XInstPrinter.c
+		arch/M680X/M680XModule.c
+    )
+    set(HEADERS_M680X
+		arch/M680X/M680XInstPrinter.h
+		arch/M680X/M680XDisassembler.h
+		arch/M680X/M680XDisassemblerInternals.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c)
+endif ()
+
+if (CAPSTONE_EVM_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_EVM)
+    set(SOURCES_EVM
+        arch/EVM/EVMDisassembler.c
+        arch/EVM/EVMInstPrinter.c
+        arch/EVM/EVMMapping.c
+        arch/EVM/EVMModule.c
+    )
+    set(HEADERS_EVM
+        arch/EVM/EVMDisassembler.h
+        arch/EVM/EVMInstPrinter.h
+        arch/EVM/EVMMapping.h
+        arch/EVM/EVMMappingInsn.inc
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_evm.c)
+endif ()
+
+if (CAPSTONE_MOS65XX_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_MOS65XX)
+    set(SOURCES_MOS65XX
+            arch/MOS65XX/MOS65XXModule.c
+            arch/MOS65XX/MOS65XXDisassembler.c)
+    set(HEADERS_SOURCES_MOS65XX
+            arch/MOS65XX/MOS65XXDisassembler.h
+    )
+    set(TEST_SOURCES ${TEST_SOURCES} test_mos65xx.c)
+endif ()
+
+if (CAPSTONE_OSXKERNEL_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
+endif ()
+
+set(ALL_SOURCES
+    ${SOURCES_ENGINE}
+    ${SOURCES_ARM}
+    ${SOURCES_ARM64}
+    ${SOURCES_MIPS}
+    ${SOURCES_PPC}
+    ${SOURCES_X86}
+    ${SOURCES_SPARC}
+    ${SOURCES_SYSZ}
+    ${SOURCES_XCORE}
+    ${SOURCES_M68K}
+    ${SOURCES_TMS320C64X}
+    ${SOURCES_M680X}
+    ${SOURCES_EVM}
+    ${SOURCES_MOS65XX}
+    )
+
+set(ALL_HEADERS
+    ${HEADERS_COMMON}
+    ${HEADERS_ENGINE}
+    ${HEADERS_ARM}
+    ${HEADERS_ARM64}
+    ${HEADERS_MIPS}
+    ${HEADERS_PPC}
+    ${HEADERS_X86}
+    ${HEADERS_SPARC}
+    ${HEADERS_SYSZ}
+    ${HEADERS_XCORE}
+    ${HEADERS_M68K}
+    ${HEADERS_TMS320C64X}
+    ${HEADERS_M680X}
+    ${HEADERS_EVM}
+    ${HEADERS_MOS65XX}
+    )
+
+include_directories("${PROJECT_SOURCE_DIR}/include")
+
+## properties
+# version info
+set_property(GLOBAL PROPERTY VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
+
+## targets
+if (CAPSTONE_BUILD_STATIC)
+    add_library(capstone-static STATIC ${ALL_SOURCES} ${ALL_HEADERS})
+    set_property(TARGET capstone-static PROPERTY OUTPUT_NAME capstone)
+    set(default-target capstone-static)
+endif ()
+
+# Force static runtime libraries
+if (CAPSTONE_BUILD_STATIC_RUNTIME)
+    FOREACH(flag
+	CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
+	CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
+	CMAKE_CXX_FLAGS_RELEASE  CMAKE_CXX_FLAGS_RELWITHDEBINFO
+	CMAKE_CXX_FLAGS_DEBUG  CMAKE_CXX_FLAGS_DEBUG_INIT)
+	if (MSVC)
+	    STRING(REPLACE "/MD"  "/MT" "${flag}" "${${flag}}")
+	    SET("${flag}" "${${flag}} /EHsc")
+	endif (MSVC)
+    ENDFOREACH()
+endif ()
+
+if (CAPSTONE_BUILD_SHARED)
+    add_library(capstone-shared SHARED ${ALL_SOURCES} ${ALL_HEADERS})
+    set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone)
+    set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED)
+
+    if (MSVC)
+        set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib)
+    else()
+        set_target_properties(capstone-shared PROPERTIES
+	    VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
+	    SOVERSION ${VERSION_MAJOR})
+    endif ()
+
+    if(NOT DEFINED default-target)      # honor `capstone-static` for tests first.
+        set(default-target capstone-shared)
+        add_definitions(-DCAPSTONE_SHARED)
+    endif ()
+endif ()
+
+if (CAPSTONE_BUILD_TESTS)
+    foreach (TSRC ${TEST_SOURCES})
+        STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC})
+        add_executable(${TBIN} "tests/${TSRC}")
+        target_link_libraries(${TBIN} ${default-target})
+        add_test(NAME "capstone_${TBIN}" COMMAND ${TBIN})
+    endforeach ()
+    if (CAPSTONE_ARM_SUPPORT)
+        set(ARM_REGRESS_TEST test_arm_regression.c)
+        STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST})
+        add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}")
+        target_link_libraries(${ARM_REGRESS_BIN} ${default-target})
+        add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN})
+    endif()
+    # fuzz target built with the tests
+    add_executable(fuzz_disasm suite/fuzz/onefile.c suite/fuzz/fuzz_disasm.c)
+    target_link_libraries(fuzz_disasm ${default-target})
+endif ()
+
+source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
+source_group("Source\\ARM" FILES ${SOURCES_ARM})
+source_group("Source\\ARM64" FILES ${SOURCES_ARM64})
+source_group("Source\\Mips" FILES ${SOURCES_MIPS})
+source_group("Source\\PowerPC" FILES ${SOURCES_PPC})
+source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
+source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ})
+source_group("Source\\X86" FILES ${SOURCES_X86})
+source_group("Source\\XCore" FILES ${SOURCES_XCORE})
+source_group("Source\\M68K" FILES ${SOURCES_M68K})
+source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X})
+source_group("Source\\M680X" FILES ${SOURCES_M680X})
+source_group("Source\\EVM" FILES ${SOURCES_EVM})
+source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX})
+
+source_group("Include\\Common" FILES ${HEADERS_COMMON})
+source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
+source_group("Include\\ARM" FILES ${HEADERS_ARM})
+source_group("Include\\ARM64" FILES ${HEADERS_ARM64})
+source_group("Include\\Mips" FILES ${HEADERS_MIPS})
+source_group("Include\\PowerPC" FILES ${HEADERS_PPC})
+source_group("Include\\Sparc" FILES ${HEADERS_SPARC})
+source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ})
+source_group("Include\\X86" FILES ${HEADERS_X86})
+source_group("Include\\XCore" FILES ${HEADERS_XCORE})
+source_group("Include\\M68K" FILES ${HEADERS_M68K})
+source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X})
+source_group("Include\\M680X" FILES ${HEADERS_MC680X})
+source_group("Include\\EVM" FILES ${HEADERS_EVM})
+source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX})
+
+### test library 64bit routine:
+include("GNUInstallDirs")
+
+## installation
+if (CAPSTONE_INSTALL)
+    install(FILES ${HEADERS_COMMON} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone)
+endif ()
+configure_file(capstone.pc.in ${CMAKE_BINARY_DIR}/capstone.pc @ONLY)
+
+if (CAPSTONE_BUILD_STATIC AND CAPSTONE_INSTALL)
+    install(TARGETS capstone-static
+            RUNTIME DESTINATION bin
+            LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
+            ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
+endif ()
+
+if (CAPSTONE_BUILD_SHARED AND CAPSTONE_INSTALL)
+    install(TARGETS capstone-shared
+            RUNTIME DESTINATION bin
+            LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
+            ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR})
+endif ()
+
+if (CAPSTONE_BUILD_SHARED AND CAPSTONE_BUILD_CSTOOL)
+FILE(GLOB CSTOOL_SRC cstool/*.c)
+add_executable(cstool ${CSTOOL_SRC})
+target_link_libraries(cstool ${default-target})
+
+if (CAPSTONE_INSTALL)
+    install(TARGETS cstool DESTINATION bin)
+    install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig)
+endif ()
+endif ()

COMPILE.TXT

@@ -0,0 +1,200 @@
+This documentation explains how to compile, install & run Capstone on MacOSX,
+Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows.
+
+To natively compile for Windows using Microsoft Visual Studio, see COMPILE_MSVC.TXT.
+
+To compile using CMake, see COMPILE_CMAKE.TXT.
+
+To compile using XCode on MacOSX, see xcode/README.md.
+
+To compile for Windows CE (a.k.a, Windows Embedded Compact), see windowsce/COMPILE.md.
+
+                        *-*-*-*-*-*
+
+Capstone requires no prerequisite packages, so it is easy to compile & install.
+
+
+
+(0) Tailor Capstone to your need.
+
+  Out of all archtitectures supported by Capstone, if you just need several
+  selected archs, choose the ones you want to compile in by editing "config.mk"
+  before going to next steps.
+
+  By default, all architectures are compiled.
+
+  The other way of customize Capstone without having to edit config.mk is to
+  pass the desired options on the commandline to ./make.sh. Currently,
+  Capstone supports 7 options, as followings.
+
+  - CAPSTONE_ARCHS: specify list of architectures to compiled in.
+  - CAPSTONE_USE_SYS_DYN_MEM: change this if you have your own dynamic memory management.
+  - CAPSTONE_DIET: use this to make the output binaries more compact.
+  - CAPSTONE_X86_REDUCE: another option to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE: disables AT&T syntax on x86.
+  - CAPSTONE_STATIC: build static library.
+  - CAPSTONE_SHARED: build dynamic (shared) library.
+
+  By default, Capstone uses system dynamic memory management, both DIET and X86_REDUCE
+  modes are disable, and builds all the static & shared libraries.
+
+  To avoid editing config.mk for these customization, we can pass their values to
+  make.sh, as followings.
+
+  $ CAPSTONE_ARCHS="arm aarch64 x86" CAPSTONE_USE_SYS_DYN_MEM=no CAPSTONE_DIET=yes CAPSTONE_X86_REDUCE=yes ./make.sh
+
+  NOTE: on commandline, put these values in front of ./make.sh, not after it.
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) Compile from source
+
+  On *nix (such as MacOSX, Linux, *BSD, Solaris):
+
+  - To compile for current platform, run:
+
+		$ ./make.sh
+
+  - On 64-bit OS, run the command below to cross-compile Capstone for 32-bit binary:
+
+		$ ./make.sh nix32
+
+
+
+(2) Install Capstone on *nix
+
+  To install Capstone, run:
+
+	$ sudo ./make.sh install
+
+	For FreeBSD/OpenBSD, where sudo is unavailable, run:
+
+		$ su; ./make.sh install
+
+  Users are then required to enter root password to copy Capstone into machine
+  system directories.
+
+  Afterwards, run ./tests/test* to see the tests disassembling sample code.
+
+
+  NOTE: The core framework installed by "./make.sh install" consist of
+  following files:
+
+	/usr/include/capstone/arm.h
+	/usr/include/capstone/arm64.h
+	/usr/include/capstone/capstone.h
+	/usr/include/capstone/evm.h
+	/usr/include/capstone/m680x.h
+	/usr/include/capstone/m68k.h
+	/usr/include/capstone/mips.h
+	/usr/include/capstone/mos65xx.h
+	/usr/include/capstone/platform.h
+	/usr/include/capstone/ppc.h
+	/usr/include/capstone/sparc.h
+	/usr/include/capstone/systemz.h
+	/usr/include/capstone/tms320c64x.h
+	/usr/include/capstone/x86.h
+	/usr/include/capstone/xcore.h
+	/usr/lib/libcapstone.a
+	/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
+
+
+
+(3) Cross-compile for Windows from *nix
+
+  To cross-compile for Windows, Linux & gcc-mingw-w64-i686 (and also gcc-mingw-w64-x86-64
+  for 64-bit binaries) are required.
+
+	- To cross-compile Windows 32-bit binary, simply run:
+
+		$ ./make.sh cross-win32
+
+	- To cross-compile Windows 64-bit binary, run:
+
+		$ ./make.sh cross-win64
+
+  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
+  be used on Windows machine.
+
+
+
+(4) Cross-compile for iOS from Mac OSX.
+
+  To cross-compile for iOS (iPhone/iPad/iPod), Mac OSX with XCode installed is required.
+
+	- To cross-compile for ArmV7 (iPod 4, iPad 1/2/3, iPhone4, iPhone4S), run:
+		$ ./make.sh ios_armv7
+
+	- To cross-compile for ArmV7s (iPad 4, iPhone 5C, iPad mini), run:
+		$ ./make.sh ios_armv7s
+
+	- To cross-compile for Arm64 (iPhone 5S, iPad mini Retina, iPad Air), run:
+		$ ./make.sh ios_arm64
+
+	- To cross-compile for all iDevices (armv7 + armv7s + arm64), run:
+		$ ./make.sh ios
+
+  Resulted files libcapstone.dylib, libcapstone.a & tests/test* can then
+  be used on iOS devices.
+
+
+
+(5) Cross-compile for Android
+
+  To cross-compile for Android (smartphone/tablet), Android NDK is required.
+  NOTE: Only ARM and ARM64 are currently supported.
+
+	$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
+  or
+	$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
+
+  Resulted files libcapstone.so, libcapstone.a & tests/test* can then
+  be used on Android devices.
+
+
+
+(6) Compile on Windows with Cygwin
+
+  To compile under Cygwin gcc-mingw-w64-i686 or x86_64-w64-mingw32 run:
+
+        - To compile Windows 32-bit binary under Cygwin, run:
+
+                $ ./make.sh cygwin-mingw32
+
+        - To compile Windows 64-bit binary under Cygwin, run:
+
+                $ ./make.sh cygwin-mingw64
+
+  Resulted files libcapstone.dll, libcapstone.dll.a & tests/test*.exe can then
+  be used on Windows machine.
+
+
+
+(7) By default, "cc" (default C compiler on the system) is used as compiler.
+
+	- To use "clang" compiler instead, run the command below:
+
+		$ ./make.sh clang
+
+	- To use "gcc" compiler instead, run:
+
+		$ ./make.sh gcc
+
+
+
+(8) To uninstall Capstone, run the command below:
+
+		$ sudo ./make.sh uninstall
+
+
+
+(9) Language bindings
+
+  So far, Python, Ocaml & Java are supported by bindings in the main code.
+  Look for the bindings under directory bindings/, and refer to README file
+  of corresponding languages.
+
+  Community also provide bindings for C#, Go, Ruby, NodeJS, C++ & Vala. Links to
+  these can be found at address http://capstone-engine.org/download.html

COMPILE_CMAKE.TXT

@@ -0,0 +1,114 @@
+This documentation explains how to compile Capstone with CMake, focus on
+using Microsoft Visual C as the compiler.
+
+To compile Capstone on *nix, see COMPILE.TXT.
+
+To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT.
+
+                        *-*-*-*-*-*
+
+This documentation requires CMake & Windows SDK or MS Visual Studio installed on
+your machine.
+
+Get CMake for free from http://www.cmake.org.
+
+
+
+(0) Tailor Capstone to your need.
+
+  Out of archtitectures supported by Capstone, if you just need several selected archs,
+  run "cmake" with the unwanted archs disabled (set to 0) as followings.
+
+  - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
+  - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64.
+  - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
+  - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
+  - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
+  - CAPSTONE_MOS65XX_SUPPORT: support MOS65XX. Run cmake with -DCAPSTONE_MOS65XX_SUPPORT=0 to remove MOS65XX.
+  - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC.
+  - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
+  - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
+  - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
+  - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
+  - CAPSTONE_TMS320C64X_SUPPORT: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X.
+  - CAPSTONE_EVM_SUPPORT: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM.
+  - CAPSTONE_ARCHITECUTRE_DEFAULT: Whether architectures are enabled by default.
+      Set this of OFF with -DCAPSTONE_ARCHITECUTRE_DEFAULT=OFF to dissable all architectures by default.
+      You can then enable them again with one of the CAPSTONE_<ARCH>_SUPPORT options.
+
+  By default, all architectures are compiled in.
+
+
+  Besides, Capstone also allows some more customization via following macros.
+
+  - CAPSTONE_USE_SYS_DYN_MEM: change this to OFF to use your own dynamic memory management.
+  - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact.
+  - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86.
+
+  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
+  modes are disabled. To use your own memory allocations, turn ON both DIET &
+  X86_REDUCE, run "cmake" with: -DCAPSTONE_USE_SYS_DYN_MEM=0 -DCAPSTONE_BUILD_DIET=1 -DCAPSTONE_X86_REDUCE=1
+
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) CMake allows you to generate different generators to build Capstone. Below is
+    some examples on how to build Capstone on Windows with CMake.
+
+  (*) You can let CMake select a generator for you. Do:
+
+      mkdir build
+      cd build
+      cmake ..
+
+    This last command is also where you can pass additional CMake configuration flags
+    using `-D<key>=<value>`. Then to build use:
+
+      cmake --build . --config Release
+
+
+  (*) To build Capstone using Nmake of Windows SDK, do:
+
+      mkdir build
+      cd build
+      ..\nmake.bat
+
+  After this, find the samples test*.exe, capstone.lib & capstone.dll
+  in the same directory.
+
+
+
+  (*) To build Capstone using Visual Studio, choose the generator accordingly to the
+  version of Visual Studio on your machine. For example, with Visual Studio 2013, do:
+
+      mkdir build
+      cd build
+      cmake -G "Visual Studio 12" ..
+
+  After this, find capstone.sln in the same directory. Open it with Visual Studio
+  and build the solution including libraries & all test as usual.
+
+
+
+(2) You can make sure the prior steps successfully worked by launching one of the
+  testing binary (test*.exe).
+
+(3) You can also enable just one specific architecture by passing the architecture name
+  to either the cmake.sh or nmake.bat scripts. e.g.:
+
+    ../cmake.sh x86
+
+  Will just target the x86 architecture. The list of available architectures is: ARM,
+  ARM64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX.
+
+(4) You can also create an installation image with cmake, by using the 'install' target.
+  Use:
+
+    cmake --build . --config Release --target install
+
+  This will normally install an image in a default location (`C:\Program Files` on Windows),
+  so it's good to explicitly set this location when configuring CMake. Use: `-DCMAKE_INSTALL_PREFIX=image`
+  for instance, to put the installation in the 'image' subdirectory of the build directory.

COMPILE_MSVC.TXT

@@ -0,0 +1,122 @@
+This documentation explains how to compile Capstone on Windows using
+Microsoft Visual Studio version 2010 or newer.
+
+To compile Capstone on *nix, see COMPILE.TXT
+
+To compile Capstone with CMake, see COMPILE_CMAKE.TXT
+
+                        *-*-*-*-*-*
+
+Capstone requires no prerequisite packages with default configurations, so it is
+easy to compile & install. Open the Visual Studio solution "msvc/capstone.sln"
+and follow the instructions below.
+
+NOTE: This requires Visual Studio 2010 or newer versions.
+
+If you wish to embed Capstone in a kernel driver, Visual Studio 2013 or newer
+versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
+
+
+(0) Tailor Capstone to your need.
+
+  Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
+  Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose
+  the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
+  then directly editing the projects "capstone_static" & "capstone_dll" for static
+  and dynamic libraries, respectively. This must be done before going to the next
+  steps.
+
+  In VisualStudio interface, modify the preprocessor definitions via
+  "Project Properties" -> "Configuration Properties" -> "C/C++" -> "Preprocessor"
+  to customize Capstone library, as followings.
+
+  - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
+  - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
+  - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support.
+  - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
+  - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support.
+  - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
+  - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
+  - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
+  - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
+
+  By default, all 9 architectures are compiled in.
+
+
+  Besides, Capstone also allows some more customization via following macros.
+
+  - CAPSTONE_USE_SYS_DYN_MEM: delete this to use your own dynamic memory management.
+  - CAPSTONE_DIET_NO: rename this to "CAPSTONE_DIET" to make the binaries more compact.
+  - CAPSTONE_X86_REDUCE_NO: rename this to "CAPSTONE_X86_REDUCE" to make X86 binary smaller.
+  - CAPSTONE_X86_ATT_DISABLE_NO: rename this to "CAPSTONE_X86_ATT_DISABLE" to disable
+    AT&T syntax on x86.
+
+  By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
+  modes are disable.
+
+
+  For each option, refer to docs/README for more details.
+
+
+
+(1) Compile from source on Windows with Visual Studio
+
+  - Choose the configuration and the platform you want: Release/Debug & Win32/Win64.
+  - Build only the libraries, or the libraries along with all the tests.
+  - "capstone_static_winkernel" is for compiling Capstone for a driver and
+    "test_winkernel" is a test for a driver, and those are excluded from build by
+    default. To compile them, open the Configuration Manager through the [Build]
+    menu and check "Build" check boxes for those project.
+
+
+
+(2) You can make sure the prior steps successfully worked by launching one of the
+  testing binary (test*.exe).
+
+  The testing binary for a driver "test_winkernel.sys" is made up of all tests for
+  supported architectures configured with the step (0) along side its own tests.
+  Below explains a procedure to run the test driver and check test results.
+
+  On the x64 platform, the test signing mode has to be enabled to install the test
+  driver. To do it, open the command prompt with the administrator privileges and
+  type the following command, and then restart the system to activate the change:
+
+      >bcdedit /set testsigning on
+
+  Test results from the test driver is sent to kernel debug buffer. In order to
+  see those results, download DebugView and run it with the administrator
+  privileges, then check [Capture Kernel] through the [Capture] menu.
+
+  DebugView: https://technet.microsoft.com/en-us/sysinternals/debugview.aspx
+
+  To install and uninstall the driver, use the 'sc' command. For installing and
+  executing test_winkernel.sys, execute the following commands with the
+  administrator privileges:
+
+      >sc create test_winkernel type= kernel binPath= <full path to test_winkernel.sys>
+      [SC] CreateService SUCCESS
+
+      >sc start test_winkernel
+      [SC] StartService FAILED 995:
+
+      The I/O operation has been aborted because of either a thread exit or an application request.
+
+  To uninstall the driver, execute the following commands with the administrator
+  privileges:
+
+      >sc delete test_winkernel
+      >bcdedit /deletevalue testsigning
+      
+      
+      
+(3) Installing and building capstone via vcpkg
+  
+  You can download and install capstone using the vcpkg(https://github.com/Microsoft/vcpkg) dependency manager:
+
+    git clone https://github.com/Microsoft/vcpkg.git
+    cd vcpkg
+    ./bootstrap-vcpkg.sh
+    ./vcpkg integrate install
+    vcpkg install capstone
+
+  The capstone port in vcpkg is kept up to date by Microsoft team members and community contributors. If the version is out of date, please create an issue or pull request on the vcpkg repository(https://github.com/Microsoft/vcpkg). 

CREDITS.TXT

@@ -0,0 +1,83 @@
+This file credits all the contributors of the Capstone engine project.
+
+Key developers
+==============
+1. Nguyen Anh Quynh <aquynh -at- gmail.com>
+	- Core engine
+	- Bindings: Python, Ruby, OCaml, Java, C#
+
+2. Tan Sheng Di <shengdi -at- coseinc.com>
+	- Bindings: Ruby
+
+3. Ben Nagy <ben -at- coseinc.com>
+	- Bindings: Ruby, Go
+
+4. Dang Hoang Vu <dang.hvu -at- gmail.com>
+	- Bindings: Java
+
+
+Beta testers (in random order)
+==============================
+Pancake
+Van Hauser
+FX of Phenoelit
+The Grugq, The Grugq   <-- our hero for submitting the first ever patch!
+Isaac Dawson, Veracode Inc
+Patroklos Argyroudis, Census Inc. (http://census-labs.com)
+Attila Suszter
+Le Dinh Long
+Nicolas Ruff
+Gunther
+Alex Ionescu, Winsider Seminars & Solutions Inc.
+Snare
+Daniel Godas-Lopez
+Joshua J. Drake
+Edgar Barbosa
+Ralf-Philipp Weinmann
+Hugo Fortier
+Joxean Koret
+Bruce Dang
+Andrew Dunham
+
+
+Contributors (in no particular order)
+=====================================
+(Please let us know if you want to have your name here)
+
+Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
+Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
+Daniel Pistelli: Cmake support.
+Peter Hlavaty: integrate Capstone for Windows kernel drivers.
+Guillaume Jeanne: Ocaml binding.
+Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features.
+David Martínez Moreno & Hilko Bengen: Debian package.
+Félix Cloutier: Xcode project.
+Benoit Lecocq: OpenBSD package.
+Christophe Avoinne (Hlide): Improve memory management for better performance.
+Michael Cohen & Nguyen Tan Cong: Python module installer.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Tang Yuhang: cstool.
+Andrew Dutcher: better Python setup.
+Ruben Boonen: PowerShell binding.
+David Zimmer: VB6 binding.
+Philippe Antoine: Integration with oss-fuzz and various fixes.
+Bui Dinh Cuong: Explicit registers accessed for Arm64.
+Vincent Bénony: Explicit registers accessed for X86.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Daniel Collin & Nicolas Planel: M68K architecture.
+Pranith Kumar: Explicit registers accessed for Arm64.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Koutheir Attouchi: Support for Windows CE.
+Fotis Loukos: TMS320C64x architecture.
+Wolfgang Schwotzer: M680X architecture.
+Philippe Antoine: Integration with oss-fuzz and various fixes.
+Stephen Eckels (stevemk14ebr): x86 encoding features
+Sebastian Macke: MOS65XX architecture
+Ilya Leoshkevich: SystemZ architecture improvements.
+Do Minh Tuan: Regression testing tool (cstest)
+Kevin Foo (chfl4gs): PyPI github actions workflow.

ChangeLog

@@ -0,0 +1,701 @@
+This file details the changelog of Capstone.
+
+---------------------------------
+Version 4.0.1: January 10th, 2019
+
+
+[ Core ]
+
+- Fix some issues for packaging (Debian, Gentoo).
+- Better support for building with Mingw.
+- cstool has new option -s to turn on skipdata mode.
+- cstool -v now report build settings of the core.
+- Add suite/capstone_get_setup.c so users can integrate with their own code
+  to retrieve Capstone settings at build time.
+
+
+[ Arm ]
+
+- Fix 4.0 regression: the `tbh [r0, r1, lsl #1]` instruction sets the operand.shift.value back again (see #1317)
+- Remove ARM_REG_PC group for BX instruction.
+
+
+[ X86 ]
+
+- Fix: endbr32 and endbr64 instructions are now properly decoded in both CS_MODE_32 and CS_MODE_64  (#1129)
+
+
+[ M680X ]
+
+- Fix some issues reported by clang-analyzer (#1329).
+
+
+[ Python ]
+
+- Fix skipdata setup.
+- Add getter/setter for skipdata_mnem, skipdata_callback.
+
+
+---------------------------------
+Version 4.0: December 18th, 2018
+
+
+[ Core ]
+
+- New APIs: cs_regs_access()
+- Add new options for cs_option(): CS_OPT_MNEMONIC & CS_OPT_UNSIGNED & CS_OPT_SYNTAX_MASM.
+- Various updates & bugfixes for all architectures.
+- Add 4 new architectures: EVM, M68K, M680X & TMS320C64x.
+- Add new group types: CS_GRP_PRIVILEGE & CS_GRP_BRANCH_RELATIVE.
+- Add new error types: CS_ERR_X86_MASM.
+
+
+[ X86 ]
+
+- Add XOP code condition type in x86_xop_cc.
+- Add some info on encoding to cs_x86 in cs_x86_encoding.
+- Add register flags update in cs_x86.{eflags, fpu_flags}
+- Change cs_x86.disp type from int32_t to int64_t.
+- Add new groups: X86_GRP_VM & X86_GRP_FPU.
+- Lots of new instructions (AVX)
+
+
+[ ARM64 ]
+
+- Add instruction ARM64_INS_NEGS & ARM64_INS_NGCS.
+
+
+[ Mips ]
+
+- Add mode CS_MODE_MIPS2.
+
+
+[ PPC ]
+
+- Change cs_ppc_op.imm type from int32_t to int64_t.
+- Add new groups: PPC_GRP_ICBT, PPC_GRP_P8ALTIVEC, PPC_GRP_P8VECTOR & PPC_GRP_QPX.
+- Lots of new instructions (QPX among them)
+
+
+[ Sparc ]
+
+- Change cs_sparc_op.imm type from int32_t to int64_t.
+
+
+[ Binding ]
+
+- New bindings: PowerShell & VB6
+
+
+---------------------------------
+Version 3.0.5: July 18th, 2018
+
+
+[ Core ]
+
+- Fix the include path for Android builds when building cstool.
+- Add posibility to disable universal build for Mac OS.
+- cstool: Separate instruction bytes by spaces.
+- Fix code path of pkg-config in Cmake.
+- Update XCode project for XCode 9.1.
+- Add Cortex-M support to cstool.
+- Cmake forces to be build using MT with MSVC.
+- Better support for Mac OS kernel.
+
+
+[ X86 ]
+
+- Fix some issues in handling EVEX & VEX3 instructions.
+- Fix immediate operand for AND instruction in ATT mode.
+- Fix ATT syntax when imm operand is 0.
+- Better handle XACQUIRE/XRELEASE.
+- Fix imm operand of RETF.
+
+
+[ ARM ]
+
+- Fix an integer overlow bug.
+
+
+[ ARM64 ]
+
+- Bug fix for incorrect operand type in certain load/store instructions.
+
+
+[ Mips ]
+
+- Mode CS_MODE_MIPS32R6 automatically sets CS_MODE_32
+
+
+[ PPC ]
+
+- Fix endian check.
+
+
+[ Sparc ]
+
+- Fix an integer overlow bug.
+
+
+[ SystemZ ]
+
+- Fix an integer overlow bug.
+
+
+[ Python binding ]
+
+- Raise error on accessing irrelevant data fields if skipdata & detail modes are enable.
+
+
+---------------------------------
+Version 3.0.5-rc3: July 31st, 2017
+
+
+[ Core ]
+
+- Fix compilation for MacOS kernel extension
+- cstool to support armbe and arm64be modes
+- Add nmake.bat for Windows build
+- Fix an integer overflow for Windows kernel driver
+- Support to embedded Capstone into MacOS kernel
+- cstool: fix mips64 mode
+- Fix a compiling error in MS Visual Studio 2015
+- Install pkgconfig file with CMake build
+- Fix SOVERSION property of CMake build
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+- Fix MingW build
+- Better handle CMake installation for Linux 64bit
+
+
+[ X86 ]
+
+- Support BND prefix of Intel MPX extension
+- Correct operand size for CALL/JMP in 64bit mode with prefix 0x66
+- LOCK NOP is a valid instruction
+- Fix ATT syntax for instruction with zero offset segment register
+- LES/LDS are invalid in 64bit mode
+- Fix number of operands for some MOV instructions
+
+
+[ ARM ]
+
+- Fix POP reg to update SP register
+- Update flags for UADD8 instruction
+
+
+[ ARM64 ]
+
+- Better performance with new lookup table
+- Handle system registers added in ARMv8.1/2
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ Visual Basic binding ]
+
+- New binding
+
+---------------------------------
+Version 3.0.5-rc2: March 2nd, 2017
+
+
+[ Core ]
+
+- Fix build for Visual Studio 2012
+- Fix X86_REL_ADDR macro
+- Add CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA
+- Better support for embedding Capstone into Windows kernel drivers
+- Support to embedded Capstone into MacOS kernel
+- Support MacOS 10.11 and up
+- Better support for Cygwin
+- Support build packages for FreeBSD & DragonflyBSD
+- Add a command-line tool "cstool"
+- Properly handle switching to Endian mode at run-time for Arm, Arm64, Mips & Sparc
+
+
+[ X86 ]
+
+- Some random 16-bit code can be handled wrongly.
+- Remove abundant operand type X86_OP_FP
+- Fix instructions MOVQ, LOOP, LOOPE, LOOPNE, CALL/JMP rel16, REPNE LODSD, MOV *AX, MOFFS, FAR JMP/CALL
+- Add X86_REG_EFLAGS for STC and STD
+- Fix instruction attributes for SYSEXIT, MOVW, ROL, LGS, SLDT
+- Rename registers ST0-ST7 to be consistent with asm output
+
+
+[ ARM ]
+
+- Properly handle IT instruction
+- Fix LDRSB
+- Fix writeback for LDR
+- Fix Thumb BigEndian setup
+
+
+[ ARM64 ]
+
+- Fix arith extender
+- Fix writeback for LDR
+- Rename enum arm64_mrs_reg to arm64_sysreg
+
+
+[ PowerPC ]
+
+- Print 0 offset for memory operand
+
+
+[ Sparc ]
+
+- Fix POPC instruction
+
+
+[ Python binding ]
+
+- Better PyPy support
+- Add __version__
+- Better support for Python 3
+- Fix CS_SKIPDATA_CALLBACK prototype
+- Cast skipdata function inside binding to simplify the API
+
+
+[ Java binding ]
+
+- Better handle input with invalid code
+
+
+[ PowerShell ]
+
+- New binding
+
+---------------------------------
+Version 3.0.4: July 15th, 2015
+
+
+[ Library ]
+
+- Improve cross-compile for Android using Android NDK.
+- Support cross-compile for AArch64 Android (with Linux GCC).
+- Removed osxkernel_inttypes.h that is incompatible with BSD license.
+- Make it possible to compile with CC having a space inside (like "ccache gcc").
+
+
+[ X86 ]
+
+- Fix a null pointer dereference bug on handling code with special prefixes.
+- Properly handle AL/AX/EAX operand for OUT instruction in AT&T syntax.
+- Print immediate operand in positive form in some algorithm instructions.
+- Properly decode some SSE instructions.
+
+
+[ PowerPC ]
+
+- Fixed a memory corruption bug.
+- Fixed a memory corruption bug for the engine built in DIET mode.
+
+
+[ Mips ]
+
+- Fixed instruction ID of SUBU instruction.
+- Fixed a memory corruption bug.
+
+
+[ Arm ]
+
+- Fixed a memory corruption bug on IT instruction.
+
+
+[ XCore ]
+
+- Fixed a memory corruption bug when instruction has a memory operand.
+
+
+[ Python ]
+
+- Support Virtualenv.
+- setup.py supports option --user if not in a virtualenv to allow for local usage.
+- Properly handle the destruction of Cs object in the case the shared library
+  was already unloaded.
+
+---------------------------------
+Version 3.0.3: May 08th, 2015
+
+
+[ Library ]
+
+- Support to embed into Mac OS X kernel extensions.
+- Now it is possible to compile Capstone with older C compilers, such as
+  GCC 4.8 on Ubuntu 12.04.
+- Add "test_iter" to MSVC project.
+
+
+[ X86 ]
+
+- All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
+  $1 as first operand in *AT&T* syntax (so we have "rcll $1, %edx" instead of
+  "rcll %edx").
+- CMPXCHG16B is a valid instruction with LOCK prefix.
+- Fixed a segfault on the input of 0xF3.
+
+
+[ Arm ]
+
+- BLX instruction modifies PC & LR registers.
+
+
+[ Sparc ]
+
+- Improved displacement decoding for sparc banching instructions.
+
+
+[ Python binding ]
+
+- Fix for Cython so it can properly initialize.
+- X86Op.avx_zero_mask now has c_bool type, but not c_uint8 type.
+- Properly support compile with Cygwin & install binding (setup.py).
+
+---------------------------------
+Version 3.0.2: March 11th, 2015
+
+
+[ Library ]
+
+- On *nix, only export symbols that are part of the API (instead of all
+  the internal symbols).
+
+
+[ X86 ]
+
+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
+- Fix implicit registers read/written & instruction groups of some instructions.
+- More flexible on the order of prefixes, so better handle some tricky
+  instructions.
+- REPNE prefix can go with STOS & MOVS instructions.
+- Fix a compilation bug for X86_REDUCE mode.
+- Fix operand size of instructions with operand PTR []
+
+
+[ Arm ]
+
+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
+- Fix a bug on handling the If-Then block.
+
+
+[ Mips ]
+
+- Sanity check for the input size for MIPS64 mode.
+
+
+[ MSVC ]
+
+- Compile capstone.dll with static runtime MSVCR built in.
+
+
+[ Python binding ]
+
+- Fix a compiling issue of Cython binding with gcc 4.9.
+
+---------------------------------
+Version 3.0.1: February 03rd, 2015
+
+[ X86 ]
+
+- Properly handle LOCK, REP, REPE & REPNE prefixes.
+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
+- Print LJUMP/LCALL without * as prefix for Intel syntax.
+- Handle REX prefix properly for segment/MMX related instructions (x86_64).
+- Instruction with length > 15 is consider invalid.
+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
+  FSTP, FSTPNCE, NOP.
+- Handle some tricky code for some X86_64 instructions with REX prefix.
+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
+- MOV32ms & MOV32sm should reference word rather than dword.
+
+
+[ Arm64 ]
+
+- BL & BLR instructions do not read SP register.
+- Print absolute (rather than relative) address for instructions B, BL,
+  CBNZ, ADR.
+
+
+[ Arm ]
+
+- Instructions ADC & SBC do not update flags.
+- BL & BLX do not read SP, but PC register.
+- Alias LDR instruction with operands [sp], 4 to POP.
+- Print immediate operand of MVN instruction in positive hexadecimal form.
+
+
+[ PowerPC ]
+
+- Fix some compilation bugs when DIET mode is enable.
+- Populate SLWI/SRWI instruction details with SH operand.
+
+
+[ Python binding ]
+
+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
+- Fixed a memory leak for Cython disasm functions when we immaturely quit
+  the enumeration of disassembled instructions.
+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
+  at the same time.
+- Fix a memory leaking bug when when we stop enumeration over the disassembled
+  instructions prematurely.
+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
+
+---------------------------------
+Version 3.0: November 19th, 2014
+
+[ API ]
+
+- New API: cs_disasm_iter & cs_malloc. See docs/README for tutorials.
+- Renamed cs_disasm_ex to cs_disasm (cs_disasm_ex is still supported, but
+  marked obsolete to be removed in future)
+- Support SKIPDATA mode, so Capstone can jump over unknown data and keep going
+  from the next legitimate instruction. See docs/README for tutorials.
+- More details provided in cs_detail struct for all architectures.
+- API version was bumped to 3.0.
+
+
+[ Bindings ]
+
+- Python binding supports Python3 (besides Python2).
+- Support Ocaml binding.
+- Java: add close() method to be used to deinitialize a Capstone object when
+  no longer use it.
+
+
+[ Architectures ]
+
+- New architectures: Sparc, SystemZ & XCore.
+- Important bugfixes for Arm, Arm64, Mips, PowerPC & X86.
+- Support more instructions for Arm, Arm64, Mips, PowerPC & X86.
+- Always expose absolute addresses rather than relative addresses (Arm, Arm64,
+  Mips, PPC, Sparc, X86).
+- Use common instruction operand types REG, IMM, MEM & FP across all
+  architectures (to enable cross-architecture analysis).
+- Use common instruction group types across all architectures (to enable
+  cross-architecture analysis).
+
+
+[ X86 ]
+
+- X86 engine is mature & handles all the malware tricks (that we are aware of).
+- Added a lot of new instructions (such as AVX512, 3DNow, etc).
+- Add prefix symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE.
+- Print immediate in positive form & hexadecimal for AND/OR/XOR instructions.
+- More friendly disassembly for JMP16i (in the form segment:offset)
+
+
+[ Mips ]
+
+- Engine added supports for new hardware modes: Mips32R6 (CS_MODE_MIPS32R6) &
+  MipsGP64 (CS_MODE_MIPSGP64).
+- Removed the ABI-only mode CS_MODE_N64.
+- New modes CS_MODE_MIPS32 & CS_MODE_MIPS64 (to use instead of CS_MODE_32 &
+  CS_MODE_64).
+
+
+[ ARM ]
+
+- Support new mode CS_MODE_V8 for Armv8 A32 encodings.
+- Print immediate in positive form & hexadecimal for AND/ORR/EOR/BIC instructions
+
+
+[ ARM64 ]
+
+- Print immediate in hexadecimal for AND/ORR/EOR/TST instructions.
+
+
+[ PowerPC ]
+
+- Do not print a dot in front of absolute address.
+
+
+[ Other features ]
+
+- Support for Microsoft Visual Studio (so enable Windows native compilation).
+- Support CMake compilation.
+- Cross-compile for Android.
+- Build libraries/tests using XCode project
+- Much faster, while consuming less memory for all architectures.
+
+---------------------------------
+Version 2.1.2: April 3rd, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.2 just fine.
+
+[ Core changes]
+
+- Support cross-compilation for all iDevices (iPhone/iPad/iPod).
+- X86: do not print memory offset in negative form.
+- Fix a bug in X86 when Capstone cannot handle short instruction.
+- Print negative number above -9 without prefix 0x (arm64, mips, arm).
+- Correct the SONAME setup for library versioning (Linux, *BSD, Solaris).
+- Set library versioning for dylib of OSX.
+
+---------------------------------
+Version 2.1.1: March 13th, 2014
+
+This is a stable release to fix some bugs deep in the core. There is no update
+to any architectures or bindings, so bindings version 2.1 can be used with this
+version 2.1.1 just fine.
+
+[ Core changes]
+
+- Fix a buffer overflow bug in Thumb mode (ARM). Some special input can
+  trigger this flaw.
+- Fix a crash issue when embedding Capstone into OSX kernel. This should
+  also enable Capstone to be embedded into other systems with limited stack
+  memory size such as Linux kernel or some firmwares.
+- Use a proper SONAME for library versioning (Linux).
+
+---------------------------------
+Version 2.1: March 5th, 2014
+
+[ API changes ]
+
+- API version has been bumped to 2.1.
+- Change prototype of cs_close() to be able to invalidate closed handle.
+  See http://capstone-engine.org/version_2.1_API.html for more information.
+- Extend cs_support() to handle more query types, not only about supported
+  architectures. This change is backward compatible, however, so existent code
+  do not need to be modified to support this.
+- New query type CS_SUPPORT_DIET for cs_support() to ask about diet status of
+  the engine.
+- New error code CS_ERR_DIET to report errors about newly added diet mode.
+- New error code CS_ERR_VERSION to report issue of incompatible versions between
+  bindings & core engine.
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses about 40% less memory, while still faster
+  than version 2.0.
+- All architectures are much smaller: binaries size reduce at least 30%.
+  Especially, X86-only binary reduces from 1.9MB to just 720KB.
+- Support "diet" mode, in which engine size is further reduced (by around 40%)
+  for embedding purpose. The price to pay is that we have to sacrifice some
+  non-critical data fields. See http://capstone-engine.org/diet.html for more
+  details.
+
+
+[ Architectures ]
+
+- Update all 5 architectures to fix bugs.
+- PowerPC:
+	- New instructions: FMR & MSYNC.
+- Mips:
+	- New instruction: DLSA
+- X86:
+	- Properly handle AVX-512 instructions.
+	- New instructions: PSETPM, SALC, INT1, GETSEC.
+	- Fix some memory leaking issues in case of prefixed instructions such
+	  as LOCK, REP, REPNE.
+
+
+[ Python binding ]
+
+- Verify the core version at initialization time. Refuse to run if its version
+  is different from the core's version.
+- New API disasm_lite() added to Cs class. This light API only returns tuples of
+  (address, size, mnemonic, op_str), rather than list of CsInsn objects. This
+  improves performance by around 30% in some benchmarks.
+- New API version_bind() returns binding's version, which might differ from
+  the core's API version if the binding is out-of-date.
+- New API debug() returns information on Cython support, diet status & archs
+  compiled in.
+- Fixed some memory leaking bugs for Cython binding.
+- Fix a bug crashing Cython code when accessing @regs_read/regs_write/groups.
+- Support diet mode.
+
+
+[ Java binding ]
+
+- Fix some memory leaking bugs.
+- New API version() returns combined version.
+- Support diet mode.
+- Better support for detail option.
+
+
+[ Miscellaneous ]
+
+- make.sh now can uninstall the core engine. This is done with:
+
+	$ sudo ./make.sh uninstall
+
+----------------------------------
+Version 2.0: January 22nd, 2014
+
+Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes.
+
+[ API changes ]
+
+- API version has been bumped to 2.0 (see cs_version() API)
+- New API cs_strerror(errno) returns a string describing error code given
+  in its only argument.
+- cs_version() now returns combined version encoding both major & minor versions.
+- New option CS_OPT_MODE allows to change engine’s mode at run-time with
+  cs_option().
+- New option CS_OPT_MEM allows to specify user-defined functions for dynamically
+  memory management used internally by Capstone. This is useful to embed Capstone
+  into special environments such as kernel or firware.
+- New API cs_support() can be used to check if this lib supports a particular
+  architecture (this is necessary since we now allow to choose which architectures
+  to compile in).
+- The detail option is OFF by default now. To get detail information, it should be
+  explicitly turned ON. The details then can be accessed using cs_insn.detail
+  pointer (to newly added structure cs_detail)
+
+
+[ Core changes ]
+
+- On memory usage, Capstone uses much less memory, but a lot faster now.
+- User now can choose which architectures to be supported by modifying config.mk
+  before compiling/installing.
+
+
+[ Architectures ]
+
+- Arm
+     - Support Big-Endian mode (besides Little-Endian mode).
+     - Support friendly register, so instead of output sub "r12,r11,0x14",
+	 we have "sub ip,fp,0x14".
+- Arm64: support Big-Endian mode (besides Little-Endian mode).
+- PowerPC: newly added.
+- Mips: support friendly register, so instead of output "srl $2,$1,0x1f",
+     we have "srl $v0,$at,0x1f".
+- X86: bug fixes.
+
+
+[ Python binding ]
+
+- Python binding is vastly improved in performance: around 3 ~ 4 times faster
+  than in 1.0.
+- Cython support has been added, which can further speed up over the default
+  pure Python binding (up to 30% in some cases)
+- Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list)
+  to return succesfully disassembled instructions. This improves the performance
+  and reduces memory usage.
+
+
+[ Java binding ]
+
+- Better performance & bug fixes.
+
+
+[ Miscellaneous ]
+
+- Fixed some installation issues with Gentoo Linux.
+- Capstone now can easily compile/install on all *nix, including Linux, OSX,
+  {Net, Free, Open}BSD & Solaris.
+
+----------------------------------
+[Version 1.0]: December 18th, 2013
+
+- Initial public release.
+

HACK.TXT

@@ -0,0 +1,102 @@
+Code structure
+--------------
+
+Capstone source is organized as followings.
+
+.                   <- core engine + README + COMPILE.TXT etc
+├── arch            <- code handling disasm engine for each arch
+│   ├── AArch64     <- ARM64 (aka ARMv8) engine
+│   ├── ARM         <- ARM engine
+│   ├── EVM         <- Ethereum engine
+│   ├── M680X       <- M680X engine
+│   ├── M68K        <- M68K engine
+│   ├── Mips        <- Mips engine
+│   ├── MOS65XX     <- MOS65XX engine
+│   ├── PowerPC     <- PowerPC engine
+│   ├── Sparc       <- Sparc engine
+│   ├── SystemZ     <- SystemZ engine
+│   ├── TMS320C64x  <- TMS320C64x engine
+│   ├── X86         <- X86 engine
+│   └── XCore       <- XCore engine
+├── bindings        <- all bindings are under this dir
+│   ├── java        <- Java bindings + test code
+│   ├── ocaml       <- Ocaml bindings + test code
+│   └── python      <- Python bindings + test code
+├── contrib         <- Code contributed by community to help Capstone integration
+├── cstool          <- Cstool
+├── docs            <- Documentation
+├── include         <- API headers in C language (*.h)
+├── msvc            <- Microsoft Visual Studio support (for Windows compile)
+├── packages        <- Packages for Linux/OSX/BSD.
+├── windows         <- Windows support (for Windows kernel driver compile)
+├── suite           <- Development test tools - for Capstone developers only
+├── tests           <- Test code (in C language)
+└── xcode           <- Xcode support (for MacOSX compile)
+
+
+Follow instructions in COMPILE.TXT for how to compile and run test code.
+
+Note: if you find some strange bugs, it is recommended to firstly clean
+the code and try to recompile/reinstall again. This can be done with:
+
+	$ ./make.sh
+	$ sudo ./make.sh install
+
+Then test Capstone with cstool, for example:
+
+	$ cstool x32 "90 91"
+
+At the same time, for Java/Ocaml/Python bindings, be sure to always use
+the bindings coming with the core to avoid potential incompatibility issue
+with older versions.
+See bindings/<language>/README for detail instructions on how to compile &
+install the bindings.
+
+
+Coding style
+------------
+- C code follows Linux kernel coding style, using tabs for indentation.
+- Python code uses 4 spaces for indentation.
+
+
+Adding an architecture
+----------------------
+
+Obviously, you first need to write all the logic and put it in a new directory arch/newarch
+Then, you have to modify other files.
+(You can look for one architecture such as EVM in these files to get what you need to do)
+
+Integrate:
+- cs.c
+- cstool/cstool.c
+- cstool/cstool_newarch.c: print the architecture specific details
+- include/capstone/capstone.h
+- include/capstone/newarch.h: create this file to export all specifics about the new architecture
+
+Compile:
+- CMakeLists.txt
+- Makefile
+- config.mk
+
+Tests:
+- tests/Makefile
+- tests/test_basic.c
+- tests/test_detail.c
+- tests/test_iter.c
+- tests/test_newarch.c
+- suite/fuzz/fuzz_disasm.c: add the architecture and its modes to the list of fuzzed platforms
+
+Bindings:
+- bindings/Makefile
+- bindings/const_generator.py: add the header file and the architecture
+- bindings/python/Makefile
+- bindings/python/capstone/__init__.py
+- bindings/python/capstone/newarch.py: define the python structures
+- bindings/python/capstone/newarch_const.py: generate this file
+- bindings/python/test_newarch.py: create a basic decoding test
+- bindings/python/test_all.py
+
+Docs:
+- README.md
+- HACK.txt
+- CREDITS.txt: add your name

LEB128.h

@@ -0,0 +1,38 @@
+//===- llvm/Support/LEB128.h - [SU]LEB128 utility functions -----*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares some utility functions for encoding SLEB128 and
+// ULEB128 values.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_LLVM_SUPPORT_LEB128_H
+#define CS_LLVM_SUPPORT_LEB128_H
+
+#include "include/capstone/capstone.h"
+
+/// Utility function to decode a ULEB128 value.
+static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
+{
+	const uint8_t *orig_p = p;
+	uint64_t Value = 0;
+	unsigned Shift = 0;
+	do {
+		Value += (uint64_t)(*p & 0x7f) << Shift;
+		Shift += 7;
+	} while (*p++ >= 128);
+	if (n)
+		*n = (unsigned)(p - orig_p);
+	return Value;
+}
+
+#endif  // LLVM_SYSTEM_LEB128_H

LICENSE.TXT

@@ -0,0 +1,31 @@
+This is the software license for Capstone disassembly framework.
+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
+
+See http://www.capstone-engine.org for further information.
+
+Copyright (c) 2013, COSEINC.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+* Neither the name of the developer(s) nor the names of its
+  contributors may be used to endorse or promote products derived from this
+  software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.

LICENSE_LLVM.TXT

@@ -0,0 +1,71 @@
+==============================================================================
+LLVM Release License
+==============================================================================
+University of Illinois/NCSA
+Open Source License
+
+Copyright (c) 2003-2013 University of Illinois at Urbana-Champaign.
+All rights reserved.
+
+Developed by:
+
+    LLVM Team
+
+    University of Illinois at Urbana-Champaign
+
+    http://llvm.org
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal with
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimers.
+
+    * Redistributions in binary form must reproduce the above copyright notice,
+      this list of conditions and the following disclaimers in the
+      documentation and/or other materials provided with the distribution.
+
+    * Neither the names of the LLVM Team, University of Illinois at
+      Urbana-Champaign, nor the names of its contributors may be used to
+      endorse or promote products derived from this Software without specific
+      prior written permission.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+SOFTWARE.
+
+==============================================================================
+Copyrights and Licenses for Third Party Software Distributed with LLVM:
+==============================================================================
+The LLVM software contains code written by third parties.  Such software will
+have its own individual LICENSE.TXT file in the directory in which it appears.
+This file will describe the copyrights, license, and restrictions which apply
+to that code.
+
+The disclaimer of warranty in the University of Illinois Open Source License
+applies to all code in the LLVM Distribution, and nothing in any of the
+other licenses gives permission to use the names of the LLVM Team or the
+University of Illinois to endorse or promote products derived from this
+Software.
+
+The following pieces of software have additional or alternate copyrights,
+licenses, and/or restrictions:
+
+Program             Directory
+-------             ---------
+Autoconf            llvm/autoconf
+                    llvm/projects/ModuleMaker/autoconf
+                    llvm/projects/sample/autoconf
+Google Test         llvm/utils/unittest/googletest
+OpenBSD regex       llvm/lib/Support/{reg*, COPYRIGHT.regex}
+pyyaml tests        llvm/test/YAMLParser/{*.data, LICENSE.TXT}
+ARM contributions   llvm/lib/Target/ARM/LICENSE.TXT
+md5 contributions   llvm/lib/Support/MD5.cpp llvm/include/llvm/Support/MD5.h

MCDisassembler.h

@@ -0,0 +1,14 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_MCDISASSEMBLER_H
+#define CS_MCDISASSEMBLER_H
+
+typedef enum DecodeStatus {
+	MCDisassembler_Fail = 0,
+	MCDisassembler_SoftFail = 1,
+	MCDisassembler_Success = 3,
+} DecodeStatus;
+
+#endif
+

MCFixedLenDisassembler.h

@@ -0,0 +1,30 @@
+//===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// Fixed length disassembler decoder state machine driver.
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+#define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
+
+// Disassembler state machine opcodes.
+enum DecoderOps {
+	MCD_OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
+	MCD_OPC_FilterValue,      // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
+	MCD_OPC_CheckField,       // OPC_CheckField(uint8_t Start, uint8_t Len,
+							  //                uleb128 Val, uint16_t NumToSkip)
+	MCD_OPC_CheckPredicate,   // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
+	MCD_OPC_Decode,           // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
+	MCD_OPC_SoftFail,         // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
+	MCD_OPC_Fail              // OPC_Fail()
+};
+
+#endif

MCInst.c

@@ -0,0 +1,182 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <Availability.h>
+#include <libkern/libkern.h>
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+#include <string.h>
+
+#include "MCInst.h"
+#include "utils.h"
+
+#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
+
+void MCInst_Init(MCInst *inst)
+{
+	unsigned int i;
+
+	for (i = 0; i < 48; i++) {
+		inst->Operands[i].Kind = kInvalid;
+		inst->Operands[i].ImmVal = 0;
+	}
+
+	inst->Opcode = 0;
+	inst->OpcodePub = 0;
+	inst->size = 0;
+	inst->has_imm = false;
+	inst->op1_size = 0;
+	inst->writeback = false;
+	inst->ac_idx = 0;
+	inst->popcode_adjust = 0;
+	inst->assembly[0] = '\0';
+}
+
+void MCInst_clear(MCInst *inst)
+{
+	inst->size = 0;
+}
+
+// do not free @Op
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
+{
+	int i;
+
+	for(i = inst->size; i > index; i--)
+		//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
+		inst->Operands[i] = inst->Operands[i-1];
+
+	inst->Operands[index] = *Op;
+	inst->size++;
+}
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op)
+{
+	inst->Opcode = Op;
+}
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
+{
+	inst->OpcodePub = Op;
+}
+
+unsigned MCInst_getOpcode(const MCInst *inst)
+{
+	return inst->Opcode;
+}
+
+unsigned MCInst_getOpcodePub(const MCInst *inst)
+{
+	return inst->OpcodePub;
+}
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
+{
+	return &inst->Operands[i];
+}
+
+unsigned MCInst_getNumOperands(const MCInst *inst)
+{
+	return inst->size;
+}
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
+{
+	inst->Operands[inst->size] = *Op;
+
+	inst->size++;
+}
+
+bool MCOperand_isValid(const MCOperand *op)
+{
+	return op->Kind != kInvalid;
+}
+
+bool MCOperand_isReg(const MCOperand *op)
+{
+	return op->Kind == kRegister;
+}
+
+bool MCOperand_isImm(const MCOperand *op)
+{
+	return op->Kind == kImmediate;
+}
+
+bool MCOperand_isFPImm(const MCOperand *op)
+{
+	return op->Kind == kFPImmediate;
+}
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op)
+{
+	return op->RegVal;
+}
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg)
+{
+	op->RegVal = Reg;
+}
+
+int64_t MCOperand_getImm(MCOperand *op)
+{
+	return op->ImmVal;
+}
+
+void MCOperand_setImm(MCOperand *op, int64_t Val)
+{
+	op->ImmVal = Val;
+}
+
+double MCOperand_getFPImm(const MCOperand *op)
+{
+	return op->FPImmVal;
+}
+
+void MCOperand_setFPImm(MCOperand *op, double Val)
+{
+	op->FPImmVal = Val;
+}
+
+MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+
+	return op;
+}
+
+void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
+{
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->Kind = kRegister;
+	op->RegVal = Reg;
+}
+
+MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
+{
+	MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
+
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+
+	return op;
+}
+
+void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
+{
+	MCOperand *op = &(mcInst->Operands[mcInst->size]);
+	mcInst->size++;
+
+	op->Kind = kImmediate;
+	op->ImmVal = Val;
+}

MCInst.h

@@ -0,0 +1,135 @@
+//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the MCInst and MCOperand classes, which
+// is the basic representation used to represent low-level machine code
+// instructions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_MCINST_H
+#define CS_MCINST_H
+
+#include "include/capstone/capstone.h"
+
+typedef struct MCInst MCInst;
+typedef struct cs_struct cs_struct;
+typedef struct MCOperand MCOperand;
+
+/// MCOperand - Instances of this class represent operands of the MCInst class.
+/// This is a simple discriminated union.
+struct MCOperand {
+	enum {
+		kInvalid = 0,                 ///< Uninitialized.
+		kRegister,                ///< Register operand.
+		kImmediate,               ///< Immediate operand.
+		kFPImmediate,             ///< Floating-point immediate operand.
+	} MachineOperandType;
+	unsigned char Kind;
+
+	union {
+		unsigned RegVal;
+		int64_t ImmVal;
+		double FPImmVal;
+	};
+};
+
+bool MCOperand_isValid(const MCOperand *op);
+
+bool MCOperand_isReg(const MCOperand *op);
+
+bool MCOperand_isImm(const MCOperand *op);
+
+bool MCOperand_isFPImm(const MCOperand *op);
+
+bool MCOperand_isInst(const MCOperand *op);
+
+/// getReg - Returns the register number.
+unsigned MCOperand_getReg(const MCOperand *op);
+
+/// setReg - Set the register number.
+void MCOperand_setReg(MCOperand *op, unsigned Reg);
+
+int64_t MCOperand_getImm(MCOperand *op);
+
+void MCOperand_setImm(MCOperand *op, int64_t Val);
+
+double MCOperand_getFPImm(const MCOperand *op);
+
+void MCOperand_setFPImm(MCOperand *op, double Val);
+
+const MCInst *MCOperand_getInst(const MCOperand *op);
+
+void MCOperand_setInst(MCOperand *op, const MCInst *Val);
+
+// create Reg operand in the next slot
+void MCOperand_CreateReg0(MCInst *inst, unsigned Reg);
+
+// create Reg operand use the last-unused slot
+MCOperand *MCOperand_CreateReg1(MCInst *inst, unsigned Reg);
+
+// create Imm operand in the next slot
+void MCOperand_CreateImm0(MCInst *inst, int64_t Val);
+
+// create Imm operand in the last-unused slot
+MCOperand *MCOperand_CreateImm1(MCInst *inst, int64_t Val);
+
+/// MCInst - Instances of this class represent a single low-level machine
+/// instruction.
+struct MCInst {
+	unsigned OpcodePub;
+	uint8_t size;	// number of operands
+	bool has_imm;	// indicate this instruction has an X86_OP_IMM operand - used for ATT syntax
+	uint8_t op1_size; // size of 1st operand - for X86 Intel syntax
+	unsigned Opcode;
+	MCOperand Operands[48];
+	cs_insn *flat_insn;	// insn to be exposed to public
+	uint64_t address;	// address of this insn
+	cs_struct *csh;	// save the main csh
+	uint8_t x86opsize;	// opsize for [mem] operand
+
+	// (Optional) instruction prefix, which can be up to 4 bytes.
+	// A prefix byte gets value 0 when irrelevant.
+	// This is copied from cs_x86 struct
+	uint8_t x86_prefix[4];
+	uint8_t imm_size;	// immediate size for X86_OP_IMM operand
+	bool writeback;	// writeback for ARM
+	// operand access index for list of registers sharing the same access right (for ARM)
+	uint8_t ac_idx;
+	uint8_t popcode_adjust;   // Pseudo X86 instruction adjust
+	char assembly[8];	// for special instruction, so that we dont need printer
+	unsigned char evm_data[32];	// for EVM PUSH operand
+};
+
+void MCInst_Init(MCInst *inst);
+
+void MCInst_clear(MCInst *inst);
+
+// do not free operand after inserting
+void MCInst_insert0(MCInst *inst, int index, MCOperand *Op);
+
+void MCInst_setOpcode(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcode(const MCInst*);
+
+void MCInst_setOpcodePub(MCInst *inst, unsigned Op);
+
+unsigned MCInst_getOpcodePub(const MCInst*);
+
+MCOperand *MCInst_getOperand(MCInst *inst, unsigned i);
+
+unsigned MCInst_getNumOperands(const MCInst *inst);
+
+// This addOperand2 function doesnt free Op
+void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
+
+#endif

MCInstrDesc.c

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include "MCInstrDesc.h"
+
+/// isPredicate - Set if this is one of the operands that made up of
+/// the predicate operand that controls an isPredicable() instruction.
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_Predicate);
+}
+
+/// isOptionalDef - Set if this operand is a optional def.
+///
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m)
+{
+	return m->Flags & (1 << MCOI_OptionalDef);
+}

MCInstrDesc.h

@@ -0,0 +1,144 @@
+//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MCOperandInfo and MCInstrDesc classes, which
+// are used to describe target instructions and their operands.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_LLVM_MC_MCINSTRDESC_H
+#define CS_LLVM_MC_MCINSTRDESC_H
+
+#include "capstone/platform.h"
+
+//===----------------------------------------------------------------------===//
+// Machine Operand Flags and Description
+//===----------------------------------------------------------------------===//
+
+// Operand constraints
+enum MCOI_OperandConstraint {
+	MCOI_TIED_TO = 0,    // Must be allocated the same register as.
+	MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
+};
+
+/// OperandFlags - These are flags set on operands, but should be considered
+/// private, all access should go through the MCOperandInfo accessors.
+/// See the accessors for a description of what these are.
+enum MCOI_OperandFlags {
+	MCOI_LookupPtrRegClass = 0,
+	MCOI_Predicate,
+	MCOI_OptionalDef
+};
+
+/// Operand Type - Operands are tagged with one of the values of this enum.
+enum MCOI_OperandType {
+	MCOI_OPERAND_UNKNOWN,
+	MCOI_OPERAND_IMMEDIATE,
+	MCOI_OPERAND_REGISTER,
+	MCOI_OPERAND_MEMORY,
+	MCOI_OPERAND_PCREL
+};
+
+
+/// MCOperandInfo - This holds information about one operand of a machine
+/// instruction, indicating the register class for register operands, etc.
+///
+typedef struct MCOperandInfo {
+	/// RegClass - This specifies the register class enumeration of the operand
+	/// if the operand is a register.  If isLookupPtrRegClass is set, then this is
+	/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
+	/// get a dynamic register class.
+	int16_t RegClass;
+
+	/// Flags - These are flags from the MCOI::OperandFlags enum.
+	uint8_t Flags;
+
+	/// OperandType - Information about the type of the operand.
+	uint8_t OperandType;
+
+	/// Lower 16 bits are used to specify which constraints are set. The higher 16
+	/// bits are used to specify the value of constraints (4 bits each).
+	uint32_t Constraints;
+	/// Currently no other information.
+} MCOperandInfo;
+
+
+//===----------------------------------------------------------------------===//
+// Machine Instruction Flags and Description
+//===----------------------------------------------------------------------===//
+
+/// MCInstrDesc flags - These should be considered private to the
+/// implementation of the MCInstrDesc class.  Clients should use the predicate
+/// methods on MCInstrDesc, not use these directly.  These all correspond to
+/// bitfields in the MCInstrDesc::Flags field.
+enum {
+	MCID_Variadic = 0,
+	MCID_HasOptionalDef,
+	MCID_Pseudo,
+	MCID_Return,
+	MCID_Call,
+	MCID_Barrier,
+	MCID_Terminator,
+	MCID_Branch,
+	MCID_IndirectBranch,
+	MCID_Compare,
+	MCID_MoveImm,
+	MCID_Bitcast,
+	MCID_Select,
+	MCID_DelaySlot,
+	MCID_FoldableAsLoad,
+	MCID_MayLoad,
+	MCID_MayStore,
+	MCID_Predicable,
+	MCID_NotDuplicable,
+	MCID_UnmodeledSideEffects,
+	MCID_Commutable,
+	MCID_ConvertibleTo3Addr,
+	MCID_UsesCustomInserter,
+	MCID_HasPostISelHook,
+	MCID_Rematerializable,
+	MCID_CheapAsAMove,
+	MCID_ExtraSrcRegAllocReq,
+	MCID_ExtraDefRegAllocReq,
+	MCID_RegSequence,
+	MCID_ExtractSubreg,
+	MCID_InsertSubreg
+};
+
+/// MCInstrDesc - Describe properties that are true of each instruction in the
+/// target description file.  This captures information about side effects,
+/// register use and many other things.  There is one instance of this struct
+/// for each target instruction class, and the MachineInstr class points to
+/// this struct directly to describe itself.
+typedef struct MCInstrDesc {
+	unsigned short  Opcode;        // The opcode number
+	unsigned char  NumOperands;   // Num of args (may be more if variable_ops)
+	unsigned char  NumDefs;       // Num of args that are definitions
+	unsigned short  SchedClass;    // enum identifying instr sched class
+	unsigned char  Size;          // Number of bytes in encoding.
+	unsigned        Flags;         // Flags identifying machine instr class
+	uint64_t        TSFlags;       // Target Specific Flag values
+	char ImplicitUses;  // Registers implicitly read by this instr
+	char ImplicitDefs;  // Registers implicitly defined by this instr
+	const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
+	uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any     
+	// A complex method to determine is a certain is deprecated or not, and return        
+	// the reason for deprecation.
+	//bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);           
+	unsigned char ComplexDeprecationInfo;	// dummy field, just to satisfy initializer
+} MCInstrDesc;
+
+bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
+
+bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
+
+#endif

MCRegisterInfo.c

@@ -0,0 +1,143 @@
+//=== MC/MCRegisterInfo.cpp - Target Register Description -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements MCRegisterInfo functions.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include "MCRegisterInfo.h"
+
+/// DiffListIterator - Base iterator class that can traverse the
+/// differentially encoded register and regunit lists in DiffLists.
+/// Don't use this class directly, use one of the specialized sub-classes
+/// defined below.
+typedef struct DiffListIterator {
+	uint16_t Val;
+	const MCPhysReg *List;
+} DiffListIterator;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		const MCRegisterDesc *D, unsigned NR,
+		unsigned RA, unsigned PC,
+		const MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2], unsigned NRU,
+		const MCPhysReg *DL,
+		const char *Strings,
+		const uint16_t *SubIndices, unsigned NumIndices,
+		const uint16_t *RET)
+{
+	RI->Desc = D;
+	RI->NumRegs = NR;
+	RI->RAReg = RA;
+	RI->PCReg = PC;
+	RI->Classes = C;
+	RI->DiffLists = DL;
+	RI->RegStrings = Strings;
+	RI->NumClasses = NC;
+	RI->RegUnitRoots = RURoots;
+	RI->NumRegUnits = NRU;
+	RI->SubRegIndices = SubIndices;
+	RI->NumSubRegIndices = NumIndices;
+	RI->RegEncodingTable = RET;
+}
+
+static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList)
+{
+	d->Val = InitVal;
+	d->List = DiffList;
+}
+
+static uint16_t DiffListIterator_getVal(DiffListIterator *d)
+{
+	return d->Val;
+}
+
+static bool DiffListIterator_next(DiffListIterator *d)
+{
+	MCPhysReg D;
+
+	if (d->List == 0)
+		return false;
+
+	D = *d->List;
+	d->List++;
+	d->Val += D;
+
+	if (!D)
+		d->List = 0;
+
+	return (D != 0);
+}
+
+static bool DiffListIterator_isValid(DiffListIterator *d)
+{
+	return (d->List != 0);
+}
+
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC)
+{
+	DiffListIterator iter;
+
+	if (Reg >= RI->NumRegs) {
+		return 0;
+	}
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		uint16_t val = DiffListIterator_getVal(&iter);
+		if (MCRegisterClass_contains(RC, val) && Reg ==  MCRegisterInfo_getSubReg(RI, val, SubIdx))
+			return val;
+
+		DiffListIterator_next(&iter);
+	}
+
+	return 0;
+}
+
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
+{
+	DiffListIterator iter;
+	const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
+
+	DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
+	DiffListIterator_next(&iter);
+
+	while(DiffListIterator_isValid(&iter)) {
+		if (*SRI == Idx)
+			return DiffListIterator_getVal(&iter);
+		DiffListIterator_next(&iter);
+		++SRI;
+	}
+
+	return 0;
+}
+
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i)
+{
+	//assert(i < getNumRegClasses() && "Register Class ID out of range");
+	if (i >= RI->NumClasses)
+		return 0;
+	return &(RI->Classes[i]);
+}
+
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg)
+{
+	unsigned InByte = Reg % 8;
+	unsigned Byte = Reg / 8;
+
+	if (Byte >= c->RegSetSize)
+		return false;
+
+	return (c->RegSet[Byte] & (1 << InByte)) != 0;
+}

MCRegisterInfo.h

@@ -0,0 +1,116 @@
+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information about a
+// target machines register file.  This information is used for a variety of
+// purposed, especially register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_LLVM_MC_MCREGISTERINFO_H
+#define CS_LLVM_MC_MCREGISTERINFO_H
+
+#include "capstone/platform.h"
+
+/// An unsigned integer type large enough to represent all physical registers,
+/// but not necessarily virtual registers.
+typedef uint16_t MCPhysReg;
+typedef const MCPhysReg* iterator;
+
+typedef struct MCRegisterClass {
+	iterator RegsBegin;
+	const uint8_t *RegSet;
+	uint32_t NameIdx;
+	uint16_t RegsSize;
+	uint16_t RegSetSize;
+	uint16_t ID;
+	uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
+	int8_t CopyCost;
+	bool Allocatable;
+} MCRegisterClass;
+
+/// MCRegisterDesc - This record contains information about a particular
+/// register.  The SubRegs field is a zero terminated array of registers that
+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
+/// of AX. The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of the specific register, e.g. RAX, EAX, are
+/// super-registers of AX.
+///
+typedef struct MCRegisterDesc {
+	uint32_t Name;      // Printable name for the reg (for debugging)
+	uint32_t SubRegs;   // Sub-register set, described above
+	uint32_t SuperRegs; // Super-register set, described above
+
+	// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
+	// sub-register in SubRegs.
+	uint32_t SubRegIndices;
+
+	// RegUnits - Points to the list of register units. The low 4 bits holds the
+	// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
+	uint32_t RegUnits;
+
+	/// Index into list with lane mask sequences. The sequence contains a lanemask
+	/// for every register unit.
+	uint16_t RegUnitLaneMasks;
+} MCRegisterDesc;
+
+/// MCRegisterInfo base class - We assume that the target defines a static
+/// array of MCRegisterDesc objects that represent all of the machine
+/// registers that the target has.  As such, we simply have to track a pointer
+/// to this array so that we can turn register number into a register
+/// descriptor.
+///
+/// Note this class is designed to be a base class of TargetRegisterInfo, which
+/// is the interface used by codegen. However, specific targets *should never*
+/// specialize this class. MCRegisterInfo should only contain getters to access
+/// TableGen generated physical register data. It must not be extended with
+/// virtual methods.
+///
+typedef struct MCRegisterInfo {
+	const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+	unsigned NumRegs;                           // Number of entries in the array
+	unsigned RAReg;                             // Return address register
+	unsigned PCReg;                             // Program counter register
+	const MCRegisterClass *Classes;             // Pointer to the regclass array
+	unsigned NumClasses;                        // Number of entries in the array
+	unsigned NumRegUnits;                       // Number of regunits.
+	uint16_t (*RegUnitRoots)[2];          // Pointer to regunit root table.
+	const MCPhysReg *DiffLists;                 // Pointer to the difflists array
+	const char *RegStrings;                     // Pointer to the string table.
+	const uint16_t *SubRegIndices;              // Pointer to the subreg lookup
+	// array.
+	unsigned NumSubRegIndices;                  // Number of subreg indices.
+	const uint16_t *RegEncodingTable;           // Pointer to array of register
+	// encodings.
+} MCRegisterInfo;
+
+void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
+		const MCRegisterDesc *D, unsigned NR, unsigned RA,
+		unsigned PC,
+		const MCRegisterClass *C, unsigned NC,
+		uint16_t (*RURoots)[2],
+		unsigned NRU,
+		const MCPhysReg *DL,
+		const char *Strings,
+		const uint16_t *SubIndices,
+		unsigned NumIndices,
+		const uint16_t *RET);
+
+unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC);
+
+unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
+
+const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i);
+
+bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg);
+
+#endif

Makefile

@@ -0,0 +1,549 @@
+# Capstone Disassembly Engine
+# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
+
+include config.mk
+include pkgconfig.mk	# package version
+include functions.mk
+
+# Verbose output?
+V ?= 0
+
+OS := $(shell uname)
+ifeq ($(OS),Darwin)
+LIBARCHS ?= x86_64
+PREFIX ?= /usr/local
+endif
+
+ifeq ($(PKG_EXTRA),)
+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR)
+else
+PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA)
+endif
+
+ifeq ($(CROSS),)
+RANLIB ?= ranlib
+else ifeq ($(ANDROID), 1)
+CC = $(CROSS)/../../bin/clang
+AR = $(CROSS)/ar
+RANLIB = $(CROSS)/ranlib
+STRIP = $(CROSS)/strip
+else
+CC = $(CROSS)gcc
+AR = $(CROSS)ar
+RANLIB = $(CROSS)ranlib
+STRIP = $(CROSS)strip
+endif
+
+ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
+CFLAGS ?= -Os
+CFLAGS += -DCAPSTONE_DIET
+else
+CFLAGS ?= -O3
+endif
+
+ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
+CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
+endif
+
+CFLAGS += -fPIC -Wall -Wwrite-strings -Wmissing-prototypes -Iinclude
+
+ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
+CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
+endif
+
+ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes)
+CFLAGS += -DCAPSTONE_HAS_OSXKERNEL
+SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path)
+CFLAGS += -mmacosx-version-min=10.5 \
+		  -isysroot$(SDKROOT) \
+		  -I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \
+		  -mkernel \
+		  -fno-builtin
+endif
+
+PREFIX ?= /usr
+DESTDIR ?=
+ifndef BUILDDIR
+BLDIR = .
+OBJDIR = .
+else
+BLDIR = $(abspath $(BUILDDIR))
+OBJDIR = $(BLDIR)/obj
+endif
+INCDIR ?= $(PREFIX)/include
+
+UNAME_S := $(shell uname -s)
+
+LIBDIRARCH ?= lib
+# Uncomment the below line to installs x86_64 libs to lib64/ directory.
+# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
+#LIBDIRARCH ?= lib64
+LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
+BINDIR = $(DESTDIR)$(PREFIX)/bin
+
+LIBDATADIR = $(LIBDIR)
+
+# Don't redefine $LIBDATADIR when global environment variable
+# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework.
+
+ifndef USE_GENERIC_LIBDATADIR
+ifeq ($(UNAME_S), FreeBSD)
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+endif
+ifeq ($(UNAME_S), DragonFly)
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+endif
+endif
+
+INSTALL_BIN ?= install
+INSTALL_DATA ?= $(INSTALL_BIN) -m0644
+INSTALL_LIB ?= $(INSTALL_BIN) -m0755
+
+LIBNAME = capstone
+
+
+DEP_ARM =
+DEP_ARM += $(wildcard arch/ARM/ARM*.inc)
+
+LIBOBJ_ARM =
+ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ARM
+	LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c)
+	LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
+endif
+
+DEP_ARM64 =
+DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc)
+
+LIBOBJ_ARM64 =
+ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_ARM64
+	LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
+	LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_M68K =
+DEP_M68K += $(wildcard arch/M68K/M68K*.h)
+
+LIBOBJ_M68K =
+ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_M68K
+	LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c)
+	LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o)
+endif
+
+DEP_MIPS =
+DEP_MIPS += $(wildcard arch/Mips/Mips*.inc)
+
+LIBOBJ_MIPS =
+ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_MIPS
+	LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c)
+	LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_PPC =
+DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc)
+
+LIBOBJ_PPC =
+ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_POWERPC
+	LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c)
+	LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_SPARC =
+DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc)
+
+LIBOBJ_SPARC =
+ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_SPARC
+	LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c)
+	LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_SYSZ =
+DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc)
+
+LIBOBJ_SYSZ =
+ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_SYSZ
+	LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
+	LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
+endif
+
+
+# by default, we compile full X86 instruction sets
+X86_REDUCE =
+ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE)))
+X86_REDUCE = _reduce
+CFLAGS += -DCAPSTONE_X86_REDUCE -Os
+endif
+
+DEP_X86 =
+DEP_X86 += arch/X86/X86GenAsmWriter$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86GenRegisterInfo.inc
+DEP_X86 += arch/X86/X86MappingInsn$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86MappingInsnOp$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86ImmSize.inc
+
+LIBOBJ_X86 =
+ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_X86
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
+# assembly syntax is irrelevant in Diet mode, when this info is suppressed
+ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
+ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
+endif
+endif
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
+	LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
+endif
+
+
+DEP_XCORE =
+DEP_XCORE += $(wildcard arch/XCore/XCore*.inc)
+
+LIBOBJ_XCORE =
+ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_XCORE
+	LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c)
+	LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_TMS320C64X =
+DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc)
+
+LIBOBJ_TMS320C64X =
+ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_TMS320C64X
+	LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c)
+	LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o)
+endif
+
+DEP_M680X =
+DEP_M680X += $(wildcard arch/M680X/*.inc)
+DEP_M680X += $(wildcard arch/M680X/M680X*.h)
+
+LIBOBJ_M680X =
+ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_M680X
+	LIBSRC_M680X += $(wildcard arch/M680X/*.c)
+	LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_EVM =
+DEP_EVM += $(wildcard arch/EVM/EVM*.inc)
+
+LIBOBJ_EVM =
+ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_EVM
+	LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c)
+	LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_MOS65XX =
+DEP_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.inc)
+
+LIBOBJ_MOS65XX =
+ifneq (,$(findstring mos65xx,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_MOS65XX
+	LIBSRC_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.c)
+	LIBOBJ_MOS65XX += $(LIBSRC_MOS65XX:%.c=$(OBJDIR)/%.o)
+endif
+
+
+LIBOBJ =
+LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ)
+LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX)
+LIBOBJ += $(OBJDIR)/MCInst.o
+
+
+ifeq ($(PKG_EXTRA),)
+PKGCFGDIR = $(LIBDATADIR)/pkgconfig
+else
+PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
+ifeq ($(PKGCFGDIR),)
+PKGCFGDIR = $(LIBDATADIR)/pkgconfig
+endif
+endif
+
+API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
+VERSION_EXT =
+
+IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ")
+ifeq ($(IS_APPLE),1)
+# on MacOS, do not build in Universal format by default
+MACOS_UNIVERSAL ?= no
+ifeq ($(MACOS_UNIVERSAL),yes)
+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+endif
+EXT = dylib
+VERSION_EXT = $(API_MAJOR).$(EXT)
+$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR)
+AR_EXT = a
+# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE
+# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default
+ifneq ($(HOMEBREW_CAPSTONE),1)
+ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
+# remove string check because OSX kernel complains about missing symbols
+CFLAGS += -D_FORTIFY_SOURCE=0
+endif
+endif
+else
+CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
+$(LIBNAME)_LDFLAGS += -shared
+# Cygwin?
+IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l)
+ifeq ($(IS_CYGWIN),1)
+EXT = dll
+AR_EXT = lib
+# Cygwin doesn't like -fPIC
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+else
+# mingw?
+IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l)
+ifeq ($(IS_MINGW),1)
+EXT = dll
+AR_EXT = lib
+# mingw doesn't like -fPIC either
+CFLAGS := $(CFLAGS:-fPIC=)
+# On Windows we need the shared library to be executable
+else
+# Linux, *BSD
+EXT = so
+VERSION_EXT = $(EXT).$(API_MAJOR)
+AR_EXT = a
+$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT)
+endif
+endif
+endif
+
+ifeq ($(CAPSTONE_SHARED),yes)
+ifeq ($(IS_MINGW),1)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
+else ifeq ($(IS_CYGWIN),1)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
+else	# *nix
+LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT)
+CFLAGS += -fvisibility=hidden
+endif
+endif
+
+ifeq ($(CAPSTONE_STATIC),yes)
+ifeq ($(IS_MINGW),1)
+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
+else ifeq ($(IS_CYGWIN),1)
+ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
+else
+ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT)
+endif
+endif
+
+PKGCFGF = $(BLDIR)/$(LIBNAME).pc
+
+.PHONY: all clean install uninstall dist
+
+all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	@V=$(V) CC=$(CC) $(MAKE) -C cstool
+ifndef BUILDDIR
+	$(MAKE) -C tests
+	$(MAKE) -C suite/fuzz
+else
+	$(MAKE) -C tests BUILDDIR=$(BLDIR)
+	$(MAKE) -C suite/fuzz BUILDDIR=$(BLDIR)
+endif
+	$(call install-library,$(BLDIR)/tests/)
+endif
+
+ifeq ($(CAPSTONE_SHARED),yes)
+$(LIBRARY): $(LIBOBJ)
+ifeq ($(V),0)
+	$(call log,LINK,$(@:$(BLDIR)/%=%))
+	@$(create-library)
+else
+	$(create-library)
+endif
+endif
+
+$(LIBOBJ): config.mk *.h include/capstone/*.h
+
+$(LIBOBJ_ARM): $(DEP_ARM)
+$(LIBOBJ_ARM64): $(DEP_ARM64)
+$(LIBOBJ_M68K): $(DEP_M68K)
+$(LIBOBJ_MIPS): $(DEP_MIPS)
+$(LIBOBJ_PPC): $(DEP_PPC)
+$(LIBOBJ_SPARC): $(DEP_SPARC)
+$(LIBOBJ_SYSZ): $(DEP_SYSZ)
+$(LIBOBJ_X86): $(DEP_X86)
+$(LIBOBJ_XCORE): $(DEP_XCORE)
+$(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X)
+$(LIBOBJ_M680X): $(DEP_M680X)
+$(LIBOBJ_EVM): $(DEP_EVM)
+$(LIBOBJ_MOS65XX): $(DEP_MOS65XX)
+
+ifeq ($(CAPSTONE_STATIC),yes)
+$(ARCHIVE): $(LIBOBJ)
+	@rm -f $(ARCHIVE)
+ifeq ($(V),0)
+	$(call log,AR,$(@:$(BLDIR)/%=%))
+	@$(create-archive)
+else
+	$(create-archive)
+endif
+endif
+
+$(PKGCFGF):
+ifeq ($(V),0)
+	$(call log,GEN,$(@:$(BLDIR)/%=%))
+	@$(generate-pkgcfg)
+else
+	$(generate-pkgcfg)
+endif
+
+install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
+	mkdir -p $(LIBDIR)
+	$(call install-library,$(LIBDIR))
+ifeq ($(CAPSTONE_STATIC),yes)
+	$(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
+endif
+	mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
+	$(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
+	mkdir -p $(PKGCFGDIR)
+	$(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	mkdir -p $(BINDIR)
+	$(INSTALL_LIB) cstool/cstool $(BINDIR)
+endif
+
+uninstall:
+	rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
+	rm -f $(LIBDIR)/lib$(LIBNAME).*
+	rm -f $(PKGCFGDIR)/$(LIBNAME).pc
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	rm -f $(BINDIR)/cstool
+endif
+
+clean:
+	rm -f $(LIBOBJ)
+	rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
+	rm -f $(PKGCFGF)
+	[ "${ANDROID}" = "1" ] && rm -rf android-ndk-* || true
+
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	$(MAKE) -C cstool clean
+	$(MAKE) -C tests clean
+	$(MAKE) -C suite/fuzz clean
+	rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
+endif
+
+ifdef BUILDDIR
+	rm -rf $(BUILDDIR)
+endif
+
+ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
+	$(MAKE) -C bindings/python clean
+	$(MAKE) -C bindings/java clean
+	$(MAKE) -C bindings/ocaml clean
+endif
+
+
+TAG ?= HEAD
+ifeq ($(TAG), HEAD)
+DIST_VERSION = latest
+else
+DIST_VERSION = $(TAG)
+endif
+
+dist:
+	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
+	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
+
+
+TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc
+TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_mos65xx
+TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
+TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
+TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
+TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static
+TESTS += test_mos65xx.static
+check: $(TESTS) fuzztest fuzzallcorp
+test_%:
+	./tests/$@ > /dev/null && echo OK || echo FAILED
+
+FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs')
+
+fuzztest:
+	./suite/fuzz/fuzz_disasm $(FUZZ_INPUTS)
+
+fuzzallcorp:
+ifneq ($(wildcard suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest),)
+	./suite/fuzz/fuzz_bindisasm suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest/
+else
+	@echo "Skipping tests on whole corpus"
+endif
+
+$(OBJDIR)/%.o: %.c
+	@mkdir -p $(@D)
+ifeq ($(V),0)
+	$(call log,CC,$(@:$(OBJDIR)/%=%))
+	@$(compile)
+else
+	$(compile)
+endif
+
+
+ifeq ($(CAPSTONE_SHARED),yes)
+define install-library
+	$(INSTALL_LIB) $(LIBRARY) $1
+	$(if $(VERSION_EXT),
+		cd $1 && \
+		rm -f lib$(LIBNAME).$(EXT) && \
+		ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
+endef
+else
+define install-library
+endef
+endif
+
+
+define create-archive
+	$(AR) q $(ARCHIVE) $(LIBOBJ)
+	$(RANLIB) $(ARCHIVE)
+endef
+
+
+define create-library
+	$(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
+endef
+
+
+define generate-pkgcfg
+	mkdir -p $(BLDIR)
+	echo 'Name: capstone' > $(PKGCFGF)
+	echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
+	echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
+	echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
+	echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
+	echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
+	echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
+	echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
+endef

MathExtras.h

@@ -0,0 +1,442 @@
+//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains some functions that are useful for math stuff.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
+#define CS_LLVM_SUPPORT_MATHEXTRAS_H
+
+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+#include "windowsce/intrin.h"
+#elif defined(_MSC_VER)
+#include <intrin.h>
+#endif
+
+#ifndef __cplusplus
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#define inline /* inline */
+#endif
+#endif
+
+// NOTE: The following support functions use the _32/_64 extensions instead of
+// type overloading so that signed and unsigned integers can be used without
+// ambiguity.
+
+/// Hi_32 - This function returns the high 32 bits of a 64 bit value.
+static inline uint32_t Hi_32(uint64_t Value) {
+	return (uint32_t)(Value >> 32);
+}
+
+/// Lo_32 - This function returns the low 32 bits of a 64 bit value.
+static inline uint32_t Lo_32(uint64_t Value) {
+	return (uint32_t)(Value);
+}
+
+/// isUIntN - Checks if an unsigned integer fits into the given (dynamic)
+/// bit width.
+static inline bool isUIntN(unsigned N, uint64_t x) {
+	return x == (x & (~0ULL >> (64 - N)));
+}
+
+/// isIntN - Checks if an signed integer fits into the given (dynamic)
+/// bit width.
+//static inline bool isIntN(unsigned N, int64_t x) {
+//  return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
+//}
+
+/// isMask_32 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (32 bit
+/// version).   Ex. isMask_32(0x0000FFFFU) == true.
+static inline bool isMask_32(uint32_t Value) {
+	return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isMask_64 - This function returns true if the argument is a sequence of ones
+/// starting at the least significant bit with the remainder zero (64 bit
+/// version).
+static inline bool isMask_64(uint64_t Value) {
+	return Value && ((Value + 1) & Value) == 0;
+}
+
+/// isShiftedMask_32 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (32 bit version.)
+/// Ex. isShiftedMask_32(0x0000FF00U) == true.
+static inline bool isShiftedMask_32(uint32_t Value) {
+	return isMask_32((Value - 1) | Value);
+}
+
+/// isShiftedMask_64 - This function returns true if the argument contains a
+/// sequence of ones with the remainder zero (64 bit version.)
+static inline bool isShiftedMask_64(uint64_t Value) {
+	return isMask_64((Value - 1) | Value);
+}
+
+/// isPowerOf2_32 - This function returns true if the argument is a power of
+/// two > 0. Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
+static inline bool isPowerOf2_32(uint32_t Value) {
+	return Value && !(Value & (Value - 1));
+}
+
+/// CountLeadingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the most significant bit to the first one
+/// bit.  Ex. CountLeadingZeros_32(0x00F000FF) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountLeadingZeros_32(uint32_t Value) {
+	unsigned Count; // result
+#if __GNUC__ >= 4
+	// PowerPC is defined for __builtin_clz(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+	if (!Value) return 32;
+#endif
+	Count = __builtin_clz(Value);
+#else
+	unsigned Shift;
+	if (!Value) return 32;
+	Count = 0;
+	// bisection method for count leading zeros
+	for (Shift = 32 >> 1; Shift; Shift >>= 1) {
+		uint32_t Tmp = Value >> Shift;
+		if (Tmp) {
+			Value = Tmp;
+		} else {
+			Count |= Shift;
+		}
+	}
+#endif
+	return Count;
+}
+
+/// CountLeadingOnes_32 - this function performs the operation of
+/// counting the number of ones from the most significant bit to the first zero
+/// bit.  Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountLeadingOnes_32(uint32_t Value) {
+	return CountLeadingZeros_32(~Value);
+}
+
+/// CountLeadingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the most significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountLeadingZeros_64(uint64_t Value) {
+	unsigned Count; // result
+#if __GNUC__ >= 4
+	// PowerPC is defined for __builtin_clzll(0)
+#if !defined(__ppc__) && !defined(__ppc64__)
+	if (!Value) return 64;
+#endif
+	Count = __builtin_clzll(Value);
+#else
+#ifndef _MSC_VER
+	unsigned Shift;
+	if (sizeof(long) == sizeof(int64_t))
+	{
+		if (!Value) return 64;
+		Count = 0;
+		// bisection method for count leading zeros
+		for (Shift = 64 >> 1; Shift; Shift >>= 1) {
+			uint64_t Tmp = Value >> Shift;
+			if (Tmp) {
+				Value = Tmp;
+			} else {
+				Count |= Shift;
+			}
+		}
+	}
+	else
+#endif
+	{
+		// get hi portion
+		uint32_t Hi = Hi_32(Value);
+
+		// if some bits in hi portion
+		if (Hi) {
+			// leading zeros in hi portion plus all bits in lo portion
+			Count = CountLeadingZeros_32(Hi);
+		} else {
+			// get lo portion
+			uint32_t Lo = Lo_32(Value);
+			// same as 32 bit value
+			Count = CountLeadingZeros_32(Lo)+32;
+		}
+	}
+#endif
+	return Count;
+}
+
+/// CountLeadingOnes_64 - This function performs the operation
+/// of counting the number of ones from the most significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountLeadingOnes_64(uint64_t Value) {
+	return CountLeadingZeros_64(~Value);
+}
+
+/// CountTrailingZeros_32 - this function performs the platform optimal form of
+/// counting the number of zeros from the least significant bit to the first one
+/// bit.  Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
+/// Returns 32 if the word is zero.
+static inline unsigned CountTrailingZeros_32(uint32_t Value) {
+#if __GNUC__ >= 4
+	return Value ? __builtin_ctz(Value) : 32;
+#else
+	static const unsigned Mod37BitPosition[] = {
+		32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
+		4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
+		5, 20, 8, 19, 18
+	};
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return Mod37BitPosition[(-Value & Value) % 37];
+	return Mod37BitPosition[((1 + ~Value) & Value) % 37];
+#endif
+}
+
+/// CountTrailingOnes_32 - this function performs the operation of
+/// counting the number of ones from the least significant bit to the first zero
+/// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
+/// Returns 32 if the word is all ones.
+static inline unsigned CountTrailingOnes_32(uint32_t Value) {
+	return CountTrailingZeros_32(~Value);
+}
+
+/// CountTrailingZeros_64 - This function performs the platform optimal form
+/// of counting the number of zeros from the least significant bit to the first
+/// one bit (64 bit edition.)
+/// Returns 64 if the word is zero.
+static inline unsigned CountTrailingZeros_64(uint64_t Value) {
+#if __GNUC__ >= 4
+	return Value ? __builtin_ctzll(Value) : 64;
+#else
+	static const unsigned Mod67Position[] = {
+		64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
+		4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
+		47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
+		29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
+		7, 48, 35, 6, 34, 33, 0
+	};
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return Mod67Position[(-Value & Value) % 67];
+	return Mod67Position[((1 + ~Value) & Value) % 67];
+#endif
+}
+
+/// CountTrailingOnes_64 - This function performs the operation
+/// of counting the number of ones from the least significant bit to the first
+/// zero bit (64 bit edition.)
+/// Returns 64 if the word is all ones.
+static inline unsigned CountTrailingOnes_64(uint64_t Value) {
+	return CountTrailingZeros_64(~Value);
+}
+
+/// CountPopulation_32 - this function counts the number of set bits in a value.
+/// Ex. CountPopulation(0xF000F000) = 8
+/// Returns 0 if the word is zero.
+static inline unsigned CountPopulation_32(uint32_t Value) {
+#if __GNUC__ >= 4
+	return __builtin_popcount(Value);
+#else
+	uint32_t v = Value - ((Value >> 1) & 0x55555555);
+	v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
+	return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
+#endif
+}
+
+/// CountPopulation_64 - this function counts the number of set bits in a value,
+/// (64 bit edition.)
+static inline unsigned CountPopulation_64(uint64_t Value) {
+#if __GNUC__ >= 4
+	return __builtin_popcountll(Value);
+#else
+	uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
+	v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
+	v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
+	return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
+#endif
+}
+
+/// Log2_32 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (32 bit edition.)
+/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
+static inline unsigned Log2_32(uint32_t Value) {
+	return 31 - CountLeadingZeros_32(Value);
+}
+
+/// Log2_64 - This function returns the floor log base 2 of the specified value,
+/// -1 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64(uint64_t Value) {
+	return 63 - CountLeadingZeros_64(Value);
+}
+
+/// Log2_32_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 32 if the value is zero. (32 bit edition).
+/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
+static inline unsigned Log2_32_Ceil(uint32_t Value) {
+	return 32-CountLeadingZeros_32(Value-1);
+}
+
+/// Log2_64_Ceil - This function returns the ceil log base 2 of the specified
+/// value, 64 if the value is zero. (64 bit edition.)
+static inline unsigned Log2_64_Ceil(uint64_t Value) {
+	return 64-CountLeadingZeros_64(Value-1);
+}
+
+/// GreatestCommonDivisor64 - Return the greatest common divisor of the two
+/// values using Euclid's algorithm.
+static inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
+	while (B) {
+		uint64_t T = B;
+		B = A % B;
+		A = T;
+	}
+	return A;
+}
+
+/// BitsToDouble - This function takes a 64-bit integer and returns the bit
+/// equivalent double.
+static inline double BitsToDouble(uint64_t Bits) {
+	union {
+		uint64_t L;
+		double D;
+	} T;
+	T.L = Bits;
+	return T.D;
+}
+
+/// BitsToFloat - This function takes a 32-bit integer and returns the bit
+/// equivalent float.
+static inline float BitsToFloat(uint32_t Bits) {
+	union {
+		uint32_t I;
+		float F;
+	} T;
+	T.I = Bits;
+	return T.F;
+}
+
+/// DoubleToBits - This function takes a double and returns the bit
+/// equivalent 64-bit integer.  Note that copying doubles around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint64_t DoubleToBits(double Double) {
+	union {
+		uint64_t L;
+		double D;
+	} T;
+	T.D = Double;
+	return T.L;
+}
+
+/// FloatToBits - This function takes a float and returns the bit
+/// equivalent 32-bit integer.  Note that copying floats around
+/// changes the bits of NaNs on some hosts, notably x86, so this
+/// routine cannot be used if these bits are needed.
+static inline uint32_t FloatToBits(float Float) {
+	union {
+		uint32_t I;
+		float F;
+	} T;
+	T.F = Float;
+	return T.I;
+}
+
+/// MinAlign - A and B are either alignments or offsets.  Return the minimum
+/// alignment that may be assumed after adding the two together.
+static inline uint64_t MinAlign(uint64_t A, uint64_t B) {
+	// The largest power of 2 that divides both A and B.
+	//
+	// Replace "-Value" by "1+~Value" in the following commented code to avoid 
+	// MSVC warning C4146
+	//    return (A | B) & -(A | B);
+	return (A | B) & (1 + ~(A | B));
+}
+
+/// NextPowerOf2 - Returns the next power of two (in 64-bits)
+/// that is strictly greater than A.  Returns zero on overflow.
+static inline uint64_t NextPowerOf2(uint64_t A) {
+	A |= (A >> 1);
+	A |= (A >> 2);
+	A |= (A >> 4);
+	A |= (A >> 8);
+	A |= (A >> 16);
+	A |= (A >> 32);
+	return A + 1;
+}
+
+/// Returns the next integer (mod 2**64) that is greater than or equal to
+/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
+///
+/// Examples:
+/// \code
+///   RoundUpToAlignment(5, 8) = 8
+///   RoundUpToAlignment(17, 8) = 24
+///   RoundUpToAlignment(~0LL, 8) = 0
+/// \endcode
+static inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
+	return ((Value + Align - 1) / Align) * Align;
+}
+
+/// Returns the offset to the next integer (mod 2**64) that is greater than
+/// or equal to \p Value and is a multiple of \p Align. \p Align must be
+/// non-zero.
+static inline uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align) {
+	return RoundUpToAlignment(Value, Align) - Value;
+}
+
+/// abs64 - absolute value of a 64-bit int.  Not all environments support
+/// "abs" on whatever their name for the 64-bit int type is.  The absolute
+/// value of the largest negative number is undefined, as with "abs".
+static inline int64_t abs64(int64_t x) {
+	return (x < 0) ? -x : x;
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 32-bit int.
+/// Requires 0 < B <= 32.
+static inline int32_t SignExtend32(uint32_t X, unsigned B) {
+	return (int32_t)(X << (32 - B)) >> (32 - B);
+}
+
+/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
+/// Requires 0 < B <= 64.
+static inline int64_t SignExtend64(uint64_t X, unsigned B) {
+	return (int64_t)(X << (64 - B)) >> (64 - B);
+}
+
+/// \brief Count number of 0's from the most significant bit to the least
+///   stopping at the first 1.
+///
+/// Only unsigned integral types are allowed.
+///
+/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
+///   valid arguments.
+static inline unsigned int countLeadingZeros(int x)
+{
+	int i;
+	const unsigned bits = sizeof(x) * 8;
+	unsigned count = bits;
+
+	if (x < 0) {
+		return 0;
+	}
+	for (i = bits; --i; ) {
+		if (x == 0) break;
+		count--;
+		x >>= 1;
+	}
+
+	return count;
+}
+
+#endif

README.md

@@ -0,0 +1,67 @@
+Capstone Engine
+===============
+
+[![Build Status](https://travis-ci.org/aquynh/capstone.svg?branch=master)](https://travis-ci.org/aquynh/capstone)
+[![Build status](https://ci.appveyor.com/api/projects/status/a4wvbn89wu3pinas/branch/master?svg=true)](https://ci.appveyor.com/project/aquynh/capstone/branch/master)
+[![pypi package](https://badge.fury.io/py/capstone.svg)](https://pypi.python.org/pypi/capstone)
+[![pypi downloads](https://pepy.tech/badge/capstone)](https://pepy.tech/project/capstone)
+
+Capstone is a disassembly framework with the target of becoming the ultimate
+disasm engine for binary analysis and reversing in the security community.
+
+Created by Nguyen Anh Quynh, then developed and maintained by a small community,
+Capstone offers some unparalleled features:
+
+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Ethereum VM, M68K,
+  Mips, MOS65XX, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64).
+
+- Having clean/simple/lightweight/intuitive architecture-neutral API.
+
+- Provide details on disassembled instruction (called “decomposer” by others).
+
+- Provide semantics of the disassembled instruction, such as list of implicit
+  registers read & written.
+
+- Implemented in pure C language, with lightweight bindings for D, Clojure, F#,
+  Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python,
+  Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala
+  (ready either in main code, or provided externally by the community).
+
+- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
+  Linux, \*BSD, Solaris, etc.
+
+- Thread-safe by design.
+
+- Special support for embedding into firmware or OS kernel.
+
+- High performance & suitable for malware analysis (capable of handling various
+  X86 malware tricks).
+
+- Distributed under the open source BSD license.
+
+Further information is available at http://www.capstone-engine.org
+
+
+Compile
+-------
+
+See COMPILE.TXT file for how to compile and install Capstone.
+
+
+Documentation
+-------------
+
+See docs/README for how to customize & program your own tools with Capstone.
+
+
+Hack
+----
+
+See HACK.TXT file for the structure of the source code.
+
+
+License
+-------
+
+This project is released under the BSD license. If you redistribute the binary
+or source code of Capstone, please attach file LICENSE.TXT with your products.

SPONSORS.TXT

@@ -0,0 +1,20 @@
+* Version 4.0.1 - January 10th, 2019
+
+Release 4.0.1 was sponsored by the following companies (in no particular order).
+
+- NowSecure: https://www.nowsecure.com
+- Verichains: https://verichains.io
+- Vsec: https://vsec.com.vn
+
+-----------------------------------
+* Version 4.0 - December 18th, 2018
+
+Capstone 4.0 version marks 5 years of the project!
+This release was sponsored by the following companies (in no particular order).
+
+- Thinkst Canary: https://canary.tools
+- NowSecure: https://www.nowsecure.com
+- ECQ: https://e-cq.net
+- Senrio: https://senr.io
+- GracefulBits: https://gracefulbits.com
+- Catena Cyber: https://catenacyber.fr

SStream.c

@@ -0,0 +1,188 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include <stdarg.h>
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <Availability.h>
+#include <libkern/libkern.h>
+#include <i386/limits.h>
+#else
+#include <stdio.h>
+#include <limits.h>
+#endif
+#include <string.h>
+
+#include <capstone/platform.h>
+
+#include "SStream.h"
+#include "cs_priv.h"
+#include "utils.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable: 4996) // disable MSVC's warning on strcpy()
+#endif
+
+void SStream_Init(SStream *ss)
+{
+	ss->index = 0;
+	ss->buffer[0] = '\0';
+}
+
+void SStream_concat0(SStream *ss, const char *s)
+{
+#ifndef CAPSTONE_DIET
+	unsigned int len = (unsigned int) strlen(s);
+
+	memcpy(ss->buffer + ss->index, s, len);
+	ss->index += len;
+	ss->buffer[ss->index] = '\0';
+#endif
+}
+
+void SStream_concat(SStream *ss, const char *fmt, ...)
+{
+#ifndef CAPSTONE_DIET
+	va_list ap;
+	int ret;
+
+	va_start(ap, fmt);
+	ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
+	va_end(ap);
+	ss->index += ret;
+#endif
+}
+
+// print number with prefix #
+void printInt64Bang(SStream *O, int64_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "#0x%"PRIx64, val);
+		else
+			SStream_concat(O, "#%"PRIu64, val);
+	} else {
+		if (val <- HEX_THRESHOLD) {
+			if (val == LONG_MIN)
+				SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val);
+			else
+				SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val);
+		}
+		else
+			SStream_concat(O, "#-%"PRIu64, -val);
+	}
+}
+
+void printUInt64Bang(SStream *O, uint64_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "#0x%"PRIx64, val);
+	else
+		SStream_concat(O, "#%"PRIu64, val);
+}
+
+// print number
+void printInt64(SStream *O, int64_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "0x%"PRIx64, val);
+		else
+			SStream_concat(O, "%"PRIu64, val);
+	} else {
+		if (val <- HEX_THRESHOLD) {
+			if (val == LONG_MIN)
+				SStream_concat(O, "-0x%"PRIx64, (uint64_t)val);
+			else
+				SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val);
+		}
+		else
+			SStream_concat(O, "-%"PRIu64, -val);
+	}
+}
+
+// print number in decimal mode
+void printInt32BangDec(SStream *O, int32_t val)
+{
+	if (val >= 0)
+		SStream_concat(O, "#%u", val);
+	else
+		if (val == INT_MIN)
+			SStream_concat(O, "#-%u", val);
+		else
+			SStream_concat(O, "#-%u", (uint32_t)-val);
+}
+
+void printInt32Bang(SStream *O, int32_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "#0x%x", val);
+		else
+			SStream_concat(O, "#%u", val);
+	} else {
+		if (val <- HEX_THRESHOLD) {
+			if (val == INT_MIN)
+				SStream_concat(O, "#-0x%x", (uint32_t)val);
+			else
+				SStream_concat(O, "#-0x%x", (uint32_t)-val);
+		}
+		else
+			SStream_concat(O, "#-%u", -val);
+	}
+}
+
+void printInt32(SStream *O, int32_t val)
+{
+	if (val >= 0) {
+		if (val > HEX_THRESHOLD)
+			SStream_concat(O, "0x%x", val);
+		else
+			SStream_concat(O, "%u", val);
+	} else {
+		if (val <- HEX_THRESHOLD) {
+			if (val == INT_MIN)
+				SStream_concat(O, "-0x%x", (uint32_t)val);
+			else
+				SStream_concat(O, "-0x%x", (uint32_t)-val);
+			}
+		else
+			SStream_concat(O, "-%u", -val);
+	}
+}
+
+void printUInt32Bang(SStream *O, uint32_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "#0x%x", val);
+	else
+		SStream_concat(O, "#%u", val);
+}
+
+void printUInt32(SStream *O, uint32_t val)
+{
+	if (val > HEX_THRESHOLD)
+		SStream_concat(O, "0x%x", val);
+	else
+		SStream_concat(O, "%u", val);
+}
+
+/*
+   int main()
+   {
+   SStream ss;
+   int64_t i;
+
+   SStream_Init(&ss);
+
+   SStream_concat(&ss, "hello ");
+   SStream_concat(&ss, "%d - 0x%x", 200, 16);
+
+   i = 123;
+   SStream_concat(&ss, " + %ld", i);
+   SStream_concat(&ss, "%s", "haaaaa");
+
+   printf("%s\n", ss.buffer);
+
+   return 0;
+   }
+ */

SStream.h

@@ -0,0 +1,37 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_SSTREAM_H_
+#define CS_SSTREAM_H_
+
+#include "include/capstone/platform.h"
+
+typedef struct SStream {
+	char buffer[512];
+	int index;
+} SStream;
+
+void SStream_Init(SStream *ss);
+
+void SStream_concat(SStream *ss, const char *fmt, ...);
+
+void SStream_concat0(SStream *ss, const char *s);
+
+void printInt64Bang(SStream *O, int64_t val);
+
+void printUInt64Bang(SStream *O, uint64_t val);
+
+void printInt64(SStream *O, int64_t val);
+
+void printInt32Bang(SStream *O, int32_t val);
+
+void printInt32(SStream *O, int32_t val);
+
+void printUInt32Bang(SStream *O, uint32_t val);
+
+void printUInt32(SStream *O, uint32_t val);
+
+// print number in decimal mode
+void printInt32BangDec(SStream *O, int32_t val);
+
+#endif

TODO

@@ -0,0 +1,16 @@
+Issues to be solved in next versions
+
+
+[Core]
+
+- X86 can already handle all the malware tricks we are aware of. If you find
+  any such instruction sequence that Capstone disassembles wrongly or fails
+  completely, please report. Fixing this issue is always the top priority of
+  our project.
+
+- More optimization for better performance.
+
+
+[Bindings]
+
+- OCaml binding is working, but still needs to support the core API better.

arch/AArch64/AArch64AddressingModes.h

@@ -0,0 +1,225 @@
+//===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the AArch64 addressing mode implementation stuff.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CS_AARCH64_ADDRESSINGMODES_H
+#define CS_AARCH64_ADDRESSINGMODES_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#include "../../MathExtras.h"
+
+/// AArch64_AM - AArch64 Addressing Mode Stuff
+
+//===----------------------------------------------------------------------===//
+// Shifts
+//
+
+typedef enum AArch64_AM_ShiftExtendType {
+	AArch64_AM_InvalidShiftExtend = -1,
+	AArch64_AM_LSL = 0,
+	AArch64_AM_LSR,
+	AArch64_AM_ASR,
+	AArch64_AM_ROR,
+	AArch64_AM_MSL,
+
+	AArch64_AM_UXTB,
+	AArch64_AM_UXTH,
+	AArch64_AM_UXTW,
+	AArch64_AM_UXTX,
+
+	AArch64_AM_SXTB,
+	AArch64_AM_SXTH,
+	AArch64_AM_SXTW,
+	AArch64_AM_SXTX,
+} AArch64_AM_ShiftExtendType;
+
+/// getShiftName - Get the string encoding for the shift type.
+static inline const char *AArch64_AM_getShiftExtendName(AArch64_AM_ShiftExtendType ST)
+{
+	switch (ST) {
+		default: return NULL; // never reach
+		case AArch64_AM_LSL: return "lsl";
+		case AArch64_AM_LSR: return "lsr";
+		case AArch64_AM_ASR: return "asr";
+		case AArch64_AM_ROR: return "ror";
+		case AArch64_AM_MSL: return "msl";
+		case AArch64_AM_UXTB: return "uxtb";
+		case AArch64_AM_UXTH: return "uxth";
+		case AArch64_AM_UXTW: return "uxtw";
+		case AArch64_AM_UXTX: return "uxtx";
+		case AArch64_AM_SXTB: return "sxtb";
+		case AArch64_AM_SXTH: return "sxth";
+		case AArch64_AM_SXTW: return "sxtw";
+		case AArch64_AM_SXTX: return "sxtx";
+	}
+}
+
+/// getShiftType - Extract the shift type.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm)
+{
+	switch ((Imm >> 6) & 0x7) {
+		default: return AArch64_AM_InvalidShiftExtend;
+		case 0: return AArch64_AM_LSL;
+		case 1: return AArch64_AM_LSR;
+		case 2: return AArch64_AM_ASR;
+		case 3: return AArch64_AM_ROR;
+		case 4: return AArch64_AM_MSL;
+	}
+}
+
+/// getShiftValue - Extract the shift value.
+static inline unsigned AArch64_AM_getShiftValue(unsigned Imm)
+{
+	return Imm & 0x3f;
+}
+
+//===----------------------------------------------------------------------===//
+// Extends
+//
+
+/// getArithShiftValue - get the arithmetic shift value.
+static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm)
+{
+	return Imm & 0x7;
+}
+
+/// getExtendType - Extract the extend type for operands of arithmetic ops.
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm)
+{
+	// assert((Imm & 0x7) == Imm && "invalid immediate!");
+	switch (Imm) {
+		default: // llvm_unreachable("Compiler bug!");
+		case 0: return AArch64_AM_UXTB;
+		case 1: return AArch64_AM_UXTH;
+		case 2: return AArch64_AM_UXTW;
+		case 3: return AArch64_AM_UXTX;
+		case 4: return AArch64_AM_SXTB;
+		case 5: return AArch64_AM_SXTH;
+		case 6: return AArch64_AM_SXTW;
+		case 7: return AArch64_AM_SXTX;
+	}
+}
+
+static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm)
+{
+	return AArch64_AM_getExtendType((Imm >> 3) & 0x7);
+}
+
+static inline uint64_t ror(uint64_t elt, unsigned size)
+{
+	return ((elt & 1) << (size-1)) | (elt >> 1);
+}
+
+/// decodeLogicalImmediate - Decode a logical immediate value in the form
+/// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
+/// integer value it represents with regSize bits.
+static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned regSize)
+{
+	// Extract the N, imms, and immr fields.
+	unsigned N = (val >> 12) & 1;
+	unsigned immr = (val >> 6) & 0x3f;
+	unsigned imms = val & 0x3f;
+	unsigned i;
+
+	// assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
+	int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	// assert(len >= 0 && "undefined logical immediate encoding");
+	unsigned size = (1 << len);
+	unsigned R = immr & (size - 1);
+	unsigned S = imms & (size - 1);
+	// assert(S != size - 1 && "undefined logical immediate encoding");
+	uint64_t pattern = (1ULL << (S + 1)) - 1;
+	for (i = 0; i < R; ++i)
+		pattern = ror(pattern, size);
+
+	// Replicate the pattern to fill the regSize.
+	while (size != regSize) {
+		pattern |= (pattern << size);
+		size *= 2;
+	}
+
+	return pattern;
+}
+
+/// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
+/// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
+/// is a valid encoding for an integer value with regSize bits.
+static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
+{
+	unsigned size;
+	unsigned S;
+	int len;
+	// Extract the N and imms fields needed for checking.
+	unsigned N = (val >> 12) & 1;
+	unsigned imms = val & 0x3f;
+
+	if (regSize == 32 && N != 0) // undefined logical immediate encoding
+		return false;
+	len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
+	if (len < 0) // undefined logical immediate encoding
+		return false;
+	size = (1 << len);
+	S = imms & (size - 1);
+	if (S == size - 1) // undefined logical immediate encoding
+		return false;
+
+	return true;
+}
+
+//===----------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
+{
+	// We expect an 8-bit binary encoding of a floating-point number here.
+	union {
+		uint32_t I;
+		float F;
+	} FPUnion;
+
+	uint8_t Sign = (Imm >> 7) & 0x1;
+	uint8_t Exp = (Imm >> 4) & 0x7;
+	uint8_t Mantissa = Imm & 0xf;
+
+	//   8-bit FP    iEEEE Float Encoding
+	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+	//
+	// where B = NOT(b);
+
+	FPUnion.I = 0;
+	FPUnion.I |= ((uint32_t)Sign) << 31;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	FPUnion.I |= (Exp & 0x3) << 23;
+	FPUnion.I |= Mantissa << 19;
+
+	return FPUnion.F;
+}
+
+//===--------------------------------------------------------------------===//
+// AdvSIMD Modified Immediates
+//===--------------------------------------------------------------------===//
+
+static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm)
+{
+	static const uint32_t lookup[16] = {
+		0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, 
+		0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, 
+		0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, 
+		0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
+        };
+	return lookup[Imm & 0x0f] | ((uint64_t)lookup[Imm >> 4] << 32);
+}
+
+#endif

arch/AArch64/AArch64BaseInfo.c

@@ -0,0 +1,987 @@
+//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for AArch64.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_ARM64
+
+#if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
+#pragma warning(disable:4996)			// disable MSVC's warning on strcpy()
+#pragma warning(disable:28719)		// disable MSVC's warning on strcpy()
+#endif
+
+#include "../../utils.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "AArch64BaseInfo.h"
+
+const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid)
+{
+	unsigned i;
+	for (i = 0; i < N->NumPairs; ++i) {
+		if (N->Pairs[i].Value == Value) {
+			*Valid = true;
+			return N->Pairs[i].Name;
+		}
+	}
+
+	*Valid = false;
+	return 0;
+}
+
+// compare s1 with lower(s2)
+// return true if s1 == lower(f2), and false otherwise
+static bool compare_lower_str(const char *s1, const char *s2)
+{
+	bool res;
+	char *lower = cs_strdup(s2), *c;
+	for (c = lower; *c; c++)
+		*c = (char)tolower((int) *c);
+
+	res = (strcmp(s1, lower) == 0);
+	cs_mem_free(lower);
+
+	return res;
+}
+
+uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid)
+{
+	unsigned i;
+	for (i = 0; i < N->NumPairs; ++i) {
+		if (compare_lower_str(N->Pairs[i].Name, Name)) {
+			*Valid = true;
+			return N->Pairs[i].Value;
+		}
+	}
+
+	*Valid = false;
+	return (uint32_t)-1;
+}
+
+bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value)
+{
+	return Value < N->TooBigImm;
+}
+
+// return a string representing the number X
+// NOTE: caller must free() the result itself to avoid memory leak
+static char *utostr(uint64_t X, bool isNeg)
+{
+	char Buffer[22];
+	char *BufPtr = Buffer+21;
+	char *result;
+
+	Buffer[21] = '\0';
+	if (X == 0) *--BufPtr = '0';  // Handle special case...
+
+	while (X) {
+		*--BufPtr = X % 10 + '0';
+		X /= 10;
+	}
+
+	if (isNeg) *--BufPtr = '-';   // Add negative sign...
+
+	result = cs_strdup(BufPtr);
+	return result;
+}
+
+static const A64NamedImmMapper_Mapping SysRegPairs[] = {
+	{"pan", A64SysReg_PAN},
+	{"uao", A64SysReg_UAO},
+	{"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
+	{"osdtrtx_el1",  A64SysReg_OSDTRTX_EL1},
+	{"teecr32_el1", A64SysReg_TEECR32_EL1},
+	{"mdccint_el1", A64SysReg_MDCCINT_EL1},
+	{"mdscr_el1", A64SysReg_MDSCR_EL1},
+	{"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
+	{"oseccr_el1", A64SysReg_OSECCR_EL1},
+	{"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
+	{"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
+	{"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
+	{"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
+	{"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
+	{"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
+	{"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
+	{"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
+	{"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
+	{"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
+	{"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
+	{"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
+	{"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
+	{"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
+	{"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
+	{"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
+	{"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
+	{"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
+	{"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
+	{"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
+	{"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
+	{"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
+	{"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
+	{"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
+	{"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
+	{"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
+	{"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
+	{"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
+	{"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
+	{"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
+	{"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
+	{"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
+	{"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
+	{"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
+	{"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
+	{"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
+	{"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
+	{"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
+	{"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
+	{"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
+	{"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
+	{"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
+	{"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
+	{"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
+	{"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
+	{"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
+	{"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
+	{"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
+	{"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
+	{"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
+	{"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
+	{"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
+	{"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
+	{"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
+	{"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
+	{"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
+	{"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
+	{"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
+	{"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
+	{"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
+	{"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
+	{"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
+	{"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
+	{"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
+	{"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
+	{"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
+	{"osdlr_el1", A64SysReg_OSDLR_EL1},
+	{"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
+	{"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
+	{"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
+	{"csselr_el1", A64SysReg_CSSELR_EL1},
+	{"vpidr_el2", A64SysReg_VPIDR_EL2},
+	{"vmpidr_el2", A64SysReg_VMPIDR_EL2},
+	{"sctlr_el1", A64SysReg_SCTLR_EL1},
+	{"sctlr_el12", A64SysReg_SCTLR_EL12},
+	{"sctlr_el2", A64SysReg_SCTLR_EL2},
+	{"sctlr_el3", A64SysReg_SCTLR_EL3},
+	{"actlr_el1", A64SysReg_ACTLR_EL1},
+	{"actlr_el2", A64SysReg_ACTLR_EL2},
+	{"actlr_el3", A64SysReg_ACTLR_EL3},
+	{"cpacr_el1", A64SysReg_CPACR_EL1},
+	{"cpacr_el12", A64SysReg_CPACR_EL12},
+	{"hcr_el2", A64SysReg_HCR_EL2},
+	{"scr_el3", A64SysReg_SCR_EL3},
+	{"mdcr_el2", A64SysReg_MDCR_EL2},
+	{"sder32_el3", A64SysReg_SDER32_EL3},
+	{"cptr_el2", A64SysReg_CPTR_EL2},
+	{"cptr_el3", A64SysReg_CPTR_EL3},
+	{"hstr_el2", A64SysReg_HSTR_EL2},
+	{"hacr_el2", A64SysReg_HACR_EL2},
+	{"mdcr_el3", A64SysReg_MDCR_EL3},
+	{"ttbr0_el1", A64SysReg_TTBR0_EL1},
+	{"ttbr0_el12", A64SysReg_TTBR0_EL12},
+	{"ttbr0_el2", A64SysReg_TTBR0_EL2},
+	{"ttbr0_el3", A64SysReg_TTBR0_EL3},
+	{"ttbr1_el1", A64SysReg_TTBR1_EL1},
+	{"ttbr1_el12", A64SysReg_TTBR1_EL12},
+	{"ttbr1_el2", A64SysReg_TTBR1_EL2},
+	{"tcr_el1", A64SysReg_TCR_EL1},
+	{"tcr_el12", A64SysReg_TCR_EL12},
+	{"tcr_el2", A64SysReg_TCR_EL2},
+	{"tcr_el3", A64SysReg_TCR_EL3},
+	{"vttbr_el2", A64SysReg_VTTBR_EL2},
+	{"vtcr_el2", A64SysReg_VTCR_EL2},
+	{"dacr32_el2", A64SysReg_DACR32_EL2},
+	{"spsr_el1", A64SysReg_SPSR_EL1},
+	{"spsr_el12", A64SysReg_SPSR_EL12},
+	{"spsr_el2", A64SysReg_SPSR_EL2},
+	{"spsr_el3", A64SysReg_SPSR_EL3},
+	{"elr_el1", A64SysReg_ELR_EL1},
+	{"elr_el12", A64SysReg_ELR_EL12},
+	{"elr_el2", A64SysReg_ELR_EL2},
+	{"elr_el3", A64SysReg_ELR_EL3},
+	{"sp_el0", A64SysReg_SP_EL0},
+	{"sp_el1", A64SysReg_SP_EL1},
+	{"sp_el2", A64SysReg_SP_EL2},
+	{"spsel", A64SysReg_SPSel},
+	{"nzcv", A64SysReg_NZCV},
+	{"daif", A64SysReg_DAIF},
+	{"currentel", A64SysReg_CurrentEL},
+	{"spsr_irq", A64SysReg_SPSR_irq},
+	{"spsr_abt", A64SysReg_SPSR_abt},
+	{"spsr_und", A64SysReg_SPSR_und},
+	{"spsr_fiq", A64SysReg_SPSR_fiq},
+	{"fpcr", A64SysReg_FPCR},
+	{"fpsr", A64SysReg_FPSR},
+	{"dspsr_el0", A64SysReg_DSPSR_EL0},
+	{"dlr_el0", A64SysReg_DLR_EL0},
+	{"ifsr32_el2", A64SysReg_IFSR32_EL2},
+	{"afsr0_el1", A64SysReg_AFSR0_EL1},
+	{"afsr0_el12", A64SysReg_AFSR0_EL12},
+	{"afsr0_el2", A64SysReg_AFSR0_EL2},
+	{"afsr0_el3", A64SysReg_AFSR0_EL3},
+	{"afsr1_el1", A64SysReg_AFSR1_EL1},
+	{"afsr1_el12", A64SysReg_AFSR1_EL12},
+	{"afsr1_el2", A64SysReg_AFSR1_EL2},
+	{"afsr1_el3", A64SysReg_AFSR1_EL3},
+	{"esr_el1", A64SysReg_ESR_EL1},
+	{"esr_el12", A64SysReg_ESR_EL12},
+	{"esr_el2", A64SysReg_ESR_EL2},
+	{"esr_el3", A64SysReg_ESR_EL3},
+	{"fpexc32_el2", A64SysReg_FPEXC32_EL2},
+	{"far_el1", A64SysReg_FAR_EL1},
+	{"far_el12", A64SysReg_FAR_EL12},
+	{"far_el2", A64SysReg_FAR_EL2},
+	{"far_el3", A64SysReg_FAR_EL3},
+	{"hpfar_el2", A64SysReg_HPFAR_EL2},
+	{"par_el1", A64SysReg_PAR_EL1},
+	{"pmcr_el0", A64SysReg_PMCR_EL0},
+	{"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
+	{"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
+	{"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
+	{"pmselr_el0", A64SysReg_PMSELR_EL0},
+	{"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
+	{"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
+	{"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
+	{"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
+	{"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
+	{"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
+	{"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
+	{"mair_el1", A64SysReg_MAIR_EL1},
+	{"mair_el12", A64SysReg_MAIR_EL12},
+	{"mair_el2", A64SysReg_MAIR_EL2},
+	{"mair_el3", A64SysReg_MAIR_EL3},
+	{"amair_el1", A64SysReg_AMAIR_EL1},
+	{"amair_el12", A64SysReg_AMAIR_EL12},
+	{"amair_el2", A64SysReg_AMAIR_EL2},
+	{"amair_el3", A64SysReg_AMAIR_EL3},
+	{"vbar_el1", A64SysReg_VBAR_EL1},
+	{"vbar_el12", A64SysReg_VBAR_EL12},
+	{"vbar_el2", A64SysReg_VBAR_EL2},
+	{"vbar_el3", A64SysReg_VBAR_EL3},
+	{"rmr_el1", A64SysReg_RMR_EL1},
+	{"rmr_el2", A64SysReg_RMR_EL2},
+	{"rmr_el3", A64SysReg_RMR_EL3},
+	{"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
+	{"contextidr_el12", A64SysReg_CONTEXTIDR_EL12},
+	{"contextidr_el2", A64SysReg_CONTEXTIDR_EL2},
+	{"tpidr_el0", A64SysReg_TPIDR_EL0},
+	{"tpidr_el2", A64SysReg_TPIDR_EL2},
+	{"tpidr_el3", A64SysReg_TPIDR_EL3},
+	{"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
+	{"tpidr_el1", A64SysReg_TPIDR_EL1},
+	{"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
+	{"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
+	{"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
+	{"cntkctl_el12", A64SysReg_CNTKCTL_EL12},
+	{"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
+	{"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
+	{"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02},
+	{"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
+	{"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
+	{"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
+	{"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
+	{"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2},
+	{"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2},
+	{"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2},
+	{"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
+	{"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
+	{"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02},
+	{"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
+	{"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
+	{"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
+	{"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02},
+	{"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
+	{"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02},
+	{"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
+	{"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02},
+	{"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
+	{"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
+	{"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
+	{"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
+	{"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
+	{"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
+	{"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
+	{"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
+	{"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
+	{"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
+	{"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
+	{"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
+	{"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
+	{"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
+	{"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
+	{"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
+	{"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
+	{"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
+	{"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
+	{"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
+	{"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
+	{"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
+	{"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
+	{"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
+	{"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
+	{"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
+	{"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
+	{"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
+	{"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
+	{"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
+	{"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
+	{"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
+	{"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
+	{"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
+	{"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
+	{"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
+	{"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
+	{"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
+	{"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
+	{"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
+	{"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
+	{"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
+	{"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
+	{"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
+	{"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
+	{"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
+	{"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
+	{"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
+	{"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
+	{"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
+	{"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
+	{"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
+	{"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
+	{"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
+	{"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
+	{"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
+	{"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
+	{"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
+	{"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
+	{"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
+	{"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
+	{"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
+	{"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
+	{"lorc_el1", A64SysReg_LORC_EL1},
+	{"lorea_el1", A64SysReg_LOREA_EL1},
+	{"lorn_el1", A64SysReg_LORN_EL1},
+	{"lorsa_el1", A64SysReg_LORSA_EL1},
+
+	// Trace registers
+	{"trcprgctlr", A64SysReg_TRCPRGCTLR},
+	{"trcprocselr", A64SysReg_TRCPROCSELR},
+	{"trcconfigr", A64SysReg_TRCCONFIGR},
+	{"trcauxctlr", A64SysReg_TRCAUXCTLR},
+	{"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
+	{"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
+	{"trcstallctlr", A64SysReg_TRCSTALLCTLR},
+	{"trctsctlr", A64SysReg_TRCTSCTLR},
+	{"trcsyncpr", A64SysReg_TRCSYNCPR},
+	{"trcccctlr", A64SysReg_TRCCCCTLR},
+	{"trcbbctlr", A64SysReg_TRCBBCTLR},
+	{"trctraceidr", A64SysReg_TRCTRACEIDR},
+	{"trcqctlr", A64SysReg_TRCQCTLR},
+	{"trcvictlr", A64SysReg_TRCVICTLR},
+	{"trcviiectlr", A64SysReg_TRCVIIECTLR},
+	{"trcvissctlr", A64SysReg_TRCVISSCTLR},
+	{"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
+	{"trcvdctlr", A64SysReg_TRCVDCTLR},
+	{"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
+	{"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
+	{"trcseqevr0", A64SysReg_TRCSEQEVR0},
+	{"trcseqevr1", A64SysReg_TRCSEQEVR1},
+	{"trcseqevr2", A64SysReg_TRCSEQEVR2},
+	{"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
+	{"trcseqstr", A64SysReg_TRCSEQSTR},
+	{"trcextinselr", A64SysReg_TRCEXTINSELR},
+	{"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
+	{"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
+	{"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
+	{"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
+	{"trccntctlr0", A64SysReg_TRCCNTCTLR0},
+	{"trccntctlr1", A64SysReg_TRCCNTCTLR1},
+	{"trccntctlr2", A64SysReg_TRCCNTCTLR2},
+	{"trccntctlr3", A64SysReg_TRCCNTCTLR3},
+	{"trccntvr0", A64SysReg_TRCCNTVR0},
+	{"trccntvr1", A64SysReg_TRCCNTVR1},
+	{"trccntvr2", A64SysReg_TRCCNTVR2},
+	{"trccntvr3", A64SysReg_TRCCNTVR3},
+	{"trcimspec0", A64SysReg_TRCIMSPEC0},
+	{"trcimspec1", A64SysReg_TRCIMSPEC1},
+	{"trcimspec2", A64SysReg_TRCIMSPEC2},
+	{"trcimspec3", A64SysReg_TRCIMSPEC3},
+	{"trcimspec4", A64SysReg_TRCIMSPEC4},
+	{"trcimspec5", A64SysReg_TRCIMSPEC5},
+	{"trcimspec6", A64SysReg_TRCIMSPEC6},
+	{"trcimspec7", A64SysReg_TRCIMSPEC7},
+	{"trcrsctlr2", A64SysReg_TRCRSCTLR2},
+	{"trcrsctlr3", A64SysReg_TRCRSCTLR3},
+	{"trcrsctlr4", A64SysReg_TRCRSCTLR4},
+	{"trcrsctlr5", A64SysReg_TRCRSCTLR5},
+	{"trcrsctlr6", A64SysReg_TRCRSCTLR6},
+	{"trcrsctlr7", A64SysReg_TRCRSCTLR7},
+	{"trcrsctlr8", A64SysReg_TRCRSCTLR8},
+	{"trcrsctlr9", A64SysReg_TRCRSCTLR9},
+	{"trcrsctlr10", A64SysReg_TRCRSCTLR10},
+	{"trcrsctlr11", A64SysReg_TRCRSCTLR11},
+	{"trcrsctlr12", A64SysReg_TRCRSCTLR12},
+	{"trcrsctlr13", A64SysReg_TRCRSCTLR13},
+	{"trcrsctlr14", A64SysReg_TRCRSCTLR14},
+	{"trcrsctlr15", A64SysReg_TRCRSCTLR15},
+	{"trcrsctlr16", A64SysReg_TRCRSCTLR16},
+	{"trcrsctlr17", A64SysReg_TRCRSCTLR17},
+	{"trcrsctlr18", A64SysReg_TRCRSCTLR18},
+	{"trcrsctlr19", A64SysReg_TRCRSCTLR19},
+	{"trcrsctlr20", A64SysReg_TRCRSCTLR20},
+	{"trcrsctlr21", A64SysReg_TRCRSCTLR21},
+	{"trcrsctlr22", A64SysReg_TRCRSCTLR22},
+	{"trcrsctlr23", A64SysReg_TRCRSCTLR23},
+	{"trcrsctlr24", A64SysReg_TRCRSCTLR24},
+	{"trcrsctlr25", A64SysReg_TRCRSCTLR25},
+	{"trcrsctlr26", A64SysReg_TRCRSCTLR26},
+	{"trcrsctlr27", A64SysReg_TRCRSCTLR27},
+	{"trcrsctlr28", A64SysReg_TRCRSCTLR28},
+	{"trcrsctlr29", A64SysReg_TRCRSCTLR29},
+	{"trcrsctlr30", A64SysReg_TRCRSCTLR30},
+	{"trcrsctlr31", A64SysReg_TRCRSCTLR31},
+	{"trcssccr0", A64SysReg_TRCSSCCR0},
+	{"trcssccr1", A64SysReg_TRCSSCCR1},
+	{"trcssccr2", A64SysReg_TRCSSCCR2},
+	{"trcssccr3", A64SysReg_TRCSSCCR3},
+	{"trcssccr4", A64SysReg_TRCSSCCR4},
+	{"trcssccr5", A64SysReg_TRCSSCCR5},
+	{"trcssccr6", A64SysReg_TRCSSCCR6},
+	{"trcssccr7", A64SysReg_TRCSSCCR7},
+	{"trcsscsr0", A64SysReg_TRCSSCSR0},
+	{"trcsscsr1", A64SysReg_TRCSSCSR1},
+	{"trcsscsr2", A64SysReg_TRCSSCSR2},
+	{"trcsscsr3", A64SysReg_TRCSSCSR3},
+	{"trcsscsr4", A64SysReg_TRCSSCSR4},
+	{"trcsscsr5", A64SysReg_TRCSSCSR5},
+	{"trcsscsr6", A64SysReg_TRCSSCSR6},
+	{"trcsscsr7", A64SysReg_TRCSSCSR7},
+	{"trcsspcicr0", A64SysReg_TRCSSPCICR0},
+	{"trcsspcicr1", A64SysReg_TRCSSPCICR1},
+	{"trcsspcicr2", A64SysReg_TRCSSPCICR2},
+	{"trcsspcicr3", A64SysReg_TRCSSPCICR3},
+	{"trcsspcicr4", A64SysReg_TRCSSPCICR4},
+	{"trcsspcicr5", A64SysReg_TRCSSPCICR5},
+	{"trcsspcicr6", A64SysReg_TRCSSPCICR6},
+	{"trcsspcicr7", A64SysReg_TRCSSPCICR7},
+	{"trcpdcr", A64SysReg_TRCPDCR},
+	{"trcacvr0", A64SysReg_TRCACVR0},
+	{"trcacvr1", A64SysReg_TRCACVR1},
+	{"trcacvr2", A64SysReg_TRCACVR2},
+	{"trcacvr3", A64SysReg_TRCACVR3},
+	{"trcacvr4", A64SysReg_TRCACVR4},
+	{"trcacvr5", A64SysReg_TRCACVR5},
+	{"trcacvr6", A64SysReg_TRCACVR6},
+	{"trcacvr7", A64SysReg_TRCACVR7},
+	{"trcacvr8", A64SysReg_TRCACVR8},
+	{"trcacvr9", A64SysReg_TRCACVR9},
+	{"trcacvr10", A64SysReg_TRCACVR10},
+	{"trcacvr11", A64SysReg_TRCACVR11},
+	{"trcacvr12", A64SysReg_TRCACVR12},
+	{"trcacvr13", A64SysReg_TRCACVR13},
+	{"trcacvr14", A64SysReg_TRCACVR14},
+	{"trcacvr15", A64SysReg_TRCACVR15},
+	{"trcacatr0", A64SysReg_TRCACATR0},
+	{"trcacatr1", A64SysReg_TRCACATR1},
+	{"trcacatr2", A64SysReg_TRCACATR2},
+	{"trcacatr3", A64SysReg_TRCACATR3},
+	{"trcacatr4", A64SysReg_TRCACATR4},
+	{"trcacatr5", A64SysReg_TRCACATR5},
+	{"trcacatr6", A64SysReg_TRCACATR6},
+	{"trcacatr7", A64SysReg_TRCACATR7},
+	{"trcacatr8", A64SysReg_TRCACATR8},
+	{"trcacatr9", A64SysReg_TRCACATR9},
+	{"trcacatr10", A64SysReg_TRCACATR10},
+	{"trcacatr11", A64SysReg_TRCACATR11},
+	{"trcacatr12", A64SysReg_TRCACATR12},
+	{"trcacatr13", A64SysReg_TRCACATR13},
+	{"trcacatr14", A64SysReg_TRCACATR14},
+	{"trcacatr15", A64SysReg_TRCACATR15},
+	{"trcdvcvr0", A64SysReg_TRCDVCVR0},
+	{"trcdvcvr1", A64SysReg_TRCDVCVR1},
+	{"trcdvcvr2", A64SysReg_TRCDVCVR2},
+	{"trcdvcvr3", A64SysReg_TRCDVCVR3},
+	{"trcdvcvr4", A64SysReg_TRCDVCVR4},
+	{"trcdvcvr5", A64SysReg_TRCDVCVR5},
+	{"trcdvcvr6", A64SysReg_TRCDVCVR6},
+	{"trcdvcvr7", A64SysReg_TRCDVCVR7},
+	{"trcdvcmr0", A64SysReg_TRCDVCMR0},
+	{"trcdvcmr1", A64SysReg_TRCDVCMR1},
+	{"trcdvcmr2", A64SysReg_TRCDVCMR2},
+	{"trcdvcmr3", A64SysReg_TRCDVCMR3},
+	{"trcdvcmr4", A64SysReg_TRCDVCMR4},
+	{"trcdvcmr5", A64SysReg_TRCDVCMR5},
+	{"trcdvcmr6", A64SysReg_TRCDVCMR6},
+	{"trcdvcmr7", A64SysReg_TRCDVCMR7},
+	{"trccidcvr0", A64SysReg_TRCCIDCVR0},
+	{"trccidcvr1", A64SysReg_TRCCIDCVR1},
+	{"trccidcvr2", A64SysReg_TRCCIDCVR2},
+	{"trccidcvr3", A64SysReg_TRCCIDCVR3},
+	{"trccidcvr4", A64SysReg_TRCCIDCVR4},
+	{"trccidcvr5", A64SysReg_TRCCIDCVR5},
+	{"trccidcvr6", A64SysReg_TRCCIDCVR6},
+	{"trccidcvr7", A64SysReg_TRCCIDCVR7},
+	{"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
+	{"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
+	{"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
+	{"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
+	{"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
+	{"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
+	{"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
+	{"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
+	{"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
+	{"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
+	{"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
+	{"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
+	{"trcitctrl", A64SysReg_TRCITCTRL},
+	{"trcclaimset", A64SysReg_TRCCLAIMSET},
+	{"trcclaimclr", A64SysReg_TRCCLAIMCLR},
+
+	// GICv3 registers
+	{"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
+	{"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
+	{"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
+	{"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
+	{"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
+	{"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
+	{"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
+	{"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
+	{"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
+	{"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
+	{"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
+	{"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
+	{"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
+	{"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
+	{"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
+	{"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
+	{"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
+	{"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
+	{"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
+	{"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
+	{"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
+	{"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
+	{"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
+	{"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
+	{"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
+	{"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
+	{"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
+	{"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
+	{"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
+	{"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
+	{"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
+	{"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
+	{"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
+	{"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
+	{"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
+	{"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
+	{"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
+	{"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
+	{"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
+	{"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
+	{"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
+	{"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
+	{"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
+	{"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
+	{"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
+	{"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
+	{"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
+	{"ich_lr15_el2", A64SysReg_ICH_LR15_EL2},
+
+	// Statistical profiling registers
+	{"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1},
+	{"pmbptr_el1", A64SysReg_PMBPTR_EL1},
+	{"pmbsr_el1", A64SysReg_PMBSR_EL1},
+	{"pmscr_el1", A64SysReg_PMSCR_EL1},
+	{"pmscr_el12", A64SysReg_PMSCR_EL12},
+	{"pmscr_el2", A64SysReg_PMSCR_EL2},
+	{"pmsicr_el1", A64SysReg_PMSICR_EL1},
+	{"pmsirr_el1", A64SysReg_PMSIRR_EL1},
+	{"pmsfcr_el1", A64SysReg_PMSFCR_EL1},
+	{"pmsevfr_el1", A64SysReg_PMSEVFR_EL1},
+	{"pmslatfr_el1", A64SysReg_PMSLATFR_EL1}
+};
+
+static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
+	{"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
+};
+
+// result must be a big enough buffer: 128 bytes is more than enough
+void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result)
+{
+	int dummy;
+	uint32_t Op0, Op1, CRn, CRm, Op2;
+	char *Op0S, *Op1S, *CRnS, *CRmS, *Op2S;
+	unsigned i;
+
+	// First search the registers shared by all
+	for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
+		if (SysRegPairs[i].Value == Bits) {
+			strcpy(result, SysRegPairs[i].Name);
+			return;
+		}
+	}
+
+	// Next search for target specific registers
+	// if (FeatureBits & AArch64_ProcCyclone) {
+	if (true) {
+		for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) {
+			if (CycloneSysRegPairs[i].Value == Bits) {
+				strcpy(result, CycloneSysRegPairs[i].Name);
+				return;
+			}
+		}
+	}
+
+	// Now try the instruction-specific registers (either read-only or
+	// write-only).
+	for (i = 0; i < S->NumInstPairs; ++i) {
+		if (S->InstPairs[i].Value == Bits) {
+			strcpy(result, S->InstPairs[i].Name);
+			return;
+		}
+	}
+
+	Op0 = (Bits >> 14) & 0x3;
+	Op1 = (Bits >> 11) & 0x7;
+	CRn = (Bits >> 7) & 0xf;
+	CRm = (Bits >> 3) & 0xf;
+	Op2 = Bits & 0x7;
+
+	Op0S = utostr(Op0, false);
+	Op1S = utostr(Op1, false);
+	CRnS = utostr(CRn, false);
+	CRmS = utostr(CRm, false);
+	Op2S = utostr(Op2, false);
+
+	//printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
+	dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
+	(void)dummy;
+
+	cs_mem_free(Op0S);
+	cs_mem_free(Op1S);
+	cs_mem_free(CRnS);
+	cs_mem_free(CRmS);
+	cs_mem_free(Op2S);
+}
+
+static const A64NamedImmMapper_Mapping TLBIPairs[] = {
+	{"ipas2e1is", A64TLBI_IPAS2E1IS},
+	{"ipas2le1is", A64TLBI_IPAS2LE1IS},
+	{"vmalle1is", A64TLBI_VMALLE1IS},
+	{"alle2is", A64TLBI_ALLE2IS},
+	{"alle3is", A64TLBI_ALLE3IS},
+	{"vae1is", A64TLBI_VAE1IS},
+	{"vae2is", A64TLBI_VAE2IS},
+	{"vae3is", A64TLBI_VAE3IS},
+	{"aside1is", A64TLBI_ASIDE1IS},
+	{"vaae1is", A64TLBI_VAAE1IS},
+	{"alle1is", A64TLBI_ALLE1IS},
+	{"vale1is", A64TLBI_VALE1IS},
+	{"vale2is", A64TLBI_VALE2IS},
+	{"vale3is", A64TLBI_VALE3IS},
+	{"vmalls12e1is", A64TLBI_VMALLS12E1IS},
+	{"vaale1is", A64TLBI_VAALE1IS},
+	{"ipas2e1", A64TLBI_IPAS2E1},
+	{"ipas2le1", A64TLBI_IPAS2LE1},
+	{"vmalle1", A64TLBI_VMALLE1},
+	{"alle2", A64TLBI_ALLE2},
+	{"alle3", A64TLBI_ALLE3},
+	{"vae1", A64TLBI_VAE1},
+	{"vae2", A64TLBI_VAE2},
+	{"vae3", A64TLBI_VAE3},
+	{"aside1", A64TLBI_ASIDE1},
+	{"vaae1", A64TLBI_VAAE1},
+	{"alle1", A64TLBI_ALLE1},
+	{"vale1", A64TLBI_VALE1},
+	{"vale2", A64TLBI_VALE2},
+	{"vale3", A64TLBI_VALE3},
+	{"vmalls12e1", A64TLBI_VMALLS12E1},
+	{"vaale1", A64TLBI_VAALE1}
+};
+
+const A64NamedImmMapper A64TLBI_TLBIMapper = {
+	TLBIPairs,
+	ARR_SIZE(TLBIPairs),
+	0,
+};
+
+static const A64NamedImmMapper_Mapping ATPairs[] = {
+	{"s1e1r", A64AT_S1E1R},
+	{"s1e2r", A64AT_S1E2R},
+	{"s1e3r", A64AT_S1E3R},
+	{"s1e1w", A64AT_S1E1W},
+	{"s1e2w", A64AT_S1E2W},
+	{"s1e3w", A64AT_S1E3W},
+	{"s1e0r", A64AT_S1E0R},
+	{"s1e0w", A64AT_S1E0W},
+	{"s12e1r", A64AT_S12E1R},
+	{"s12e1w", A64AT_S12E1W},
+	{"s12e0r", A64AT_S12E0R},
+	{"s12e0w", A64AT_S12E0W}
+};
+
+const A64NamedImmMapper A64AT_ATMapper = {
+	ATPairs,
+	ARR_SIZE(ATPairs),
+	0,
+};
+
+static const A64NamedImmMapper_Mapping DBarrierPairs[] = {
+	{"oshld", A64DB_OSHLD},
+	{"oshst", A64DB_OSHST},
+	{"osh", A64DB_OSH},
+	{"nshld", A64DB_NSHLD},
+	{"nshst", A64DB_NSHST},
+	{"nsh", A64DB_NSH},
+	{"ishld", A64DB_ISHLD},
+	{"ishst", A64DB_ISHST},
+	{"ish", A64DB_ISH},
+	{"ld", A64DB_LD},
+	{"st", A64DB_ST},
+	{"sy", A64DB_SY}
+};
+
+const A64NamedImmMapper A64DB_DBarrierMapper = {
+	DBarrierPairs,
+	ARR_SIZE(DBarrierPairs),
+	16,
+};
+
+static const A64NamedImmMapper_Mapping DCPairs[] = {
+	{"zva", A64DC_ZVA},
+	{"ivac", A64DC_IVAC},
+	{"isw", A64DC_ISW},
+	{"cvac", A64DC_CVAC},
+	{"csw", A64DC_CSW},
+	{"cvau", A64DC_CVAU},
+	{"civac", A64DC_CIVAC},
+	{"cisw", A64DC_CISW}
+};
+
+const A64NamedImmMapper A64DC_DCMapper = {
+	DCPairs,
+	ARR_SIZE(DCPairs),
+	0,
+};
+
+static const A64NamedImmMapper_Mapping ICPairs[] = {
+	{"ialluis",  A64IC_IALLUIS},
+	{"iallu", A64IC_IALLU},
+	{"ivau", A64IC_IVAU}
+};
+
+const A64NamedImmMapper A64IC_ICMapper = {
+	ICPairs,
+	ARR_SIZE(ICPairs),
+	0,
+};
+
+static const A64NamedImmMapper_Mapping ISBPairs[] = {
+	{"sy",  A64DB_SY},
+};
+
+const A64NamedImmMapper A64ISB_ISBMapper = {
+	ISBPairs,
+	ARR_SIZE(ISBPairs),
+	16,
+};
+
+static const A64NamedImmMapper_Mapping PRFMPairs[] = {
+	{"pldl1keep", A64PRFM_PLDL1KEEP},
+	{"pldl1strm", A64PRFM_PLDL1STRM},
+	{"pldl2keep", A64PRFM_PLDL2KEEP},
+	{"pldl2strm", A64PRFM_PLDL2STRM},
+	{"pldl3keep", A64PRFM_PLDL3KEEP},
+	{"pldl3strm", A64PRFM_PLDL3STRM},
+	{"plil1keep", A64PRFM_PLIL1KEEP},
+	{"plil1strm", A64PRFM_PLIL1STRM},
+	{"plil2keep", A64PRFM_PLIL2KEEP},
+	{"plil2strm", A64PRFM_PLIL2STRM},
+	{"plil3keep", A64PRFM_PLIL3KEEP},
+	{"plil3strm", A64PRFM_PLIL3STRM},
+	{"pstl1keep", A64PRFM_PSTL1KEEP},
+	{"pstl1strm", A64PRFM_PSTL1STRM},
+	{"pstl2keep", A64PRFM_PSTL2KEEP},
+	{"pstl2strm", A64PRFM_PSTL2STRM},
+	{"pstl3keep", A64PRFM_PSTL3KEEP},
+	{"pstl3strm", A64PRFM_PSTL3STRM}
+};
+
+const A64NamedImmMapper A64PRFM_PRFMMapper = {
+	PRFMPairs,
+	ARR_SIZE(PRFMPairs),
+	32,
+};
+
+static const A64NamedImmMapper_Mapping PStatePairs[] = {
+	{"spsel", A64PState_SPSel},
+	{"daifset", A64PState_DAIFSet},
+	{"daifclr", A64PState_DAIFClr},
+	{"pan", A64PState_PAN},
+	{"uao", A64PState_UAO}
+};
+
+const A64NamedImmMapper A64PState_PStateMapper = {
+	PStatePairs,
+	ARR_SIZE(PStatePairs),
+	0,
+};
+
+static const A64NamedImmMapper_Mapping MRSPairs[] = {
+	{"mdccsr_el0", A64SysReg_MDCCSR_EL0},
+	{"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
+	{"mdrar_el1", A64SysReg_MDRAR_EL1},
+	{"oslsr_el1", A64SysReg_OSLSR_EL1},
+	{"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
+	{"pmceid0_el0", A64SysReg_PMCEID0_EL0},
+	{"pmceid1_el0", A64SysReg_PMCEID1_EL0},
+	{"midr_el1", A64SysReg_MIDR_EL1},
+	{"ccsidr_el1", A64SysReg_CCSIDR_EL1},
+	{"clidr_el1", A64SysReg_CLIDR_EL1},
+	{"ctr_el0", A64SysReg_CTR_EL0},
+	{"mpidr_el1", A64SysReg_MPIDR_EL1},
+	{"revidr_el1", A64SysReg_REVIDR_EL1},
+	{"aidr_el1", A64SysReg_AIDR_EL1},
+	{"dczid_el0", A64SysReg_DCZID_EL0},
+	{"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
+	{"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
+	{"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
+	{"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
+	{"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
+	{"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
+	{"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
+	{"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
+	{"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1},
+	{"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
+	{"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
+	{"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
+	{"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
+	{"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
+	{"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
+	{"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1},
+	{"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1},
+	{"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1},
+	{"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1},
+	{"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1},
+	{"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1},
+	{"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1},
+	{"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1},
+	{"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1},
+	{"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1},
+	{"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1},
+	{"lorid_el1", A64SysReg_LORID_EL1},
+	{"mvfr0_el1", A64SysReg_MVFR0_EL1},
+	{"mvfr1_el1", A64SysReg_MVFR1_EL1},
+	{"mvfr2_el1", A64SysReg_MVFR2_EL1},
+	{"rvbar_el1", A64SysReg_RVBAR_EL1},
+	{"rvbar_el2", A64SysReg_RVBAR_EL2},
+	{"rvbar_el3", A64SysReg_RVBAR_EL3},
+	{"isr_el1", A64SysReg_ISR_EL1},
+	{"cntpct_el0", A64SysReg_CNTPCT_EL0},
+	{"cntvct_el0", A64SysReg_CNTVCT_EL0},
+
+	// Trace registers
+	{"trcstatr", A64SysReg_TRCSTATR},
+	{"trcidr8", A64SysReg_TRCIDR8},
+	{"trcidr9", A64SysReg_TRCIDR9},
+	{"trcidr10", A64SysReg_TRCIDR10},
+	{"trcidr11", A64SysReg_TRCIDR11},
+	{"trcidr12", A64SysReg_TRCIDR12},
+	{"trcidr13", A64SysReg_TRCIDR13},
+	{"trcidr0", A64SysReg_TRCIDR0},
+	{"trcidr1", A64SysReg_TRCIDR1},
+	{"trcidr2", A64SysReg_TRCIDR2},
+	{"trcidr3", A64SysReg_TRCIDR3},
+	{"trcidr4", A64SysReg_TRCIDR4},
+	{"trcidr5", A64SysReg_TRCIDR5},
+	{"trcidr6", A64SysReg_TRCIDR6},
+	{"trcidr7", A64SysReg_TRCIDR7},
+	{"trcoslsr", A64SysReg_TRCOSLSR},
+	{"trcpdsr", A64SysReg_TRCPDSR},
+	{"trcdevaff0", A64SysReg_TRCDEVAFF0},
+	{"trcdevaff1", A64SysReg_TRCDEVAFF1},
+	{"trclsr", A64SysReg_TRCLSR},
+	{"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
+	{"trcdevarch", A64SysReg_TRCDEVARCH},
+	{"trcdevid", A64SysReg_TRCDEVID},
+	{"trcdevtype", A64SysReg_TRCDEVTYPE},
+	{"trcpidr4", A64SysReg_TRCPIDR4},
+	{"trcpidr5", A64SysReg_TRCPIDR5},
+	{"trcpidr6", A64SysReg_TRCPIDR6},
+	{"trcpidr7", A64SysReg_TRCPIDR7},
+	{"trcpidr0", A64SysReg_TRCPIDR0},
+	{"trcpidr1", A64SysReg_TRCPIDR1},
+	{"trcpidr2", A64SysReg_TRCPIDR2},
+	{"trcpidr3", A64SysReg_TRCPIDR3},
+	{"trccidr0", A64SysReg_TRCCIDR0},
+	{"trccidr1", A64SysReg_TRCCIDR1},
+	{"trccidr2", A64SysReg_TRCCIDR2},
+	{"trccidr3", A64SysReg_TRCCIDR3},
+
+	// GICv3 registers
+	{"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
+	{"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
+	{"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
+	{"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
+	{"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
+	{"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
+	{"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
+	{"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2},
+
+	// Statistical profiling registers
+	{"pmsidr_el1", A64SysReg_PMSIDR_EL1},
+	{"pmbidr_el1", A64SysReg_PMBIDR_EL1}
+};
+
+const A64SysRegMapper AArch64_MRSMapper = {
+	NULL,
+	MRSPairs,
+	ARR_SIZE(MRSPairs),
+};
+
+static const A64NamedImmMapper_Mapping MSRPairs[] = {
+	{"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
+	{"oslar_el1", A64SysReg_OSLAR_EL1},
+	{"pmswinc_el0", A64SysReg_PMSWINC_EL0},
+
+	// Trace registers
+	{"trcoslar", A64SysReg_TRCOSLAR},
+	{"trclar", A64SysReg_TRCLAR},
+
+	// GICv3 registers
+	{"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
+	{"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
+	{"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
+	{"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
+	{"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
+	{"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
+};
+
+const A64SysRegMapper AArch64_MSRMapper = {
+	NULL,
+	MSRPairs,
+	ARR_SIZE(MSRPairs),
+};
+
+#endif

arch/AArch64/AArch64Disassembler.h

@@ -0,0 +1,16 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_AARCH64_DISASSEMBLER_H
+#define CS_AARCH64_DISASSEMBLER_H
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+void AArch64_init(MCRegisterInfo *MRI);
+
+bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif

arch/AArch64/AArch64GenSubtargetInfo.inc

@@ -0,0 +1,29 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Subtarget Enumeration Source Fragment                                       *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+enum {
+  AArch64_FeatureCRC =  1ULL << 0,
+  AArch64_FeatureCrypto =  1ULL << 1,
+  AArch64_FeatureFPARMv8 =  1ULL << 2,
+  AArch64_FeatureNEON =  1ULL << 3,
+  AArch64_FeatureZCRegMove =  1ULL << 4,
+  AArch64_FeatureZCZeroing =  1ULL << 5,
+  AArch64_ProcA53 =  1ULL << 6,
+  AArch64_ProcA57 =  1ULL << 7,
+  AArch64_ProcCyclone =  1ULL << 8
+};
+
+#endif // GET_SUBTARGETINFO_ENUM
+

arch/AArch64/AArch64InstPrinter.h

@@ -0,0 +1,28 @@
+//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an AArch64 MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_LLVM_AARCH64INSTPRINTER_H
+#define CS_LLVM_AARCH64INSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void AArch64_printInst(MCInst *MI, SStream *O, void *);
+
+void AArch64_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm, MCInst *mci);
+
+#endif

arch/AArch64/AArch64Mapping.h

@@ -0,0 +1,41 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_ARM64_MAP_H
+#define CS_ARM64_MAP_H
+
+#include "capstone/capstone.h"
+
+// return name of regiser in friendly string
+const char *AArch64_reg_name(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction info
+void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *AArch64_insn_name(csh handle, unsigned int id);
+
+const char *AArch64_group_name(csh handle, unsigned int id);
+
+// map instruction name to public instruction ID
+arm64_reg AArch64_map_insn(const char *name);
+
+// map internal vregister to public register
+arm64_reg AArch64_map_vregister(unsigned int r);
+
+void arm64_op_addReg(MCInst *MI, int reg);
+
+void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp);
+
+void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp);
+
+void arm64_op_addFP(MCInst *MI, float fp);
+
+void arm64_op_addImm(MCInst *MI, int64_t imm);
+
+uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id);
+
+void AArch64_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count);
+
+#endif

arch/AArch64/AArch64Module.c

@@ -0,0 +1,44 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_ARM64
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "AArch64Disassembler.h"
+#include "AArch64InstPrinter.h"
+#include "AArch64Mapping.h"
+#include "AArch64Module.h"
+
+cs_err AArch64_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	AArch64_init(mri);
+	ud->printer = AArch64_printInst;
+	ud->printer_info = mri;
+	ud->getinsn_info = mri;
+	ud->disasm = AArch64_getInstruction;
+	ud->reg_name = AArch64_reg_name;
+	ud->insn_id = AArch64_get_insn_id;
+	ud->insn_name = AArch64_insn_name;
+	ud->group_name = AArch64_group_name;
+	ud->post_printer = AArch64_post_printer;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = AArch64_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	if (type == CS_OPT_MODE) {
+		handle->mode = (cs_mode)value;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

arch/AArch64/AArch64Module.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_AARCH64_MODULE_H
+#define CS_AARCH64_MODULE_H
+
+#include "../../utils.h"
+
+cs_err AArch64_global_init(cs_struct *ud);
+cs_err AArch64_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

arch/ARM/ARMAddressingModes.h

@@ -0,0 +1,670 @@
+//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the ARM addressing mode implementation stuff.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
+#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
+
+#include "capstone/platform.h"
+#include "../../MathExtras.h"
+
+/// ARM_AM - ARM Addressing Mode Stuff
+typedef enum ARM_AM_ShiftOpc {
+	ARM_AM_no_shift = 0,
+	ARM_AM_asr,
+	ARM_AM_lsl,
+	ARM_AM_lsr,
+	ARM_AM_ror,
+	ARM_AM_rrx
+} ARM_AM_ShiftOpc;
+
+typedef enum ARM_AM_AddrOpc {
+	ARM_AM_sub = 0,
+	ARM_AM_add
+} ARM_AM_AddrOpc;
+
+static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
+{
+	return Op == ARM_AM_sub ? "-" : "";
+}
+
+static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
+{
+	switch (Op) {
+		default: return "";	//llvm_unreachable("Unknown shift opc!");
+		case ARM_AM_asr: return "asr";
+		case ARM_AM_lsl: return "lsl";
+		case ARM_AM_lsr: return "lsr";
+		case ARM_AM_ror: return "ror";
+		case ARM_AM_rrx: return "rrx";
+	}
+}
+
+static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
+{
+	switch (Op) {
+		default: return (unsigned int)-1;	//llvm_unreachable("Unknown shift opc!");
+		case ARM_AM_asr: return 2;
+		case ARM_AM_lsl: return 0;
+		case ARM_AM_lsr: return 1;
+		case ARM_AM_ror: return 3;
+	}
+}
+
+typedef enum ARM_AM_AMSubMode {
+	ARM_AM_bad_am_submode = 0,
+	ARM_AM_ia,
+	ARM_AM_ib,
+	ARM_AM_da,
+	ARM_AM_db
+} ARM_AM_AMSubMode;
+
+static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode)
+{
+	switch (Mode) {
+		default: return "";
+		case ARM_AM_ia: return "ia";
+		case ARM_AM_ib: return "ib";
+		case ARM_AM_da: return "da";
+		case ARM_AM_db: return "db";
+	}
+}
+
+/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
+///
+static inline unsigned rotr32(unsigned Val, unsigned Amt)
+{
+	//assert(Amt < 32 && "Invalid rotate amount");
+	return (Val >> Amt) | (Val << ((32-Amt)&31));
+}
+
+/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
+///
+static inline unsigned rotl32(unsigned Val, unsigned Amt)
+{
+	//assert(Amt < 32 && "Invalid rotate amount");
+	return (Val << Amt) | (Val >> ((32-Amt)&31));
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #1: shift_operand with registers
+//===--------------------------------------------------------------------===//
+//
+// This 'addressing mode' is used for arithmetic instructions.  It can
+// represent things like:
+//   reg
+//   reg [asr|lsl|lsr|ror|rrx] reg
+//   reg [asr|lsl|lsr|ror|rrx] imm
+//
+// This is stored three operands [rega, regb, opc].  The first is the base
+// reg, the second is the shift amount (or reg0 if not present or imm).  The
+// third operand encodes the shift opcode and the imm if a reg isn't present.
+//
+static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
+{
+	return ShOp | (Imm << 3);
+}
+
+static inline unsigned getSORegOffset(unsigned Op)
+{
+	return Op >> 3;
+}
+
+static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
+{
+	return (ARM_AM_ShiftOpc)(Op & 7);
+}
+
+/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
+/// the 8-bit imm value.
+static inline unsigned getSOImmValImm(unsigned Imm)
+{
+	return Imm & 0xFF;
+}
+
+/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
+/// the rotate amount.
+static inline unsigned getSOImmValRot(unsigned Imm)
+{
+	return (Imm >> 8) * 2;
+}
+
+/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
+/// computing the rotate amount to use.  If this immediate value cannot be
+/// handled with a single shifter-op, determine a good rotate amount that will
+/// take a maximal chunk of bits out of the immediate.
+static inline unsigned getSOImmValRotate(unsigned Imm)
+{
+	unsigned TZ, RotAmt;
+	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
+	// of zero.
+	if ((Imm & ~255U) == 0) return 0;
+
+	// Use CTZ to compute the rotate amount.
+	TZ = CountTrailingZeros_32(Imm);
+
+	// Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
+	// not 9.
+	RotAmt = TZ & ~1;
+
+	// If we can handle this spread, return it.
+	if ((rotr32(Imm, RotAmt) & ~255U) == 0)
+		return (32-RotAmt)&31;  // HW rotates right, not left.
+
+	// For values like 0xF000000F, we should ignore the low 6 bits, then
+	// retry the hunt.
+	if (Imm & 63U) {
+		unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
+		unsigned RotAmt2 = TZ2 & ~1;
+		if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
+			return (32-RotAmt2)&31;  // HW rotates right, not left.
+	}
+
+	// Otherwise, we have no way to cover this span of bits with a single
+	// shifter_op immediate.  Return a chunk of bits that will be useful to
+	// handle.
+	return (32-RotAmt)&31;  // HW rotates right, not left.
+}
+
+/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
+/// into an shifter_operand immediate operand, return the 12-bit encoding for
+/// it.  If not, return -1.
+static inline int getSOImmVal(unsigned Arg)
+{
+	unsigned RotAmt;
+	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
+	// of zero.
+	if ((Arg & ~255U) == 0) return Arg;
+
+	RotAmt = getSOImmValRotate(Arg);
+
+	// If this cannot be handled with a single shifter_op, bail out.
+	if (rotr32(~255U, RotAmt) & Arg)
+		return -1;
+
+	// Encode this correctly.
+	return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
+}
+
+/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
+/// or'ing together two SOImmVal's.
+static inline bool isSOImmTwoPartVal(unsigned V)
+{
+	// If this can be handled with a single shifter_op, bail out.
+	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	if (V == 0)
+		return false;
+
+	// If this can be handled with two shifter_op's, accept.
+	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	return V == 0;
+}
+
+/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
+/// return the first chunk of it.
+static inline unsigned getSOImmTwoPartFirst(unsigned V)
+{
+	return rotr32(255U, getSOImmValRotate(V)) & V;
+}
+
+/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
+/// return the second chunk of it.
+static inline unsigned getSOImmTwoPartSecond(unsigned V)
+{
+	// Mask out the first hunk.
+	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+
+	// Take what's left.
+	//assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
+	return V;
+}
+
+/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
+/// by a left shift. Returns the shift amount to use.
+static inline unsigned getThumbImmValShift(unsigned Imm)
+{
+	// 8-bit (or less) immediates are trivially immediate operand with a shift
+	// of zero.
+	if ((Imm & ~255U) == 0) return 0;
+
+	// Use CTZ to compute the shift amount.
+	return CountTrailingZeros_32(Imm);
+}
+
+/// isThumbImmShiftedVal - Return true if the specified value can be obtained
+/// by left shifting a 8-bit immediate.
+static inline bool isThumbImmShiftedVal(unsigned V)
+{
+	// If this can be handled with
+	V = (~255U << getThumbImmValShift(V)) & V;
+	return V == 0;
+}
+
+/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
+/// by a left shift. Returns the shift amount to use.
+static inline unsigned getThumbImm16ValShift(unsigned Imm)
+{
+	// 16-bit (or less) immediates are trivially immediate operand with a shift
+	// of zero.
+	if ((Imm & ~65535U) == 0) return 0;
+
+	// Use CTZ to compute the shift amount.
+	return CountTrailingZeros_32(Imm);
+}
+
+/// isThumbImm16ShiftedVal - Return true if the specified value can be
+/// obtained by left shifting a 16-bit immediate.
+static inline bool isThumbImm16ShiftedVal(unsigned V)
+{
+	// If this can be handled with
+	V = (~65535U << getThumbImm16ValShift(V)) & V;
+	return V == 0;
+}
+
+/// getThumbImmNonShiftedVal - If V is a value that satisfies
+/// isThumbImmShiftedVal, return the non-shiftd value.
+static inline unsigned getThumbImmNonShiftedVal(unsigned V)
+{
+	return V >> getThumbImmValShift(V);
+}
+
+
+/// getT2SOImmValSplat - Return the 12-bit encoded representation
+/// if the specified value can be obtained by splatting the low 8 bits
+/// into every other byte or every byte of a 32-bit value. i.e.,
+///     00000000 00000000 00000000 abcdefgh    control = 0
+///     00000000 abcdefgh 00000000 abcdefgh    control = 1
+///     abcdefgh 00000000 abcdefgh 00000000    control = 2
+///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
+/// Return -1 if none of the above apply.
+/// See ARM Reference Manual A6.3.2.
+static inline int getT2SOImmValSplatVal(unsigned V)
+{
+	unsigned u, Vs, Imm;
+	// control = 0
+	if ((V & 0xffffff00) == 0)
+		return V;
+
+	// If the value is zeroes in the first byte, just shift those off
+	Vs = ((V & 0xff) == 0) ? V >> 8 : V;
+	// Any passing value only has 8 bits of payload, splatted across the word
+	Imm = Vs & 0xff;
+	// Likewise, any passing values have the payload splatted into the 3rd byte
+	u = Imm | (Imm << 16);
+
+	// control = 1 or 2
+	if (Vs == u)
+		return (((Vs == V) ? 1 : 2) << 8) | Imm;
+
+	// control = 3
+	if (Vs == (u | (u << 8)))
+		return (3 << 8) | Imm;
+
+	return -1;
+}
+
+/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
+/// specified value is a rotated 8-bit value. Return -1 if no rotation
+/// encoding is possible.
+/// See ARM Reference Manual A6.3.2.
+static inline int getT2SOImmValRotateVal(unsigned V)
+{
+	unsigned RotAmt = CountLeadingZeros_32(V);
+	if (RotAmt >= 24)
+		return -1;
+
+	// If 'Arg' can be handled with a single shifter_op return the value.
+	if ((rotr32(0xff000000U, RotAmt) & V) == V)
+		return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
+
+	return -1;
+}
+
+/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
+/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
+/// encoding for it.  If not, return -1.
+/// See ARM Reference Manual A6.3.2.
+static inline int getT2SOImmVal(unsigned Arg)
+{
+	int Rot;
+	// If 'Arg' is an 8-bit splat, then get the encoded value.
+	int Splat = getT2SOImmValSplatVal(Arg);
+	if (Splat != -1)
+		return Splat;
+
+	// If 'Arg' can be handled with a single shifter_op return the value.
+	Rot = getT2SOImmValRotateVal(Arg);
+	if (Rot != -1)
+		return Rot;
+
+	return -1;
+}
+
+static inline unsigned getT2SOImmValRotate(unsigned V)
+{
+	unsigned RotAmt;
+
+	if ((V & ~255U) == 0)
+		return 0;
+
+	// Use CTZ to compute the rotate amount.
+	RotAmt = CountTrailingZeros_32(V);
+	return (32 - RotAmt) & 31;
+}
+
+static inline bool isT2SOImmTwoPartVal (unsigned Imm)
+{
+	unsigned V = Imm;
+	// Passing values can be any combination of splat values and shifter
+	// values. If this can be handled with a single shifter or splat, bail
+	// out. Those should be handled directly, not with a two-part val.
+	if (getT2SOImmValSplatVal(V) != -1)
+		return false;
+	V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
+	if (V == 0)
+		return false;
+
+	// If this can be handled as an immediate, accept.
+	if (getT2SOImmVal(V) != -1) return true;
+
+	// Likewise, try masking out a splat value first.
+	V = Imm;
+	if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
+		V &= ~0xff00ff00U;
+	else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
+		V &= ~0x00ff00ffU;
+	// If what's left can be handled as an immediate, accept.
+	if (getT2SOImmVal(V) != -1) return true;
+
+	// Otherwise, do not accept.
+	return false;
+}
+
+static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm)
+{
+	//assert (isT2SOImmTwoPartVal(Imm) &&
+	//        "Immedate cannot be encoded as two part immediate!");
+	// Try a shifter operand as one part
+	unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
+	// If the rest is encodable as an immediate, then return it.
+	if (getT2SOImmVal(V) != -1) return V;
+
+	// Try masking out a splat value first.
+	if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
+		return Imm & 0xff00ff00U;
+
+	// The other splat is all that's left as an option.
+	//assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
+	return Imm & 0x00ff00ffU;
+}
+
+static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
+{
+	// Mask out the first hunk
+	Imm ^= getT2SOImmTwoPartFirst(Imm);
+	// Return what's left
+	//assert (getT2SOImmVal(Imm) != -1 &&
+	//        "Unable to encode second part of T2 two part SO immediate");
+	return Imm;
+}
+
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #2
+//===--------------------------------------------------------------------===//
+//
+// This is used for most simple load/store instructions.
+//
+// addrmode2 := reg +/- reg shop imm
+// addrmode2 := reg +/- imm12
+//
+// The first operand is always a Reg.  The second operand is a reg if in
+// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
+// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
+// fourth operand 16-17 encodes the index mode.
+//
+// If this addressing mode is a frame index (before prolog/epilog insertion
+// and code rewriting), this operand will have the form:  FI#, reg0, <offs>
+// with no shift amount for the frame offset.
+//
+static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO,
+		unsigned IdxMode)
+{
+	//assert(Imm12 < (1 << 12) && "Imm too large!");
+	bool isSub = Opc == ARM_AM_sub;
+	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
+}
+
+static inline unsigned getAM2Offset(unsigned AM2Opc)
+{
+	return AM2Opc & ((1 << 12)-1);
+}
+
+static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc)
+{
+	return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
+{
+	return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
+}
+
+static inline unsigned getAM2IdxMode(unsigned AM2Opc)
+{
+	return (AM2Opc >> 16);
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #3
+//===--------------------------------------------------------------------===//
+//
+// This is used for sign-extending loads, and load/store-pair instructions.
+//
+// addrmode3 := reg +/- reg
+// addrmode3 := reg +/- imm8
+//
+// The first operand is always a Reg.  The second operand is a reg if in
+// reg/reg form, otherwise it's reg#0.  The third field encodes the operation
+// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
+// index mode.
+
+/// getAM3Opc - This function encodes the addrmode3 opc field.
+static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset,
+		unsigned IdxMode)
+{
+	bool isSub = Opc == ARM_AM_sub;
+	return ((int)isSub << 8) | Offset | (IdxMode << 9);
+}
+
+static inline unsigned char getAM3Offset(unsigned AM3Opc)
+{
+	return AM3Opc & 0xFF;
+}
+
+static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc)
+{
+	return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+static inline unsigned getAM3IdxMode(unsigned AM3Opc)
+{
+	return (AM3Opc >> 9);
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #4
+//===--------------------------------------------------------------------===//
+//
+// This is used for load / store multiple instructions.
+//
+// addrmode4 := reg, <mode>
+//
+// The four modes are:
+//    IA - Increment after
+//    IB - Increment before
+//    DA - Decrement after
+//    DB - Decrement before
+// For VFP instructions, only the IA and DB modes are valid.
+
+static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode)
+{
+	return (ARM_AM_AMSubMode)(Mode & 0x7);
+}
+
+static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
+{
+	return (int)SubMode;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #5
+//===--------------------------------------------------------------------===//
+//
+// This is used for coprocessor instructions, such as FP load/stores.
+//
+// addrmode5 := reg +/- imm8*4
+//
+// The first operand is always a Reg.  The second operand encodes the
+// operation in bit 8 and the immediate in bits 0-7.
+
+/// getAM5Opc - This function encodes the addrmode5 opc field.
+static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
+{
+	bool isSub = Opc == ARM_AM_sub;
+	return ((int)isSub << 8) | Offset;
+}
+static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
+{
+	return AM5Opc & 0xFF;
+}
+static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
+{
+	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
+}
+
+//===--------------------------------------------------------------------===//
+// Addressing Mode #6
+//===--------------------------------------------------------------------===//
+//
+// This is used for NEON load / store instructions.
+//
+// addrmode6 := reg with optional alignment
+//
+// This is stored in two operands [regaddr, align].  The first is the
+// address register.  The second operand is the value of the alignment
+// specifier in bytes or zero if no explicit alignment.
+// Valid alignments depend on the specific instruction.
+
+//===--------------------------------------------------------------------===//
+// NEON Modified Immediates
+//===--------------------------------------------------------------------===//
+//
+// Several NEON instructions (e.g., VMOV) take a "modified immediate"
+// vector operand, where a small immediate encoded in the instruction
+// specifies a full NEON vector value.  These modified immediates are
+// represented here as encoded integers.  The low 8 bits hold the immediate
+// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
+// the "Cmode" field of the instruction.  The interfaces below treat the
+// Op and Cmode values as a single 5-bit value.
+
+static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val)
+{
+	return (OpCmode << 8) | Val;
+}
+static inline unsigned getNEONModImmOpCmode(unsigned ModImm)
+{
+	return (ModImm >> 8) & 0x1f;
+}
+static inline unsigned getNEONModImmVal(unsigned ModImm)
+{
+	return ModImm & 0xff;
+}
+
+/// decodeNEONModImm - Decode a NEON modified immediate value into the
+/// element value and the element size in bits.  (If the element size is
+/// smaller than the vector, it is splatted into all the elements.)
+static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits)
+{
+	unsigned OpCmode = getNEONModImmOpCmode(ModImm);
+	unsigned Imm8 = getNEONModImmVal(ModImm);
+	uint64_t Val = 0;
+	unsigned ByteNum;
+
+	if (OpCmode == 0xe) {
+		// 8-bit vector elements
+		Val = Imm8;
+		*EltBits = 8;
+	} else if ((OpCmode & 0xc) == 0x8) {
+		// 16-bit vector elements
+		ByteNum = (OpCmode & 0x6) >> 1;
+		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		*EltBits = 16;
+	} else if ((OpCmode & 0x8) == 0) {
+		// 32-bit vector elements, zero with one byte set
+		ByteNum = (OpCmode & 0x6) >> 1;
+		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		*EltBits = 32;
+	} else if ((OpCmode & 0xe) == 0xc) {
+		// 32-bit vector elements, one byte with low bits set
+		ByteNum = 1 + (OpCmode & 0x1);
+		Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
+		*EltBits = 32;
+	} else if (OpCmode == 0x1e) {
+		// 64-bit vector elements
+		for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
+			if ((ModImm >> ByteNum) & 1)
+				Val |= (uint64_t)0xff << (8 * ByteNum);
+		}
+		*EltBits = 64;
+	} else {
+		//llvm_unreachable("Unsupported NEON immediate");
+	}
+	return Val;
+}
+
+ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode);
+
+//===--------------------------------------------------------------------===//
+// Floating-point Immediates
+//
+static inline float getFPImmFloat(unsigned Imm)
+{
+	// We expect an 8-bit binary encoding of a floating-point number here.
+	union {
+		uint32_t I;
+		float F;
+	} FPUnion;
+
+	uint8_t Sign = (Imm >> 7) & 0x1;
+	uint8_t Exp = (Imm >> 4) & 0x7;
+	uint8_t Mantissa = Imm & 0xf;
+
+	//   8-bit FP    iEEEE Float Encoding
+	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
+	//
+	// where B = NOT(b);
+
+	FPUnion.I = 0;
+	FPUnion.I |= ((uint32_t) Sign) << 31;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	FPUnion.I |= (Exp & 0x3) << 23;
+	FPUnion.I |= Mantissa << 19;
+	return FPUnion.F;
+}
+
+#endif
+

arch/ARM/ARMBaseInfo.h

@@ -0,0 +1,432 @@
+//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone helper functions and enum definitions for
+// the ARM target useful for the compiler back-end and the MC libraries.
+// As such, it deliberately does not include references to LLVM core
+// code gen types, passes, etc..
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_ARMBASEINFO_H
+#define CS_ARMBASEINFO_H
+
+#include "capstone/arm.h"
+
+// Defines symbolic names for ARM registers.  This defines a mapping from
+// register name to register number.
+//
+#define GET_REGINFO_ENUM
+#include "ARMGenRegisterInfo.inc"
+
+// Enums corresponding to ARM condition codes
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+typedef enum ARMCC_CondCodes { // Meaning (integer)          Meaning (floating-point)
+	ARMCC_EQ,            // Equal                      Equal
+	ARMCC_NE,            // Not equal                  Not equal, or unordered
+	ARMCC_HS,            // Carry set                  >, ==, or unordered
+	ARMCC_LO,            // Carry clear                Less than
+	ARMCC_MI,            // Minus, negative            Less than
+	ARMCC_PL,            // Plus, positive or zero     >, ==, or unordered
+	ARMCC_VS,            // Overflow                   Unordered
+	ARMCC_VC,            // No overflow                Not unordered
+	ARMCC_HI,            // Unsigned higher            Greater than, or unordered
+	ARMCC_LS,            // Unsigned lower or same     Less than or equal
+	ARMCC_GE,            // Greater than or equal      Greater than or equal
+	ARMCC_LT,            // Less than                  Less than, or unordered
+	ARMCC_GT,            // Greater than               Greater than
+	ARMCC_LE,            // Less than or equal         <, ==, or unordered
+	ARMCC_AL             // Always (unconditional)     Always (unconditional)
+} ARMCC_CondCodes;
+
+inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
+{
+	switch (CC) {
+		case ARMCC_EQ: return ARMCC_NE;
+		case ARMCC_NE: return ARMCC_EQ;
+		case ARMCC_HS: return ARMCC_LO;
+		case ARMCC_LO: return ARMCC_HS;
+		case ARMCC_MI: return ARMCC_PL;
+		case ARMCC_PL: return ARMCC_MI;
+		case ARMCC_VS: return ARMCC_VC;
+		case ARMCC_VC: return ARMCC_VS;
+		case ARMCC_HI: return ARMCC_LS;
+		case ARMCC_LS: return ARMCC_HI;
+		case ARMCC_GE: return ARMCC_LT;
+		case ARMCC_LT: return ARMCC_GE;
+		case ARMCC_GT: return ARMCC_LE;
+		case ARMCC_LE: return ARMCC_GT;
+		default: return ARMCC_AL;
+	}
+}
+
+inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
+{
+	switch (CC) {
+		case ARMCC_EQ:  return "eq";
+		case ARMCC_NE:  return "ne";
+		case ARMCC_HS:  return "hs";
+		case ARMCC_LO:  return "lo";
+		case ARMCC_MI:  return "mi";
+		case ARMCC_PL:  return "pl";
+		case ARMCC_VS:  return "vs";
+		case ARMCC_VC:  return "vc";
+		case ARMCC_HI:  return "hi";
+		case ARMCC_LS:  return "ls";
+		case ARMCC_GE:  return "ge";
+		case ARMCC_LT:  return "lt";
+		case ARMCC_GT:  return "gt";
+		case ARMCC_LE:  return "le";
+		case ARMCC_AL:  return "al";
+		default: return "";
+	}
+}
+
+inline static const char *ARM_PROC_IFlagsToString(unsigned val)
+{
+	switch (val) {
+		case ARM_CPSFLAG_F: return "f";
+		case ARM_CPSFLAG_I: return "i";
+		case ARM_CPSFLAG_A: return "a";
+		default: return "";
+	}
+}
+
+inline static const char *ARM_PROC_IModToString(unsigned val)
+{
+	switch (val) {
+		case ARM_CPSMODE_IE: return "ie";
+		case ARM_CPSMODE_ID: return "id";
+		default: return "";
+	}
+}
+
+inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
+{
+	switch (val) {
+		default: return "BUGBUG";
+		case ARM_MB_SY:    return "sy";
+		case ARM_MB_ST:    return "st";
+		case ARM_MB_LD: return HasV8 ? "ld" : "#0xd";
+		case ARM_MB_RESERVED_12: return "#0xc";
+		case ARM_MB_ISH:   return "ish";
+		case ARM_MB_ISHST: return "ishst";
+		case ARM_MB_ISHLD: return HasV8 ?  "ishld" : "#0x9";
+		case ARM_MB_RESERVED_8: return "#0x8";
+		case ARM_MB_NSH:   return "nsh";
+		case ARM_MB_NSHST: return "nshst";
+		case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5";
+		case ARM_MB_RESERVED_4: return "#0x4";
+		case ARM_MB_OSH:   return "osh";
+		case ARM_MB_OSHST: return "oshst";
+		case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1";
+		case ARM_MB_RESERVED_0: return "#0x0";
+	}
+}
+
+enum ARM_ISB_InstSyncBOpt {
+    ARM_ISB_RESERVED_0 = 0,
+    ARM_ISB_RESERVED_1 = 1,
+    ARM_ISB_RESERVED_2 = 2,
+    ARM_ISB_RESERVED_3 = 3,
+    ARM_ISB_RESERVED_4 = 4,
+    ARM_ISB_RESERVED_5 = 5,
+    ARM_ISB_RESERVED_6 = 6,
+    ARM_ISB_RESERVED_7 = 7,
+    ARM_ISB_RESERVED_8 = 8,
+    ARM_ISB_RESERVED_9 = 9,
+    ARM_ISB_RESERVED_10 = 10,
+    ARM_ISB_RESERVED_11 = 11,
+    ARM_ISB_RESERVED_12 = 12,
+    ARM_ISB_RESERVED_13 = 13,
+    ARM_ISB_RESERVED_14 = 14,
+    ARM_ISB_SY = 15
+};
+
+inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
+{
+	switch (val) {
+		default: // never reach
+		case ARM_ISB_RESERVED_0:  return "#0x0";
+		case ARM_ISB_RESERVED_1:  return "#0x1";
+		case ARM_ISB_RESERVED_2:  return "#0x2";
+		case ARM_ISB_RESERVED_3:  return "#0x3";
+		case ARM_ISB_RESERVED_4:  return "#0x4";
+		case ARM_ISB_RESERVED_5:  return "#0x5";
+		case ARM_ISB_RESERVED_6:  return "#0x6";
+		case ARM_ISB_RESERVED_7:  return "#0x7";
+		case ARM_ISB_RESERVED_8:  return "#0x8";
+		case ARM_ISB_RESERVED_9:  return "#0x9";
+		case ARM_ISB_RESERVED_10: return "#0xa";
+		case ARM_ISB_RESERVED_11: return "#0xb";
+		case ARM_ISB_RESERVED_12: return "#0xc";
+		case ARM_ISB_RESERVED_13: return "#0xd";
+		case ARM_ISB_RESERVED_14: return "#0xe";
+		case ARM_ISB_SY:          return "sy";
+	}
+}
+
+/// isARMLowRegister - Returns true if the register is a low register (r0-r7).
+///
+static inline bool isARMLowRegister(unsigned Reg)
+{
+	//using namespace ARM;
+	switch (Reg) {
+		case ARM_R0:  case ARM_R1:  case ARM_R2:  case ARM_R3:
+		case ARM_R4:  case ARM_R5:  case ARM_R6:  case ARM_R7:
+			return true;
+		default:
+			return false;
+	}
+}
+
+/// ARMII - This namespace holds all of the target specific flags that
+/// instruction info tracks.
+///
+/// ARM Index Modes
+enum ARMII_IndexMode {
+	ARMII_IndexModeNone  = 0,
+	ARMII_IndexModePre   = 1,
+	ARMII_IndexModePost  = 2,
+	ARMII_IndexModeUpd   = 3
+};
+
+/// ARM Addressing Modes
+typedef enum ARMII_AddrMode {
+	ARMII_AddrModeNone    = 0,
+	ARMII_AddrMode1       = 1,
+	ARMII_AddrMode2       = 2,
+	ARMII_AddrMode3       = 3,
+	ARMII_AddrMode4       = 4,
+	ARMII_AddrMode5       = 5,
+	ARMII_AddrMode6       = 6,
+	ARMII_AddrModeT1_1    = 7,
+	ARMII_AddrModeT1_2    = 8,
+	ARMII_AddrModeT1_4    = 9,
+	ARMII_AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
+	ARMII_AddrModeT2_i12  = 11,
+	ARMII_AddrModeT2_i8   = 12,
+	ARMII_AddrModeT2_so   = 13,
+	ARMII_AddrModeT2_pc   = 14, // +/- i12 for pc relative data
+	ARMII_AddrModeT2_i8s4 = 15, // i8 * 4
+	ARMII_AddrMode_i12    = 16
+} ARMII_AddrMode;
+
+inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
+{
+	switch (addrmode) {
+		case ARMII_AddrModeNone:    return "AddrModeNone";
+		case ARMII_AddrMode1:       return "AddrMode1";
+		case ARMII_AddrMode2:       return "AddrMode2";
+		case ARMII_AddrMode3:       return "AddrMode3";
+		case ARMII_AddrMode4:       return "AddrMode4";
+		case ARMII_AddrMode5:       return "AddrMode5";
+		case ARMII_AddrMode6:       return "AddrMode6";
+		case ARMII_AddrModeT1_1:    return "AddrModeT1_1";
+		case ARMII_AddrModeT1_2:    return "AddrModeT1_2";
+		case ARMII_AddrModeT1_4:    return "AddrModeT1_4";
+		case ARMII_AddrModeT1_s:    return "AddrModeT1_s";
+		case ARMII_AddrModeT2_i12:  return "AddrModeT2_i12";
+		case ARMII_AddrModeT2_i8:   return "AddrModeT2_i8";
+		case ARMII_AddrModeT2_so:   return "AddrModeT2_so";
+		case ARMII_AddrModeT2_pc:   return "AddrModeT2_pc";
+		case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4";
+		case ARMII_AddrMode_i12:    return "AddrMode_i12";
+	}
+}
+
+/// Target Operand Flag enum.
+enum ARMII_TOF {
+	//===------------------------------------------------------------------===//
+	// ARM Specific MachineOperand flags.
+
+	ARMII_MO_NO_FLAG,
+
+	/// MO_LO16 - On a symbol operand, this represents a relocation containing
+	/// lower 16 bit of the address. Used only via movw instruction.
+	ARMII_MO_LO16,
+
+	/// MO_HI16 - On a symbol operand, this represents a relocation containing
+	/// higher 16 bit of the address. Used only via movt instruction.
+	ARMII_MO_HI16,
+
+	/// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+	/// i.e. "FOO$non_lazy_ptr".
+	/// Used only via movw instruction.
+	ARMII_MO_LO16_NONLAZY,
+
+	/// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+	/// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
+	ARMII_MO_HI16_NONLAZY,
+
+	/// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the PC relative address of the
+	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
+	/// Used only via movw instruction.
+	ARMII_MO_LO16_NONLAZY_PIC,
+
+	/// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+	/// relocation containing lower 16 bit of the PC relative address of the
+	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
+	/// Used only via movt instruction.
+	ARMII_MO_HI16_NONLAZY_PIC,
+
+	/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
+	/// call operand.
+	ARMII_MO_PLT
+};
+
+enum {
+	//===------------------------------------------------------------------===//
+	// Instruction Flags.
+
+	//===------------------------------------------------------------------===//
+	// This four-bit field describes the addressing mode used.
+	ARMII_AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
+
+	// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
+	// and store ops only.  Generic "updating" flag is used for ld/st multiple.
+	// The index mode enums are declared in ARMBaseInfo.h
+	ARMII_IndexModeShift = 5,
+	ARMII_IndexModeMask  = 3 << ARMII_IndexModeShift,
+
+	//===------------------------------------------------------------------===//
+	// Instruction encoding formats.
+	//
+	ARMII_FormShift     = 7,
+	ARMII_FormMask      = 0x3f << ARMII_FormShift,
+
+	// Pseudo instructions
+	ARMII_Pseudo        = 0  << ARMII_FormShift,
+
+	// Multiply instructions
+	ARMII_MulFrm        = 1  << ARMII_FormShift,
+
+	// Branch instructions
+	ARMII_BrFrm         = 2  << ARMII_FormShift,
+	ARMII_BrMiscFrm     = 3  << ARMII_FormShift,
+
+	// Data Processing instructions
+	ARMII_DPFrm         = 4  << ARMII_FormShift,
+	ARMII_DPSoRegFrm    = 5  << ARMII_FormShift,
+
+	// Load and Store
+	ARMII_LdFrm         = 6  << ARMII_FormShift,
+	ARMII_StFrm         = 7  << ARMII_FormShift,
+	ARMII_LdMiscFrm     = 8  << ARMII_FormShift,
+	ARMII_StMiscFrm     = 9  << ARMII_FormShift,
+	ARMII_LdStMulFrm    = 10 << ARMII_FormShift,
+
+	ARMII_LdStExFrm     = 11 << ARMII_FormShift,
+
+	// Miscellaneous arithmetic instructions
+	ARMII_ArithMiscFrm  = 12 << ARMII_FormShift,
+	ARMII_SatFrm        = 13 << ARMII_FormShift,
+
+	// Extend instructions
+	ARMII_ExtFrm        = 14 << ARMII_FormShift,
+
+	// VFP formats
+	ARMII_VFPUnaryFrm   = 15 << ARMII_FormShift,
+	ARMII_VFPBinaryFrm  = 16 << ARMII_FormShift,
+	ARMII_VFPConv1Frm   = 17 << ARMII_FormShift,
+	ARMII_VFPConv2Frm   = 18 << ARMII_FormShift,
+	ARMII_VFPConv3Frm   = 19 << ARMII_FormShift,
+	ARMII_VFPConv4Frm   = 20 << ARMII_FormShift,
+	ARMII_VFPConv5Frm   = 21 << ARMII_FormShift,
+	ARMII_VFPLdStFrm    = 22 << ARMII_FormShift,
+	ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
+	ARMII_VFPMiscFrm    = 24 << ARMII_FormShift,
+
+	// Thumb format
+	ARMII_ThumbFrm      = 25 << ARMII_FormShift,
+
+	// Miscelleaneous format
+	ARMII_MiscFrm       = 26 << ARMII_FormShift,
+
+	// NEON formats
+	ARMII_NGetLnFrm     = 27 << ARMII_FormShift,
+	ARMII_NSetLnFrm     = 28 << ARMII_FormShift,
+	ARMII_NDupFrm       = 29 << ARMII_FormShift,
+	ARMII_NLdStFrm      = 30 << ARMII_FormShift,
+	ARMII_N1RegModImmFrm= 31 << ARMII_FormShift,
+	ARMII_N2RegFrm      = 32 << ARMII_FormShift,
+	ARMII_NVCVTFrm      = 33 << ARMII_FormShift,
+	ARMII_NVDupLnFrm    = 34 << ARMII_FormShift,
+	ARMII_N2RegVShLFrm  = 35 << ARMII_FormShift,
+	ARMII_N2RegVShRFrm  = 36 << ARMII_FormShift,
+	ARMII_N3RegFrm      = 37 << ARMII_FormShift,
+	ARMII_N3RegVShFrm   = 38 << ARMII_FormShift,
+	ARMII_NVExtFrm      = 39 << ARMII_FormShift,
+	ARMII_NVMulSLFrm    = 40 << ARMII_FormShift,
+	ARMII_NVTBLFrm      = 41 << ARMII_FormShift,
+
+	//===------------------------------------------------------------------===//
+	// Misc flags.
+
+	// UnaryDP - Indicates this is a unary data processing instruction, i.e.
+	// it doesn't have a Rn operand.
+	ARMII_UnaryDP       = 1 << 13,
+
+	// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
+	// a 16-bit Thumb instruction if certain conditions are met.
+	ARMII_Xform16Bit    = 1 << 14,
+
+	// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
+	// instruction. Used by the parser to determine whether to require the 'S'
+	// suffix on the mnemonic (when not in an IT block) or preclude it (when
+	// in an IT block).
+	ARMII_ThumbArithFlagSetting = 1 << 18,
+
+	//===------------------------------------------------------------------===//
+	// Code domain.
+	ARMII_DomainShift   = 15,
+	ARMII_DomainMask    = 7 << ARMII_DomainShift,
+	ARMII_DomainGeneral = 0 << ARMII_DomainShift,
+	ARMII_DomainVFP     = 1 << ARMII_DomainShift,
+	ARMII_DomainNEON    = 2 << ARMII_DomainShift,
+	ARMII_DomainNEONA8  = 4 << ARMII_DomainShift,
+
+	//===------------------------------------------------------------------===//
+	// Field shifts - such shifts are used to set field while generating
+	// machine instructions.
+	//
+	// FIXME: This list will need adjusting/fixing as the MC code emitter
+	// takes shape and the ARMCodeEmitter.cpp bits go away.
+	ARMII_ShiftTypeShift = 4,
+
+	ARMII_M_BitShift     = 5,
+	ARMII_ShiftImmShift  = 5,
+	ARMII_ShiftShift     = 7,
+	ARMII_N_BitShift     = 7,
+	ARMII_ImmHiShift     = 8,
+	ARMII_SoRotImmShift  = 8,
+	ARMII_RegRsShift     = 8,
+	ARMII_ExtRotImmShift = 10,
+	ARMII_RegRdLoShift   = 12,
+	ARMII_RegRdShift     = 12,
+	ARMII_RegRdHiShift   = 16,
+	ARMII_RegRnShift     = 16,
+	ARMII_S_BitShift     = 20,
+	ARMII_W_BitShift     = 21,
+	ARMII_AM3_I_BitShift = 22,
+	ARMII_D_BitShift     = 22,
+	ARMII_U_BitShift     = 23,
+	ARMII_P_BitShift     = 24,
+	ARMII_I_BitShift     = 25,
+	ARMII_CondShift      = 28
+};
+
+#endif

arch/ARM/ARMDisassembler.h

@@ -0,0 +1,18 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_ARMDISASSEMBLER_H
+#define CS_ARMDISASSEMBLER_H
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+
+void ARM_init(MCRegisterInfo *MRI);
+
+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+uint64_t ARM_getFeatureBits(unsigned int mode);
+
+#endif

arch/ARM/ARMGenSubtargetInfo.inc

@@ -0,0 +1,72 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|*                                                                            *|
+|*Subtarget Enumeration Source Fragment                                       *|
+|*                                                                            *|
+|* Automatically generated file, do not edit!                                 *|
+|*                                                                            *|
+\*===----------------------------------------------------------------------===*/
+
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+#define ARM_FeatureAClass (1ULL << 0)
+#define ARM_FeatureAvoidMOVsShOp (1ULL << 1)
+#define ARM_FeatureAvoidPartialCPSR (1ULL << 2)
+#define ARM_FeatureCRC (1ULL << 3)
+#define ARM_FeatureCrypto (1ULL << 4)
+#define ARM_FeatureD16 (1ULL << 5)
+#define ARM_FeatureDB (1ULL << 6)
+#define ARM_FeatureDSPThumb2 (1ULL << 7)
+#define ARM_FeatureFP16 (1ULL << 8)
+#define ARM_FeatureFPARMv8 (1ULL << 9)
+#define ARM_FeatureHWDiv (1ULL << 10)
+#define ARM_FeatureHWDivARM (1ULL << 11)
+#define ARM_FeatureHasRAS (1ULL << 12)
+#define ARM_FeatureHasSlowFPVMLx (1ULL << 13)
+#define ARM_FeatureMClass (1ULL << 14)
+#define ARM_FeatureMP (1ULL << 15)
+#define ARM_FeatureNEON (1ULL << 16)
+#define ARM_FeatureNEONForFP (1ULL << 17)
+#define ARM_FeatureNaClTrap (1ULL << 18)
+#define ARM_FeatureNoARM (1ULL << 19)
+#define ARM_FeaturePerfMon (1ULL << 20)
+#define ARM_FeaturePref32BitThumb (1ULL << 21)
+#define ARM_FeatureRClass (1ULL << 22)
+#define ARM_FeatureSlowFPBrcc (1ULL << 23)
+#define ARM_FeatureT2XtPk (1ULL << 24)
+#define ARM_FeatureThumb2 (1ULL << 25)
+#define ARM_FeatureTrustZone (1ULL << 26)
+#define ARM_FeatureVFP2 (1ULL << 27)
+#define ARM_FeatureVFP3 (1ULL << 28)
+#define ARM_FeatureVFP4 (1ULL << 29)
+#define ARM_FeatureVFPOnlySP (1ULL << 30)
+#define ARM_FeatureVMLxForwarding (1ULL << 31)
+#define ARM_FeatureVirtualization (1ULL << 32)
+#define ARM_FeatureZCZeroing (1ULL << 33)
+#define ARM_HasV4TOps (1ULL << 34)
+#define ARM_HasV5TEOps (1ULL << 35)
+#define ARM_HasV5TOps (1ULL << 36)
+#define ARM_HasV6MOps (1ULL << 37)
+#define ARM_HasV6Ops (1ULL << 38)
+#define ARM_HasV6T2Ops (1ULL << 39)
+#define ARM_HasV7Ops (1ULL << 40)
+#define ARM_HasV8Ops (1ULL << 41)
+#define ARM_ModeThumb (1ULL << 42)
+#define ARM_ProcA5 (1ULL << 43)
+#define ARM_ProcA7 (1ULL << 44)
+#define ARM_ProcA8 (1ULL << 45)
+#define ARM_ProcA9 (1ULL << 46)
+#define ARM_ProcA12 (1ULL << 47)
+#define ARM_ProcA15 (1ULL << 48)
+#define ARM_ProcA17 (1ULL << 49)
+#define ARM_ProcA53 (1ULL << 50)
+#define ARM_ProcA57 (1ULL << 51)
+#define ARM_ProcKrait (1ULL << 52)
+#define ARM_ProcR5 (1ULL << 53)
+#define ARM_ProcSwift (1ULL << 54)
+
+#endif // GET_SUBTARGETINFO_ENUM

arch/ARM/ARMInstPrinter.h

@@ -0,0 +1,43 @@
+//===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an ARM MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_ARMINSTPRINTER_H
+#define CS_ARMINSTPRINTER_H
+
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+
+void ARM_printInst(MCInst *MI, SStream *O, void *Info);
+void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci);
+
+// setup handle->get_regname
+void ARM_getRegName(cs_struct *handle, int value);
+
+// specify vector data type for vector instructions
+void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd);
+
+void ARM_addVectorDataSize(MCInst *MI, int size);
+
+void ARM_addReg(MCInst *MI, int reg);
+
+// load usermode registers (LDM, STM)
+void ARM_addUserMode(MCInst *MI);
+
+// sysreg for MRS/MSR
+void ARM_addSysReg(MCInst *MI, arm_sysreg reg);
+
+#endif

arch/ARM/ARMMapping.c

@@ -0,0 +1,952 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef CAPSTONE_HAS_ARM
+
+#include <stdio.h>	// debug
+#include <string.h>
+
+#include "../../cs_priv.h"
+
+#include "ARMMapping.h"
+
+#define GET_INSTRINFO_ENUM
+#include "ARMGenInstrInfo.inc"
+
+#ifndef CAPSTONE_DIET
+static const name_map reg_name_maps[] = {
+	{ ARM_REG_INVALID, NULL },
+	{ ARM_REG_APSR, "apsr"},
+	{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
+	{ ARM_REG_CPSR, "cpsr"},
+	{ ARM_REG_FPEXC, "fpexc"},
+	{ ARM_REG_FPINST, "fpinst"},
+	{ ARM_REG_FPSCR, "fpscr"},
+	{ ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
+	{ ARM_REG_FPSID, "fpsid"},
+	{ ARM_REG_ITSTATE, "itstate"},
+	{ ARM_REG_LR, "lr"},
+	{ ARM_REG_PC, "pc"},
+	{ ARM_REG_SP, "sp"},
+	{ ARM_REG_SPSR, "spsr"},
+	{ ARM_REG_D0, "d0"},
+	{ ARM_REG_D1, "d1"},
+	{ ARM_REG_D2, "d2"},
+	{ ARM_REG_D3, "d3"},
+	{ ARM_REG_D4, "d4"},
+	{ ARM_REG_D5, "d5"},
+	{ ARM_REG_D6, "d6"},
+	{ ARM_REG_D7, "d7"},
+	{ ARM_REG_D8, "d8"},
+	{ ARM_REG_D9, "d9"},
+	{ ARM_REG_D10, "d10"},
+	{ ARM_REG_D11, "d11"},
+	{ ARM_REG_D12, "d12"},
+	{ ARM_REG_D13, "d13"},
+	{ ARM_REG_D14, "d14"},
+	{ ARM_REG_D15, "d15"},
+	{ ARM_REG_D16, "d16"},
+	{ ARM_REG_D17, "d17"},
+	{ ARM_REG_D18, "d18"},
+	{ ARM_REG_D19, "d19"},
+	{ ARM_REG_D20, "d20"},
+	{ ARM_REG_D21, "d21"},
+	{ ARM_REG_D22, "d22"},
+	{ ARM_REG_D23, "d23"},
+	{ ARM_REG_D24, "d24"},
+	{ ARM_REG_D25, "d25"},
+	{ ARM_REG_D26, "d26"},
+	{ ARM_REG_D27, "d27"},
+	{ ARM_REG_D28, "d28"},
+	{ ARM_REG_D29, "d29"},
+	{ ARM_REG_D30, "d30"},
+	{ ARM_REG_D31, "d31"},
+	{ ARM_REG_FPINST2, "fpinst2"},
+	{ ARM_REG_MVFR0, "mvfr0"},
+	{ ARM_REG_MVFR1, "mvfr1"},
+	{ ARM_REG_MVFR2, "mvfr2"},
+	{ ARM_REG_Q0, "q0"},
+	{ ARM_REG_Q1, "q1"},
+	{ ARM_REG_Q2, "q2"},
+	{ ARM_REG_Q3, "q3"},
+	{ ARM_REG_Q4, "q4"},
+	{ ARM_REG_Q5, "q5"},
+	{ ARM_REG_Q6, "q6"},
+	{ ARM_REG_Q7, "q7"},
+	{ ARM_REG_Q8, "q8"},
+	{ ARM_REG_Q9, "q9"},
+	{ ARM_REG_Q10, "q10"},
+	{ ARM_REG_Q11, "q11"},
+	{ ARM_REG_Q12, "q12"},
+	{ ARM_REG_Q13, "q13"},
+	{ ARM_REG_Q14, "q14"},
+	{ ARM_REG_Q15, "q15"},
+	{ ARM_REG_R0, "r0"},
+	{ ARM_REG_R1, "r1"},
+	{ ARM_REG_R2, "r2"},
+	{ ARM_REG_R3, "r3"},
+	{ ARM_REG_R4, "r4"},
+	{ ARM_REG_R5, "r5"},
+	{ ARM_REG_R6, "r6"},
+	{ ARM_REG_R7, "r7"},
+	{ ARM_REG_R8, "r8"},
+	{ ARM_REG_R9, "sb"},
+	{ ARM_REG_R10, "sl"},
+	{ ARM_REG_R11, "fp"},
+	{ ARM_REG_R12, "ip"},
+	{ ARM_REG_S0, "s0"},
+	{ ARM_REG_S1, "s1"},
+	{ ARM_REG_S2, "s2"},
+	{ ARM_REG_S3, "s3"},
+	{ ARM_REG_S4, "s4"},
+	{ ARM_REG_S5, "s5"},
+	{ ARM_REG_S6, "s6"},
+	{ ARM_REG_S7, "s7"},
+	{ ARM_REG_S8, "s8"},
+	{ ARM_REG_S9, "s9"},
+	{ ARM_REG_S10, "s10"},
+	{ ARM_REG_S11, "s11"},
+	{ ARM_REG_S12, "s12"},
+	{ ARM_REG_S13, "s13"},
+	{ ARM_REG_S14, "s14"},
+	{ ARM_REG_S15, "s15"},
+	{ ARM_REG_S16, "s16"},
+	{ ARM_REG_S17, "s17"},
+	{ ARM_REG_S18, "s18"},
+	{ ARM_REG_S19, "s19"},
+	{ ARM_REG_S20, "s20"},
+	{ ARM_REG_S21, "s21"},
+	{ ARM_REG_S22, "s22"},
+	{ ARM_REG_S23, "s23"},
+	{ ARM_REG_S24, "s24"},
+	{ ARM_REG_S25, "s25"},
+	{ ARM_REG_S26, "s26"},
+	{ ARM_REG_S27, "s27"},
+	{ ARM_REG_S28, "s28"},
+	{ ARM_REG_S29, "s29"},
+	{ ARM_REG_S30, "s30"},
+	{ ARM_REG_S31, "s31"},
+};
+static const name_map reg_name_maps2[] = {
+	{ ARM_REG_INVALID, NULL },
+	{ ARM_REG_APSR, "apsr"},
+	{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
+	{ ARM_REG_CPSR, "cpsr"},
+	{ ARM_REG_FPEXC, "fpexc"},
+	{ ARM_REG_FPINST, "fpinst"},
+	{ ARM_REG_FPSCR, "fpscr"},
+	{ ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
+	{ ARM_REG_FPSID, "fpsid"},
+	{ ARM_REG_ITSTATE, "itstate"},
+	{ ARM_REG_LR, "lr"},
+	{ ARM_REG_PC, "pc"},
+	{ ARM_REG_SP, "sp"},
+	{ ARM_REG_SPSR, "spsr"},
+	{ ARM_REG_D0, "d0"},
+	{ ARM_REG_D1, "d1"},
+	{ ARM_REG_D2, "d2"},
+	{ ARM_REG_D3, "d3"},
+	{ ARM_REG_D4, "d4"},
+	{ ARM_REG_D5, "d5"},
+	{ ARM_REG_D6, "d6"},
+	{ ARM_REG_D7, "d7"},
+	{ ARM_REG_D8, "d8"},
+	{ ARM_REG_D9, "d9"},
+	{ ARM_REG_D10, "d10"},
+	{ ARM_REG_D11, "d11"},
+	{ ARM_REG_D12, "d12"},
+	{ ARM_REG_D13, "d13"},
+	{ ARM_REG_D14, "d14"},
+	{ ARM_REG_D15, "d15"},
+	{ ARM_REG_D16, "d16"},
+	{ ARM_REG_D17, "d17"},
+	{ ARM_REG_D18, "d18"},
+	{ ARM_REG_D19, "d19"},
+	{ ARM_REG_D20, "d20"},
+	{ ARM_REG_D21, "d21"},
+	{ ARM_REG_D22, "d22"},
+	{ ARM_REG_D23, "d23"},
+	{ ARM_REG_D24, "d24"},
+	{ ARM_REG_D25, "d25"},
+	{ ARM_REG_D26, "d26"},
+	{ ARM_REG_D27, "d27"},
+	{ ARM_REG_D28, "d28"},
+	{ ARM_REG_D29, "d29"},
+	{ ARM_REG_D30, "d30"},
+	{ ARM_REG_D31, "d31"},
+	{ ARM_REG_FPINST2, "fpinst2"},
+	{ ARM_REG_MVFR0, "mvfr0"},
+	{ ARM_REG_MVFR1, "mvfr1"},
+	{ ARM_REG_MVFR2, "mvfr2"},
+	{ ARM_REG_Q0, "q0"},
+	{ ARM_REG_Q1, "q1"},
+	{ ARM_REG_Q2, "q2"},
+	{ ARM_REG_Q3, "q3"},
+	{ ARM_REG_Q4, "q4"},
+	{ ARM_REG_Q5, "q5"},
+	{ ARM_REG_Q6, "q6"},
+	{ ARM_REG_Q7, "q7"},
+	{ ARM_REG_Q8, "q8"},
+	{ ARM_REG_Q9, "q9"},
+	{ ARM_REG_Q10, "q10"},
+	{ ARM_REG_Q11, "q11"},
+	{ ARM_REG_Q12, "q12"},
+	{ ARM_REG_Q13, "q13"},
+	{ ARM_REG_Q14, "q14"},
+	{ ARM_REG_Q15, "q15"},
+	{ ARM_REG_R0, "r0"},
+	{ ARM_REG_R1, "r1"},
+	{ ARM_REG_R2, "r2"},
+	{ ARM_REG_R3, "r3"},
+	{ ARM_REG_R4, "r4"},
+	{ ARM_REG_R5, "r5"},
+	{ ARM_REG_R6, "r6"},
+	{ ARM_REG_R7, "r7"},
+	{ ARM_REG_R8, "r8"},
+	{ ARM_REG_R9, "r9"},
+	{ ARM_REG_R10, "r10"},
+	{ ARM_REG_R11, "r11"},
+	{ ARM_REG_R12, "r12"},
+	{ ARM_REG_S0, "s0"},
+	{ ARM_REG_S1, "s1"},
+	{ ARM_REG_S2, "s2"},
+	{ ARM_REG_S3, "s3"},
+	{ ARM_REG_S4, "s4"},
+	{ ARM_REG_S5, "s5"},
+	{ ARM_REG_S6, "s6"},
+	{ ARM_REG_S7, "s7"},
+	{ ARM_REG_S8, "s8"},
+	{ ARM_REG_S9, "s9"},
+	{ ARM_REG_S10, "s10"},
+	{ ARM_REG_S11, "s11"},
+	{ ARM_REG_S12, "s12"},
+	{ ARM_REG_S13, "s13"},
+	{ ARM_REG_S14, "s14"},
+	{ ARM_REG_S15, "s15"},
+	{ ARM_REG_S16, "s16"},
+	{ ARM_REG_S17, "s17"},
+	{ ARM_REG_S18, "s18"},
+	{ ARM_REG_S19, "s19"},
+	{ ARM_REG_S20, "s20"},
+	{ ARM_REG_S21, "s21"},
+	{ ARM_REG_S22, "s22"},
+	{ ARM_REG_S23, "s23"},
+	{ ARM_REG_S24, "s24"},
+	{ ARM_REG_S25, "s25"},
+	{ ARM_REG_S26, "s26"},
+	{ ARM_REG_S27, "s27"},
+	{ ARM_REG_S28, "s28"},
+	{ ARM_REG_S29, "s29"},
+	{ ARM_REG_S30, "s30"},
+	{ ARM_REG_S31, "s31"},
+};
+#endif
+
+const char *ARM_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (reg >= ARR_SIZE(reg_name_maps))
+		return NULL;
+
+	return reg_name_maps[reg].name;
+#else
+	return NULL;
+#endif
+}
+
+const char *ARM_reg_name2(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	if (reg >= ARR_SIZE(reg_name_maps2))
+		return NULL;
+
+	return reg_name_maps2[reg].name;
+#else
+	return NULL;
+#endif
+}
+
+static const insn_map insns[] = {
+	// dummy item
+	{
+		0, 0,
+#ifndef CAPSTONE_DIET
+		{ 0 }, { 0 }, { 0 }, 0, 0
+#endif
+	},
+
+#include "ARMMappingInsn.inc"
+};
+
+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	//printf(">> id = %u\n", id);
+	if (i != 0) {
+		insn->id = insns[i].mapid;
+
+		if (h->detail) {
+#ifndef CAPSTONE_DIET
+			cs_struct handle;
+			handle.detail = h->detail;
+
+			memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
+			insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
+
+			memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
+			insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
+
+			memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
+			insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
+
+			insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR);
+
+			if (insns[i].branch || insns[i].indirect_branch) {
+				// this insn also belongs to JUMP group. add JUMP group
+				insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP;
+				insn->detail->groups_count++;
+			}
+#endif
+		}
+	}
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map insn_name_maps[] = {
+	{ ARM_INS_INVALID, NULL },
+
+	{ ARM_INS_ADC, "adc" },
+	{ ARM_INS_ADD, "add" },
+	{ ARM_INS_ADR, "adr" },
+	{ ARM_INS_AESD, "aesd" },
+	{ ARM_INS_AESE, "aese" },
+	{ ARM_INS_AESIMC, "aesimc" },
+	{ ARM_INS_AESMC, "aesmc" },
+	{ ARM_INS_AND, "and" },
+	{ ARM_INS_BFC, "bfc" },
+	{ ARM_INS_BFI, "bfi" },
+	{ ARM_INS_BIC, "bic" },
+	{ ARM_INS_BKPT, "bkpt" },
+	{ ARM_INS_BL, "bl" },
+	{ ARM_INS_BLX, "blx" },
+	{ ARM_INS_BX, "bx" },
+	{ ARM_INS_BXJ, "bxj" },
+	{ ARM_INS_B, "b" },
+	{ ARM_INS_CDP, "cdp" },
+	{ ARM_INS_CDP2, "cdp2" },
+	{ ARM_INS_CLREX, "clrex" },
+	{ ARM_INS_CLZ, "clz" },
+	{ ARM_INS_CMN, "cmn" },
+	{ ARM_INS_CMP, "cmp" },
+	{ ARM_INS_CPS, "cps" },
+	{ ARM_INS_CRC32B, "crc32b" },
+	{ ARM_INS_CRC32CB, "crc32cb" },
+	{ ARM_INS_CRC32CH, "crc32ch" },
+	{ ARM_INS_CRC32CW, "crc32cw" },
+	{ ARM_INS_CRC32H, "crc32h" },
+	{ ARM_INS_CRC32W, "crc32w" },
+	{ ARM_INS_DBG, "dbg" },
+	{ ARM_INS_DMB, "dmb" },
+	{ ARM_INS_DSB, "dsb" },
+	{ ARM_INS_EOR, "eor" },
+	{ ARM_INS_ERET, "eret" },
+	{ ARM_INS_VMOV, "vmov" },
+	{ ARM_INS_FLDMDBX, "fldmdbx" },
+	{ ARM_INS_FLDMIAX, "fldmiax" },
+	{ ARM_INS_VMRS, "vmrs" },
+	{ ARM_INS_FSTMDBX, "fstmdbx" },
+	{ ARM_INS_FSTMIAX, "fstmiax" },
+	{ ARM_INS_HINT, "hint" },
+	{ ARM_INS_HLT, "hlt" },
+	{ ARM_INS_HVC, "hvc" },
+	{ ARM_INS_ISB, "isb" },
+	{ ARM_INS_LDA, "lda" },
+	{ ARM_INS_LDAB, "ldab" },
+	{ ARM_INS_LDAEX, "ldaex" },
+	{ ARM_INS_LDAEXB, "ldaexb" },
+	{ ARM_INS_LDAEXD, "ldaexd" },
+	{ ARM_INS_LDAEXH, "ldaexh" },
+	{ ARM_INS_LDAH, "ldah" },
+	{ ARM_INS_LDC2L, "ldc2l" },
+	{ ARM_INS_LDC2, "ldc2" },
+	{ ARM_INS_LDCL, "ldcl" },
+	{ ARM_INS_LDC, "ldc" },
+	{ ARM_INS_LDMDA, "ldmda" },
+	{ ARM_INS_LDMDB, "ldmdb" },
+	{ ARM_INS_LDM, "ldm" },
+	{ ARM_INS_LDMIB, "ldmib" },
+	{ ARM_INS_LDRBT, "ldrbt" },
+	{ ARM_INS_LDRB, "ldrb" },
+	{ ARM_INS_LDRD, "ldrd" },
+	{ ARM_INS_LDREX, "ldrex" },
+	{ ARM_INS_LDREXB, "ldrexb" },
+	{ ARM_INS_LDREXD, "ldrexd" },
+	{ ARM_INS_LDREXH, "ldrexh" },
+	{ ARM_INS_LDRH, "ldrh" },
+	{ ARM_INS_LDRHT, "ldrht" },
+	{ ARM_INS_LDRSB, "ldrsb" },
+	{ ARM_INS_LDRSBT, "ldrsbt" },
+	{ ARM_INS_LDRSH, "ldrsh" },
+	{ ARM_INS_LDRSHT, "ldrsht" },
+	{ ARM_INS_LDRT, "ldrt" },
+	{ ARM_INS_LDR, "ldr" },
+	{ ARM_INS_MCR, "mcr" },
+	{ ARM_INS_MCR2, "mcr2" },
+	{ ARM_INS_MCRR, "mcrr" },
+	{ ARM_INS_MCRR2, "mcrr2" },
+	{ ARM_INS_MLA, "mla" },
+	{ ARM_INS_MLS, "mls" },
+	{ ARM_INS_MOV, "mov" },
+	{ ARM_INS_MOVT, "movt" },
+	{ ARM_INS_MOVW, "movw" },
+	{ ARM_INS_MRC, "mrc" },
+	{ ARM_INS_MRC2, "mrc2" },
+	{ ARM_INS_MRRC, "mrrc" },
+	{ ARM_INS_MRRC2, "mrrc2" },
+	{ ARM_INS_MRS, "mrs" },
+	{ ARM_INS_MSR, "msr" },
+	{ ARM_INS_MUL, "mul" },
+	{ ARM_INS_MVN, "mvn" },
+	{ ARM_INS_ORR, "orr" },
+	{ ARM_INS_PKHBT, "pkhbt" },
+	{ ARM_INS_PKHTB, "pkhtb" },
+	{ ARM_INS_PLDW, "pldw" },
+	{ ARM_INS_PLD, "pld" },
+	{ ARM_INS_PLI, "pli" },
+	{ ARM_INS_QADD, "qadd" },
+	{ ARM_INS_QADD16, "qadd16" },
+	{ ARM_INS_QADD8, "qadd8" },
+	{ ARM_INS_QASX, "qasx" },
+	{ ARM_INS_QDADD, "qdadd" },
+	{ ARM_INS_QDSUB, "qdsub" },
+	{ ARM_INS_QSAX, "qsax" },
+	{ ARM_INS_QSUB, "qsub" },
+	{ ARM_INS_QSUB16, "qsub16" },
+	{ ARM_INS_QSUB8, "qsub8" },
+	{ ARM_INS_RBIT, "rbit" },
+	{ ARM_INS_REV, "rev" },
+	{ ARM_INS_REV16, "rev16" },
+	{ ARM_INS_REVSH, "revsh" },
+	{ ARM_INS_RFEDA, "rfeda" },
+	{ ARM_INS_RFEDB, "rfedb" },
+	{ ARM_INS_RFEIA, "rfeia" },
+	{ ARM_INS_RFEIB, "rfeib" },
+	{ ARM_INS_RSB, "rsb" },
+	{ ARM_INS_RSC, "rsc" },
+	{ ARM_INS_SADD16, "sadd16" },
+	{ ARM_INS_SADD8, "sadd8" },
+	{ ARM_INS_SASX, "sasx" },
+	{ ARM_INS_SBC, "sbc" },
+	{ ARM_INS_SBFX, "sbfx" },
+	{ ARM_INS_SDIV, "sdiv" },
+	{ ARM_INS_SEL, "sel" },
+	{ ARM_INS_SETEND, "setend" },
+	{ ARM_INS_SHA1C, "sha1c" },
+	{ ARM_INS_SHA1H, "sha1h" },
+	{ ARM_INS_SHA1M, "sha1m" },
+	{ ARM_INS_SHA1P, "sha1p" },
+	{ ARM_INS_SHA1SU0, "sha1su0" },
+	{ ARM_INS_SHA1SU1, "sha1su1" },
+	{ ARM_INS_SHA256H, "sha256h" },
+	{ ARM_INS_SHA256H2, "sha256h2" },
+	{ ARM_INS_SHA256SU0, "sha256su0" },
+	{ ARM_INS_SHA256SU1, "sha256su1" },
+	{ ARM_INS_SHADD16, "shadd16" },
+	{ ARM_INS_SHADD8, "shadd8" },
+	{ ARM_INS_SHASX, "shasx" },
+	{ ARM_INS_SHSAX, "shsax" },
+	{ ARM_INS_SHSUB16, "shsub16" },
+	{ ARM_INS_SHSUB8, "shsub8" },
+	{ ARM_INS_SMC, "smc" },
+	{ ARM_INS_SMLABB, "smlabb" },
+	{ ARM_INS_SMLABT, "smlabt" },
+	{ ARM_INS_SMLAD, "smlad" },
+	{ ARM_INS_SMLADX, "smladx" },
+	{ ARM_INS_SMLAL, "smlal" },
+	{ ARM_INS_SMLALBB, "smlalbb" },
+	{ ARM_INS_SMLALBT, "smlalbt" },
+	{ ARM_INS_SMLALD, "smlald" },
+	{ ARM_INS_SMLALDX, "smlaldx" },
+	{ ARM_INS_SMLALTB, "smlaltb" },
+	{ ARM_INS_SMLALTT, "smlaltt" },
+	{ ARM_INS_SMLATB, "smlatb" },
+	{ ARM_INS_SMLATT, "smlatt" },
+	{ ARM_INS_SMLAWB, "smlawb" },
+	{ ARM_INS_SMLAWT, "smlawt" },
+	{ ARM_INS_SMLSD, "smlsd" },
+	{ ARM_INS_SMLSDX, "smlsdx" },
+	{ ARM_INS_SMLSLD, "smlsld" },
+	{ ARM_INS_SMLSLDX, "smlsldx" },
+	{ ARM_INS_SMMLA, "smmla" },
+	{ ARM_INS_SMMLAR, "smmlar" },
+	{ ARM_INS_SMMLS, "smmls" },
+	{ ARM_INS_SMMLSR, "smmlsr" },
+	{ ARM_INS_SMMUL, "smmul" },
+	{ ARM_INS_SMMULR, "smmulr" },
+	{ ARM_INS_SMUAD, "smuad" },
+	{ ARM_INS_SMUADX, "smuadx" },
+	{ ARM_INS_SMULBB, "smulbb" },
+	{ ARM_INS_SMULBT, "smulbt" },
+	{ ARM_INS_SMULL, "smull" },
+	{ ARM_INS_SMULTB, "smultb" },
+	{ ARM_INS_SMULTT, "smultt" },
+	{ ARM_INS_SMULWB, "smulwb" },
+	{ ARM_INS_SMULWT, "smulwt" },
+	{ ARM_INS_SMUSD, "smusd" },
+	{ ARM_INS_SMUSDX, "smusdx" },
+	{ ARM_INS_SRSDA, "srsda" },
+	{ ARM_INS_SRSDB, "srsdb" },
+	{ ARM_INS_SRSIA, "srsia" },
+	{ ARM_INS_SRSIB, "srsib" },
+	{ ARM_INS_SSAT, "ssat" },
+	{ ARM_INS_SSAT16, "ssat16" },
+	{ ARM_INS_SSAX, "ssax" },
+	{ ARM_INS_SSUB16, "ssub16" },
+	{ ARM_INS_SSUB8, "ssub8" },
+	{ ARM_INS_STC2L, "stc2l" },
+	{ ARM_INS_STC2, "stc2" },
+	{ ARM_INS_STCL, "stcl" },
+	{ ARM_INS_STC, "stc" },
+	{ ARM_INS_STL, "stl" },
+	{ ARM_INS_STLB, "stlb" },
+	{ ARM_INS_STLEX, "stlex" },
+	{ ARM_INS_STLEXB, "stlexb" },
+	{ ARM_INS_STLEXD, "stlexd" },
+	{ ARM_INS_STLEXH, "stlexh" },
+	{ ARM_INS_STLH, "stlh" },
+	{ ARM_INS_STMDA, "stmda" },
+	{ ARM_INS_STMDB, "stmdb" },
+	{ ARM_INS_STM, "stm" },
+	{ ARM_INS_STMIB, "stmib" },
+	{ ARM_INS_STRBT, "strbt" },
+	{ ARM_INS_STRB, "strb" },
+	{ ARM_INS_STRD, "strd" },
+	{ ARM_INS_STREX, "strex" },
+	{ ARM_INS_STREXB, "strexb" },
+	{ ARM_INS_STREXD, "strexd" },
+	{ ARM_INS_STREXH, "strexh" },
+	{ ARM_INS_STRH, "strh" },
+	{ ARM_INS_STRHT, "strht" },
+	{ ARM_INS_STRT, "strt" },
+	{ ARM_INS_STR, "str" },
+	{ ARM_INS_SUB, "sub" },
+	{ ARM_INS_SVC, "svc" },
+	{ ARM_INS_SWP, "swp" },
+	{ ARM_INS_SWPB, "swpb" },
+	{ ARM_INS_SXTAB, "sxtab" },
+	{ ARM_INS_SXTAB16, "sxtab16" },
+	{ ARM_INS_SXTAH, "sxtah" },
+	{ ARM_INS_SXTB, "sxtb" },
+	{ ARM_INS_SXTB16, "sxtb16" },
+	{ ARM_INS_SXTH, "sxth" },
+	{ ARM_INS_TEQ, "teq" },
+	{ ARM_INS_TRAP, "trap" },
+	{ ARM_INS_TST, "tst" },
+	{ ARM_INS_UADD16, "uadd16" },
+	{ ARM_INS_UADD8, "uadd8" },
+	{ ARM_INS_UASX, "uasx" },
+	{ ARM_INS_UBFX, "ubfx" },
+	{ ARM_INS_UDF, "udf" },
+	{ ARM_INS_UDIV, "udiv" },
+	{ ARM_INS_UHADD16, "uhadd16" },
+	{ ARM_INS_UHADD8, "uhadd8" },
+	{ ARM_INS_UHASX, "uhasx" },
+	{ ARM_INS_UHSAX, "uhsax" },
+	{ ARM_INS_UHSUB16, "uhsub16" },
+	{ ARM_INS_UHSUB8, "uhsub8" },
+	{ ARM_INS_UMAAL, "umaal" },
+	{ ARM_INS_UMLAL, "umlal" },
+	{ ARM_INS_UMULL, "umull" },
+	{ ARM_INS_UQADD16, "uqadd16" },
+	{ ARM_INS_UQADD8, "uqadd8" },
+	{ ARM_INS_UQASX, "uqasx" },
+	{ ARM_INS_UQSAX, "uqsax" },
+	{ ARM_INS_UQSUB16, "uqsub16" },
+	{ ARM_INS_UQSUB8, "uqsub8" },
+	{ ARM_INS_USAD8, "usad8" },
+	{ ARM_INS_USADA8, "usada8" },
+	{ ARM_INS_USAT, "usat" },
+	{ ARM_INS_USAT16, "usat16" },
+	{ ARM_INS_USAX, "usax" },
+	{ ARM_INS_USUB16, "usub16" },
+	{ ARM_INS_USUB8, "usub8" },
+	{ ARM_INS_UXTAB, "uxtab" },
+	{ ARM_INS_UXTAB16, "uxtab16" },
+	{ ARM_INS_UXTAH, "uxtah" },
+	{ ARM_INS_UXTB, "uxtb" },
+	{ ARM_INS_UXTB16, "uxtb16" },
+	{ ARM_INS_UXTH, "uxth" },
+	{ ARM_INS_VABAL, "vabal" },
+	{ ARM_INS_VABA, "vaba" },
+	{ ARM_INS_VABDL, "vabdl" },
+	{ ARM_INS_VABD, "vabd" },
+	{ ARM_INS_VABS, "vabs" },
+	{ ARM_INS_VACGE, "vacge" },
+	{ ARM_INS_VACGT, "vacgt" },
+	{ ARM_INS_VADD, "vadd" },
+	{ ARM_INS_VADDHN, "vaddhn" },
+	{ ARM_INS_VADDL, "vaddl" },
+	{ ARM_INS_VADDW, "vaddw" },
+	{ ARM_INS_VAND, "vand" },
+	{ ARM_INS_VBIC, "vbic" },
+	{ ARM_INS_VBIF, "vbif" },
+	{ ARM_INS_VBIT, "vbit" },
+	{ ARM_INS_VBSL, "vbsl" },
+	{ ARM_INS_VCEQ, "vceq" },
+	{ ARM_INS_VCGE, "vcge" },
+	{ ARM_INS_VCGT, "vcgt" },
+	{ ARM_INS_VCLE, "vcle" },
+	{ ARM_INS_VCLS, "vcls" },
+	{ ARM_INS_VCLT, "vclt" },
+	{ ARM_INS_VCLZ, "vclz" },
+	{ ARM_INS_VCMP, "vcmp" },
+	{ ARM_INS_VCMPE, "vcmpe" },
+	{ ARM_INS_VCNT, "vcnt" },
+	{ ARM_INS_VCVTA, "vcvta" },
+	{ ARM_INS_VCVTB, "vcvtb" },
+	{ ARM_INS_VCVT, "vcvt" },
+	{ ARM_INS_VCVTM, "vcvtm" },
+	{ ARM_INS_VCVTN, "vcvtn" },
+	{ ARM_INS_VCVTP, "vcvtp" },
+	{ ARM_INS_VCVTT, "vcvtt" },
+	{ ARM_INS_VDIV, "vdiv" },
+	{ ARM_INS_VDUP, "vdup" },
+	{ ARM_INS_VEOR, "veor" },
+	{ ARM_INS_VEXT, "vext" },
+	{ ARM_INS_VFMA, "vfma" },
+	{ ARM_INS_VFMS, "vfms" },
+	{ ARM_INS_VFNMA, "vfnma" },
+	{ ARM_INS_VFNMS, "vfnms" },
+	{ ARM_INS_VHADD, "vhadd" },
+	{ ARM_INS_VHSUB, "vhsub" },
+	{ ARM_INS_VLD1, "vld1" },
+	{ ARM_INS_VLD2, "vld2" },
+	{ ARM_INS_VLD3, "vld3" },
+	{ ARM_INS_VLD4, "vld4" },
+	{ ARM_INS_VLDMDB, "vldmdb" },
+	{ ARM_INS_VLDMIA, "vldmia" },
+	{ ARM_INS_VLDR, "vldr" },
+	{ ARM_INS_VMAXNM, "vmaxnm" },
+	{ ARM_INS_VMAX, "vmax" },
+	{ ARM_INS_VMINNM, "vminnm" },
+	{ ARM_INS_VMIN, "vmin" },
+	{ ARM_INS_VMLA, "vmla" },
+	{ ARM_INS_VMLAL, "vmlal" },
+	{ ARM_INS_VMLS, "vmls" },
+	{ ARM_INS_VMLSL, "vmlsl" },
+	{ ARM_INS_VMOVL, "vmovl" },
+	{ ARM_INS_VMOVN, "vmovn" },
+	{ ARM_INS_VMSR, "vmsr" },
+	{ ARM_INS_VMUL, "vmul" },
+	{ ARM_INS_VMULL, "vmull" },
+	{ ARM_INS_VMVN, "vmvn" },
+	{ ARM_INS_VNEG, "vneg" },
+	{ ARM_INS_VNMLA, "vnmla" },
+	{ ARM_INS_VNMLS, "vnmls" },
+	{ ARM_INS_VNMUL, "vnmul" },
+	{ ARM_INS_VORN, "vorn" },
+	{ ARM_INS_VORR, "vorr" },
+	{ ARM_INS_VPADAL, "vpadal" },
+	{ ARM_INS_VPADDL, "vpaddl" },
+	{ ARM_INS_VPADD, "vpadd" },
+	{ ARM_INS_VPMAX, "vpmax" },
+	{ ARM_INS_VPMIN, "vpmin" },
+	{ ARM_INS_VQABS, "vqabs" },
+	{ ARM_INS_VQADD, "vqadd" },
+	{ ARM_INS_VQDMLAL, "vqdmlal" },
+	{ ARM_INS_VQDMLSL, "vqdmlsl" },
+	{ ARM_INS_VQDMULH, "vqdmulh" },
+	{ ARM_INS_VQDMULL, "vqdmull" },
+	{ ARM_INS_VQMOVUN, "vqmovun" },
+	{ ARM_INS_VQMOVN, "vqmovn" },
+	{ ARM_INS_VQNEG, "vqneg" },
+	{ ARM_INS_VQRDMULH, "vqrdmulh" },
+	{ ARM_INS_VQRSHL, "vqrshl" },
+	{ ARM_INS_VQRSHRN, "vqrshrn" },
+	{ ARM_INS_VQRSHRUN, "vqrshrun" },
+	{ ARM_INS_VQSHL, "vqshl" },
+	{ ARM_INS_VQSHLU, "vqshlu" },
+	{ ARM_INS_VQSHRN, "vqshrn" },
+	{ ARM_INS_VQSHRUN, "vqshrun" },
+	{ ARM_INS_VQSUB, "vqsub" },
+	{ ARM_INS_VRADDHN, "vraddhn" },
+	{ ARM_INS_VRECPE, "vrecpe" },
+	{ ARM_INS_VRECPS, "vrecps" },
+	{ ARM_INS_VREV16, "vrev16" },
+	{ ARM_INS_VREV32, "vrev32" },
+	{ ARM_INS_VREV64, "vrev64" },
+	{ ARM_INS_VRHADD, "vrhadd" },
+	{ ARM_INS_VRINTA, "vrinta" },
+	{ ARM_INS_VRINTM, "vrintm" },
+	{ ARM_INS_VRINTN, "vrintn" },
+	{ ARM_INS_VRINTP, "vrintp" },
+	{ ARM_INS_VRINTR, "vrintr" },
+	{ ARM_INS_VRINTX, "vrintx" },
+	{ ARM_INS_VRINTZ, "vrintz" },
+	{ ARM_INS_VRSHL, "vrshl" },
+	{ ARM_INS_VRSHRN, "vrshrn" },
+	{ ARM_INS_VRSHR, "vrshr" },
+	{ ARM_INS_VRSQRTE, "vrsqrte" },
+	{ ARM_INS_VRSQRTS, "vrsqrts" },
+	{ ARM_INS_VRSRA, "vrsra" },
+	{ ARM_INS_VRSUBHN, "vrsubhn" },
+	{ ARM_INS_VSELEQ, "vseleq" },
+	{ ARM_INS_VSELGE, "vselge" },
+	{ ARM_INS_VSELGT, "vselgt" },
+	{ ARM_INS_VSELVS, "vselvs" },
+	{ ARM_INS_VSHLL, "vshll" },
+	{ ARM_INS_VSHL, "vshl" },
+	{ ARM_INS_VSHRN, "vshrn" },
+	{ ARM_INS_VSHR, "vshr" },
+	{ ARM_INS_VSLI, "vsli" },
+	{ ARM_INS_VSQRT, "vsqrt" },
+	{ ARM_INS_VSRA, "vsra" },
+	{ ARM_INS_VSRI, "vsri" },
+	{ ARM_INS_VST1, "vst1" },
+	{ ARM_INS_VST2, "vst2" },
+	{ ARM_INS_VST3, "vst3" },
+	{ ARM_INS_VST4, "vst4" },
+	{ ARM_INS_VSTMDB, "vstmdb" },
+	{ ARM_INS_VSTMIA, "vstmia" },
+	{ ARM_INS_VSTR, "vstr" },
+	{ ARM_INS_VSUB, "vsub" },
+	{ ARM_INS_VSUBHN, "vsubhn" },
+	{ ARM_INS_VSUBL, "vsubl" },
+	{ ARM_INS_VSUBW, "vsubw" },
+	{ ARM_INS_VSWP, "vswp" },
+	{ ARM_INS_VTBL, "vtbl" },
+	{ ARM_INS_VTBX, "vtbx" },
+	{ ARM_INS_VCVTR, "vcvtr" },
+	{ ARM_INS_VTRN, "vtrn" },
+	{ ARM_INS_VTST, "vtst" },
+	{ ARM_INS_VUZP, "vuzp" },
+	{ ARM_INS_VZIP, "vzip" },
+	{ ARM_INS_ADDW, "addw" },
+	{ ARM_INS_ASR, "asr" },
+	{ ARM_INS_DCPS1, "dcps1" },
+	{ ARM_INS_DCPS2, "dcps2" },
+	{ ARM_INS_DCPS3, "dcps3" },
+	{ ARM_INS_IT, "it" },
+	{ ARM_INS_LSL, "lsl" },
+	{ ARM_INS_LSR, "lsr" },
+	{ ARM_INS_ORN, "orn" },
+	{ ARM_INS_ROR, "ror" },
+	{ ARM_INS_RRX, "rrx" },
+	{ ARM_INS_SUBW, "subw" },
+	{ ARM_INS_TBB, "tbb" },
+	{ ARM_INS_TBH, "tbh" },
+	{ ARM_INS_CBNZ, "cbnz" },
+	{ ARM_INS_CBZ, "cbz" },
+	{ ARM_INS_POP, "pop" },
+	{ ARM_INS_PUSH, "push" },
+
+	// special instructions
+	{ ARM_INS_NOP, "nop" },
+	{ ARM_INS_YIELD, "yield" },
+	{ ARM_INS_WFE, "wfe" },
+	{ ARM_INS_WFI, "wfi" },
+	{ ARM_INS_SEV, "sev" },
+	{ ARM_INS_SEVL, "sevl" },
+	{ ARM_INS_VPUSH, "vpush" },
+	{ ARM_INS_VPOP, "vpop" },
+};
+#endif
+
+const char *ARM_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ARM_INS_ENDING)
+		return NULL;
+
+	return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static const name_map group_name_maps[] = {
+	// generic groups
+	{ ARM_GRP_INVALID, NULL },
+	{ ARM_GRP_JUMP,	"jump" },
+	{ ARM_GRP_CALL,	"call" },
+	{ ARM_GRP_INT,	"int" },
+	{ ARM_GRP_PRIVILEGE, "privilege" },
+	{ ARM_GRP_BRANCH_RELATIVE, "branch_relative" },
+
+	// architecture-specific groups
+	{ ARM_GRP_CRYPTO, "crypto" },
+	{ ARM_GRP_DATABARRIER, "databarrier" },
+	{ ARM_GRP_DIVIDE, "divide" },
+	{ ARM_GRP_FPARMV8, "fparmv8" },
+	{ ARM_GRP_MULTPRO, "multpro" },
+	{ ARM_GRP_NEON, "neon" },
+	{ ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" },
+	{ ARM_GRP_THUMB2DSP, "THUMB2DSP" },
+	{ ARM_GRP_TRUSTZONE, "TRUSTZONE" },
+	{ ARM_GRP_V4T, "v4t" },
+	{ ARM_GRP_V5T, "v5t" },
+	{ ARM_GRP_V5TE, "v5te" },
+	{ ARM_GRP_V6, "v6" },
+	{ ARM_GRP_V6T2, "v6t2" },
+	{ ARM_GRP_V7, "v7" },
+	{ ARM_GRP_V8, "v8" },
+	{ ARM_GRP_VFP2, "vfp2" },
+	{ ARM_GRP_VFP3, "vfp3" },
+	{ ARM_GRP_VFP4, "vfp4" },
+	{ ARM_GRP_ARM, "arm" },
+	{ ARM_GRP_MCLASS, "mclass" },
+	{ ARM_GRP_NOTMCLASS, "notmclass" },
+	{ ARM_GRP_THUMB, "thumb" },
+	{ ARM_GRP_THUMB1ONLY, "thumb1only" },
+	{ ARM_GRP_THUMB2, "thumb2" },
+	{ ARM_GRP_PREV8, "prev8" },
+	{ ARM_GRP_FPVMLX, "fpvmlx" },
+	{ ARM_GRP_MULOPS, "mulops" },
+	{ ARM_GRP_CRC, "crc" },
+	{ ARM_GRP_DPVFP, "dpvfp" },
+	{ ARM_GRP_V6M, "v6m" },
+	{ ARM_GRP_VIRTUALIZATION, "virtualization" },
+};
+#endif
+
+const char *ARM_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
+// list all relative branch instructions
+// ie: insns[i].branch && !insns[i].indirect_branch
+static const unsigned int insn_rel[] = {
+	ARM_BL,
+	ARM_BLX_pred,
+	ARM_Bcc,
+	ARM_t2B,
+	ARM_t2Bcc,
+	ARM_tB,
+	ARM_tBcc,
+	ARM_tCBNZ,
+	ARM_tCBZ,
+	ARM_BL_pred,
+	ARM_BLXi,
+	ARM_tBL,
+	ARM_tBLXi,
+	0
+};
+
+static const unsigned int insn_blx_rel_to_arm[] = {
+	ARM_tBLXi,
+	0
+};
+
+// check if this insn is relative branch
+bool ARM_rel_branch(cs_struct *h, unsigned int id)
+{
+	int i;
+
+	for (i = 0; insn_rel[i]; i++) {
+		if (id == insn_rel[i]) {
+			return true;
+		}
+	}
+
+	// not found
+	return false;
+}
+
+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) {
+	int i;
+
+	for (i = 0; insn_blx_rel_to_arm[i]; i++)
+		if (id == insn_blx_rel_to_arm[i])
+			return true;
+
+	// not found
+	return false;
+
+}
+
+#ifndef CAPSTONE_DIET
+// map instruction to its characteristics
+typedef struct insn_op {
+	uint8_t access[7];
+} insn_op;
+
+static insn_op insn_ops[] = {
+	{
+		// NULL item
+		{ 0 }
+	},
+
+#include "ARMMappingInsnOp.inc"
+};
+
+// given internal insn id, return operand access info
+uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
+{
+	int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
+	if (i != 0) {
+		return insn_ops[i].access;
+	}
+
+	return NULL;
+}
+
+void ARM_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count)
+{
+	uint8_t i;
+	uint8_t read_count, write_count;
+	cs_arm *arm = &(insn->detail->arm);
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
+
+	// explicit registers
+	for (i = 0; i < arm->op_count; i++) {
+		cs_arm_op *op = &(arm->operands[i]);
+		switch((int)op->type) {
+			case ARM_OP_REG:
+				if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
+					regs_read[read_count] = (uint16_t)op->reg;
+					read_count++;
+				}
+				if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
+					regs_write[write_count] = (uint16_t)op->reg;
+					write_count++;
+				}
+				break;
+			case ARM_OP_MEM:
+				// registers appeared in memory references always being read
+				if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
+					regs_read[read_count] = (uint16_t)op->mem.base;
+					read_count++;
+				}
+				if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
+					regs_read[read_count] = (uint16_t)op->mem.index;
+					read_count++;
+				}
+				if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
+					regs_write[write_count] = (uint16_t)op->mem.base;
+					write_count++;
+				}
+			default:
+				break;
+		}
+	}
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+}
+#endif
+
+#endif

arch/ARM/ARMMapping.h

@@ -0,0 +1,32 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifndef CS_ARM_MAP_H
+#define CS_ARM_MAP_H
+
+#include "../../include/capstone/capstone.h"
+#include "../../utils.h"
+
+// return name of regiser in friendly string
+const char *ARM_reg_name(csh handle, unsigned int reg);
+const char *ARM_reg_name2(csh handle, unsigned int reg);
+
+// given internal insn id, return public instruction ID
+void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+
+const char *ARM_insn_name(csh handle, unsigned int id);
+
+const char *ARM_group_name(csh handle, unsigned int id);
+
+// check if this insn is relative branch
+bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
+
+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
+
+uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
+
+void ARM_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count);
+
+#endif

arch/ARM/ARMModule.c

@@ -0,0 +1,63 @@
+/* Capstone Disassembly Engine */
+/* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
+
+#ifdef CAPSTONE_HAS_ARM
+
+#include "../../cs_priv.h"
+#include "../../MCRegisterInfo.h"
+#include "ARMDisassembler.h"
+#include "ARMInstPrinter.h"
+#include "ARMMapping.h"
+#include "ARMModule.h"
+
+cs_err ARM_global_init(cs_struct *ud)
+{
+	MCRegisterInfo *mri;
+	mri = cs_mem_malloc(sizeof(*mri));
+
+	ARM_init(mri);
+	ARM_getRegName(ud, 0);	// use default get_regname
+
+	ud->printer = ARM_printInst;
+	ud->printer_info = mri;
+	ud->reg_name = ARM_reg_name;
+	ud->insn_id = ARM_get_insn_id;
+	ud->insn_name = ARM_insn_name;
+	ud->group_name = ARM_group_name;
+	ud->post_printer = ARM_post_printer;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = ARM_reg_access;
+#endif
+
+	if (ud->mode & CS_MODE_THUMB)
+		ud->disasm = Thumb_getInstruction;
+	else
+		ud->disasm = ARM_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	switch(type) {
+		case CS_OPT_MODE:
+			if (value & CS_MODE_THUMB)
+				handle->disasm = Thumb_getInstruction;
+			else
+				handle->disasm = ARM_getInstruction;
+
+			handle->mode = (cs_mode)value;
+
+			break;
+		case CS_OPT_SYNTAX:
+			ARM_getRegName(handle, (int)value);
+			handle->syntax = (int)value;
+			break;
+		default:
+			break;
+	}
+
+	return CS_ERR_OK;
+}
+
+#endif

arch/ARM/ARMModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_ARM_MODULE_H
+#define CS_ARM_MODULE_H
+
+#include "../../utils.h"
+
+cs_err ARM_global_init(cs_struct *ud);
+cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

arch/EVM/EVMDisassembler.c

@@ -0,0 +1,379 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include <string.h>
+#include <stddef.h> // offsetof macro
+                    // alternatively #include "../../utils.h" like everyone else
+
+#include "EVMDisassembler.h"
+#include "EVMMapping.h"
+
+static short opcodes[256] = {
+	EVM_INS_STOP,
+	EVM_INS_ADD,
+	EVM_INS_MUL,
+	EVM_INS_SUB,
+	EVM_INS_DIV,
+	EVM_INS_SDIV,
+	EVM_INS_MOD,
+	EVM_INS_SMOD,
+	EVM_INS_ADDMOD,
+	EVM_INS_MULMOD,
+	EVM_INS_EXP,
+	EVM_INS_SIGNEXTEND,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_LT,
+	EVM_INS_GT,
+	EVM_INS_SLT,
+	EVM_INS_SGT,
+	EVM_INS_EQ,
+	EVM_INS_ISZERO,
+	EVM_INS_AND,
+	EVM_INS_OR,
+	EVM_INS_XOR,
+	EVM_INS_NOT,
+	EVM_INS_BYTE,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_SHA3,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_ADDRESS,
+	EVM_INS_BALANCE,
+	EVM_INS_ORIGIN,
+	EVM_INS_CALLER,
+	EVM_INS_CALLVALUE,
+	EVM_INS_CALLDATALOAD,
+	EVM_INS_CALLDATASIZE,
+	EVM_INS_CALLDATACOPY,
+	EVM_INS_CODESIZE,
+	EVM_INS_CODECOPY,
+	EVM_INS_GASPRICE,
+	EVM_INS_EXTCODESIZE,
+	EVM_INS_EXTCODECOPY,
+	EVM_INS_RETURNDATASIZE,
+	EVM_INS_RETURNDATACOPY,
+	-1,
+	EVM_INS_BLOCKHASH,
+	EVM_INS_COINBASE,
+	EVM_INS_TIMESTAMP,
+	EVM_INS_NUMBER,
+	EVM_INS_DIFFICULTY,
+	EVM_INS_GASLIMIT,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_POP,
+	EVM_INS_MLOAD,
+	EVM_INS_MSTORE,
+	EVM_INS_MSTORE8,
+	EVM_INS_SLOAD,
+	EVM_INS_SSTORE,
+	EVM_INS_JUMP,
+	EVM_INS_JUMPI,
+	EVM_INS_PC,
+	EVM_INS_MSIZE,
+	EVM_INS_GAS,
+	EVM_INS_JUMPDEST,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_PUSH1,
+	EVM_INS_PUSH2,
+	EVM_INS_PUSH3,
+	EVM_INS_PUSH4,
+	EVM_INS_PUSH5,
+	EVM_INS_PUSH6,
+	EVM_INS_PUSH7,
+	EVM_INS_PUSH8,
+	EVM_INS_PUSH9,
+	EVM_INS_PUSH10,
+	EVM_INS_PUSH11,
+	EVM_INS_PUSH12,
+	EVM_INS_PUSH13,
+	EVM_INS_PUSH14,
+	EVM_INS_PUSH15,
+	EVM_INS_PUSH16,
+	EVM_INS_PUSH17,
+	EVM_INS_PUSH18,
+	EVM_INS_PUSH19,
+	EVM_INS_PUSH20,
+	EVM_INS_PUSH21,
+	EVM_INS_PUSH22,
+	EVM_INS_PUSH23,
+	EVM_INS_PUSH24,
+	EVM_INS_PUSH25,
+	EVM_INS_PUSH26,
+	EVM_INS_PUSH27,
+	EVM_INS_PUSH28,
+	EVM_INS_PUSH29,
+	EVM_INS_PUSH30,
+	EVM_INS_PUSH31,
+	EVM_INS_PUSH32,
+	EVM_INS_DUP1,
+	EVM_INS_DUP2,
+	EVM_INS_DUP3,
+	EVM_INS_DUP4,
+	EVM_INS_DUP5,
+	EVM_INS_DUP6,
+	EVM_INS_DUP7,
+	EVM_INS_DUP8,
+	EVM_INS_DUP9,
+	EVM_INS_DUP10,
+	EVM_INS_DUP11,
+	EVM_INS_DUP12,
+	EVM_INS_DUP13,
+	EVM_INS_DUP14,
+	EVM_INS_DUP15,
+	EVM_INS_DUP16,
+	EVM_INS_SWAP1,
+	EVM_INS_SWAP2,
+	EVM_INS_SWAP3,
+	EVM_INS_SWAP4,
+	EVM_INS_SWAP5,
+	EVM_INS_SWAP6,
+	EVM_INS_SWAP7,
+	EVM_INS_SWAP8,
+	EVM_INS_SWAP9,
+	EVM_INS_SWAP10,
+	EVM_INS_SWAP11,
+	EVM_INS_SWAP12,
+	EVM_INS_SWAP13,
+	EVM_INS_SWAP14,
+	EVM_INS_SWAP15,
+	EVM_INS_SWAP16,
+	EVM_INS_LOG0,
+	EVM_INS_LOG1,
+	EVM_INS_LOG2,
+	EVM_INS_LOG3,
+	EVM_INS_LOG4,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_CREATE,
+	EVM_INS_CALL,
+	EVM_INS_CALLCODE,
+	EVM_INS_RETURN,
+	EVM_INS_DELEGATECALL,
+	EVM_INS_CALLBLACKBOX,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_STATICCALL,
+	-1,
+	-1,
+	EVM_INS_REVERT,
+	-1,
+	EVM_INS_SUICIDE,
+};
+
+bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+	MCInst *MI, uint16_t *size, uint64_t address, void *inst_info)
+{
+	unsigned char opcode;
+
+	if (code_len == 0)
+		return false;
+
+	opcode = code[0];
+	if (opcodes[opcode] == -1) {
+		// invalid opcode
+		return false;
+	}
+
+	// valid opcode
+	MI->address = address;
+	MI->OpcodePub = MI->Opcode = opcode;
+
+	if (opcode >= EVM_INS_PUSH1 && opcode <= EVM_INS_PUSH32) {
+		unsigned char len = (opcode - EVM_INS_PUSH1 + 1);
+		if (code_len < 1 + len) {
+			// not enough data
+			return false;
+		}
+
+		*size = 1 + len;
+		memcpy(MI->evm_data, code + 1, len);
+	} else
+		*size = 1;
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, evm)+sizeof(cs_evm));
+		EVM_get_insn_id((cs_struct *)ud, MI->flat_insn, opcode);
+
+		if (MI->flat_insn->detail->evm.pop) {
+			MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_READ;
+			MI->flat_insn->detail->groups_count++;
+		}
+
+		if (MI->flat_insn->detail->evm.push) {
+			MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_WRITE;
+			MI->flat_insn->detail->groups_count++;
+		}
+
+		// setup groups
+		switch(opcode) {
+			default:
+				break;
+			case EVM_INS_ADD:
+			case EVM_INS_MUL:
+			case EVM_INS_SUB:
+			case EVM_INS_DIV:
+			case EVM_INS_SDIV:
+			case EVM_INS_MOD:
+			case EVM_INS_SMOD:
+			case EVM_INS_ADDMOD:
+			case EVM_INS_MULMOD:
+			case EVM_INS_EXP:
+			case EVM_INS_SIGNEXTEND:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MATH;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_MSTORE:
+			case EVM_INS_MSTORE8:
+			case EVM_INS_CALLDATACOPY:
+			case EVM_INS_CODECOPY:
+			case EVM_INS_EXTCODECOPY:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_WRITE;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_MLOAD:
+			case EVM_INS_CREATE:
+			case EVM_INS_CALL:
+			case EVM_INS_CALLCODE:
+			case EVM_INS_RETURN:
+			case EVM_INS_DELEGATECALL:
+			case EVM_INS_REVERT:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_READ;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_SSTORE:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_WRITE;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_SLOAD:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_READ;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_JUMP:
+			case EVM_INS_JUMPI:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_JUMP;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_STOP:
+			case EVM_INS_SUICIDE:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_HALT;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+		}
+	}
+
+	return true;
+}

arch/EVM/EVMDisassembler.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifndef CS_EVMDISASSEMBLER_H
+#define CS_EVMDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif

arch/EVM/EVMInstPrinter.c

@@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include "EVMInstPrinter.h"
+#include "EVMMapping.h"
+
+
+void EVM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
+{
+	SStream_concat(O, EVM_insn_name((csh)MI->csh, MI->Opcode));
+
+	if (MI->Opcode >= EVM_INS_PUSH1 && MI->Opcode <= EVM_INS_PUSH32) {
+		unsigned int i;
+
+		SStream_concat0(O, "\t");
+		for (i = 0; i < MI->Opcode - EVM_INS_PUSH1 + 1; i++) {
+			SStream_concat(O, "%02x", MI->evm_data[i]);
+		}
+	}
+}

arch/EVM/EVMInstPrinter.h

@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifndef CS_EVMINSTPRINTER_H
+#define CS_EVMINSTPRINTER_H
+
+
+#include "capstone/capstone.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../cs_priv.h"
+
+struct SStream;
+
+void EVM_printInst(MCInst *MI, struct SStream *O, void *Info);
+
+#endif

arch/EVM/EVMMapping.c

@@ -0,0 +1,344 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifdef CAPSTONE_HAS_EVM
+
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "EVMMapping.h"
+
+#ifndef CAPSTONE_DIET
+static cs_evm insns[256] = {
+#include "EVMMappingInsn.inc"
+};
+#endif
+
+// look for @id in @insns, given its size in @max.
+// return -1 if not found
+static int evm_insn_find(cs_evm *insns, unsigned int max, unsigned int id)
+{
+	if (id >= max)
+		return -1;
+
+	if (insns[id].fee == 0xffffffff)
+		// unused opcode
+		return -1;
+
+	return (int)id;
+}
+
+// fill in details
+void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	insn->id = id;
+#ifndef CAPSTONE_DIET
+	if (evm_insn_find(insns, ARR_SIZE(insns), id) > 0) {
+		if (h->detail) {
+			memcpy(&insn->detail->evm, &insns[id], sizeof(insns[id]));
+		}
+	}
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map insn_name_maps[256] = {
+	{ EVM_INS_STOP, "stop" },
+	{ EVM_INS_ADD, "add" },
+	{ EVM_INS_MUL, "mul" },
+	{ EVM_INS_SUB, "sub" },
+	{ EVM_INS_DIV, "div" },
+	{ EVM_INS_SDIV, "sdiv" },
+	{ EVM_INS_MOD, "mod" },
+	{ EVM_INS_SMOD, "smod" },
+	{ EVM_INS_ADDMOD, "addmod" },
+	{ EVM_INS_MULMOD, "mulmod" },
+	{ EVM_INS_EXP, "exp" },
+	{ EVM_INS_SIGNEXTEND, "signextend" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_LT, "lt" },
+	{ EVM_INS_GT, "gt" },
+	{ EVM_INS_SLT, "slt" },
+	{ EVM_INS_SGT, "sgt" },
+	{ EVM_INS_EQ, "eq" },
+	{ EVM_INS_ISZERO, "iszero" },
+	{ EVM_INS_AND, "and" },
+	{ EVM_INS_OR, "or" },
+	{ EVM_INS_XOR, "xor" },
+	{ EVM_INS_NOT, "not" },
+	{ EVM_INS_BYTE, "byte" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_SHA3, "sha3" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_ADDRESS, "address" },
+	{ EVM_INS_BALANCE, "balance" },
+	{ EVM_INS_ORIGIN, "origin" },
+	{ EVM_INS_CALLER, "caller" },
+	{ EVM_INS_CALLVALUE, "callvalue" },
+	{ EVM_INS_CALLDATALOAD, "calldataload" },
+	{ EVM_INS_CALLDATASIZE, "calldatasize" },
+	{ EVM_INS_CALLDATACOPY, "calldatacopy" },
+	{ EVM_INS_CODESIZE, "codesize" },
+	{ EVM_INS_CODECOPY, "codecopy" },
+	{ EVM_INS_GASPRICE, "gasprice" },
+	{ EVM_INS_EXTCODESIZE, "extcodesize" },
+	{ EVM_INS_EXTCODECOPY, "extcodecopy" },
+	{ EVM_INS_RETURNDATASIZE, "returndatasize" },
+	{ EVM_INS_RETURNDATACOPY, "returndatacopy" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_BLOCKHASH, "blockhash" },
+	{ EVM_INS_COINBASE, "coinbase" },
+	{ EVM_INS_TIMESTAMP, "timestamp" },
+	{ EVM_INS_NUMBER, "number" },
+	{ EVM_INS_DIFFICULTY, "difficulty" },
+	{ EVM_INS_GASLIMIT, "gaslimit" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_POP, "pop" },
+	{ EVM_INS_MLOAD, "mload" },
+	{ EVM_INS_MSTORE, "mstore" },
+	{ EVM_INS_MSTORE8, "mstore8" },
+	{ EVM_INS_SLOAD, "sload" },
+	{ EVM_INS_SSTORE, "sstore" },
+	{ EVM_INS_JUMP, "jump" },
+	{ EVM_INS_JUMPI, "jumpi" },
+	{ EVM_INS_PC, "pc" },
+	{ EVM_INS_MSIZE, "msize" },
+	{ EVM_INS_GAS, "gas" },
+	{ EVM_INS_JUMPDEST, "jumpdest" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_PUSH1, "push1" },
+	{ EVM_INS_PUSH2, "push2" },
+	{ EVM_INS_PUSH3, "push3" },
+	{ EVM_INS_PUSH4, "push4" },
+	{ EVM_INS_PUSH5, "push5" },
+	{ EVM_INS_PUSH6, "push6" },
+	{ EVM_INS_PUSH7, "push7" },
+	{ EVM_INS_PUSH8, "push8" },
+	{ EVM_INS_PUSH9, "push9" },
+	{ EVM_INS_PUSH10, "push10" },
+	{ EVM_INS_PUSH11, "push11" },
+	{ EVM_INS_PUSH12, "push12" },
+	{ EVM_INS_PUSH13, "push13" },
+	{ EVM_INS_PUSH14, "push14" },
+	{ EVM_INS_PUSH15, "push15" },
+	{ EVM_INS_PUSH16, "push16" },
+	{ EVM_INS_PUSH17, "push17" },
+	{ EVM_INS_PUSH18, "push18" },
+	{ EVM_INS_PUSH19, "push19" },
+	{ EVM_INS_PUSH20, "push20" },
+	{ EVM_INS_PUSH21, "push21" },
+	{ EVM_INS_PUSH22, "push22" },
+	{ EVM_INS_PUSH23, "push23" },
+	{ EVM_INS_PUSH24, "push24" },
+	{ EVM_INS_PUSH25, "push25" },
+	{ EVM_INS_PUSH26, "push26" },
+	{ EVM_INS_PUSH27, "push27" },
+	{ EVM_INS_PUSH28, "push28" },
+	{ EVM_INS_PUSH29, "push29" },
+	{ EVM_INS_PUSH30, "push30" },
+	{ EVM_INS_PUSH31, "push31" },
+	{ EVM_INS_PUSH32, "push32" },
+	{ EVM_INS_DUP1, "dup1" },
+	{ EVM_INS_DUP2, "dup2" },
+	{ EVM_INS_DUP3, "dup3" },
+	{ EVM_INS_DUP4, "dup4" },
+	{ EVM_INS_DUP5, "dup5" },
+	{ EVM_INS_DUP6, "dup6" },
+	{ EVM_INS_DUP7, "dup7" },
+	{ EVM_INS_DUP8, "dup8" },
+	{ EVM_INS_DUP9, "dup9" },
+	{ EVM_INS_DUP10, "dup10" },
+	{ EVM_INS_DUP11, "dup11" },
+	{ EVM_INS_DUP12, "dup12" },
+	{ EVM_INS_DUP13, "dup13" },
+	{ EVM_INS_DUP14, "dup14" },
+	{ EVM_INS_DUP15, "dup15" },
+	{ EVM_INS_DUP16, "dup16" },
+	{ EVM_INS_SWAP1, "swap1" },
+	{ EVM_INS_SWAP2, "swap2" },
+	{ EVM_INS_SWAP3, "swap3" },
+	{ EVM_INS_SWAP4, "swap4" },
+	{ EVM_INS_SWAP5, "swap5" },
+	{ EVM_INS_SWAP6, "swap6" },
+	{ EVM_INS_SWAP7, "swap7" },
+	{ EVM_INS_SWAP8, "swap8" },
+	{ EVM_INS_SWAP9, "swap9" },
+	{ EVM_INS_SWAP10, "swap10" },
+	{ EVM_INS_SWAP11, "swap11" },
+	{ EVM_INS_SWAP12, "swap12" },
+	{ EVM_INS_SWAP13, "swap13" },
+	{ EVM_INS_SWAP14, "swap14" },
+	{ EVM_INS_SWAP15, "swap15" },
+	{ EVM_INS_SWAP16, "swap16" },
+	{ EVM_INS_LOG0, "log0" },
+	{ EVM_INS_LOG1, "log1" },
+	{ EVM_INS_LOG2, "log2" },
+	{ EVM_INS_LOG3, "log3" },
+	{ EVM_INS_LOG4, "log4" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_CREATE, "create" },
+	{ EVM_INS_CALL, "call" },
+	{ EVM_INS_CALLCODE, "callcode" },
+	{ EVM_INS_RETURN, "return" },
+	{ EVM_INS_DELEGATECALL, "delegatecall" },
+	{ EVM_INS_CALLBLACKBOX, "callblackbox" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_STATICCALL, "staticcall" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_REVERT, "revert" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_SUICIDE, "suicide" },
+};
+#endif
+
+const char *EVM_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ARR_SIZE(insn_name_maps))
+		return NULL;
+	else
+		return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	// generic groups
+	{ EVM_GRP_INVALID, NULL },
+	{ EVM_GRP_JUMP,	"jump" },
+	// special groups
+	{ EVM_GRP_MATH,	"math" },
+	{ EVM_GRP_STACK_WRITE, "stack_write" },
+	{ EVM_GRP_STACK_READ, "stack_read" },
+	{ EVM_GRP_MEM_WRITE, "mem_write" },
+	{ EVM_GRP_MEM_READ, "mem_read" },
+	{ EVM_GRP_STORE_WRITE, "store_write" },
+	{ EVM_GRP_STORE_READ, "store_read" },
+	{ EVM_GRP_HALT, "halt" },
+};
+#endif
+
+const char *EVM_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+#endif

arch/EVM/EVMMapping.h

@@ -0,0 +1,8 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include <capstone/capstone.h>
+
+void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+const char *EVM_insn_name(csh handle, unsigned int id);
+const char *EVM_group_name(csh handle, unsigned int id);

arch/EVM/EVMMappingInsn.inc

@@ -0,0 +1,259 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+{ 0, 0, 0 }, // STOP
+{ 2, 1, 3 }, // ADD
+{ 2, 1, 5 }, // MUL
+{ 2, 1, 3 }, // SUB
+{ 2, 1, 5 }, // DIV
+{ 2, 1, 5 }, // SDIV
+{ 2, 1, 5 }, // MOD
+{ 2, 1, 5 }, // SMOD
+{ 3, 1, 8 }, // ADDMOD
+{ 3, 1, 8 }, // MULMOD
+{ 2, 1, 10 }, // EXP
+{ 2, 1, 5 }, // SIGNEXTEND
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 1, 3 }, // LT
+{ 2, 1, 3 }, // GT
+{ 2, 1, 3 }, // SLT
+{ 2, 1, 3 }, // SGT
+{ 2, 1, 3 }, // EQ
+{ 1, 1, 3 }, // ISZERO
+{ 2, 1, 3 }, // AND
+{ 2, 1, 3 }, // OR
+{ 2, 1, 3 }, // XOR
+{ 1, 1, 3 }, // NOT
+{ 2, 1, 3 }, // BYTE
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 1, 30 }, // SHA3
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 1, 2 }, // ADDRESS
+{ 1, 1, 20 }, // BALANCE
+{ 0, 1, 2 }, // ORIGIN
+{ 0, 1, 2 }, // CALLER
+{ 0, 1, 2 }, // CALLVALUE
+{ 1, 1, 3 }, // CALLDATALOAD
+{ 0, 1, 2 }, // CALLDATASIZE
+{ 3, 0, 3 }, // CALLDATACOPY
+{ 0, 1, 2 }, // CODESIZE
+{ 3, 0, 3 }, // CODECOPY
+{ 0, 1, 2 }, // GASPRICE
+{ 1, 1, 20 }, // EXTCODESIZE
+{ 4, 0, 20 }, // EXTCODECOPY
+{ 0, 1, 2 }, // RETURNDATASIZE
+{ 3, 0, 3 }, // RETURNDATACOPY
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 1, 20 }, // BLOCKHASH
+{ 0, 1, 2 }, // COINBASE
+{ 0, 1, 2 }, // TIMESTAMP
+{ 0, 1, 2 }, // NUMBER
+{ 0, 1, 2 }, // DIFFICULTY
+{ 0, 1, 2 }, // GASLIMIT
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 0, 2 }, // POP
+{ 1, 1, 3 }, // MLOAD
+{ 2, 0, 3 }, // MSTORE
+{ 2, 0, 3 }, // MSTORE8
+{ 1, 1, 50 }, // SLOAD
+{ 2, 0, 0 }, // SSTORE
+{ 1, 0, 8 }, // JUMP
+{ 2, 0, 10 }, // JUMPI
+{ 0, 1, 2 }, // GETPC
+{ 0, 1, 2 }, // MSIZE
+{ 0, 1, 2 }, // GAS
+{ 0, 0, 1 }, // JUMPDEST
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 1, 3 }, // PUSH1
+{ 0, 1, 3 }, // PUSH2
+{ 0, 1, 3 }, // PUSH3
+{ 0, 1, 3 }, // PUSH4
+{ 0, 1, 3 }, // PUSH5
+{ 0, 1, 3 }, // PUSH6
+{ 0, 1, 3 }, // PUSH7
+{ 0, 1, 3 }, // PUSH8
+{ 0, 1, 3 }, // PUSH9
+{ 0, 1, 3 }, // PUSH10
+{ 0, 1, 3 }, // PUSH11
+{ 0, 1, 3 }, // PUSH12
+{ 0, 1, 3 }, // PUSH13
+{ 0, 1, 3 }, // PUSH14
+{ 0, 1, 3 }, // PUSH15
+{ 0, 1, 3 }, // PUSH16
+{ 0, 1, 3 }, // PUSH17
+{ 0, 1, 3 }, // PUSH18
+{ 0, 1, 3 }, // PUSH19
+{ 0, 1, 3 }, // PUSH20
+{ 0, 1, 3 }, // PUSH21
+{ 0, 1, 3 }, // PUSH22
+{ 0, 1, 3 }, // PUSH23
+{ 0, 1, 3 }, // PUSH24
+{ 0, 1, 3 }, // PUSH25
+{ 0, 1, 3 }, // PUSH26
+{ 0, 1, 3 }, // PUSH27
+{ 0, 1, 3 }, // PUSH28
+{ 0, 1, 3 }, // PUSH29
+{ 0, 1, 3 }, // PUSH30
+{ 0, 1, 3 }, // PUSH31
+{ 0, 1, 3 }, // PUSH32
+{ 1, 2, 3 }, // DUP1
+{ 2, 3, 3 }, // DUP2
+{ 3, 4, 3 }, // DUP3
+{ 4, 5, 3 }, // DUP4
+{ 5, 6, 3 }, // DUP5
+{ 6, 7, 3 }, // DUP6
+{ 7, 8, 3 }, // DUP7
+{ 8, 9, 3 }, // DUP8
+{ 9, 10, 3 }, // DUP9
+{ 10, 11, 3 }, // DUP10
+{ 11, 12, 3 }, // DUP11
+{ 12, 13, 3 }, // DUP12
+{ 13, 14, 3 }, // DUP13
+{ 14, 15, 3 }, // DUP14
+{ 15, 16, 3 }, // DUP15
+{ 16, 17, 3 }, // DUP16
+{ 2, 2, 3 }, // SWAP1
+{ 3, 3, 3 }, // SWAP2
+{ 4, 4, 3 }, // SWAP3
+{ 5, 5, 3 }, // SWAP4
+{ 6, 6, 3 }, // SWAP5
+{ 7, 7, 3 }, // SWAP6
+{ 8, 8, 3 }, // SWAP7
+{ 9, 9, 3 }, // SWAP8
+{ 10, 10, 3 }, // SWAP9
+{ 11, 11, 3 }, // SWAP10
+{ 12, 12, 3 }, // SWAP11
+{ 13, 13, 3 }, // SWAP12
+{ 14, 14, 3 }, // SWAP13
+{ 15, 15, 3 }, // SWAP14
+{ 16, 16, 3 }, // SWAP15
+{ 17, 17, 3 }, // SWAP16
+{ 2, 0, 375 }, // LOG0
+{ 3, 0, 750 }, // LOG1
+{ 4, 0, 1125 }, // LOG2
+{ 5, 0, 1500 }, // LOG3
+{ 6, 0, 1875 }, // LOG4
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 3, 1, 32000 }, // CREATE
+{ 7, 1, 40 }, // CALL
+{ 7, 1, 40 }, // CALLCODE
+{ 2, 0, 0 }, // RETURN
+{ 6, 1, 40 }, // DELEGATECALL
+{ 7, 1, 40 }, // CALLBLACKBOX
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 6, 1, 40 }, // STATICCALL
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 0, 0 }, // REVERT
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 0, 0 }, // SUICIDE

arch/EVM/EVMModule.c

@@ -0,0 +1,33 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifdef CAPSTONE_HAS_EVM
+
+#include "../../cs_priv.h"
+#include "EVMDisassembler.h"
+#include "EVMInstPrinter.h"
+#include "EVMMapping.h"
+#include "EVMModule.h"
+
+cs_err EVM_global_init(cs_struct *ud)
+{
+	// verify if requested mode is valid
+	if (ud->mode)
+		return CS_ERR_MODE;
+
+	ud->printer = EVM_printInst;
+	ud->printer_info = NULL;
+	ud->insn_id = EVM_get_insn_id;
+	ud->insn_name = EVM_insn_name;
+	ud->group_name = EVM_group_name;
+	ud->disasm = EVM_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	return CS_ERR_OK;
+}
+
+#endif

arch/EVM/EVMModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_EVM_MODULE_H
+#define CS_EVM_MODULE_H
+
+#include "../../utils.h"
+
+cs_err EVM_global_init(cs_struct *ud);
+cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

arch/M680X/M680XDisassembler.h

@@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XDISASSEMBLER_H
+#define CS_M680XDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+	MCInst *instr, uint16_t *size, uint64_t address, void *info);
+void M680X_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+void M680X_reg_access(const cs_insn *insn,
+	cs_regs regs_read, uint8_t *regs_read_count,
+	cs_regs regs_write, uint8_t *regs_write_count);
+
+#endif
+

arch/M680X/M680XDisassemblerInternals.h

@@ -0,0 +1,57 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XDISASSEMBLERINTERNALS_H
+#define CS_M680XDISASSEMBLERINTERNALS_H
+
+#include "../../MCInst.h"
+#include "../../include/capstone/m680x.h"
+
+typedef enum e_cpu_type {
+	M680X_CPU_TYPE_INVALID,
+	M680X_CPU_TYPE_6301,	// M680X Hitachi HD6301,HD6303 mode
+	M680X_CPU_TYPE_6309,	// M680X Hitachi HD6309 mode
+	M680X_CPU_TYPE_6800,	// M680X Motorola 6800,6802 mode
+	M680X_CPU_TYPE_6801,	// M680X Motorola 6801,6803 mode
+	M680X_CPU_TYPE_6805,	// M680X Motorola/Freescale M68HC05 mode
+	M680X_CPU_TYPE_6808,	// M680X Motorola/Freescale M68HC08 mode
+	M680X_CPU_TYPE_6809,	// M680X Motorola 6809 mode
+	M680X_CPU_TYPE_6811,	// M680X Motorola/Freescale M68HC11 mode
+	M680X_CPU_TYPE_CPU12,	// M680X Motorola/Freescale CPU12 mode
+	// used on M68HC12/HCS12
+	M680X_CPU_TYPE_HCS08,	// M680X Freescale HCS08 mode
+	M680X_CPU_TYPE_ENDING,
+} e_cpu_type;
+
+struct inst_page1;
+struct inst_pageX;
+
+typedef struct {
+	const struct inst_page1 *inst_page1_table;
+	const struct inst_pageX *inst_overlay_table[2];
+	size_t overlay_table_size[2];
+	uint8_t pageX_prefix[3];
+	const struct inst_pageX *inst_pageX_table[3];
+	size_t pageX_table_size[3];
+	const uint8_t *reg_byte_size;
+	const bool *tfr_reg_valid;
+	m680x_insn insn_cc_not_modified[2];
+} cpu_tables;
+
+/* Private, For internal use only */
+typedef struct m680x_info {
+	const uint8_t *code;	// code buffer
+	uint32_t size;		// byte size of code
+	uint16_t offset;	// address offset of first byte in code buffer
+	e_cpu_type cpu_type;	// The CPU type to be used for disassembling
+	cs_m680x m680x;		// M680X specific properties
+	const cpu_tables *cpu;
+	m680x_insn insn;	// Instruction ID
+	uint8_t insn_size;	// byte size of instruction
+} m680x_info;
+
+extern cs_err M680X_disassembler_init(cs_struct *ud);
+extern cs_err M680X_instprinter_init(cs_struct *ud);
+
+#endif
+

arch/M680X/M680XInstPrinter.c

@@ -0,0 +1,365 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifdef CAPSTONE_HAS_M680X
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <capstone/platform.h>
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../utils.h"
+#include "M680XInstPrinter.h"
+#include "M680XDisassembler.h"
+#include "M680XDisassemblerInternals.h"
+
+#ifndef CAPSTONE_DIET
+static const char s_reg_names[][10] = {
+	"<invalid>", "a", "b", "e", "f", "0", "d", "w", "cc", "dp", "md",
+	"hx", "h", "x", "y", "s", "u", "v", "q", "pc", "tmp2", "tmp3",
+};
+
+static const char s_instruction_names[][6] = {
+	"invld", "aba", "abx", "aby", "adc", "adca", "adcb", "adcd", "adcr",
+	"add", "adda", "addb", "addd", "adde", "addf", "addr", "addw",
+	"aim", "ais", "aix", "and", "anda", "andb", "andcc", "andd", "andr",
+	"asl", "asla", "aslb", "asld",
+	"asr", "asra", "asrb", "asrd", "asrx",
+	"band",
+	"bcc", "bclr", "bcs", "beor", "beq", "bge", "bgnd", "bgt", "bhcc",
+	"bhcs", "bhi",
+	"biand", "bieor", "bih", "bil",
+	"bior", "bit", "bita", "bitb", "bitd", "bitmd", "ble", "bls", "blt",
+	"bmc",
+	"bmi", "bms",
+	"bne", "bor", "bpl", "brclr", "brset", "bra", "brn", "bset", "bsr",
+	"bvc", "bvs",
+	"call", "cba", "cbeq", "cbeqa", "cbeqx", "clc", "cli",
+	"clr", "clra", "clrb", "clrd", "clre", "clrf", "clrh", "clrw", "clrx",
+	"clv", "cmp",
+	"cmpa", "cmpb", "cmpd", "cmpe", "cmpf", "cmpr", "cmps", "cmpu", "cmpw",
+	"cmpx", "cmpy",
+	"com", "coma", "comb", "comd", "come", "comf", "comw", "comx", "cpd",
+	"cphx", "cps", "cpx", "cpy",
+	"cwai", "daa", "dbeq", "dbne", "dbnz", "dbnza", "dbnzx",
+	"dec", "deca", "decb", "decd", "dece", "decf", "decw",
+	"decx", "des", "dex", "dey",
+	"div", "divd", "divq", "ediv", "edivs", "eim", "emacs", "emaxd",
+	"emaxm", "emind", "eminm", "emul", "emuls",
+	"eor", "eora", "eorb", "eord", "eorr", "etbl",
+	"exg", "fdiv", "ibeq", "ibne", "idiv", "idivs", "illgl",
+	"inc", "inca", "incb", "incd", "ince", "incf", "incw", "incx",
+	"ins", "inx", "iny",
+	"jmp", "jsr",
+	"lbcc", "lbcs", "lbeq", "lbge", "lbgt", "lbhi", "lble", "lbls", "lblt",
+	"lbmi", "lbne", "lbpl", "lbra", "lbrn", "lbsr", "lbvc", "lbvs",
+	"lda", "ldaa", "ldab", "ldb", "ldbt", "ldd", "lde", "ldf", "ldhx",
+	"ldmd",
+	"ldq", "lds", "ldu", "ldw", "ldx", "ldy",
+	"leas", "leau", "leax", "leay",
+	"lsl", "lsla", "lslb", "lsld", "lslx",
+	"lsr", "lsra", "lsrb", "lsrd", "lsrw", "lsrx",
+	"maxa", "maxm", "mem", "mina", "minm", "mov", "movb", "movw", "mul",
+	"muld",
+	"neg", "nega", "negb", "negd", "negx",
+	"nop", "nsa", "oim", "ora", "oraa", "orab", "orb", "orcc", "ord", "orr",
+	"psha", "pshb", "pshc", "pshd", "pshh", "pshs", "pshsw", "pshu",
+	"pshuw", "pshx", "pshy",
+	"pula", "pulb", "pulc", "puld", "pulh", "puls", "pulsw", "pulu",
+	"puluw", "pulx", "puly", "rev", "revw",
+	"rol", "rola", "rolb", "rold", "rolw", "rolx",
+	"ror", "rora", "rorb", "rord", "rorw", "rorx",
+	"rsp", "rtc", "rti", "rts", "sba", "sbc", "sbca", "sbcb", "sbcd",
+	"sbcr",
+	"sec", "sei", "sev", "sex", "sexw", "slp", "sta", "staa", "stab", "stb",
+	"stbt", "std", "ste", "stf", "stop", "sthx",
+	"stq", "sts", "stu", "stw", "stx", "sty",
+	"sub", "suba", "subb", "subd", "sube", "subf", "subr", "subw",
+	"swi", "swi2", "swi3",
+	"sync", "tab", "tap", "tax", "tba", "tbeq", "tbl", "tbne", "test",
+	"tfm", "tfr",
+	"tim", "tpa",
+	"tst", "tsta", "tstb", "tstd", "tste", "tstf", "tstw", "tstx",
+	"tsx", "tsy", "txa", "txs", "tys", "wai", "wait", "wav", "wavr",
+	"xgdx", "xgdy",
+};
+
+static name_map s_group_names[] = {
+	{ M680X_GRP_INVALID, "<invalid>" },
+	{ M680X_GRP_JUMP,  "jump" },
+	{ M680X_GRP_CALL,  "call" },
+	{ M680X_GRP_RET, "return" },
+	{ M680X_GRP_INT, "interrupt" },
+	{ M680X_GRP_IRET,  "interrupt_return" },
+	{ M680X_GRP_PRIV,  "privileged" },
+	{ M680X_GRP_BRAREL,  "branch_relative" },
+};
+#endif
+
+static void printRegName(cs_struct *handle, SStream *OS, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	SStream_concat(OS, handle->reg_name((csh)handle, reg));
+#endif
+}
+
+static void printInstructionName(cs_struct *handle, SStream *OS,
+	unsigned int insn)
+{
+#ifndef CAPSTONE_DIET
+	SStream_concat(OS, handle->insn_name((csh)handle, insn));
+#endif
+}
+
+static uint32_t get_unsigned(int32_t value, int byte_size)
+{
+	switch (byte_size) {
+	case 1:
+		return (uint32_t)(value & 0xff);
+
+	case 2:
+		return (uint32_t)(value & 0xffff);
+
+	default:
+	case 4:
+		return (uint32_t)value;
+	}
+}
+
+static void printIncDec(bool isPost, SStream *O, m680x_info *info,
+	cs_m680x_op *op)
+{
+	static const char s_inc_dec[][3] = { "--", "-", "", "+", "++" };
+
+	if (!op->idx.inc_dec)
+		return;
+
+	if ((!isPost && !(op->idx.flags & M680X_IDX_POST_INC_DEC)) ||
+		(isPost && (op->idx.flags & M680X_IDX_POST_INC_DEC))) {
+		const char *prePostfix = "";
+
+		if (info->cpu_type == M680X_CPU_TYPE_CPU12)
+			prePostfix = (op->idx.inc_dec < 0) ? "-" : "+";
+		else if (op->idx.inc_dec >= -2 && (op->idx.inc_dec <= 2)) {
+			prePostfix = (char *)s_inc_dec[op->idx.inc_dec + 2];
+		}
+
+		SStream_concat(O, prePostfix);
+	}
+}
+
+static void printOperand(MCInst *MI, SStream *O, m680x_info *info,
+	cs_m680x_op *op)
+{
+	switch (op->type) {
+	case M680X_OP_REGISTER:
+		printRegName(MI->csh, O, op->reg);
+		break;
+
+	case M680X_OP_CONSTANT:
+		SStream_concat(O, "%u", op->const_val);
+		break;
+
+	case M680X_OP_IMMEDIATE:
+		if (MI->csh->imm_unsigned)
+			SStream_concat(O, "#%u",
+				get_unsigned(op->imm, op->size));
+		else
+			SStream_concat(O, "#%d", op->imm);
+
+		break;
+
+	case M680X_OP_INDEXED:
+		if (op->idx.flags & M680X_IDX_INDIRECT)
+			SStream_concat(O, "[");
+
+		if (op->idx.offset_reg != M680X_REG_INVALID)
+			printRegName(MI->csh, O, op->idx.offset_reg);
+		else if (op->idx.offset_bits > 0) {
+			if (op->idx.base_reg == M680X_REG_PC)
+				SStream_concat(O, "$%04X", op->idx.offset_addr);
+			else
+				SStream_concat(O, "%d", op->idx.offset);
+		}
+		else if (op->idx.inc_dec != 0 &&
+			info->cpu_type == M680X_CPU_TYPE_CPU12)
+			SStream_concat(O, "%d", abs(op->idx.inc_dec));
+
+		if (!(op->idx.flags & M680X_IDX_NO_COMMA))
+			SStream_concat(O, ",");
+
+		printIncDec(false, O, info, op);
+
+		printRegName(MI->csh, O, op->idx.base_reg);
+
+		if (op->idx.base_reg == M680X_REG_PC &&
+			(op->idx.offset_bits > 0))
+			SStream_concat(O, "R");
+
+		printIncDec(true, O, info, op);
+
+		if (op->idx.flags & M680X_IDX_INDIRECT)
+			SStream_concat(O, "]");
+
+		break;
+
+	case M680X_OP_RELATIVE:
+		SStream_concat(O, "$%04X", op->rel.address);
+		break;
+
+	case M680X_OP_DIRECT:
+		SStream_concat(O, "$%02X", op->direct_addr);
+		break;
+
+	case M680X_OP_EXTENDED:
+		if (op->ext.indirect)
+			SStream_concat(O, "[$%04X]", op->ext.address);
+		else {
+			if (op->ext.address < 256) {
+				SStream_concat(O, ">$%04X", op->ext.address);
+			}
+			else {
+				SStream_concat(O, "$%04X", op->ext.address);
+			}
+		}
+
+		break;
+
+	default:
+		SStream_concat(O, "<invalid_operand>");
+		break;
+	}
+}
+
+static const char *getDelimiter(m680x_info *info, cs_m680x *m680x)
+{
+	bool indexed = false;
+	int count = 0;
+	int i;
+
+	if (info->insn == M680X_INS_TFM)
+		return ",";
+
+	if (m680x->op_count > 1) {
+		for (i  = 0; i < m680x->op_count; ++i) {
+			if (m680x->operands[i].type == M680X_OP_INDEXED)
+				indexed = true;
+
+			if (m680x->operands[i].type != M680X_OP_REGISTER)
+				count++;
+		}
+	}
+
+	return (indexed && (count >= 1)) ? ";" : ",";
+};
+
+void M680X_printInst(MCInst *MI, SStream *O, void *PrinterInfo)
+{
+	m680x_info *info = (m680x_info *)PrinterInfo;
+	cs_m680x *m680x = &info->m680x;
+	cs_detail *detail = MI->flat_insn->detail;
+	int suppress_operands = 0;
+	const char *delimiter = getDelimiter(info, m680x);
+	int i;
+
+	if (detail != NULL)
+		memcpy(&detail->m680x, m680x, sizeof(cs_m680x));
+
+	if (info->insn == M680X_INS_INVLD || info->insn == M680X_INS_ILLGL) {
+		if (m680x->op_count)
+			SStream_concat(O, "fcb $%02X", m680x->operands[0].imm);
+		else
+			SStream_concat(O, "fcb $<unknown>");
+
+		return;
+	}
+
+	printInstructionName(MI->csh, O, info->insn);
+	SStream_concat(O, " ");
+
+	if ((m680x->flags & M680X_FIRST_OP_IN_MNEM) != 0)
+		suppress_operands++;
+
+	if ((m680x->flags & M680X_SECOND_OP_IN_MNEM) != 0)
+		suppress_operands++;
+
+	for (i  = 0; i < m680x->op_count; ++i) {
+		if (i >= suppress_operands) {
+			printOperand(MI, O, info, &m680x->operands[i]);
+
+			if ((i + 1) != m680x->op_count)
+				SStream_concat(O, delimiter);
+		}
+	}
+}
+
+const char *M680X_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+
+	if (reg >= ARR_SIZE(s_reg_names))
+		return NULL;
+
+	return s_reg_names[(int)reg];
+#else
+	return NULL;
+#endif
+}
+
+const char *M680X_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+
+	if (id >= ARR_SIZE(s_instruction_names))
+		return NULL;
+	else
+		return s_instruction_names[(int)id];
+
+#else
+	return NULL;
+#endif
+}
+
+const char *M680X_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(s_group_names, ARR_SIZE(s_group_names), id);
+#else
+	return NULL;
+#endif
+}
+
+cs_err M680X_instprinter_init(cs_struct *ud)
+{
+#ifndef CAPSTONE_DIET
+
+	if (M680X_REG_ENDING != ARR_SIZE(s_reg_names)) {
+		fprintf(stderr, "Internal error: Size mismatch in enum "
+			"m680x_reg and s_reg_names\n");
+
+		return CS_ERR_MODE;
+	}
+
+	if (M680X_INS_ENDING != ARR_SIZE(s_instruction_names)) {
+		fprintf(stderr, "Internal error: Size mismatch in enum "
+			"m680x_insn and s_instruction_names\n");
+
+		return CS_ERR_MODE;
+	}
+
+	if (M680X_GRP_ENDING != ARR_SIZE(s_group_names)) {
+		fprintf(stderr, "Internal error: Size mismatch in enum "
+			"m680x_group_type and s_group_names\n");
+
+		return CS_ERR_MODE;
+	}
+
+#endif
+
+	return CS_ERR_OK;
+}
+
+#endif
+

arch/M680X/M680XInstPrinter.h

@@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XINSTPRINTER_H
+#define CS_M680XINSTPRINTER_H
+
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+struct SStream;
+
+void M680X_init(MCRegisterInfo *MRI);
+
+void M680X_printInst(MCInst *MI, struct SStream *O, void *Info);
+const char *M680X_reg_name(csh handle, unsigned int reg);
+const char *M680X_insn_name(csh handle, unsigned int id);
+const char *M680X_group_name(csh handle, unsigned int id);
+void M680X_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm,
+	MCInst *mci);
+
+#endif
+
+

arch/M680X/M680XModule.c

@@ -0,0 +1,77 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifdef CAPSTONE_HAS_M680X
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "M680XDisassembler.h"
+#include "M680XDisassemblerInternals.h"
+#include "M680XInstPrinter.h"
+#include "M680XModule.h"
+
+cs_err M680X_global_init(cs_struct *ud)
+{
+	m680x_info *info;
+	cs_err errcode;
+
+	/* Do some validation checks */
+	errcode = M680X_disassembler_init(ud);
+
+	if (errcode != CS_ERR_OK)
+		return errcode;
+
+	errcode =  M680X_instprinter_init(ud);
+
+	if (errcode != CS_ERR_OK)
+		return errcode;
+
+	// verify if requested mode is valid
+	if (ud->mode & ~(CS_MODE_M680X_6800 | CS_MODE_M680X_6801 |
+			CS_MODE_M680X_6805 | CS_MODE_M680X_6808 |
+			CS_MODE_M680X_6809 | CS_MODE_M680X_6811 |
+			CS_MODE_M680X_6301 | CS_MODE_M680X_6309 |
+			CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08)) {
+		// At least one mode is not supported by M680X
+		return CS_ERR_MODE;
+	}
+
+	if (!(ud->mode & (CS_MODE_M680X_6800 | CS_MODE_M680X_6801 |
+				CS_MODE_M680X_6805 | CS_MODE_M680X_6808 |
+				CS_MODE_M680X_6809 | CS_MODE_M680X_6811 |
+				CS_MODE_M680X_6301 | CS_MODE_M680X_6309 |
+				CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08))) {
+		// At least the cpu type has to be selected. No default.
+		return CS_ERR_MODE;
+	}
+
+	info = cs_mem_malloc(sizeof(m680x_info));
+
+	if (!info)
+		return CS_ERR_MEM;
+
+	ud->printer = M680X_printInst;
+	ud->printer_info = info;
+	ud->getinsn_info = NULL;
+	ud->disasm = M680X_getInstruction;
+	ud->reg_name = M680X_reg_name;
+	ud->insn_id = M680X_get_insn_id;
+	ud->insn_name = M680X_insn_name;
+	ud->group_name = M680X_group_name;
+	ud->skipdata_size = 1;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = M680X_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	//TODO
+	return CS_ERR_OK;
+}
+
+#endif
+

arch/M680X/M680XModule.h

@@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_M680X_MODULE_H
+#define CS_M680X_MODULE_H
+
+#include "../../utils.h"
+
+cs_err M680X_global_init(cs_struct *ud);
+cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif

arch/M680X/cpu12.inc

@@ -0,0 +1,335 @@
+
+// CPU12 instructions on PAGE1
+static const inst_page1 g_cpu12_inst_page1_table[256] = {
+	// 0x0x
+	{ M680X_INS_BGND, inh_hid, inh_hid },
+	{ M680X_INS_MEM, inh_hid, inh_hid },
+	{ M680X_INS_INY, inh_hid, inh_hid },
+	{ M680X_INS_DEY, inh_hid, inh_hid },
+	{ M680X_INS_DBEQ, loop_hid, inh_hid }, // or DBNE/IBEQ/IBNE/TBEQ/TBNE
+	{ M680X_INS_JMP, idx12_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_INX, inh_hid, inh_hid },
+	{ M680X_INS_DEX, inh_hid, inh_hid },
+	{ M680X_INS_RTC, inh_hid, inh_hid },
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_BSET, idx12_hid, imm8_hid },
+	{ M680X_INS_BCLR, idx12_hid, imm8_hid },
+	{ M680X_INS_BRSET, idx12_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, idx12_hid, imm8rel_hid },
+	// 0x1x
+	{ M680X_INS_ANDCC, imm8_hid, inh_hid },
+	{ M680X_INS_EDIV, inh_hid, inh_hid },
+	{ M680X_INS_MUL, inh_hid, inh_hid },
+	{ M680X_INS_EMUL, inh_hid, inh_hid },
+	{ M680X_INS_ORCC, imm8_hid, inh_hid },
+	{ M680X_INS_JSR, idx12_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_JSR, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LEAY, idx12_hid, inh_hid },
+	{ M680X_INS_LEAX, idx12_hid, inh_hid },
+	{ M680X_INS_LEAS, idx12_hid, inh_hid },
+	{ M680X_INS_BSET, ext_hid, imm8_hid },
+	{ M680X_INS_BCLR, ext_hid, imm8_hid },
+	{ M680X_INS_BRSET, ext_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, ext_hid, imm8rel_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_BRN, rel8_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BVC, rel8_hid, inh_hid },
+	{ M680X_INS_BVS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BGE, rel8_hid, inh_hid },
+	{ M680X_INS_BLT, rel8_hid, inh_hid },
+	{ M680X_INS_BGT, rel8_hid, inh_hid },
+	{ M680X_INS_BLE, rel8_hid, inh_hid },
+	// 0x3x
+	{ M680X_INS_PULX, inh_hid, inh_hid },
+	{ M680X_INS_PULY, inh_hid, inh_hid },
+	{ M680X_INS_PULA, inh_hid, inh_hid },
+	{ M680X_INS_PULB, inh_hid, inh_hid },
+	{ M680X_INS_PSHX, inh_hid, inh_hid },
+	{ M680X_INS_PSHY, inh_hid, inh_hid },
+	{ M680X_INS_PSHA, inh_hid, inh_hid },
+	{ M680X_INS_PSHB, inh_hid, inh_hid },
+	{ M680X_INS_PULC, inh_hid, inh_hid },
+	{ M680X_INS_PSHC, inh_hid, inh_hid },
+	{ M680X_INS_PULD, inh_hid, inh_hid },
+	{ M680X_INS_PSHD, inh_hid, inh_hid },
+	{ M680X_INS_WAVR, inh_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_WAI, inh_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	// 0x4x
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_ASLA, inh_hid, inh_hid },
+	{ M680X_INS_LSRD, inh_hid, inh_hid },
+	{ M680X_INS_CALL, ext_hid, index_hid },
+	{ M680X_INS_CALL, idx12_hid, index_hid },
+	{ M680X_INS_BSET, dir_hid, imm8_hid },
+	{ M680X_INS_BCLR, dir_hid, imm8_hid },
+	{ M680X_INS_BRSET, dir_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, dir_hid, imm8rel_hid },
+	// 0x5x
+	{ M680X_INS_NEGB, inh_hid, inh_hid },
+	{ M680X_INS_COMB, inh_hid, inh_hid },
+	{ M680X_INS_INCB, inh_hid, inh_hid },
+	{ M680X_INS_DECB, inh_hid, inh_hid },
+	{ M680X_INS_LSRB, inh_hid, inh_hid },
+	{ M680X_INS_ROLB, inh_hid, inh_hid },
+	{ M680X_INS_RORB, inh_hid, inh_hid },
+	{ M680X_INS_ASRB, inh_hid, inh_hid },
+	{ M680X_INS_ASLB, inh_hid, inh_hid },
+	{ M680X_INS_ASLD, inh_hid, inh_hid },
+	{ M680X_INS_STAA, dir_hid, inh_hid },
+	{ M680X_INS_STAB, dir_hid, inh_hid },
+	{ M680X_INS_STD, dir_hid, inh_hid },
+	{ M680X_INS_STY, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	{ M680X_INS_STS, dir_hid, inh_hid },
+	// 0x6x
+	{ M680X_INS_NEG, idx12_hid, inh_hid },
+	{ M680X_INS_COM, idx12_hid, inh_hid },
+	{ M680X_INS_INC, idx12_hid, inh_hid },
+	{ M680X_INS_DEC, idx12_hid, inh_hid },
+	{ M680X_INS_LSR, idx12_hid, inh_hid },
+	{ M680X_INS_ROL, idx12_hid, inh_hid },
+	{ M680X_INS_ROR, idx12_hid, inh_hid },
+	{ M680X_INS_ASR, idx12_hid, inh_hid },
+	{ M680X_INS_ASL, idx12_hid, inh_hid },
+	{ M680X_INS_CLR, idx12_hid, inh_hid },
+	{ M680X_INS_STAA, idx12_hid, inh_hid },
+	{ M680X_INS_STAB, idx12_hid, inh_hid },
+	{ M680X_INS_STD, idx12_hid, inh_hid },
+	{ M680X_INS_STY, idx12_hid, inh_hid },
+	{ M680X_INS_STX, idx12_hid, inh_hid },
+	{ M680X_INS_STS, idx12_hid, inh_hid },
+	// 0x7x
+	{ M680X_INS_NEG, ext_hid, inh_hid },
+	{ M680X_INS_COM, ext_hid, inh_hid },
+	{ M680X_INS_INC, ext_hid, inh_hid },
+	{ M680X_INS_DEC, ext_hid, inh_hid },
+	{ M680X_INS_LSR, ext_hid, inh_hid },
+	{ M680X_INS_ROL, ext_hid, inh_hid },
+	{ M680X_INS_ROR, ext_hid, inh_hid },
+	{ M680X_INS_ASR, ext_hid, inh_hid },
+	{ M680X_INS_ASL, ext_hid, inh_hid },
+	{ M680X_INS_CLR, ext_hid, inh_hid },
+	{ M680X_INS_STAA, ext_hid, inh_hid },
+	{ M680X_INS_STAB, ext_hid, inh_hid },
+	{ M680X_INS_STD, ext_hid, inh_hid },
+	{ M680X_INS_STY, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+	{ M680X_INS_STS, ext_hid, inh_hid },
+	// 0x8x
+	{ M680X_INS_SUBA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPA, imm8_hid, inh_hid },
+	{ M680X_INS_SBCA, imm8_hid, inh_hid },
+	{ M680X_INS_SUBD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDA, imm8_hid, inh_hid },
+	{ M680X_INS_BITA, imm8_hid, inh_hid },
+	{ M680X_INS_LDAA, imm8_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	{ M680X_INS_EORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADCA, imm8_hid, inh_hid },
+	{ M680X_INS_ORAA, imm8_hid, inh_hid },
+	{ M680X_INS_ADDA, imm8_hid, inh_hid },
+	{ M680X_INS_CPD, imm16_hid, inh_hid },
+	{ M680X_INS_CPY, imm16_hid, inh_hid },
+	{ M680X_INS_CPX, imm16_hid, inh_hid },
+	{ M680X_INS_CPS, imm16_hid, inh_hid },
+	// 0x9x
+	{ M680X_INS_SUBA, dir_hid, inh_hid },
+	{ M680X_INS_CMPA, dir_hid, inh_hid },
+	{ M680X_INS_SBCA, dir_hid, inh_hid },
+	{ M680X_INS_SUBD, dir_hid, inh_hid },
+	{ M680X_INS_ANDA, dir_hid, inh_hid },
+	{ M680X_INS_BITA, dir_hid, inh_hid },
+	{ M680X_INS_LDAA, dir_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_EORA, dir_hid, inh_hid },
+	{ M680X_INS_ADCA, dir_hid, inh_hid },
+	{ M680X_INS_ORAA, dir_hid, inh_hid },
+	{ M680X_INS_ADDA, dir_hid, inh_hid },
+	{ M680X_INS_CPD, dir_hid, inh_hid },
+	{ M680X_INS_CPY, dir_hid, inh_hid },
+	{ M680X_INS_CPX, dir_hid, inh_hid },
+	{ M680X_INS_CPS, dir_hid, inh_hid },
+	// 0xAx
+	{ M680X_INS_SUBA, idx12_hid, inh_hid },
+	{ M680X_INS_CMPA, idx12_hid, inh_hid },
+	{ M680X_INS_SBCA, idx12_hid, inh_hid },
+	{ M680X_INS_SUBD, idx12_hid, inh_hid },
+	{ M680X_INS_ANDA, idx12_hid, inh_hid },
+	{ M680X_INS_BITA, idx12_hid, inh_hid },
+	{ M680X_INS_LDAA, idx12_hid, inh_hid },
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_EORA, idx12_hid, inh_hid },
+	{ M680X_INS_ADCA, idx12_hid, inh_hid },
+	{ M680X_INS_ORAA, idx12_hid, inh_hid },
+	{ M680X_INS_ADDA, idx12_hid, inh_hid },
+	{ M680X_INS_CPD, idx12_hid, inh_hid },
+	{ M680X_INS_CPY, idx12_hid, inh_hid },
+	{ M680X_INS_CPX, idx12_hid, inh_hid },
+	{ M680X_INS_CPS, idx12_hid, inh_hid },
+	// 0xBx
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_SUBD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_TFR, rr12_hid, inh_hid }, // or EXG
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_CPD, ext_hid, inh_hid },
+	{ M680X_INS_CPY, ext_hid, inh_hid },
+	{ M680X_INS_CPX, ext_hid, inh_hid },
+	{ M680X_INS_CPS, ext_hid, inh_hid },
+	// 0xCx
+	{ M680X_INS_SUBB, imm8_hid, inh_hid },
+	{ M680X_INS_CMPB, imm8_hid, inh_hid },
+	{ M680X_INS_SBCB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDB, imm8_hid, inh_hid },
+	{ M680X_INS_BITB, imm8_hid, inh_hid },
+	{ M680X_INS_LDAB, imm8_hid, inh_hid },
+	{ M680X_INS_CLRB, inh_hid, inh_hid },
+	{ M680X_INS_EORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADCB, imm8_hid, inh_hid },
+	{ M680X_INS_ORAB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDB, imm8_hid, inh_hid },
+	{ M680X_INS_LDD, imm16_hid, inh_hid },
+	{ M680X_INS_LDY, imm16_hid, inh_hid },
+	{ M680X_INS_LDX, imm16_hid, inh_hid },
+	{ M680X_INS_LDS, imm16_hid, inh_hid },
+	// 0xDx
+	{ M680X_INS_SUBB, dir_hid, inh_hid },
+	{ M680X_INS_CMPB, dir_hid, inh_hid },
+	{ M680X_INS_SBCB, dir_hid, inh_hid },
+	{ M680X_INS_ADDD, dir_hid, inh_hid },
+	{ M680X_INS_ANDB, dir_hid, inh_hid },
+	{ M680X_INS_BITB, dir_hid, inh_hid },
+	{ M680X_INS_LDAB, dir_hid, inh_hid },
+	{ M680X_INS_TSTB, inh_hid, inh_hid },
+	{ M680X_INS_EORB, dir_hid, inh_hid },
+	{ M680X_INS_ADCB, dir_hid, inh_hid },
+	{ M680X_INS_ORAB, dir_hid, inh_hid },
+	{ M680X_INS_ADDB, dir_hid, inh_hid },
+	{ M680X_INS_LDD, dir_hid, inh_hid },
+	{ M680X_INS_LDY, dir_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_LDS, dir_hid, inh_hid },
+	// 0xEx
+	{ M680X_INS_SUBB, idx12_hid, inh_hid },
+	{ M680X_INS_CMPB, idx12_hid, inh_hid },
+	{ M680X_INS_SBCB, idx12_hid, inh_hid },
+	{ M680X_INS_ADDD, idx12_hid, inh_hid },
+	{ M680X_INS_ANDB, idx12_hid, inh_hid },
+	{ M680X_INS_BITB, idx12_hid, inh_hid },
+	{ M680X_INS_LDAB, idx12_hid, inh_hid },
+	{ M680X_INS_TST, idx12_hid, inh_hid },
+	{ M680X_INS_EORB, idx12_hid, inh_hid },
+	{ M680X_INS_ADCB, idx12_hid, inh_hid },
+	{ M680X_INS_ORAB, idx12_hid, inh_hid },
+	{ M680X_INS_ADDB, idx12_hid, inh_hid },
+	{ M680X_INS_LDD, idx12_hid, inh_hid },
+	{ M680X_INS_LDY, idx12_hid, inh_hid },
+	{ M680X_INS_LDX, idx12_hid, inh_hid },
+	{ M680X_INS_LDS, idx12_hid, inh_hid },
+	// 0xFx
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_ADDD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_TST, ext_hid, inh_hid },
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_LDD, ext_hid, inh_hid },
+	{ M680X_INS_LDY, ext_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_LDS, ext_hid, inh_hid },
+};
+
+// CPU12 instructions on PAGE2
+static const inst_pageX g_cpu12_inst_page2_table[] = {
+	{ 0x00, M680X_INS_MOVW, imm16i12x_hid, inh_hid },
+	{ 0x01, M680X_INS_MOVW, exti12x_hid, inh_hid },
+	{ 0x02, M680X_INS_MOVW, idx12_hid, idx12_hid },
+	{ 0x03, M680X_INS_MOVW, imm16_hid,  ext_hid },
+	{ 0x04, M680X_INS_MOVW, ext_hid, ext_hid },
+	{ 0x05, M680X_INS_MOVW, idx12_hid, ext_hid },
+	{ 0x06, M680X_INS_ABA, inh_hid, inh_hid },
+	{ 0x07, M680X_INS_DAA, inh_hid, inh_hid },
+	{ 0x08, M680X_INS_MOVB, imm8i12x_hid, inh_hid },
+	{ 0x09, M680X_INS_MOVB, exti12x_hid, inh_hid },
+	{ 0x0a, M680X_INS_MOVB, idx12_hid, idx12_hid },
+	{ 0x0b, M680X_INS_MOVB, imm8_hid, ext_hid },
+	{ 0x0c, M680X_INS_MOVB, ext_hid, ext_hid },
+	{ 0x0d, M680X_INS_MOVB, idx12_hid, ext_hid },
+	{ 0x0e, M680X_INS_TAB, inh_hid, inh_hid },
+	{ 0x0f, M680X_INS_TBA, inh_hid, inh_hid },
+	{ 0x10, M680X_INS_IDIV, inh_hid, inh_hid },
+	{ 0x11, M680X_INS_FDIV, inh_hid, inh_hid },
+	{ 0x12, M680X_INS_EMACS, ext_hid, inh_hid },
+	{ 0x13, M680X_INS_EMULS, inh_hid, inh_hid },
+	{ 0x14, M680X_INS_EDIVS, inh_hid, inh_hid },
+	{ 0x15, M680X_INS_IDIVS, inh_hid, inh_hid },
+	{ 0x16, M680X_INS_SBA, inh_hid, inh_hid },
+	{ 0x17, M680X_INS_CBA, inh_hid, inh_hid },
+	{ 0x18, M680X_INS_MAXA, idx12_hid, inh_hid },
+	{ 0x19, M680X_INS_MINA, idx12_hid, inh_hid },
+	{ 0x1a, M680X_INS_EMAXD, idx12_hid, inh_hid },
+	{ 0x1b, M680X_INS_EMIND, idx12_hid, inh_hid },
+	{ 0x1c, M680X_INS_MAXM, idx12_hid, inh_hid },
+	{ 0x1d, M680X_INS_MINM, idx12_hid, inh_hid },
+	{ 0x1e, M680X_INS_EMAXM, idx12_hid, inh_hid },
+	{ 0x1f, M680X_INS_EMINM, idx12_hid, inh_hid },
+	{ 0x20, M680X_INS_LBRA, rel16_hid, inh_hid },
+	{ 0x21, M680X_INS_LBRN, rel16_hid, inh_hid },
+	{ 0x22, M680X_INS_LBHI, rel16_hid, inh_hid },
+	{ 0x23, M680X_INS_LBLS, rel16_hid, inh_hid },
+	{ 0x24, M680X_INS_LBCC, rel16_hid, inh_hid },
+	{ 0x25, M680X_INS_LBCS, rel16_hid, inh_hid },
+	{ 0x26, M680X_INS_LBNE, rel16_hid, inh_hid },
+	{ 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid },
+	{ 0x28, M680X_INS_LBVC, rel16_hid, inh_hid },
+	{ 0x29, M680X_INS_LBVS, rel16_hid, inh_hid },
+	{ 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid },
+	{ 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid },
+	{ 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid },
+	{ 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid },
+	{ 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid },
+	{ 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid },
+	{ 0x3a, M680X_INS_REV, inh_hid, inh_hid },
+	{ 0x3b, M680X_INS_REVW, inh_hid, inh_hid },
+	{ 0x3c, M680X_INS_WAV, inh_hid, inh_hid },
+	{ 0x3d, M680X_INS_TBL, idx12s_hid, inh_hid },
+	{ 0x3e, M680X_INS_STOP, inh_hid, inh_hid },
+	{ 0x3f, M680X_INS_ETBL, idx12s_hid, inh_hid },
+};
+

arch/M680X/hcs08.inc

@@ -0,0 +1,60 @@
+
+// Additional instructions only supported on HCS08
+static const inst_pageX g_hcs08_inst_overlay_table[] = {
+	{ 0x32, M680X_INS_LDHX, ext_hid, inh_hid },
+	{ 0x3e, M680X_INS_CPHX, ext_hid, inh_hid },
+	{ 0x82, M680X_INS_BGND, inh_hid, inh_hid },
+	{ 0x96, M680X_INS_STHX, ext_hid, inh_hid },
+};
+
+// HCS08 PAGE2 instructions (prefix 0x9E)
+static const inst_pageX g_hcs08_inst_page2_table[] = {
+	{ 0x60, M680X_INS_NEG, idxS_hid, inh_hid },
+	{ 0x61, M680X_INS_CBEQ, idxS_hid,rel8_hid },
+	{ 0x63, M680X_INS_COM, idxS_hid, inh_hid },
+	{ 0x64, M680X_INS_LSR, idxS_hid, inh_hid },
+	{ 0x66, M680X_INS_ROR, idxS_hid, inh_hid },
+	{ 0x67, M680X_INS_ASR, idxS_hid, inh_hid },
+	{ 0x68, M680X_INS_LSL, idxS_hid, inh_hid },
+	{ 0x69, M680X_INS_ROL, idxS_hid, inh_hid },
+	{ 0x6a, M680X_INS_DEC, idxS_hid, inh_hid },
+	{ 0x6b, M680X_INS_DBNZ, idxS_hid,rel8_hid },
+	{ 0x6c, M680X_INS_INC, idxS_hid, inh_hid },
+	{ 0x6d, M680X_INS_TST, idxS_hid, inh_hid },
+	{ 0x6f, M680X_INS_CLR, idxS_hid, inh_hid },
+	{ 0xae, M680X_INS_LDHX, idxX0_hid, inh_hid },
+	{ 0xbe, M680X_INS_LDHX, idxX16_hid, inh_hid },
+	{ 0xce, M680X_INS_LDHX, idxX_hid, inh_hid },
+	{ 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid },
+	{ 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid },
+	{ 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid },
+	{ 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid },
+	{ 0xd4, M680X_INS_AND, idxS16_hid, inh_hid },
+	{ 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid },
+	{ 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid },
+	{ 0xd7, M680X_INS_STA, idxS16_hid, inh_hid },
+	{ 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid },
+	{ 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid },
+	{ 0xda, M680X_INS_ORA, idxS16_hid, inh_hid },
+	{ 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid },
+	{ 0xde, M680X_INS_LDX, idxS16_hid, inh_hid },
+	{ 0xdf, M680X_INS_STX, idxS16_hid, inh_hid },
+	{ 0xe0, M680X_INS_SUB, idxS_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMP, idxS_hid, inh_hid },
+	{ 0xe2, M680X_INS_SBC, idxS_hid, inh_hid },
+	{ 0xe3, M680X_INS_CPX, idxS_hid, inh_hid },
+	{ 0xe4, M680X_INS_AND, idxS_hid, inh_hid },
+	{ 0xe5, M680X_INS_BIT, idxS_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDA, idxS_hid, inh_hid },
+	{ 0xe7, M680X_INS_STA, idxS_hid, inh_hid },
+	{ 0xe8, M680X_INS_EOR, idxS_hid, inh_hid },
+	{ 0xe9, M680X_INS_ADC, idxS_hid, inh_hid },
+	{ 0xea, M680X_INS_ORA, idxS_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADD, idxS_hid, inh_hid },
+	{ 0xee, M680X_INS_LDX, idxS_hid, inh_hid },
+	{ 0xef, M680X_INS_STX, idxS_hid, inh_hid },
+	{ 0xf3, M680X_INS_CPHX, idxS_hid, inh_hid },
+	{ 0xfe, M680X_INS_LDHX, idxS_hid, inh_hid },
+	{ 0xff, M680X_INS_STHX, idxS_hid, inh_hid },
+};
+

arch/M680X/hd6301.inc

@@ -0,0 +1,15 @@
+
+// Additional instructions only supported on HD6301/3
+static const inst_pageX g_hd6301_inst_overlay_table[] = {
+	{ 0x18, M680X_INS_XGDX, inh_hid, inh_hid },
+	{ 0x1a, M680X_INS_SLP, inh_hid, inh_hid },
+	{ 0x61, M680X_INS_AIM, imm8_hid, idxX_hid },
+	{ 0x62, M680X_INS_OIM, imm8_hid, idxX_hid },
+	{ 0x65, M680X_INS_EIM, imm8_hid, idxX_hid },
+	{ 0x6B, M680X_INS_TIM, imm8_hid, idxX_hid },
+	{ 0x71, M680X_INS_AIM, imm8_hid, dir_hid },
+	{ 0x72, M680X_INS_OIM, imm8_hid, dir_hid },
+	{ 0x75, M680X_INS_EIM, imm8_hid, dir_hid },
+	{ 0x7B, M680X_INS_TIM, imm8_hid, dir_hid },
+};
+

arch/M680X/hd6309.inc

@@ -0,0 +1,259 @@
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// Additional instructions only supported on HD6309 PAGE1
+static const inst_pageX g_hd6309_inst_overlay_table[] = {
+	{ 0x01, M680X_INS_OIM, imm8_hid, dir_hid },
+	{ 0x02, M680X_INS_AIM, imm8_hid, dir_hid },
+	{ 0x05, M680X_INS_EIM, imm8_hid, dir_hid },
+	{ 0x0B, M680X_INS_TIM, imm8_hid, dir_hid },
+	{ 0x14, M680X_INS_SEXW, inh_hid, inh_hid },
+	{ 0x61, M680X_INS_OIM, imm8_hid, idx09_hid },
+	{ 0x62, M680X_INS_AIM, imm8_hid, idx09_hid },
+	{ 0x65, M680X_INS_EIM, imm8_hid, idx09_hid },
+	{ 0x6B, M680X_INS_TIM, imm8_hid, idx09_hid },
+	{ 0x71, M680X_INS_OIM, imm8_hid, ext_hid },
+	{ 0x72, M680X_INS_AIM, imm8_hid, ext_hid },
+	{ 0x75, M680X_INS_EIM, imm8_hid, ext_hid },
+	{ 0x7B, M680X_INS_TIM, imm8_hid, ext_hid },
+	{ 0xCD, M680X_INS_LDQ, imm32_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// HD6309 PAGE2 instructions (with prefix 0x10)
+static const inst_pageX g_hd6309_inst_page2_table[] = {
+	// 0x2x, relative long branch instructions
+	{ 0x21, M680X_INS_LBRN, rel16_hid, inh_hid },
+	{ 0x22, M680X_INS_LBHI, rel16_hid, inh_hid },
+	{ 0x23, M680X_INS_LBLS, rel16_hid, inh_hid },
+	{ 0x24, M680X_INS_LBCC, rel16_hid, inh_hid },
+	{ 0x25, M680X_INS_LBCS, rel16_hid, inh_hid },
+	{ 0x26, M680X_INS_LBNE, rel16_hid, inh_hid },
+	{ 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid },
+	{ 0x28, M680X_INS_LBVC, rel16_hid, inh_hid },
+	{ 0x29, M680X_INS_LBVS, rel16_hid, inh_hid },
+	{ 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid },
+	{ 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid },
+	{ 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid },
+	{ 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid },
+	{ 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid },
+	{ 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid },
+	// 0x3x
+	{ 0x30, M680X_INS_ADDR, rr09_hid, inh_hid },
+	{ 0x31, M680X_INS_ADCR, rr09_hid, inh_hid },
+	{ 0x32, M680X_INS_SUBR, rr09_hid, inh_hid },
+	{ 0x33, M680X_INS_SBCR, rr09_hid, inh_hid },
+	{ 0x34, M680X_INS_ANDR, rr09_hid, inh_hid },
+	{ 0x35, M680X_INS_ORR, rr09_hid, inh_hid },
+	{ 0x36, M680X_INS_EORR, rr09_hid, inh_hid },
+	{ 0x37, M680X_INS_CMPR, rr09_hid, inh_hid },
+	{ 0x38, M680X_INS_PSHSW, inh_hid, inh_hid },
+	{ 0x39, M680X_INS_PULSW, inh_hid, inh_hid },
+	{ 0x3a, M680X_INS_PSHUW, inh_hid, inh_hid },
+	{ 0x3b, M680X_INS_PULUW, inh_hid, inh_hid },
+	{ 0x3f, M680X_INS_SWI2, inh_hid, inh_hid },
+	// 0x4x, Register D instructions
+	{ 0x40, M680X_INS_NEGD, inh_hid, inh_hid },
+	{ 0x43, M680X_INS_COMD, inh_hid, inh_hid },
+	{ 0x44, M680X_INS_LSRD, inh_hid, inh_hid },
+	{ 0x46, M680X_INS_RORD, inh_hid, inh_hid },
+	{ 0x47, M680X_INS_ASRD, inh_hid, inh_hid },
+	{ 0x48, M680X_INS_LSLD, inh_hid, inh_hid },
+	{ 0x49, M680X_INS_ROLD, inh_hid, inh_hid },
+	{ 0x4a, M680X_INS_DECD, inh_hid, inh_hid },
+	{ 0x4c, M680X_INS_INCD, inh_hid, inh_hid },
+	{ 0x4d, M680X_INS_TSTD, inh_hid, inh_hid },
+	{ 0x4f, M680X_INS_CLRD, inh_hid, inh_hid },
+	// 0x5x, Register W instructions
+	{ 0x53, M680X_INS_COMW, inh_hid, inh_hid },
+	{ 0x54, M680X_INS_LSRW, inh_hid, inh_hid },
+	{ 0x56, M680X_INS_RORW, inh_hid, inh_hid },
+	{ 0x59, M680X_INS_ROLW, inh_hid, inh_hid },
+	{ 0x5a, M680X_INS_DECW, inh_hid, inh_hid },
+	{ 0x5c, M680X_INS_INCW, inh_hid, inh_hid },
+	{ 0x5d, M680X_INS_TSTW, inh_hid, inh_hid },
+	{ 0x5f, M680X_INS_CLRW, inh_hid, inh_hid },
+	// 0x8x, immediate instructionY with register D,W,Y
+	{ 0x80, M680X_INS_SUBW, imm16_hid, inh_hid },
+	{ 0x81, M680X_INS_CMPW, imm16_hid, inh_hid },
+	{ 0x82, M680X_INS_SBCD, imm16_hid, inh_hid },
+	{ 0x83, M680X_INS_CMPD, imm16_hid, inh_hid },
+	{ 0x84, M680X_INS_ANDD, imm16_hid, inh_hid },
+	{ 0x85, M680X_INS_BITD, imm16_hid, inh_hid },
+	{ 0x86, M680X_INS_LDW, imm16_hid, inh_hid },
+	{ 0x88, M680X_INS_EORD, imm16_hid, inh_hid },
+	{ 0x89, M680X_INS_ADCD, imm16_hid, inh_hid },
+	{ 0x8a, M680X_INS_ORD, imm16_hid, inh_hid },
+	{ 0x8b, M680X_INS_ADDW, imm16_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid },
+	{ 0x8e, M680X_INS_LDY, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register D,W,Y
+	{ 0x90, M680X_INS_SUBW, dir_hid, inh_hid },
+	{ 0x91, M680X_INS_CMPW, dir_hid, inh_hid },
+	{ 0x92, M680X_INS_SBCD, dir_hid, inh_hid },
+	{ 0x93, M680X_INS_CMPD, dir_hid, inh_hid },
+	{ 0x94, M680X_INS_ANDD, dir_hid, inh_hid },
+	{ 0x95, M680X_INS_BITD, dir_hid, inh_hid },
+	{ 0x96, M680X_INS_LDW, dir_hid, inh_hid },
+	{ 0x97, M680X_INS_STW, dir_hid, inh_hid },
+	{ 0x98, M680X_INS_EORD, dir_hid, inh_hid },
+	{ 0x99, M680X_INS_ADCD, dir_hid, inh_hid },
+	{ 0x9a, M680X_INS_ORD, dir_hid, inh_hid },
+	{ 0x9b, M680X_INS_ADDW, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPY, dir_hid, inh_hid },
+	{ 0x9e, M680X_INS_LDY, dir_hid, inh_hid },
+	{ 0x9f, M680X_INS_STY, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register D,W,Y
+	{ 0xa0, M680X_INS_SUBW, idx09_hid, inh_hid },
+	{ 0xa1, M680X_INS_CMPW, idx09_hid, inh_hid },
+	{ 0xa2, M680X_INS_SBCD, idx09_hid, inh_hid },
+	{ 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid },
+	{ 0xa4, M680X_INS_ANDD, idx09_hid, inh_hid },
+	{ 0xa5, M680X_INS_BITD, idx09_hid, inh_hid },
+	{ 0xa6, M680X_INS_LDW, idx09_hid, inh_hid },
+	{ 0xa7, M680X_INS_STW, idx09_hid, inh_hid },
+	{ 0xa8, M680X_INS_EORD, idx09_hid, inh_hid },
+	{ 0xa9, M680X_INS_ADCD, idx09_hid, inh_hid },
+	{ 0xaa, M680X_INS_ORD, idx09_hid, inh_hid },
+	{ 0xab, M680X_INS_ADDW, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPY, idx09_hid, inh_hid },
+	{ 0xae, M680X_INS_LDY, idx09_hid, inh_hid },
+	{ 0xaf, M680X_INS_STY, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register D,W,Y
+	{ 0xb0, M680X_INS_SUBW, ext_hid, inh_hid },
+	{ 0xb1, M680X_INS_CMPW, ext_hid, inh_hid },
+	{ 0xb2, M680X_INS_SBCD, ext_hid, inh_hid },
+	{ 0xb3, M680X_INS_CMPD, ext_hid, inh_hid },
+	{ 0xb4, M680X_INS_ANDD, ext_hid, inh_hid },
+	{ 0xb5, M680X_INS_BITD, ext_hid, inh_hid },
+	{ 0xb6, M680X_INS_LDW, ext_hid, inh_hid },
+	{ 0xb7, M680X_INS_STW, ext_hid, inh_hid },
+	{ 0xb8, M680X_INS_EORD, ext_hid, inh_hid },
+	{ 0xb9, M680X_INS_ADCD, ext_hid, inh_hid },
+	{ 0xba, M680X_INS_ORD, ext_hid, inh_hid },
+	{ 0xbb, M680X_INS_ADDW, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPY, ext_hid, inh_hid },
+	{ 0xbe, M680X_INS_LDY, ext_hid, inh_hid },
+	{ 0xbf, M680X_INS_STY, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register S
+	{ 0xce, M680X_INS_LDS, imm16_hid, inh_hid },
+	// 0xDx, direct instructions with register S,Q
+	{ 0xdc, M680X_INS_LDQ, dir_hid, inh_hid },
+	{ 0xdd, M680X_INS_STQ, dir_hid, inh_hid },
+	{ 0xde, M680X_INS_LDS, dir_hid, inh_hid },
+	{ 0xdf, M680X_INS_STS, dir_hid, inh_hid },
+	// 0xEx, indexed instructions with register S,Q
+	{ 0xec, M680X_INS_LDQ, idx09_hid, inh_hid },
+	{ 0xed, M680X_INS_STQ, idx09_hid, inh_hid },
+	{ 0xee, M680X_INS_LDS, idx09_hid, inh_hid },
+	{ 0xef, M680X_INS_STS, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register S,Q
+	{ 0xfc, M680X_INS_LDQ, ext_hid, inh_hid },
+	{ 0xfd, M680X_INS_STQ, ext_hid, inh_hid },
+	{ 0xfe, M680X_INS_LDS, ext_hid, inh_hid },
+	{ 0xff, M680X_INS_STS, ext_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// HD6309 PAGE3 instructions (with prefix 0x11)
+static const inst_pageX g_hd6309_inst_page3_table[] = {
+	{ 0x30, M680X_INS_BAND, bitmv_hid, inh_hid },
+	{ 0x31, M680X_INS_BIAND, bitmv_hid, inh_hid },
+	{ 0x32, M680X_INS_BOR, bitmv_hid, inh_hid },
+	{ 0x33, M680X_INS_BIOR, bitmv_hid, inh_hid },
+	{ 0x34, M680X_INS_BEOR, bitmv_hid, inh_hid },
+	{ 0x35, M680X_INS_BIEOR, bitmv_hid, inh_hid },
+	{ 0x36, M680X_INS_LDBT, bitmv_hid, inh_hid },
+	{ 0x37, M680X_INS_STBT, bitmv_hid, inh_hid },
+	{ 0x38, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x39, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x3a, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x3b, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x3c, M680X_INS_BITMD, imm8_hid, inh_hid },
+	{ 0x3d, M680X_INS_LDMD, imm8_hid, inh_hid },
+	{ 0x3f, M680X_INS_SWI3, inh_hid, inh_hid },
+	// 0x4x, Register E instructions
+	{ 0x43, M680X_INS_COME, inh_hid, inh_hid },
+	{ 0x4a, M680X_INS_DECE, inh_hid, inh_hid },
+	{ 0x4c, M680X_INS_INCE, inh_hid, inh_hid },
+	{ 0x4d, M680X_INS_TSTE, inh_hid, inh_hid },
+	{ 0x4f, M680X_INS_CLRE, inh_hid, inh_hid },
+	// 0x5x, Register F instructions
+	{ 0x53, M680X_INS_COMF, inh_hid, inh_hid },
+	{ 0x5a, M680X_INS_DECF, inh_hid, inh_hid },
+	{ 0x5c, M680X_INS_INCF, inh_hid, inh_hid },
+	{ 0x5d, M680X_INS_TSTF, inh_hid, inh_hid },
+	{ 0x5f, M680X_INS_CLRF, inh_hid, inh_hid },
+	// 0x8x, immediate instructions with register U,S,E
+	{ 0x80, M680X_INS_SUBE, imm8_hid, inh_hid },
+	{ 0x81, M680X_INS_CMPE, imm8_hid, inh_hid },
+	{ 0x83, M680X_INS_CMPU, imm16_hid, inh_hid },
+	{ 0x86, M680X_INS_LDE, imm8_hid, inh_hid },
+	{ 0x8b, M680X_INS_ADDE, imm8_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid },
+	{ 0x8d, M680X_INS_DIVD, imm8_hid, inh_hid },
+	{ 0x8e, M680X_INS_DIVQ, imm16_hid, inh_hid },
+	{ 0x8f, M680X_INS_MULD, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register U,S,E,Q
+	{ 0x90, M680X_INS_SUBE, dir_hid, inh_hid },
+	{ 0x91, M680X_INS_CMPE, dir_hid, inh_hid },
+	{ 0x93, M680X_INS_CMPU, dir_hid, inh_hid },
+	{ 0x96, M680X_INS_LDE, dir_hid, inh_hid },
+	{ 0x97, M680X_INS_STE, dir_hid, inh_hid },
+	{ 0x9b, M680X_INS_ADDE, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPS, dir_hid, inh_hid },
+	{ 0x9d, M680X_INS_DIVD, dir_hid, inh_hid },
+	{ 0x9e, M680X_INS_DIVQ, dir_hid, inh_hid },
+	{ 0x9f, M680X_INS_MULD, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register U,S,D,Q
+	{ 0xa0, M680X_INS_SUBE, idx09_hid, inh_hid },
+	{ 0xa1, M680X_INS_CMPE, idx09_hid, inh_hid },
+	{ 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid },
+	{ 0xa6, M680X_INS_LDE, idx09_hid, inh_hid },
+	{ 0xa7, M680X_INS_STE, idx09_hid, inh_hid },
+	{ 0xab, M680X_INS_ADDE, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPS, idx09_hid, inh_hid },
+	{ 0xad, M680X_INS_DIVD, idx09_hid, inh_hid },
+	{ 0xae, M680X_INS_DIVQ, idx09_hid, inh_hid },
+	{ 0xaf, M680X_INS_MULD, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register U,S,D,Q
+	{ 0xb0, M680X_INS_SUBE, ext_hid, inh_hid },
+	{ 0xb1, M680X_INS_CMPE, ext_hid, inh_hid },
+	{ 0xb3, M680X_INS_CMPU, ext_hid, inh_hid },
+	{ 0xb6, M680X_INS_LDE, ext_hid, inh_hid },
+	{ 0xb7, M680X_INS_STE, ext_hid, inh_hid },
+	{ 0xbb, M680X_INS_ADDE, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPS, ext_hid, inh_hid },
+	{ 0xbd, M680X_INS_DIVD, ext_hid, inh_hid },
+	{ 0xbe, M680X_INS_DIVQ, ext_hid, inh_hid },
+	{ 0xbf, M680X_INS_MULD, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register F
+	{ 0xc0, M680X_INS_SUBF, imm8_hid, inh_hid },
+	{ 0xc1, M680X_INS_CMPF, imm8_hid, inh_hid },
+	{ 0xc6, M680X_INS_LDF, imm8_hid, inh_hid },
+	{ 0xcb, M680X_INS_ADDF, imm8_hid, inh_hid },
+	// 0xDx, direct instructions with register F
+	{ 0xd0, M680X_INS_SUBF, dir_hid, inh_hid },
+	{ 0xd1, M680X_INS_CMPF, dir_hid, inh_hid },
+	{ 0xd6, M680X_INS_LDF, dir_hid, inh_hid },
+	{ 0xd7, M680X_INS_STF, dir_hid, inh_hid },
+	{ 0xdb, M680X_INS_ADDF, dir_hid, inh_hid },
+	// 0xEx, indexed instructions with register F
+	{ 0xe0, M680X_INS_SUBF, idx09_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMPF, idx09_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDF, idx09_hid, inh_hid },
+	{ 0xe7, M680X_INS_STF, idx09_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADDF, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register F
+	{ 0xf0, M680X_INS_SUBF, ext_hid, inh_hid },
+	{ 0xf1, M680X_INS_CMPF, ext_hid, inh_hid },
+	{ 0xf6, M680X_INS_LDF, ext_hid, inh_hid },
+	{ 0xf7, M680X_INS_STF, ext_hid, inh_hid },
+	{ 0xfb, M680X_INS_ADDF, ext_hid, inh_hid },
+};
+

arch/M680X/insn_props.inc

@@ -0,0 +1,367 @@
+
+// These temporary defines keep the following table short and handy.
+#define NOG M680X_GRP_INVALID
+#define NOR M680X_REG_INVALID
+
+static const insn_props g_insn_props[] = {
+	{ NOG, uuuu, NOR, NOR, false, false }, // INVLD
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // ABA
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_X, false, false }, // ABX
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_Y, false, false }, // ABY
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADCA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADCB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADCD
+	{ NOG, rmmm, NOR, NOR, true, false }, // ADCR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADD
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADDA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADDB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADDD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // ADDE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // ADDF
+	{ NOG, rmmm, NOR, NOR, true, false }, // ADDR
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // ADDW
+	{ NOG, rmmm, NOR, NOR, true, false }, // AIM
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // AIS
+	{ NOG, mrrr, M680X_REG_HX, NOR, false, false }, // AIX
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // AND
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ANDA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ANDB
+	{ NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ANDCC
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ANDD
+	{ NOG, rmmm, NOR, NOR, true, false }, // ANDR
+	{ NOG, mrrr, NOR, NOR, true, false }, // ASL
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASLA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASLB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASLD
+	{ NOG, mrrr, NOR, NOR, true, false }, // ASR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASRA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASRB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASRD
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // ASRX
+	{ NOG, mrrr, NOR, NOR, false, false }, // BAND
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCC
+	{ NOG, mrrr, NOR, NOR, true, false }, // BCLR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCS
+	{ NOG, mrrr, NOR, NOR, false, false }, // BEOR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BEQ
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGE
+	{ NOG, uuuu, NOR, NOR, false, false }, // BGND
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHI
+	{ NOG, mrrr, NOR, NOR, false, false }, // BIAND
+	{ NOG, mrrr, NOR, NOR, false, false }, // BIEOR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIH
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIL
+	{ NOG, mrrr, NOR, NOR, false, false }, // BIOR
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // BIT
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // BITA
+	{ NOG, rrrr, M680X_REG_B, NOR, true, false }, // BITB
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // BITD
+	{ NOG, rrrr, M680X_REG_MD, NOR, true, false }, // BITMD
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMI
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BNE
+	{ NOG, mrrr, NOR, NOR, false, false }, // BOR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BPL
+	{ M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRCLR
+	{ M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRSET
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRA
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRN never branches
+	{ NOG, mrrr, NOR, NOR, true, false }, // BSET
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // BSR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVS
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // CALL
+	{ NOG, rrrr, M680X_REG_B, M680X_REG_A, true, false }, // CBA
+	{ M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQ
+	{ M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQA
+	{ M680X_GRP_JUMP, rruu, M680X_REG_X, NOR, false, false }, // CBEQX
+	{ NOG, uuuu, NOR, NOR, true, false }, // CLC
+	{ NOG, uuuu, NOR, NOR, true, false }, // CLI
+	{ NOG, wrrr, NOR, NOR, true, false }, // CLR
+	{ NOG, wrrr, M680X_REG_A, NOR, true, false }, // CLRA
+	{ NOG, wrrr, M680X_REG_B, NOR, true, false }, // CLRB
+	{ NOG, wrrr, M680X_REG_D, NOR, true, false }, // CLRD
+	{ NOG, wrrr, M680X_REG_E, NOR, true, false }, // CLRE
+	{ NOG, wrrr, M680X_REG_F, NOR, true, false }, // CLRF
+	{ NOG, wrrr, M680X_REG_H, NOR, true, false }, // CLRH
+	{ NOG, wrrr, M680X_REG_W, NOR, true, false }, // CLRW
+	{ NOG, wrrr, M680X_REG_X, NOR, true, false }, // CLRX
+	{ NOG, uuuu, NOR, NOR, true, false }, // CLV
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMP
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMPA
+	{ NOG, rrrr, M680X_REG_B, NOR, true, false }, // CMPB
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // CMPD
+	{ NOG, rrrr, M680X_REG_E, NOR, true, false }, // CMPE
+	{ NOG, rrrr, M680X_REG_F, NOR, true, false }, // CMPF
+	{ NOG, rrrr, NOR, NOR, true, false }, // CMPR
+	{ NOG, rrrr, M680X_REG_S, NOR, true, false }, // CMPS
+	{ NOG, rrrr, M680X_REG_U, NOR, true, false }, // CMPU
+	{ NOG, rrrr, M680X_REG_W, NOR, true, false }, // CMPW
+	{ NOG, rrrr, M680X_REG_X, NOR, true, false }, // CMPX
+	{ NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CMPY
+	{ NOG, mrrr, NOR, NOR, true, false }, // COM
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // COMA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // COMB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // COMD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // COME
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // COMF
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // COMW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // COMX
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // CPD
+	{ NOG, rrrr, M680X_REG_HX, NOR, true, false }, // CPHX
+	{ NOG, rrrr, M680X_REG_S, NOR, true, false }, // CPS
+	{ NOG, rrrr, M680X_REG_X, NOR, true, false }, // CPX
+	{ NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CPY
+	{ NOG, mrrr, NOR, NOR, true, true }, // CWAI
+	{ NOG, mrrr, NOR, NOR, true, true }, // DAA
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBEQ
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNE
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNZ
+	{ M680X_GRP_JUMP, muuu, M680X_REG_A, NOR, false, false }, // DBNZA
+	{ M680X_GRP_JUMP, muuu, M680X_REG_X, NOR, false, false }, // DBNZX
+	{ NOG, mrrr, NOR, NOR, true, false }, // DEC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // DECA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // DECB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // DECD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // DECE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // DECF
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // DECW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // DECX
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // DES
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // DEX
+	{ NOG, mrrr, M680X_REG_Y, NOR, true, false }, // DEY
+	{ NOG, mmrr, NOR, NOR, true, true }, // DIV
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // DIVD
+	{ NOG, mrrr, M680X_REG_Q, NOR, true, false }, // DIVQ
+	{ NOG, mmrr, NOR, NOR, true, true }, // EDIV
+	{ NOG, mmrr, NOR, NOR, true, true }, // EDIVS
+	{ NOG, rmmm, NOR, NOR, true, false }, // EIM
+	{ NOG, mrrr, NOR, NOR, true, true }, // EMACS
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMAXD
+	{ NOG, mrrr, NOR, NOR, true, true }, // EMAXM
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMIND
+	{ NOG, mrrr, NOR, NOR, true, true }, // EMINM
+	{ NOG, mmrr, NOR, NOR, true, true }, // EMUL
+	{ NOG, mmrr, NOR, NOR, true, true }, // EMULS
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // EOR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // EORA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // EORB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // EORD
+	{ NOG, rmmm, NOR, NOR, true, false }, // EORR
+	{ NOG, rmmm, NOR, NOR, true, true }, // ETBL
+	{ NOG, mmmm, NOR, NOR, false, false }, // EXG
+	{ NOG, mmmm, NOR, NOR, true, true }, // FDIV
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBEQ
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBNE
+	{ NOG, mmmm, NOR, NOR, true, true }, // IDIV
+	{ NOG, mmmm, NOR, NOR, true, true }, // IDIVS
+	{ NOG, uuuu, NOR, NOR, false, false }, // ILLGL
+	{ NOG, mrrr, NOR, NOR, true, false }, // INC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // INCA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // INCB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // INCD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // INCE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // INCF
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // INCW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // INCX
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // INS
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // INX
+	{ NOG, mrrr, M680X_REG_Y, NOR, true, false }, // INY
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // JMP
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // JSR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBEQ
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBHI
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBMI
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBNE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBPL
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRA
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRN never branches
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // LBSR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVS
+	{ NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDA
+	{ NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDAA
+	{ NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDAB
+	{ NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDB
+	{ NOG, mrrr, NOR, NOR, false, false }, // LDBT
+	{ NOG, wrrr, M680X_REG_D, NOR, true, false }, // LDD
+	{ NOG, wrrr, M680X_REG_E, NOR, true, false }, // LDE
+	{ NOG, wrrr, M680X_REG_F, NOR, true, false }, // LDF
+	{ NOG, wrrr, M680X_REG_HX, NOR, true, false }, // LDHX
+	{ NOG, mrrr, M680X_REG_MD, NOR, false, false }, // LDMD
+	{ NOG, wrrr, M680X_REG_Q, NOR, true, false }, // LDQ
+	{ NOG, wrrr, M680X_REG_S, NOR, true, false }, // LDS
+	{ NOG, wrrr, M680X_REG_U, NOR, true, false }, // LDU
+	{ NOG, wrrr, M680X_REG_W, NOR, true, false }, // LDW
+	{ NOG, wrrr, M680X_REG_X, NOR, true, false }, // LDX
+	{ NOG, wrrr, M680X_REG_Y, NOR, true, false }, // LDY
+	{ NOG, wrrr, M680X_REG_S, NOR, false, false }, // LEAS
+	{ NOG, wrrr, M680X_REG_U, NOR, false, false }, // LEAU
+	{ NOG, wrrr, M680X_REG_X, NOR, false, false }, // LEAX
+	{ NOG, wrrr, M680X_REG_Y, NOR, false, false }, // LEAY
+	{ NOG, mrrr, NOR, NOR, true, false }, // LSL
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSLA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSLB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSLD
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSLX
+	{ NOG, mrrr, NOR, NOR, true, false }, // LSR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSRA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSRB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSRD
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // LSRW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSRX
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // MAXA
+	{ NOG, mrrr, NOR, NOR, true, true }, // MAXM
+	{ NOG, mmrr, NOR, NOR, true, true }, // MEM
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // MINA
+	{ NOG, mrrr, NOR, NOR, true, true }, // MINM
+	{ NOG, rwww, NOR, NOR, true, false }, // MOV
+	{ NOG, rwww, NOR, NOR, false, false }, // MOVB
+	{ NOG, rwww, NOR, NOR, false, false }, // MOVW
+	{ NOG, mmmm, NOR, NOR, true, true }, // MUL
+	{ NOG, mwrr, M680X_REG_D, NOR, true, true }, // MULD
+	{ NOG, mrrr, NOR, NOR, true, false }, // NEG
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // NEGA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // NEGB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // NEGD
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // NEGX
+	{ NOG, uuuu, NOR, NOR, false, false }, // NOP
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // NSA
+	{ NOG, rmmm, NOR, NOR, true, false }, // OIM
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORA
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORAA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORAB
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORB
+	{ NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ORCC
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ORD
+	{ NOG, rmmm, NOR, NOR, true, false }, // ORR
+	{ NOG, rmmm, M680X_REG_A, NOR, false, true }, // PSHA
+	{ NOG, rmmm, M680X_REG_B, NOR, false, true }, // PSHB
+	{ NOG, rmmm, M680X_REG_CC, NOR, false, true }, // PSHC
+	{ NOG, rmmm, M680X_REG_D, NOR, false, true }, // PSHD
+	{ NOG, rmmm, M680X_REG_H, NOR, false, true }, // PSHH
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // PSHS
+	{ NOG, mrrr, M680X_REG_S, M680X_REG_W, false, false }, // PSHSW
+	{ NOG, mrrr, M680X_REG_U, NOR, false, false }, // PSHU
+	{ NOG, mrrr, M680X_REG_U, M680X_REG_W, false, false }, // PSHUW
+	{ NOG, rmmm, M680X_REG_X, NOR, false, true }, // PSHX
+	{ NOG, rmmm, M680X_REG_Y, NOR, false, true }, // PSHY
+	{ NOG, wmmm, M680X_REG_A, NOR, false, true }, // PULA
+	{ NOG, wmmm, M680X_REG_B, NOR, false, true }, // PULB
+	{ NOG, wmmm, M680X_REG_CC, NOR, false, true }, // PULC
+	{ NOG, wmmm, M680X_REG_D, NOR, false, true }, // PULD
+	{ NOG, wmmm, M680X_REG_H, NOR, false, true }, // PULH
+	{ NOG, mwww, M680X_REG_S, NOR, false, false }, // PULS
+	{ NOG, mwww, M680X_REG_S, M680X_REG_W, false, false }, // PULSW
+	{ NOG, mwww, M680X_REG_U, NOR, false, false }, // PULU
+	{ NOG, mwww, M680X_REG_U, M680X_REG_W, false, false }, // PULUW
+	{ NOG, wmmm, M680X_REG_X, NOR, false, true }, // PULX
+	{ NOG, wmmm, M680X_REG_Y, NOR, false, true }, // PULY
+	{ NOG, mmrr, NOR, NOR, true, true }, // REV
+	{ NOG, mmmm, NOR, NOR, true, true }, // REVW
+	{ NOG, mrrr, NOR, NOR, true, false }, // ROL
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ROLA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ROLB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ROLD
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // ROLW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // ROLX
+	{ NOG, mrrr, NOR, NOR, true, false }, // ROR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // RORA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // RORB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // RORD
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // RORW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // RORX
+	{ NOG, wrrr, M680X_REG_S, NOR, false, false }, // RSP
+	{ M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTC
+	{ M680X_GRP_IRET, mwww, NOR, NOR, false, true }, // RTI
+	{ M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTS
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // SBA
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBCA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // SBCB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // SBCD
+	{ NOG, rmmm, NOR, NOR, true, false }, // SBCR
+	{ NOG, uuuu, NOR, NOR, true, false }, // SEC
+	{ NOG, uuuu, NOR, NOR, true, false }, // SEI
+	{ NOG, uuuu, NOR, NOR, true, false }, // SEV
+	{ NOG, wrrr, NOR, NOR, true, true }, // SEX
+	{ NOG, rwww, M680X_REG_W, NOR, true, true }, // SEXW
+	{ NOG, uuuu, NOR, NOR, false, false }, // SLP
+	{ NOG, rwww, M680X_REG_A, NOR, true, false }, // STA
+	{ NOG, rwww, M680X_REG_A, NOR, true, false }, // STAA
+	{ NOG, rwww, M680X_REG_B, NOR, true, false }, // STAB
+	{ NOG, rwww, M680X_REG_B, NOR, true, false }, // STB
+	{ NOG, rrrm, NOR, NOR, false, false }, // STBT
+	{ NOG, rwww, M680X_REG_D, NOR, true, false }, // STD
+	{ NOG, rwww, M680X_REG_E, NOR, true, false }, // STE
+	{ NOG, rwww, M680X_REG_F, NOR, true, false }, // STF
+	{ NOG, uuuu, NOR, NOR, false, false }, // STOP
+	{ NOG, rwww, M680X_REG_HX, NOR, true, false }, // STHX
+	{ NOG, rwww, M680X_REG_Q, NOR, true, false }, // STQ
+	{ NOG, rwww, M680X_REG_S, NOR, true, false }, // STS
+	{ NOG, rwww, M680X_REG_U, NOR, true, false }, // STU
+	{ NOG, rwww, M680X_REG_W, NOR, true, false }, // STW
+	{ NOG, rwww, M680X_REG_X, NOR, true, false }, // STX
+	{ NOG, rwww, M680X_REG_Y, NOR, true, false }, // STY
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUB
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUBA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // SUBB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // SUBD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // SUBE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // SUBF
+	{ NOG, rmmm, NOR, NOR, true, false }, // SUBR
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // SUBW
+	{ M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI
+	{ M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI2
+	{ M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI3
+	{ NOG, uuuu, NOR, NOR, false, false }, // SYNC
+	{ NOG, rwww, M680X_REG_A, M680X_REG_B, true, false }, // TAB
+	{ NOG, rwww, M680X_REG_A, M680X_REG_CC, false, false }, // TAP
+	{ NOG, rwww, M680X_REG_A, M680X_REG_X, false, false }, // TAX
+	{ NOG, rwww, M680X_REG_B, M680X_REG_A, true, false }, // TBA
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBEQ
+	{ NOG, rmmm, NOR, NOR, true, true }, // TBL
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBNE
+	{ NOG, uuuu, NOR, NOR, false, false }, // TEST
+	{ NOG, rwww, NOR, NOR, false, false }, // TFM
+	{ NOG, rwww, NOR, NOR, false, false }, // TFR
+	{ NOG, rrrr, NOR, NOR, true, false }, // TIM
+	{ NOG, rwww, M680X_REG_CC, M680X_REG_A, false, false }, // TPA
+	{ NOG, rrrr, NOR, NOR, true, false }, // TST
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // TSTA
+	{ NOG, rrrr, M680X_REG_B, NOR, true, false }, // TSTB
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // TSTD
+	{ NOG, rrrr, M680X_REG_E, NOR, true, false }, // TSTE
+	{ NOG, rrrr, M680X_REG_F, NOR, true, false }, // TSTF
+	{ NOG, rrrr, M680X_REG_W, NOR, true, false }, // TSTW
+	{ NOG, rrrr, M680X_REG_X, NOR, true, false }, // TSTX
+	{ NOG, rwww, M680X_REG_S, M680X_REG_HX, false, false }, // TSX
+	{ NOG, rwww, M680X_REG_S, M680X_REG_Y, false, false }, // TSY
+	{ NOG, rwww, M680X_REG_X, M680X_REG_A, false, false }, // TXA
+	{ NOG, rwww, M680X_REG_HX, M680X_REG_S, false, false }, // TXS
+	{ NOG, rwww, M680X_REG_Y, M680X_REG_S, false, false }, // TYS
+	{ NOG, mrrr, NOR, NOR, true, true }, // WAI
+	{ NOG, uuuu, NOR, NOR, true, false }, // WAIT
+	{ NOG, uuuu, NOR, NOR, true, true }, // WAV
+	{ NOG, uuuu, NOR, NOR, true, true }, // WAVR
+	{ NOG, mmmm, M680X_REG_D, M680X_REG_X, false, false }, // XGDX
+	{ NOG, mmmm, M680X_REG_D, M680X_REG_Y, false, false }, // XGDY
+};
+#undef NOR
+#undef NOG
+

arch/M680X/m6800.inc

@@ -0,0 +1,277 @@
+
+// M6800/2 instructions
+static const inst_page1 g_m6800_inst_page1_table[256] = {
+	// 0x0x, inherent instructions
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TAP, inh_hid, inh_hid },
+	{ M680X_INS_TPA, inh_hid, inh_hid },
+	{ M680X_INS_INX, inh_hid, inh_hid },
+	{ M680X_INS_DEX, inh_hid, inh_hid },
+	{ M680X_INS_CLV, inh_hid, inh_hid },
+	{ M680X_INS_SEV, inh_hid, inh_hid },
+	{ M680X_INS_CLC, inh_hid, inh_hid },
+	{ M680X_INS_SEC, inh_hid, inh_hid },
+	{ M680X_INS_CLI, inh_hid, inh_hid },
+	{ M680X_INS_SEI, inh_hid, inh_hid },
+	// 0x1x, inherent instructions
+	{ M680X_INS_SBA, inh_hid, inh_hid },
+	{ M680X_INS_CBA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TAB, inh_hid, inh_hid },
+	{ M680X_INS_TBA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_DAA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ABA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BVC, rel8_hid, inh_hid },
+	{ M680X_INS_BVS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BGE, rel8_hid, inh_hid },
+	{ M680X_INS_BLT, rel8_hid, inh_hid },
+	{ M680X_INS_BGT, rel8_hid, inh_hid },
+	{ M680X_INS_BLE, rel8_hid, inh_hid },
+	// 0x3x, inherent instructions
+	{ M680X_INS_TSX, inh_hid, inh_hid },
+	{ M680X_INS_INS, inh_hid, inh_hid },
+	{ M680X_INS_PULA, inh_hid, inh_hid },
+	{ M680X_INS_PULB, inh_hid, inh_hid },
+	{ M680X_INS_DES, inh_hid, inh_hid },
+	{ M680X_INS_TXS, inh_hid, inh_hid },
+	{ M680X_INS_PSHA, inh_hid, inh_hid },
+	{ M680X_INS_PSHB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_WAI, inh_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	// 0x4x, Register A instructions
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_ASLA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	// 0x5x, Register B instructions
+	{ M680X_INS_NEGB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMB, inh_hid, inh_hid },
+	{ M680X_INS_LSRB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORB, inh_hid, inh_hid },
+	{ M680X_INS_ASRB, inh_hid, inh_hid },
+	{ M680X_INS_ASLB, inh_hid, inh_hid },
+	{ M680X_INS_ROLB, inh_hid, inh_hid },
+	{ M680X_INS_DECB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCB, inh_hid, inh_hid },
+	{ M680X_INS_TSTB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRB, inh_hid, inh_hid },
+	// 0x6x, indexed instructions
+	{ M680X_INS_NEG, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idxX_hid, inh_hid },
+	{ M680X_INS_LSR, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idxX_hid, inh_hid },
+	{ M680X_INS_ASR, idxX_hid, inh_hid },
+	{ M680X_INS_ASL, idxX_hid, inh_hid },
+	{ M680X_INS_ROL, idxX_hid, inh_hid },
+	{ M680X_INS_DEC, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idxX_hid, inh_hid },
+	{ M680X_INS_TST, idxX_hid, inh_hid },
+	{ M680X_INS_JMP, idxX_hid, inh_hid },
+	{ M680X_INS_CLR, idxX_hid, inh_hid },
+	// 0x7x, extended instructions
+	{ M680X_INS_NEG, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, ext_hid, inh_hid },
+	{ M680X_INS_LSR, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, ext_hid, inh_hid },
+	{ M680X_INS_ASR, ext_hid, inh_hid },
+	{ M680X_INS_ASL, ext_hid, inh_hid },
+	{ M680X_INS_ROL, ext_hid, inh_hid },
+	{ M680X_INS_DEC, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, ext_hid, inh_hid },
+	{ M680X_INS_TST, ext_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_CLR, ext_hid, inh_hid },
+	// 0x8x, immediate instructions with Register A,X,S
+	{ M680X_INS_SUBA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPA, imm8_hid, inh_hid },
+	{ M680X_INS_SBCA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, imm8_hid, inh_hid },
+	{ M680X_INS_BITA, imm8_hid, inh_hid },
+	{ M680X_INS_LDAA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADCA, imm8_hid, inh_hid },
+	{ M680X_INS_ORAA, imm8_hid, inh_hid },
+	{ M680X_INS_ADDA, imm8_hid, inh_hid },
+	{ M680X_INS_CPX, imm16_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_LDS, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0x9x, direct instructions with register A,X,S
+	{ M680X_INS_SUBA, dir_hid, inh_hid },
+	{ M680X_INS_CMPA, dir_hid, inh_hid },
+	{ M680X_INS_SBCA, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, dir_hid, inh_hid },
+	{ M680X_INS_BITA, dir_hid, inh_hid },
+	{ M680X_INS_LDAA, dir_hid, inh_hid },
+	{ M680X_INS_STAA, dir_hid, inh_hid },
+	{ M680X_INS_EORA, dir_hid, inh_hid },
+	{ M680X_INS_ADCA, dir_hid, inh_hid },
+	{ M680X_INS_ORAA, dir_hid, inh_hid },
+	{ M680X_INS_ADDA, dir_hid, inh_hid },
+	{ M680X_INS_CPX, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDS, dir_hid, inh_hid },
+	{ M680X_INS_STS, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with Register A,X
+	{ M680X_INS_SUBA, idxX_hid, inh_hid },
+	{ M680X_INS_CMPA, idxX_hid, inh_hid },
+	{ M680X_INS_SBCA, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, idxX_hid, inh_hid },
+	{ M680X_INS_BITA, idxX_hid, inh_hid },
+	{ M680X_INS_LDAA, idxX_hid, inh_hid },
+	{ M680X_INS_STAA, idxX_hid, inh_hid },
+	{ M680X_INS_EORA, idxX_hid, inh_hid },
+	{ M680X_INS_ADCA, idxX_hid, inh_hid },
+	{ M680X_INS_ORAA, idxX_hid, inh_hid },
+	{ M680X_INS_ADDA, idxX_hid, inh_hid },
+	{ M680X_INS_CPX, idxX_hid, inh_hid },
+	{ M680X_INS_JSR, idxX_hid, inh_hid },
+	{ M680X_INS_LDS, idxX_hid, inh_hid },
+	{ M680X_INS_STS, idxX_hid, inh_hid },
+	// 0xBx, extended instructions with register A,X,S
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_STAA, ext_hid, inh_hid },
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_CPX, ext_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_LDS, ext_hid, inh_hid },
+	{ M680X_INS_STS, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register B,X
+	{ M680X_INS_SUBB, imm8_hid, inh_hid },
+	{ M680X_INS_CMPB, imm8_hid, inh_hid },
+	{ M680X_INS_SBCB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, imm8_hid, inh_hid },
+	{ M680X_INS_BITB, imm8_hid, inh_hid },
+	{ M680X_INS_LDAB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADCB, imm8_hid, inh_hid },
+	{ M680X_INS_ORAB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0xDx direct instructions with register B,X
+	{ M680X_INS_SUBB, dir_hid, inh_hid },
+	{ M680X_INS_CMPB, dir_hid, inh_hid },
+	{ M680X_INS_SBCB, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, dir_hid, inh_hid },
+	{ M680X_INS_BITB, dir_hid, inh_hid },
+	{ M680X_INS_LDAB, dir_hid, inh_hid },
+	{ M680X_INS_STAB, dir_hid, inh_hid },
+	{ M680X_INS_EORB, dir_hid, inh_hid },
+	{ M680X_INS_ADCB, dir_hid, inh_hid },
+	{ M680X_INS_ORAB, dir_hid, inh_hid },
+	{ M680X_INS_ADDB, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	// 0xEx, indexed instruction with register B,X
+	{ M680X_INS_SUBB, idxX_hid, inh_hid },
+	{ M680X_INS_CMPB, idxX_hid, inh_hid },
+	{ M680X_INS_SBCB, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, idxX_hid, inh_hid },
+	{ M680X_INS_BITB, idxX_hid, inh_hid },
+	{ M680X_INS_LDAB, idxX_hid, inh_hid },
+	{ M680X_INS_STAB, idxX_hid, inh_hid },
+	{ M680X_INS_EORB, idxX_hid, inh_hid },
+	{ M680X_INS_ADCB, idxX_hid, inh_hid },
+	{ M680X_INS_ORAB, idxX_hid, inh_hid },
+	{ M680X_INS_ADDB, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, idxX_hid, inh_hid },
+	{ M680X_INS_STX, idxX_hid, inh_hid },
+	// 0xFx, extended instructions with register B,U
+	{ M680X_INS_SUBB, ext_hid, inh_hid },
+	{ M680X_INS_CMPB, ext_hid, inh_hid },
+	{ M680X_INS_SBCB, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, ext_hid, inh_hid },
+	{ M680X_INS_BITB, ext_hid, inh_hid },
+	{ M680X_INS_LDAB, ext_hid, inh_hid },
+	{ M680X_INS_STAB, ext_hid, inh_hid },
+	{ M680X_INS_EORB, ext_hid, inh_hid },
+	{ M680X_INS_ADCB, ext_hid, inh_hid },
+	{ M680X_INS_ORAB, ext_hid, inh_hid },
+	{ M680X_INS_ADDB, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+};
+

arch/M680X/m6801.inc

@@ -0,0 +1,39 @@
+
+// Additional instructions only supported on M6801/3
+static const inst_pageX g_m6801_inst_overlay_table[] = {
+	// 0x0x, inherent instructions
+	{ 0x04, M680X_INS_LSRD, inh_hid, inh_hid },
+	{ 0x05, M680X_INS_ASLD, inh_hid, inh_hid },
+	// 0x2x, relative branch instructions
+	{ 0x21, M680X_INS_BRN, rel8_hid, inh_hid },
+	// 0x3x, inherent instructions
+	{ 0x38, M680X_INS_PULX, inh_hid, inh_hid },
+	{ 0x3A, M680X_INS_ABX, inh_hid, inh_hid },
+	{ 0x3C, M680X_INS_PSHX, inh_hid, inh_hid },
+	{ 0x3D, M680X_INS_MUL, inh_hid, inh_hid  },
+	// 0x8x, immediate instructions with Register D
+	{ 0x83, M680X_INS_SUBD, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register D
+	{ 0x93, M680X_INS_SUBD, dir_hid, inh_hid },
+	{ 0x9D, M680X_INS_JSR, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with Register D
+	{ 0xA3, M680X_INS_SUBD, idxX_hid, inh_hid },
+	// 0xBx, extended instructions with register D
+	{ 0xB3, M680X_INS_SUBD, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register D
+	{ 0xC3, M680X_INS_ADDD, imm16_hid, inh_hid },
+	{ 0xCC, M680X_INS_LDD, imm16_hid, inh_hid },
+	// 0xDx direct instructions with register D
+	{ 0xD3, M680X_INS_ADDD, dir_hid, inh_hid },
+	{ 0xDC, M680X_INS_LDD, dir_hid, inh_hid },
+	{ 0xDD, M680X_INS_STD, dir_hid, inh_hid },
+	// 0xEx, indexed instruction with register D
+	{ 0xE3, M680X_INS_ADDD, idxX_hid, inh_hid },
+	{ 0xEC, M680X_INS_LDD, idxX_hid, inh_hid },
+	{ 0xED, M680X_INS_STD, idxX_hid, inh_hid },
+	// 0xFx, extended instructions with register D
+	{ 0xF3, M680X_INS_ADDD, ext_hid, inh_hid },
+	{ 0xFC, M680X_INS_LDD, ext_hid, inh_hid },
+	{ 0xFD, M680X_INS_STD, ext_hid, inh_hid },
+};
+

arch/M680X/m6805.inc

@@ -0,0 +1,277 @@
+
+// M68HC05 instructions
+static const inst_page1 g_m6805_inst_page1_table[256] = {
+	// 0x0x, bit manipulation instructions
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	// 0x1x, bit set/clear instructions
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_BRN, rel8_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BHCC, rel8_hid, inh_hid },
+	{ M680X_INS_BHCS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BMC, rel8_hid, inh_hid },
+	{ M680X_INS_BMS, rel8_hid, inh_hid },
+	{ M680X_INS_BIL, rel8_hid, inh_hid },
+	{ M680X_INS_BIH, rel8_hid, inh_hid },
+	// 0x3x, direct instructions
+	{ M680X_INS_NEG, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, dir_hid, inh_hid },
+	{ M680X_INS_LSR, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, dir_hid, inh_hid },
+	{ M680X_INS_ASR, dir_hid, inh_hid },
+	{ M680X_INS_LSL, dir_hid, inh_hid },
+	{ M680X_INS_ROL, dir_hid, inh_hid },
+	{ M680X_INS_DEC, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, dir_hid, inh_hid },
+	{ M680X_INS_TST, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLR, dir_hid, inh_hid },
+	// 0x4x, inherent instructions
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_MUL, inh_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_LSLA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	// 0x5x, inherent instructions
+	{ M680X_INS_NEGX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMX, inh_hid, inh_hid },
+	{ M680X_INS_LSRX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORX, inh_hid, inh_hid },
+	{ M680X_INS_ASRX, inh_hid, inh_hid },
+	{ M680X_INS_LSLX, inh_hid, inh_hid },
+	{ M680X_INS_ROLX, inh_hid, inh_hid },
+	{ M680X_INS_DECX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCX, inh_hid, inh_hid },
+	{ M680X_INS_TSTX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRX, inh_hid, inh_hid },
+	// 0x6x, indexed, 1 byte offset instructions
+	{ M680X_INS_NEG, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idxX_hid, inh_hid },
+	{ M680X_INS_LSR, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idxX_hid, inh_hid },
+	{ M680X_INS_ASR, idxX_hid, inh_hid },
+	{ M680X_INS_LSL, idxX_hid, inh_hid },
+	{ M680X_INS_ROL, idxX_hid, inh_hid },
+	{ M680X_INS_DEC, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idxX_hid, inh_hid },
+	{ M680X_INS_TST, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLR, idxX_hid, inh_hid },
+	// 0x7x, indexed, no offset instructions
+	{ M680X_INS_NEG, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idxX0_hid, inh_hid },
+	{ M680X_INS_LSR, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idxX0_hid, inh_hid },
+	{ M680X_INS_ASR, idxX0_hid, inh_hid },
+	{ M680X_INS_LSL, idxX0_hid, inh_hid },
+	{ M680X_INS_ROL, idxX0_hid, inh_hid },
+	{ M680X_INS_DEC, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idxX0_hid, inh_hid },
+	{ M680X_INS_TST, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLR, idxX0_hid, inh_hid },
+	// 0x8x, inherent instructions
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_STOP, inh_hid, inh_hid },
+	{ M680X_INS_WAIT, inh_hid, inh_hid },
+	// 0x9x, inherent instructions
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TAX, inh_hid, inh_hid },
+	{ M680X_INS_CLC, inh_hid, inh_hid },
+	{ M680X_INS_SEC, inh_hid, inh_hid },
+	{ M680X_INS_CLI, inh_hid, inh_hid },
+	{ M680X_INS_SEI, inh_hid, inh_hid },
+	{ M680X_INS_RSP, inh_hid, inh_hid },
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TXA, inh_hid, inh_hid },
+	// 0xAx, immediate instructions with reg. A
+	{ M680X_INS_SUB, imm8_hid, inh_hid },
+	{ M680X_INS_CMP, imm8_hid, inh_hid },
+	{ M680X_INS_SBC, imm8_hid, inh_hid },
+	{ M680X_INS_CPX, imm8_hid, inh_hid },
+	{ M680X_INS_AND, imm8_hid, inh_hid },
+	{ M680X_INS_BIT, imm8_hid, inh_hid },
+	{ M680X_INS_LDA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EOR, imm8_hid, inh_hid },
+	{ M680X_INS_ADC, imm8_hid, inh_hid },
+	{ M680X_INS_ORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADD, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_LDX, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0xBx, direct instructions with reg. A
+	{ M680X_INS_SUB, dir_hid, inh_hid },
+	{ M680X_INS_CMP, dir_hid, inh_hid },
+	{ M680X_INS_SBC, dir_hid, inh_hid },
+	{ M680X_INS_CPX, dir_hid, inh_hid },
+	{ M680X_INS_AND, dir_hid, inh_hid },
+	{ M680X_INS_BIT, dir_hid, inh_hid },
+	{ M680X_INS_LDA, dir_hid, inh_hid },
+	{ M680X_INS_STA, dir_hid, inh_hid },
+	{ M680X_INS_EOR, dir_hid, inh_hid },
+	{ M680X_INS_ADC, dir_hid, inh_hid },
+	{ M680X_INS_ORA, dir_hid, inh_hid },
+	{ M680X_INS_ADD, dir_hid, inh_hid },
+	{ M680X_INS_JMP, dir_hid, inh_hid },
+	{ M680X_INS_JSR, dir_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	// 0xCx, extended instructions with reg. A
+	{ M680X_INS_SUB, ext_hid, inh_hid },
+	{ M680X_INS_CMP, ext_hid, inh_hid },
+	{ M680X_INS_SBC, ext_hid, inh_hid },
+	{ M680X_INS_CPX, ext_hid, inh_hid },
+	{ M680X_INS_AND, ext_hid, inh_hid },
+	{ M680X_INS_BIT, ext_hid, inh_hid },
+	{ M680X_INS_LDA, ext_hid, inh_hid },
+	{ M680X_INS_STA, ext_hid, inh_hid },
+	{ M680X_INS_EOR, ext_hid, inh_hid },
+	{ M680X_INS_ADC, ext_hid, inh_hid },
+	{ M680X_INS_ORA, ext_hid, inh_hid },
+	{ M680X_INS_ADD, ext_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+	// 0xDx, indexed with 2 byte offset instructions with reg. A
+	{ M680X_INS_SUB, idxX16_hid, inh_hid },
+	{ M680X_INS_CMP, idxX16_hid, inh_hid },
+	{ M680X_INS_SBC, idxX16_hid, inh_hid },
+	{ M680X_INS_CPX, idxX16_hid, inh_hid },
+	{ M680X_INS_AND, idxX16_hid, inh_hid },
+	{ M680X_INS_BIT, idxX16_hid, inh_hid },
+	{ M680X_INS_LDA, idxX16_hid, inh_hid },
+	{ M680X_INS_STA, idxX16_hid, inh_hid },
+	{ M680X_INS_EOR, idxX16_hid, inh_hid },
+	{ M680X_INS_ADC, idxX16_hid, inh_hid },
+	{ M680X_INS_ORA, idxX16_hid, inh_hid },
+	{ M680X_INS_ADD, idxX16_hid, inh_hid },
+	{ M680X_INS_JMP, idxX16_hid, inh_hid },
+	{ M680X_INS_JSR, idxX16_hid, inh_hid },
+	{ M680X_INS_LDX, idxX16_hid, inh_hid },
+	{ M680X_INS_STX, idxX16_hid, inh_hid },
+	// 0xEx, indexed with 1 byte offset instructions with reg. A
+	{ M680X_INS_SUB, idxX_hid, inh_hid },
+	{ M680X_INS_CMP, idxX_hid, inh_hid },
+	{ M680X_INS_SBC, idxX_hid, inh_hid },
+	{ M680X_INS_CPX, idxX_hid, inh_hid },
+	{ M680X_INS_AND, idxX_hid, inh_hid },
+	{ M680X_INS_BIT, idxX_hid, inh_hid },
+	{ M680X_INS_LDA, idxX_hid, inh_hid },
+	{ M680X_INS_STA, idxX_hid, inh_hid },
+	{ M680X_INS_EOR, idxX_hid, inh_hid },
+	{ M680X_INS_ADC, idxX_hid, inh_hid },
+	{ M680X_INS_ORA, idxX_hid, inh_hid },
+	{ M680X_INS_ADD, idxX_hid, inh_hid },
+	{ M680X_INS_JMP, idxX_hid, inh_hid },
+	{ M680X_INS_JSR, idxX_hid, inh_hid },
+	{ M680X_INS_LDX, idxX_hid, inh_hid },
+	{ M680X_INS_STX, idxX_hid, inh_hid },
+	// 0xFx, indexed without offset instructions with reg. A
+	{ M680X_INS_SUB, idxX0_hid, inh_hid },
+	{ M680X_INS_CMP, idxX0_hid, inh_hid },
+	{ M680X_INS_SBC, idxX0_hid, inh_hid },
+	{ M680X_INS_CPX, idxX0_hid, inh_hid },
+	{ M680X_INS_AND, idxX0_hid, inh_hid },
+	{ M680X_INS_BIT, idxX0_hid, inh_hid },
+	{ M680X_INS_LDA, idxX0_hid, inh_hid },
+	{ M680X_INS_STA, idxX0_hid, inh_hid },
+	{ M680X_INS_EOR, idxX0_hid, inh_hid },
+	{ M680X_INS_ADC, idxX0_hid, inh_hid },
+	{ M680X_INS_ORA, idxX0_hid, inh_hid },
+	{ M680X_INS_ADD, idxX0_hid, inh_hid },
+	{ M680X_INS_JMP, idxX0_hid, inh_hid },
+	{ M680X_INS_JSR, idxX0_hid, inh_hid },
+	{ M680X_INS_LDX, idxX0_hid, inh_hid },
+	{ M680X_INS_STX, idxX0_hid, inh_hid },
+};
+

arch/M680X/m6808.inc

@@ -0,0 +1,91 @@
+
+// Additional instructions only supported on M68HC08
+static const inst_pageX g_m6808_inst_overlay_table[] = {
+	{ 0x31, M680X_INS_CBEQ, dir_hid, rel8_hid },
+	{ 0x35, M680X_INS_STHX, dir_hid, inh_hid },
+	{ 0x3b, M680X_INS_DBNZ, dir_hid, rel8_hid },
+	{ 0x41, M680X_INS_CBEQA, imm8rel_hid, inh_hid },
+	{ 0x45, M680X_INS_LDHX, imm16_hid, inh_hid },
+	{ 0x4b, M680X_INS_DBNZA, rel8_hid, inh_hid },
+	{ 0x4e, M680X_INS_MOV, dir_hid, dir_hid },
+	{ 0x51, M680X_INS_CBEQX, imm8rel_hid, inh_hid },
+	{ 0x52, M680X_INS_DIV, inh_hid, inh_hid },
+	{ 0x55, M680X_INS_LDHX, dir_hid, inh_hid },
+	{ 0x5b, M680X_INS_DBNZX, rel8_hid, inh_hid },
+	{ 0x5e, M680X_INS_MOV, dir_hid, idxX0p_hid },
+	{ 0x61, M680X_INS_CBEQ, idxXp_hid, rel8_hid },
+	{ 0x62, M680X_INS_NSA, inh_hid, inh_hid },
+	{ 0x65, M680X_INS_CPHX, imm16_hid, inh_hid },
+	{ 0x6b, M680X_INS_DBNZ, idxX_hid, rel8_hid },
+	{ 0x6e, M680X_INS_MOV, imm8_hid, dir_hid },
+	{ 0x71, M680X_INS_CBEQ, idxX0p_hid, rel8_hid },
+	{ 0x72, M680X_INS_DAA, inh_hid, inh_hid },
+	{ 0x75, M680X_INS_CPHX, dir_hid, inh_hid },
+	{ 0x7b, M680X_INS_DBNZ, idxX0_hid, rel8_hid },
+	{ 0x7e, M680X_INS_MOV, idxX0p_hid, dir_hid },
+	{ 0x84, M680X_INS_TAP, inh_hid, inh_hid },
+	{ 0x85, M680X_INS_TPA, inh_hid, inh_hid },
+	{ 0x86, M680X_INS_PULA, inh_hid, inh_hid },
+	{ 0x87, M680X_INS_PSHA, inh_hid, inh_hid },
+	{ 0x88, M680X_INS_PULX, inh_hid, inh_hid },
+	{ 0x89, M680X_INS_PSHX, inh_hid, inh_hid },
+	{ 0x8a, M680X_INS_PULH, inh_hid, inh_hid },
+	{ 0x8b, M680X_INS_PSHH, inh_hid, inh_hid },
+	{ 0x8c, M680X_INS_CLRH, inh_hid, inh_hid },
+	{ 0x90, M680X_INS_BGE, rel8_hid, inh_hid },
+	{ 0x91, M680X_INS_BLT, rel8_hid, inh_hid },
+	{ 0x92, M680X_INS_BGT, rel8_hid, inh_hid },
+	{ 0x93, M680X_INS_BLE, rel8_hid, inh_hid },
+	{ 0x94, M680X_INS_TXS, inh_hid, inh_hid },
+	{ 0x95, M680X_INS_TSX, inh_hid, inh_hid },
+	{ 0x97, M680X_INS_TAX, inh_hid, inh_hid },
+	{ 0x9f, M680X_INS_TXA, inh_hid, inh_hid },
+	{ 0xa7, M680X_INS_AIS, imm8_hid, inh_hid },
+	{ 0xaf, M680X_INS_AIX, imm8_hid, inh_hid },
+};
+
+// M68HC08 PAGE2 instructions (prefix 0x9E)
+static const inst_pageX g_m6808_inst_page2_table[] = {
+	{ 0x60, M680X_INS_NEG, idxS_hid, inh_hid },
+	{ 0x61, M680X_INS_CBEQ, idxS_hid, rel8_hid },
+	{ 0x63, M680X_INS_COM, idxS_hid, inh_hid },
+	{ 0x64, M680X_INS_LSR, idxS_hid, inh_hid },
+	{ 0x66, M680X_INS_ROR, idxS_hid, inh_hid },
+	{ 0x67, M680X_INS_ASR, idxS_hid, inh_hid },
+	{ 0x68, M680X_INS_LSL, idxS_hid, inh_hid },
+	{ 0x69, M680X_INS_ROL, idxS_hid, inh_hid },
+	{ 0x6a, M680X_INS_DEC, idxS_hid, inh_hid },
+	{ 0x6b, M680X_INS_DBNZ, idxS_hid, rel8_hid },
+	{ 0x6c, M680X_INS_INC, idxS_hid, inh_hid },
+	{ 0x6d, M680X_INS_TST, idxS_hid, inh_hid },
+	{ 0x6f, M680X_INS_CLR, idxS_hid, inh_hid },
+	{ 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid },
+	{ 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid },
+	{ 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid },
+	{ 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid },
+	{ 0xd4, M680X_INS_AND, idxS16_hid, inh_hid },
+	{ 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid },
+	{ 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid },
+	{ 0xd7, M680X_INS_STA, idxS16_hid, inh_hid },
+	{ 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid },
+	{ 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid },
+	{ 0xda, M680X_INS_ORA, idxS16_hid, inh_hid },
+	{ 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid },
+	{ 0xde, M680X_INS_LDX, idxS16_hid, inh_hid },
+	{ 0xdf, M680X_INS_STX, idxS16_hid, inh_hid },
+	{ 0xe0, M680X_INS_SUB, idxS_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMP, idxS_hid, inh_hid },
+	{ 0xe2, M680X_INS_SBC, idxS_hid, inh_hid },
+	{ 0xe3, M680X_INS_CPX, idxS_hid, inh_hid },
+	{ 0xe4, M680X_INS_AND, idxS_hid, inh_hid },
+	{ 0xe5, M680X_INS_BIT, idxS_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDA, idxS_hid, inh_hid },
+	{ 0xe7, M680X_INS_STA, idxS_hid, inh_hid },
+	{ 0xe8, M680X_INS_EOR, idxS_hid, inh_hid },
+	{ 0xe9, M680X_INS_ADC, idxS_hid, inh_hid },
+	{ 0xea, M680X_INS_ORA, idxS_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADD, idxS_hid, inh_hid },
+	{ 0xee, M680X_INS_LDX, idxS_hid, inh_hid },
+	{ 0xef, M680X_INS_STX, idxS_hid, inh_hid },
+};
+

arch/M680X/m6809.inc

@@ -0,0 +1,352 @@
+
+// M6809/HD6309 PAGE1 instructions
+static const inst_page1 g_m6809_inst_page1_table[256] = {
+	// 0x0x, direct instructions
+	{ M680X_INS_NEG, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, dir_hid, inh_hid },
+	{ M680X_INS_LSR, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, dir_hid, inh_hid },
+	{ M680X_INS_ASR, dir_hid, inh_hid },
+	{ M680X_INS_LSL, dir_hid, inh_hid },
+	{ M680X_INS_ROL, dir_hid, inh_hid },
+	{ M680X_INS_DEC, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, dir_hid, inh_hid },
+	{ M680X_INS_TST, dir_hid, inh_hid },
+	{ M680X_INS_JMP, dir_hid, inh_hid },
+	{ M680X_INS_CLR, dir_hid, inh_hid },
+	// 0x1x, misc instructions
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE2
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE3
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_SYNC, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LBRA, rel16_hid, inh_hid },
+	{ M680X_INS_LBSR, rel16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_DAA, inh_hid, inh_hid },
+	{ M680X_INS_ORCC, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDCC, imm8_hid, inh_hid },
+	{ M680X_INS_SEX, inh_hid, inh_hid },
+	{ M680X_INS_EXG, rr09_hid, inh_hid },
+	{ M680X_INS_TFR, rr09_hid, inh_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_BRN, rel8_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BVC, rel8_hid, inh_hid },
+	{ M680X_INS_BVS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BGE, rel8_hid, inh_hid },
+	{ M680X_INS_BLT, rel8_hid, inh_hid },
+	{ M680X_INS_BGT, rel8_hid, inh_hid },
+	{ M680X_INS_BLE, rel8_hid, inh_hid },
+	// 0x3x, misc instructions
+	{ M680X_INS_LEAX, idx09_hid, inh_hid },
+	{ M680X_INS_LEAY, idx09_hid, inh_hid },
+	{ M680X_INS_LEAS, idx09_hid, inh_hid },
+	{ M680X_INS_LEAU, idx09_hid, inh_hid },
+	{ M680X_INS_PSHS, rbits_hid, inh_hid },
+	{ M680X_INS_PULS, rbits_hid, inh_hid },
+	{ M680X_INS_PSHU, rbits_hid, inh_hid },
+	{ M680X_INS_PULU, rbits_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_ABX, inh_hid, inh_hid },
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_CWAI, imm8_hid, inh_hid },
+	{ M680X_INS_MUL, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	// 0x4x, Register A instructions
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_LSLA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	// 0x5x, Register B instructions
+	{ M680X_INS_NEGB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMB, inh_hid, inh_hid },
+	{ M680X_INS_LSRB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORB, inh_hid, inh_hid },
+	{ M680X_INS_ASRB, inh_hid, inh_hid },
+	{ M680X_INS_LSLB, inh_hid, inh_hid },
+	{ M680X_INS_ROLB, inh_hid, inh_hid },
+	{ M680X_INS_DECB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCB, inh_hid, inh_hid },
+	{ M680X_INS_TSTB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRB, inh_hid, inh_hid },
+	// 0x6x, indexed instructions
+	{ M680X_INS_NEG, idx09_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idx09_hid, inh_hid },
+	{ M680X_INS_LSR, idx09_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idx09_hid, inh_hid },
+	{ M680X_INS_ASR, idx09_hid, inh_hid },
+	{ M680X_INS_LSL, idx09_hid, inh_hid },
+	{ M680X_INS_ROL, idx09_hid, inh_hid },
+	{ M680X_INS_DEC, idx09_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idx09_hid, inh_hid },
+	{ M680X_INS_TST, idx09_hid, inh_hid },
+	{ M680X_INS_JMP, idx09_hid, inh_hid },
+	{ M680X_INS_CLR, idx09_hid, inh_hid },
+	// 0x7x, extended instructions
+	{ M680X_INS_NEG, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, ext_hid, inh_hid },
+	{ M680X_INS_LSR, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, ext_hid, inh_hid },
+	{ M680X_INS_ASR, ext_hid, inh_hid },
+	{ M680X_INS_LSL, ext_hid, inh_hid },
+	{ M680X_INS_ROL, ext_hid, inh_hid },
+	{ M680X_INS_DEC, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, ext_hid, inh_hid },
+	{ M680X_INS_TST, ext_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_CLR, ext_hid, inh_hid },
+	// 0x8x, immediate instructions with Register A,D,X
+	{ M680X_INS_SUBA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPA, imm8_hid, inh_hid },
+	{ M680X_INS_SBCA, imm8_hid, inh_hid },
+	{ M680X_INS_SUBD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDA, imm8_hid, inh_hid },
+	{ M680X_INS_BITA, imm8_hid, inh_hid },
+	{ M680X_INS_LDA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADCA, imm8_hid, inh_hid },
+	{ M680X_INS_ORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADDA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPX, imm16_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_LDX, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0x9x, direct instructions with register A,D,X
+	{ M680X_INS_SUBA, dir_hid, inh_hid },
+	{ M680X_INS_CMPA, dir_hid, inh_hid },
+	{ M680X_INS_SBCA, dir_hid, inh_hid },
+	{ M680X_INS_SUBD, dir_hid, inh_hid },
+	{ M680X_INS_ANDA, dir_hid, inh_hid },
+	{ M680X_INS_BITA, dir_hid, inh_hid },
+	{ M680X_INS_LDA, dir_hid, inh_hid },
+	{ M680X_INS_STA, dir_hid, inh_hid },
+	{ M680X_INS_EORA, dir_hid, inh_hid },
+	{ M680X_INS_ADCA, dir_hid, inh_hid },
+	{ M680X_INS_ORA, dir_hid, inh_hid },
+	{ M680X_INS_ADDA, dir_hid, inh_hid },
+	{ M680X_INS_CMPX, dir_hid, inh_hid },
+	{ M680X_INS_JSR, dir_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with Register A,D,X
+	{ M680X_INS_SUBA, idx09_hid, inh_hid },
+	{ M680X_INS_CMPA, idx09_hid, inh_hid },
+	{ M680X_INS_SBCA, idx09_hid, inh_hid },
+	{ M680X_INS_SUBD, idx09_hid, inh_hid },
+	{ M680X_INS_ANDA, idx09_hid, inh_hid },
+	{ M680X_INS_BITA, idx09_hid, inh_hid },
+	{ M680X_INS_LDA, idx09_hid, inh_hid },
+	{ M680X_INS_STA, idx09_hid, inh_hid },
+	{ M680X_INS_EORA, idx09_hid, inh_hid },
+	{ M680X_INS_ADCA, idx09_hid, inh_hid },
+	{ M680X_INS_ORA, idx09_hid, inh_hid },
+	{ M680X_INS_ADDA, idx09_hid, inh_hid },
+	{ M680X_INS_CMPX, idx09_hid, inh_hid },
+	{ M680X_INS_JSR, idx09_hid, inh_hid },
+	{ M680X_INS_LDX, idx09_hid, inh_hid },
+	{ M680X_INS_STX, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register A,D,X
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_SUBD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDA, ext_hid, inh_hid },
+	{ M680X_INS_STA, ext_hid, inh_hid },
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_CMPX, ext_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register B,D,U
+	{ M680X_INS_SUBB, imm8_hid, inh_hid },
+	{ M680X_INS_CMPB, imm8_hid, inh_hid },
+	{ M680X_INS_SBCB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDB, imm8_hid, inh_hid },
+	{ M680X_INS_BITB, imm8_hid, inh_hid },
+	{ M680X_INS_LDB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADCB, imm8_hid, inh_hid },
+	{ M680X_INS_ORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDB, imm8_hid, inh_hid },
+	{ M680X_INS_LDD, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDU, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0xDx direct instructions with register B,D,U
+	{ M680X_INS_SUBB, dir_hid, inh_hid },
+	{ M680X_INS_CMPB, dir_hid, inh_hid },
+	{ M680X_INS_SBCB, dir_hid, inh_hid },
+	{ M680X_INS_ADDD, dir_hid, inh_hid },
+	{ M680X_INS_ANDB, dir_hid, inh_hid },
+	{ M680X_INS_BITB, dir_hid, inh_hid },
+	{ M680X_INS_LDB, dir_hid, inh_hid },
+	{ M680X_INS_STB, dir_hid, inh_hid },
+	{ M680X_INS_EORB, dir_hid, inh_hid },
+	{ M680X_INS_ADCB, dir_hid, inh_hid },
+	{ M680X_INS_ORB, dir_hid, inh_hid },
+	{ M680X_INS_ADDB, dir_hid, inh_hid },
+	{ M680X_INS_LDD, dir_hid, inh_hid },
+	{ M680X_INS_STD, dir_hid, inh_hid },
+	{ M680X_INS_LDU, dir_hid, inh_hid },
+	{ M680X_INS_STU, dir_hid, inh_hid },
+	// 0xEx, indexed instruction with register B,D,U
+	{ M680X_INS_SUBB, idx09_hid, inh_hid },
+	{ M680X_INS_CMPB, idx09_hid, inh_hid },
+	{ M680X_INS_SBCB, idx09_hid, inh_hid },
+	{ M680X_INS_ADDD, idx09_hid, inh_hid },
+	{ M680X_INS_ANDB, idx09_hid, inh_hid },
+	{ M680X_INS_BITB, idx09_hid, inh_hid },
+	{ M680X_INS_LDB, idx09_hid, inh_hid },
+	{ M680X_INS_STB, idx09_hid, inh_hid },
+	{ M680X_INS_EORB, idx09_hid, inh_hid },
+	{ M680X_INS_ADCB, idx09_hid, inh_hid },
+	{ M680X_INS_ORB, idx09_hid, inh_hid },
+	{ M680X_INS_ADDB, idx09_hid, inh_hid },
+	{ M680X_INS_LDD, idx09_hid, inh_hid },
+	{ M680X_INS_STD, idx09_hid, inh_hid },
+	{ M680X_INS_LDU, idx09_hid, inh_hid },
+	{ M680X_INS_STU, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register B,D,U
+	{ M680X_INS_SUBB, ext_hid, inh_hid },
+	{ M680X_INS_CMPB, ext_hid, inh_hid },
+	{ M680X_INS_SBCB, ext_hid, inh_hid },
+	{ M680X_INS_ADDD, ext_hid, inh_hid },
+	{ M680X_INS_ANDB, ext_hid, inh_hid },
+	{ M680X_INS_BITB, ext_hid, inh_hid },
+	{ M680X_INS_LDB, ext_hid, inh_hid },
+	{ M680X_INS_STB, ext_hid, inh_hid },
+	{ M680X_INS_EORB, ext_hid, inh_hid },
+	{ M680X_INS_ADCB, ext_hid, inh_hid },
+	{ M680X_INS_ORB, ext_hid, inh_hid },
+	{ M680X_INS_ADDB, ext_hid, inh_hid },
+	{ M680X_INS_LDD, ext_hid, inh_hid },
+	{ M680X_INS_STD, ext_hid, inh_hid },
+	{ M680X_INS_LDU, ext_hid, inh_hid },
+	{ M680X_INS_STU, ext_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// M6809 PAGE2 instructions (with prefix 0x10)
+static const inst_pageX g_m6809_inst_page2_table[] = {
+	// 0x2x, relative long branch instructions
+	{ 0x21, M680X_INS_LBRN, rel16_hid, inh_hid },
+	{ 0x22, M680X_INS_LBHI, rel16_hid, inh_hid },
+	{ 0x23, M680X_INS_LBLS, rel16_hid, inh_hid },
+	{ 0x24, M680X_INS_LBCC, rel16_hid, inh_hid },
+	{ 0x25, M680X_INS_LBCS, rel16_hid, inh_hid },
+	{ 0x26, M680X_INS_LBNE, rel16_hid, inh_hid },
+	{ 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid },
+	{ 0x28, M680X_INS_LBVC, rel16_hid, inh_hid },
+	{ 0x29, M680X_INS_LBVS, rel16_hid, inh_hid },
+	{ 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid },
+	{ 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid },
+	{ 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid },
+	{ 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid },
+	{ 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid },
+	{ 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid },
+	// 0x3x
+	{ 0x3f, M680X_INS_SWI2, inh_hid, inh_hid },
+	// 0x8x, immediate instructions with register D,Y
+	{ 0x83, M680X_INS_CMPD, imm16_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid },
+	{ 0x8e, M680X_INS_LDY, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register D,Y
+	{ 0x93, M680X_INS_CMPD, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPY, dir_hid, inh_hid },
+	{ 0x9e, M680X_INS_LDY, dir_hid, inh_hid },
+	{ 0x9f, M680X_INS_STY, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register D,Y
+	{ 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPY, idx09_hid, inh_hid },
+	{ 0xae, M680X_INS_LDY, idx09_hid, inh_hid },
+	{ 0xaf, M680X_INS_STY, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register D,Y
+	{ 0xb3, M680X_INS_CMPD, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPY, ext_hid, inh_hid },
+	{ 0xbe, M680X_INS_LDY, ext_hid, inh_hid },
+	{ 0xbf, M680X_INS_STY, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register S
+	{ 0xce, M680X_INS_LDS, imm16_hid, inh_hid },
+	// 0xDx, direct instructions with register S
+	{ 0xde, M680X_INS_LDS, dir_hid, inh_hid },
+	{ 0xdf, M680X_INS_STS, dir_hid, inh_hid },
+	// 0xEx, indexed instructions with register S
+	{ 0xee, M680X_INS_LDS, idx09_hid, inh_hid },
+	{ 0xef, M680X_INS_STS, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register S
+	{ 0xfe, M680X_INS_LDS, ext_hid, inh_hid },
+	{ 0xff, M680X_INS_STS, ext_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// M6809 PAGE3 instructions (with prefix 0x11)
+static const inst_pageX g_m6809_inst_page3_table[] = {
+	{ 0x3f, M680X_INS_SWI3, inh_hid, inh_hid },
+	// 0x8x, immediate instructions with register U,S
+	{ 0x83, M680X_INS_CMPU, imm16_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register U,S
+	{ 0x93, M680X_INS_CMPU, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPS, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register U,S
+	{ 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPS, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register U,S
+	{ 0xb3, M680X_INS_CMPU, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPS, ext_hid, inh_hid },
+};
+

arch/M680X/m6811.inc

@@ -0,0 +1,105 @@
+
+// Additional instructions only supported on M68HC11
+static const inst_pageX g_m6811_inst_overlay_table[] = {
+	{ 0x00, M680X_INS_TEST, inh_hid, inh_hid },
+	{ 0x02, M680X_INS_IDIV, inh_hid, inh_hid },
+	{ 0x03, M680X_INS_FDIV, inh_hid, inh_hid },
+	{ 0x12, M680X_INS_BRSET, dir_hid, imm8rel_hid },
+	{ 0x13, M680X_INS_BRCLR, dir_hid, imm8rel_hid },
+	{ 0x14, M680X_INS_BSET, dir_hid, imm8_hid },
+	{ 0x15, M680X_INS_BCLR, dir_hid, imm8_hid },
+	{ 0x1c, M680X_INS_BSET, idxX_hid, imm8_hid },
+	{ 0x1d, M680X_INS_BCLR, idxX_hid, imm8_hid },
+	{ 0x1e, M680X_INS_BRSET, idxX_hid, imm8rel_hid },
+	{ 0x1f, M680X_INS_BRCLR, idxX_hid, imm8rel_hid },
+	{ 0x8f, M680X_INS_XGDX, inh_hid, inh_hid },
+	{ 0xcf, M680X_INS_STOP, inh_hid, inh_hid },
+};
+
+// M68HC11 PAGE2 instructions
+static const inst_pageX g_m6811_inst_page2_table[] = {
+	{ 0x08, M680X_INS_INY, inh_hid, inh_hid },
+	{ 0x09, M680X_INS_DEY, inh_hid, inh_hid },
+	{ 0x1c, M680X_INS_BSET, idxY_hid, imm8_hid },
+	{ 0x1d, M680X_INS_BCLR, idxY_hid, imm8_hid },
+	{ 0x1e, M680X_INS_BRSET, idxY_hid, imm8rel_hid },
+	{ 0x1f, M680X_INS_BRCLR, idxY_hid, imm8rel_hid },
+	{ 0x30, M680X_INS_TSY, inh_hid, inh_hid },
+	{ 0x35, M680X_INS_TYS, inh_hid, inh_hid },
+	{ 0x38, M680X_INS_PULY, inh_hid, inh_hid },
+	{ 0x3a, M680X_INS_ABY, inh_hid, inh_hid },
+	{ 0x3c, M680X_INS_PSHY, inh_hid, inh_hid },
+	{ 0x60, M680X_INS_NEG, idxY_hid, inh_hid },
+	{ 0x63, M680X_INS_COM, idxY_hid, inh_hid },
+	{ 0x64, M680X_INS_LSR, idxY_hid, inh_hid },
+	{ 0x66, M680X_INS_ROR, idxY_hid, inh_hid },
+	{ 0x67, M680X_INS_ASR, idxY_hid, inh_hid },
+	{ 0x68, M680X_INS_ASL, idxY_hid, inh_hid },
+	{ 0x69, M680X_INS_ROL, idxY_hid, inh_hid },
+	{ 0x6a, M680X_INS_DEC, idxY_hid, inh_hid },
+	{ 0x6c, M680X_INS_INC, idxY_hid, inh_hid },
+	{ 0x6d, M680X_INS_TST, idxY_hid, inh_hid },
+	{ 0x6e, M680X_INS_JMP, idxY_hid, inh_hid },
+	{ 0x6f, M680X_INS_CLR, idxY_hid, inh_hid },
+	{ 0x8c, M680X_INS_CPY, imm16_hid, inh_hid },
+	{ 0x8f, M680X_INS_XGDY, inh_hid, inh_hid },
+	{ 0x9c, M680X_INS_CPY, dir_hid, inh_hid },
+	{ 0xa0, M680X_INS_SUBA, idxY_hid, inh_hid },
+	{ 0xa1, M680X_INS_CMPA, idxY_hid, inh_hid },
+	{ 0xa2, M680X_INS_SBCA, idxY_hid, inh_hid },
+	{ 0xa3, M680X_INS_SUBD, idxY_hid, inh_hid },
+	{ 0xa4, M680X_INS_ANDA, idxY_hid, inh_hid },
+	{ 0xa5, M680X_INS_BITA, idxY_hid, inh_hid },
+	{ 0xa6, M680X_INS_LDAA, idxY_hid, inh_hid },
+	{ 0xa7, M680X_INS_STAA, idxY_hid, inh_hid },
+	{ 0xa8, M680X_INS_EORA, idxY_hid, inh_hid },
+	{ 0xa9, M680X_INS_ADCA, idxY_hid, inh_hid },
+	{ 0xaa, M680X_INS_ORAA, idxY_hid, inh_hid },
+	{ 0xab, M680X_INS_ADDA, idxY_hid, inh_hid },
+	{ 0xac, M680X_INS_CPY, idxY_hid, inh_hid },
+	{ 0xad, M680X_INS_JSR, idxY_hid, inh_hid },
+	{ 0xae, M680X_INS_LDS, idxY_hid, inh_hid },
+	{ 0xaf, M680X_INS_STS, idxY_hid, inh_hid },
+	{ 0xbc, M680X_INS_CPY, ext_hid, inh_hid },
+	{ 0xce, M680X_INS_LDY, imm16_hid, inh_hid },
+	{ 0xde, M680X_INS_LDY, dir_hid, inh_hid },
+	{ 0xdf, M680X_INS_STY, dir_hid, inh_hid },
+	{ 0xe0, M680X_INS_SUBB, idxY_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMPB, idxY_hid, inh_hid },
+	{ 0xe2, M680X_INS_SBCB, idxY_hid, inh_hid },
+	{ 0xe3, M680X_INS_ADDD, idxY_hid, inh_hid },
+	{ 0xe4, M680X_INS_ANDB, idxY_hid, inh_hid },
+	{ 0xe5, M680X_INS_BITB, idxY_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDAB, idxY_hid, inh_hid },
+	{ 0xe7, M680X_INS_STAB, idxY_hid, inh_hid },
+	{ 0xe8, M680X_INS_EORB, idxY_hid, inh_hid },
+	{ 0xe9, M680X_INS_ADCB, idxY_hid, inh_hid },
+	{ 0xea, M680X_INS_ORAB, idxY_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADDB, idxY_hid, inh_hid },
+	{ 0xec, M680X_INS_LDD, idxY_hid, inh_hid },
+	{ 0xed, M680X_INS_STD, idxY_hid, inh_hid },
+	{ 0xee, M680X_INS_LDY, idxY_hid, inh_hid },
+	{ 0xef, M680X_INS_STY, idxY_hid, inh_hid },
+	{ 0xfe, M680X_INS_LDY, ext_hid, inh_hid },
+	{ 0xff, M680X_INS_STY, ext_hid, inh_hid },
+};
+
+// M68HC11 PAGE3 instructions
+static const inst_pageX g_m6811_inst_page3_table[] = {
+	{ 0x83, M680X_INS_CPD, imm16_hid, inh_hid },
+	{ 0x93, M680X_INS_CPD, dir_hid, inh_hid },
+	{ 0xa3, M680X_INS_CPD, idxX_hid, inh_hid },
+	{ 0xac, M680X_INS_CPY, idxX_hid, inh_hid },
+	{ 0xb3, M680X_INS_CPD, ext_hid, inh_hid },
+	{ 0xee, M680X_INS_LDY, idxX_hid, inh_hid },
+	{ 0xef, M680X_INS_STY, idxX_hid, inh_hid },
+};
+
+// M68HC11 PAGE4 instructions
+static const inst_pageX g_m6811_inst_page4_table[] = {
+	{ 0xa3, M680X_INS_CPD, idxY_hid, inh_hid },
+	{ 0xac, M680X_INS_CPX, idxY_hid, inh_hid },
+	{ 0xee, M680X_INS_LDX, idxY_hid, inh_hid },
+	{ 0xef, M680X_INS_STX, idxY_hid, inh_hid },
+};
+

arch/M68K/M68KDisassembler.h

@@ -0,0 +1,30 @@
+/* Capstone Disassembly Engine */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
+
+#ifndef CS_M68KDISASSEMBLER_H
+#define CS_M68KDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+/* Private, For internal use only */
+typedef struct m68k_info {
+	const uint8_t *code;
+	size_t code_len;
+	uint64_t baseAddress;
+	MCInst *inst;
+	unsigned int pc;        /* program counter */
+	unsigned int ir;        /* instruction register */
+	unsigned int type;
+	unsigned int address_mask; /* Address mask to simulate address lines */
+	cs_m68k extension;
+	uint16_t regs_read[20]; // list of implicit registers read by this insn
+	uint8_t regs_read_count; // number of implicit registers read by this insn
+	uint16_t regs_write[20]; // list of implicit registers modified by this insn
+	uint8_t regs_write_count; // number of implicit registers modified by this insn
+	uint8_t groups[8];
+	uint8_t groups_count;
+} m68k_info;
+
+bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info);
+
+#endif

arch/M68K/M68KInstPrinter.c

@@ -0,0 +1,387 @@
+/* Capstone Disassembly Engine */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
+
+#ifdef _MSC_VER
+// Disable security warnings for strcat & sprintf
+#ifndef _CRT_SECURE_NO_WARNINGS
+#define _CRT_SECURE_NO_WARNINGS
+#endif
+
+//Banned API Usage : strcat / sprintf is a Banned API as listed in dontuse.h for
+//security purposes.
+#pragma warning(disable:28719)
+#endif
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "M68KInstPrinter.h"
+
+#include "M68KDisassembler.h"
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCRegisterInfo.h"
+
+#ifndef CAPSTONE_DIET
+static const char* s_spacing = " ";
+
+static const char* s_reg_names[] = {
+	"invalid",
+	"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+	"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+	"fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
+	"pc",
+	"sr", "ccr", "sfc", "dfc", "usp", "vbr", "cacr",
+	"caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0",
+	"dtt1", "mmusr", "urp", "srp",
+
+	"fpcr", "fpsr", "fpiar",
+};
+
+static const char* s_instruction_names[] = {
+	"invalid",
+	"abcd", "add", "adda", "addi", "addq", "addx", "and", "andi", "asl", "asr", "bhs", "blo", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc",
+	"bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble", "bra", "bsr", "bchg", "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", "bfins",
+	"bfset", "bftst", "bkpt", "callm", "cas", "cas2", "chk", "chk2", "clr", "cmp", "cmpa", "cmpi", "cmpm", "cmp2", "cinvl", "cinvp", "cinva", "cpushl", "cpushp",
+	"cpusha", "dbt", "dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne", "dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge", "dblt", "dbgt", "dble", "dbra",
+	"divs", "divsl", "divu", "divul", "eor", "eori", "exg", "ext", "extb", "fabs", "fsabs", "fdabs", "facos", "fadd", "fsadd", "fdadd", "fasin",
+	"fatan", "fatanh", "fbf", "fbeq", "fbogt", "fboge", "fbolt", "fbole", "fbogl", "fbor", "fbun", "fbueq", "fbugt", "fbuge", "fbult", "fbule", "fbne", "fbt",
+	"fbsf", "fbseq", "fbgt", "fbge", "fblt", "fble", "fbgl", "fbgle", "fbngle", "fbngl", "fbnle", "fbnlt", "fbnge", "fbngt", "fbsne", "fbst", "fcmp", "fcos",
+	"fcosh", "fdbf", "fdbeq", "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule", "fdbne",
+	"fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge", "fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne",
+	"fdbst", "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp", "fgetman", "fint", "fintrz", "flog10", "flog2", "flogn", "flognp1", "fmod", "fmove",
+	"fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv",
+	"fsglmul", "fsin", "fsincos", "fsinh", "fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge", "fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq",
+	"fsugt", "fsuge", "fsult", "fsule", "fsne", "fst", "fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle", "fsgl", "fsgle", "fsngle",
+	"fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt",
+	"ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt",
+	"ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge",
+	"ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec",
+	"movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha",
+	"pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror",
+	"roxl", "roxr", "rtd", "rte", "rtm", "rtr", "rts", "sbcd", "st", "sf", "shi", "sls", "scc", "shs", "scs", "slo", "sne", "seq", "svc", "svs", "spl", "smi",
+	"sge", "slt", "sgt", "sle", "stop", "sub", "suba", "subi", "subq", "subx", "swap", "tas", "trap", "trapv", "trapt", "trapf", "traphi", "trapls",
+	"trapcc", "traphs", "trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs", "trappl", "trapmi", "trapge", "traplt", "trapgt", "traple", "tst", "unlk", "unpk",
+};
+#endif
+
+
+#ifndef CAPSTONE_DIET
+static const char* getRegName(m68k_reg reg)
+{
+	return s_reg_names[(int)reg];
+}
+
+static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix)
+{
+	unsigned int first = 0;
+	unsigned int run_length = 0;
+	int i;
+
+	for (i = 0; i < 8; ++i) {
+		if (data & (1 << i)) {
+			first = i;
+			run_length = 0;
+
+			while (i < 7 && (data & (1 << (i + 1)))) {
+				i++;
+				run_length++;
+			}
+
+			if (buffer[0] != 0)
+				strcat(buffer, "/");
+
+			sprintf(buffer + strlen(buffer), "%s%d", prefix, first);
+			if (run_length > 0)
+				sprintf(buffer + strlen(buffer), "-%s%d", prefix, first + run_length);
+		}
+	}
+}
+
+static void registerBits(SStream* O, const cs_m68k_op* op)
+{
+	char buffer[128];
+	unsigned int data = op->register_bits;
+
+	buffer[0] = 0;
+
+	if (!data) {
+		SStream_concat(O, "%s", "#$0");
+		return;
+	}
+
+	printRegbitsRange(buffer, data & 0xff, "d");
+	printRegbitsRange(buffer, (data >> 8) & 0xff, "a");
+	printRegbitsRange(buffer, (data >> 16) & 0xff, "fp");
+
+	SStream_concat(O, "%s", buffer);
+}
+
+static void registerPair(SStream* O, const cs_m68k_op* op)
+{
+	SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + op->reg_pair.reg_0],
+			s_reg_names[M68K_REG_D0 + op->reg_pair.reg_1]);
+}
+
+static void printAddressingMode(SStream* O, unsigned int pc, const cs_m68k* inst, const cs_m68k_op* op)
+{
+	switch (op->address_mode) {
+		case M68K_AM_NONE:
+			switch (op->type) {
+				case M68K_OP_REG_BITS:
+					registerBits(O, op);
+					break;
+				case M68K_OP_REG_PAIR:
+					registerPair(O, op);
+					break;
+				case M68K_OP_REG:
+					SStream_concat(O, "%s", s_reg_names[op->reg]);
+					break;
+				default:
+					break;
+			}
+			break;
+
+		case M68K_AM_REG_DIRECT_DATA: SStream_concat(O, "d%d", (op->reg - M68K_REG_D0)); break;
+		case M68K_AM_REG_DIRECT_ADDR: SStream_concat(O, "a%d", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR: SStream_concat(O, "(a%d)", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR_POST_INC: SStream_concat(O, "(a%d)+", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR_PRE_DEC: SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR_DISP: SStream_concat(O, "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), (op->mem.base_reg - M68K_REG_A0)); break;
+		case M68K_AM_PCI_DISP: SStream_concat(O, "$%x(pc)", pc + 2 + op->mem.disp); break;
+		case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break;
+		case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break;
+		case M68K_AM_IMMEDIATE:
+			 if (inst->op_size.type == M68K_SIZE_TYPE_FPU) {
+#if defined(_KERNEL_MODE)
+				 // Issue #681: Windows kernel does not support formatting float point
+				 SStream_concat(O, "#<float_point_unsupported>");
+				 break;
+#else
+				 if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE)
+					 SStream_concat(O, "#%f", op->simm);
+				 else if (inst->op_size.fpu_size == M68K_FPU_SIZE_DOUBLE)
+					 SStream_concat(O, "#%f", op->dimm);
+				 else
+					 SStream_concat(O, "#<unsupported>");
+				 break;
+#endif
+			 }
+			 SStream_concat(O, "#$%x", op->imm);
+			 break;
+		case M68K_AM_PCI_INDEX_8_BIT_DISP:
+			SStream_concat(O, "$%x(pc,%s%s.%c)", pc + 2 + op->mem.disp, s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			break;
+		case M68K_AM_AREGI_INDEX_8_BIT_DISP:
+			SStream_concat(O, "%s$%x(%s,%s%s.%c)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			break;
+		case M68K_AM_PCI_INDEX_BASE_DISP:
+		case M68K_AM_AREGI_INDEX_BASE_DISP:
+
+			if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
+				SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
+			} else {
+				if (op->mem.in_disp > 0)
+					SStream_concat(O, "$%x", op->mem.in_disp);
+			}
+
+			SStream_concat(O, "(");
+
+			if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
+			    SStream_concat(O, "pc,%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			} else {
+				if (op->mem.base_reg != M68K_REG_INVALID)
+					SStream_concat(O, "a%d,%s", op->mem.base_reg - M68K_REG_A0, s_spacing);
+				SStream_concat(O, "%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			}
+
+			if (op->mem.scale > 0)
+			    SStream_concat(O, "%s*%s%d)", s_spacing, s_spacing, op->mem.scale);
+			else
+			    SStream_concat(O, ")");
+			break;
+			// It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler. While this is not strictly correct it makes the code
+			// easier and that is what actually happens when the code is executed anyway.
+
+		case M68K_AM_PC_MEMI_POST_INDEX:
+		case M68K_AM_PC_MEMI_PRE_INDEX:
+		case M68K_AM_MEMI_PRE_INDEX:
+		case M68K_AM_MEMI_POST_INDEX:
+			SStream_concat(O, "([");
+
+			if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) {
+				SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
+			} else {
+				if (op->mem.in_disp > 0)
+					SStream_concat(O, "$%x", op->mem.in_disp);
+			}
+
+			if (op->mem.base_reg != M68K_REG_INVALID) {
+				if (op->mem.in_disp > 0)
+					SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg));
+				else
+					SStream_concat(O, "%s", getRegName(op->mem.base_reg));
+			}
+
+			if (op->address_mode == M68K_AM_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_POST_INDEX)
+			    SStream_concat(O, "]");
+
+			if (op->mem.index_reg != M68K_REG_INVALID)
+			    SStream_concat(O, ",%s%s.%c", s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+
+			if (op->mem.scale > 0)
+			    SStream_concat(O, "%s*%s%d", s_spacing, s_spacing, op->mem.scale);
+
+			if (op->address_mode == M68K_AM_MEMI_PRE_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX)
+			    SStream_concat(O, "]");
+
+			if (op->mem.out_disp > 0)
+			    SStream_concat(O, ",%s$%x", s_spacing, op->mem.out_disp);
+
+			SStream_concat(O, ")");
+			break;
+		case M68K_AM_BRANCH_DISPLACEMENT:
+			SStream_concat(O, "$%x", pc + 2 + op->br_disp.disp);
+		default:
+			break;
+	}
+
+	if (op->mem.bitfield)
+		SStream_concat(O, "{%d:%d}", op->mem.offset, op->mem.width);
+}
+#endif
+
+#define m68k_sizeof_array(array) (int)(sizeof(array)/sizeof(array[0]))
+#define m68k_min(a, b) (a < b) ? a : b
+
+void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo)
+{
+#ifndef CAPSTONE_DIET
+	m68k_info *info = (m68k_info *)PrinterInfo;
+	cs_m68k *ext = &info->extension;
+	cs_detail *detail = NULL;
+	int i = 0;
+
+	detail = MI->flat_insn->detail;
+	if (detail) {
+		int regs_read_count = m68k_min(m68k_sizeof_array(detail->regs_read), info->regs_read_count);
+		int regs_write_count = m68k_min(m68k_sizeof_array(detail->regs_write), info->regs_write_count);
+		int groups_count = m68k_min(m68k_sizeof_array(detail->groups), info->groups_count);
+
+		memcpy(&detail->m68k, ext, sizeof(cs_m68k));
+
+		memcpy(&detail->regs_read, &info->regs_read, regs_read_count * sizeof(uint16_t));
+		detail->regs_read_count = regs_read_count;
+
+		memcpy(&detail->regs_write, &info->regs_write, regs_write_count * sizeof(uint16_t));
+		detail->regs_write_count = regs_write_count;
+
+		memcpy(&detail->groups, &info->groups, groups_count);
+		detail->groups_count = groups_count;
+	}
+
+	if (MI->Opcode == M68K_INS_INVALID) {
+		if (ext->op_count)
+			SStream_concat(O, "dc.w $%x", ext->operands[0].imm);
+		else
+			SStream_concat(O, "dc.w $<unknown>");
+		return;
+	}
+
+	SStream_concat0(O, (char*)s_instruction_names[MI->Opcode]);
+
+	switch (ext->op_size.type) {
+		case M68K_SIZE_TYPE_INVALID :
+			break;
+
+		case M68K_SIZE_TYPE_CPU :
+			switch (ext->op_size.cpu_size) {
+				case M68K_CPU_SIZE_BYTE: SStream_concat0(O, ".b"); break;
+				case M68K_CPU_SIZE_WORD: SStream_concat0(O, ".w"); break;
+				case M68K_CPU_SIZE_LONG: SStream_concat0(O, ".l"); break;
+				case M68K_CPU_SIZE_NONE: break;
+			}
+			break;
+
+		case M68K_SIZE_TYPE_FPU :
+			switch (ext->op_size.fpu_size) {
+				case M68K_FPU_SIZE_SINGLE: SStream_concat0(O, ".s"); break;
+				case M68K_FPU_SIZE_DOUBLE: SStream_concat0(O, ".d"); break;
+				case M68K_FPU_SIZE_EXTENDED: SStream_concat0(O, ".x"); break;
+				case M68K_FPU_SIZE_NONE: break;
+			}
+			break;
+	}
+
+	SStream_concat0(O, " ");
+
+	// this one is a bit spacial so we do special things
+
+	if (MI->Opcode == M68K_INS_CAS2) {
+		int reg_value_0, reg_value_1;
+		printAddressingMode(O, info->pc, ext, &ext->operands[0]); SStream_concat0(O, ",");
+		printAddressingMode(O, info->pc, ext, &ext->operands[1]); SStream_concat0(O, ",");
+		reg_value_0 = ext->operands[2].register_bits >> 4;
+		reg_value_1 = ext->operands[2].register_bits & 0xf;
+		SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]);
+		return;
+	}
+
+	for (i  = 0; i < ext->op_count; ++i) {
+		printAddressingMode(O, info->pc, ext, &ext->operands[i]);
+		if ((i + 1) != ext->op_count)
+			SStream_concat(O, ",%s", s_spacing);
+	}
+#endif
+}
+
+const char* M68K_reg_name(csh handle, unsigned int reg)
+{
+#ifdef CAPSTONE_DIET
+	return NULL;
+#else
+	if (reg >= ARR_SIZE(s_reg_names)) {
+		return NULL;
+	}
+	return s_reg_names[(int)reg];
+#endif
+}
+
+void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id)
+{
+	insn->id = id; // These id's matches for 68k
+}
+
+const char* M68K_insn_name(csh handle, unsigned int id)
+{
+#ifdef CAPSTONE_DIET
+	return NULL;
+#else
+	return s_instruction_names[id];
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ M68K_GRP_INVALID , NULL },
+	{ M68K_GRP_JUMP, "jump" },
+	{ M68K_GRP_RET , "ret" },
+	{ M68K_GRP_IRET, "iret" },
+	{ M68K_GRP_BRANCH_RELATIVE, "branch_relative" },
+};
+#endif
+
+const char *M68K_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+

arch/M68K/M68KInstPrinter.h

@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015 */
+
+#ifndef CS_M68KINSTPRINTER_H
+#define CS_M68KINSTPRINTER_H
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+struct SStream;
+
+void M68K_init(MCRegisterInfo *MRI);
+void M68K_printInst(MCInst* MI, struct SStream* O, void* Info);
+const char* M68K_reg_name(csh handle, unsigned int reg);
+void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id);
+const char *M68K_insn_name(csh handle, unsigned int id);
+const char* M68K_group_name(csh handle, unsigned int id);
+void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci);
+
+#endif